From: Jin Ma Date: Mon, 25 Dec 2023 08:49:21 +0000 (+0800) Subject: RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension X-Git-Tag: binutils-2_42~348 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=77d242a06e352eee88908326d7bbf3b77086d5db;p=thirdparty%2Fbinutils-gdb.git RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension In order to make it easier to complete the compiler's support for the XTheadVector extension and to be as compatible as possible with the programming model of the 'V' extension ([1]), we consider adding a few pseudo instructions ([2]). th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0 th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs Ref: [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html [2] https://github.com/T-head-Semi/thead-extension-spec/pull/40 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for new pseudoinstructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. opcodes/ChangeLog: * riscv-opc.c: Add new pseudoinstructions. --- diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 014c2fdb80d..441bd0e660f 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -982,6 +982,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+e3057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+e3057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+e1057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+0e804257[ ]+th.vneg.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+0c804257[ ]+th.vneg.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+02860257[ ]+th.vadd.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+0285c257[ ]+th.vadd.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+0287b257[ ]+th.vadd.vi[ ]+v4,v8,15 @@ -1098,6 +1100,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a485c257[ ]+th.vsra.vx[ ]+v4,v8,a1,v0.t [ ]+[0-9a-f]+:[ ]+a480b257[ ]+th.vsra.vi[ ]+v4,v8,1,v0.t [ ]+[0-9a-f]+:[ ]+a48fb257[ ]+th.vsra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+b2804257[ ]+th.vncvt.x.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+b0804257[ ]+th.vncvt.x.x.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+b2860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+b285c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+b280b257[ ]+th.vnsrl.vi[ ]+v4,v8,1 @@ -1488,6 +1492,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+10865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2,v0.t [ ]+[0-9a-f]+:[ ]+18861257[ ]+th.vfmax.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+18865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+26841257[ ]+th.vfneg.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+24841257[ ]+th.vfneg.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+2a841257[ ]+th.vfabs.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+28841257[ ]+th.vfabs.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+22861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+22865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2 [ ]+[0-9a-f]+:[ ]+26861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12 @@ -1593,6 +1601,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+6e422257[ ]+th.vmclr.m[ ]+v4 [ ]+[0-9a-f]+:[ ]+7e422257[ ]+th.vmset.m[ ]+v4 [ ]+[0-9a-f]+:[ ]+76842257[ ]+th.vmnot.m[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 3a4dea38c8b..413f4a83a94 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1006,6 +1006,10 @@ th.vlseg8eff.v v4, 0(a0) th.vlseg8eff.v v4, (a0), v0.t + # Aliases + th.vneg.v v4, v8 + th.vneg.v v4, v8, v0.t + th.vadd.vv v4, v8, v12 th.vadd.vx v4, v8, a1 th.vadd.vi v4, v8, 15 @@ -1131,6 +1135,10 @@ th.vsra.vi v4, v8, 1, v0.t th.vsra.vi v4, v8, 31, v0.t + # Aliases + th.vncvt.x.x.v v4, v8 + th.vncvt.x.x.v v4, v8, v0.t + th.vnsrl.vv v4, v8, v12 th.vnsrl.vx v4, v8, a1 th.vnsrl.vi v4, v8, 1 @@ -1539,6 +1547,12 @@ th.vfmax.vv v4, v8, v12, v0.t th.vfmax.vf v4, v8, fa2, v0.t + # Aliases + th.vfneg.v v4, v8 + th.vfneg.v v4, v8, v0.t + th.vfabs.v v4, v8 + th.vfabs.v v4, v8, v0.t + th.vfsgnj.vv v4, v8, v12 th.vfsgnj.vf v4, v8, fa2 th.vfsgnjn.vv v4, v8, v12 @@ -1658,6 +1672,7 @@ th.vfwredsum.vs v4, v8, v12, v0.t # Aliases + th.vmmv.m v4, v8 th.vmcpy.m v4, v8 th.vmclr.m v4 th.vmset.m v4 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bf388cdaa2f..5441ec0dc28 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2579,6 +2579,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF}, {"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF}, {"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF}, +{"th.vneg.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_opcode, INSN_ALIAS }, {"th.vadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 }, {"th.vadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 }, {"th.vadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 }, @@ -2633,6 +2634,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 }, {"th.vsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 }, {"th.vsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 }, +{"th.vncvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_opcode, INSN_ALIAS }, {"th.vnsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 }, {"th.vnsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 }, {"th.vnsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 }, @@ -2807,6 +2809,8 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vfmin.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0}, {"th.vfmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0}, {"th.vfmax.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0}, +{"th.vfneg.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2, INSN_ALIAS }, +{"th.vfabs.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2, INSN_ALIAS }, {"th.vfsgnj.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0}, {"th.vfsgnj.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0}, {"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0}, @@ -2861,6 +2865,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0}, {"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0}, {"th.vmcpy.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, +{"th.vmmv.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, {"th.vmclr.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, {"th.vmset.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, {"th.vmnot.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},