From: ebotcazou Date: Sun, 12 Feb 2012 20:42:45 +0000 (+0000) Subject: * config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode, X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7a0443dcfef68735a19b6c1fae967158a9efd684;p=thirdparty%2Fgcc.git * config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode, disallow changes from SFmode to mode with different size in FP regs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@184144 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 44b8b8848e86..1a971088a8a2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,9 @@ -2012-01-29 Robert Millan +2012-02-12 Eric Botcazou + + * config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): In 64-bit mode, + disallow changes from SFmode to mode with different size in FP regs. + +2012-02-12 Robert Millan Gerald Pfeifer * ginclude/stddef.h [__FreeBSD_kernel__] (__size_t): Do not define. diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index bb6b07943503..acc6be1fe1e4 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -894,18 +894,21 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] -/* Defines invalid mode changes. Borrowed from pa64-regs.h. +/* Defines invalid mode changes. Borrowed from the PA port. SImode loads to floating-point registers are not zero-extended. The definition for LOAD_EXTEND_OP specifies that integer loads narrower than BITS_PER_WORD will be zero-extended. As a result, we inhibit changes from SImode unless they are to a mode that is - identical in size. */ + identical in size. + + Likewise for SFmode, since word-mode paradoxical subregs are + problematic on big-endian architectures. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ (TARGET_ARCH64 \ - && (FROM) == SImode \ - && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + && GET_MODE_SIZE (FROM) == 4 \ + && GET_MODE_SIZE (TO) != 4 \ ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) /* This is the order in which to allocate registers normally.