From: Sasha Levin Date: Mon, 17 Oct 2022 02:10:17 +0000 (-0400) Subject: Fixes for 5.10 X-Git-Tag: v5.4.219~51 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7a81664b05e13718f9fb3b3dd451bc91543f8bc4;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.10 Signed-off-by: Sasha Levin --- diff --git a/queue-5.10/acpi-apei-do-not-add-task_work-to-kernel-thread-to-a.patch b/queue-5.10/acpi-apei-do-not-add-task_work-to-kernel-thread-to-a.patch new file mode 100644 index 00000000000..97084b3dc32 --- /dev/null +++ b/queue-5.10/acpi-apei-do-not-add-task_work-to-kernel-thread-to-a.patch @@ -0,0 +1,78 @@ +From 693c1b7eb60490c71e8f1c2cba19a1f3404303da Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 24 Sep 2022 15:49:53 +0800 +Subject: ACPI: APEI: do not add task_work to kernel thread to avoid memory + leak + +From: Shuai Xue + +[ Upstream commit 415fed694fe11395df56e05022d6e7cee1d39dd3 ] + +If an error is detected as a result of user-space process accessing a +corrupt memory location, the CPU may take an abort. Then the platform +firmware reports kernel via NMI like notifications, e.g. NOTIFY_SEA, +NOTIFY_SOFTWARE_DELEGATED, etc. + +For NMI like notifications, commit 7f17b4a121d0 ("ACPI: APEI: Kick the +memory_failure() queue for synchronous errors") keep track of whether +memory_failure() work was queued, and make task_work pending to flush out +the queue so that the work is processed before return to user-space. + +The code use init_mm to check whether the error occurs in user space: + + if (current->mm != &init_mm) + +The condition is always true, becase _nobody_ ever has "init_mm" as a real +VM any more. + +In addition to abort, errors can also be signaled as asynchronous +exceptions, such as interrupt and SError. In such case, the interrupted +current process could be any kind of thread. When a kernel thread is +interrupted, the work ghes_kick_task_work deferred to task_work will never +be processed because entry_handler returns to call ret_to_kernel() instead +of ret_to_user(). Consequently, the estatus_node alloced from +ghes_estatus_pool in ghes_in_nmi_queue_one_entry() will not be freed. +After around 200 allocations in our platform, the ghes_estatus_pool will +run of memory and ghes_in_nmi_queue_one_entry() returns ENOMEM. As a +result, the event failed to be processed. + + sdei: event 805 on CPU 113 failed with error: -2 + +Finally, a lot of unhandled events may cause platform firmware to exceed +some threshold and reboot. + +The condition should generally just do + + if (current->mm) + +as described in active_mm.rst documentation. + +Then if an asynchronous error is detected when a kernel thread is running, +(e.g. when detected by a background scrubber), do not add task_work to it +as the original patch intends to do. + +Fixes: 7f17b4a121d0 ("ACPI: APEI: Kick the memory_failure() queue for synchronous errors") +Signed-off-by: Shuai Xue +Reviewed-by: Tony Luck +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/apei/ghes.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c +index 0c8330ed1ffd..5206fd3b7867 100644 +--- a/drivers/acpi/apei/ghes.c ++++ b/drivers/acpi/apei/ghes.c +@@ -985,7 +985,7 @@ static void ghes_proc_in_irq(struct irq_work *irq_work) + ghes_estatus_cache_add(generic, estatus); + } + +- if (task_work_pending && current->mm != &init_mm) { ++ if (task_work_pending && current->mm) { + estatus_node->task_work.func = ghes_kick_task_work; + estatus_node->task_work_cpu = smp_processor_id(); + ret = task_work_add(current, &estatus_node->task_work, +-- +2.35.1 + diff --git a/queue-5.10/acpi-video-add-toshiba-satellite-portege-z830-quirk.patch b/queue-5.10/acpi-video-add-toshiba-satellite-portege-z830-quirk.patch new file mode 100644 index 00000000000..c5e550e4d62 --- /dev/null +++ b/queue-5.10/acpi-video-add-toshiba-satellite-portege-z830-quirk.patch @@ -0,0 +1,59 @@ +From 013a0c54851ae3fe0425b623183d3637e1ba5fbb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 20:49:50 +0200 +Subject: ACPI: video: Add Toshiba Satellite/Portege Z830 quirk + +From: Arvid Norlander + +[ Upstream commit 574160b8548deff8b80b174f03201e94ab8431e2 ] + +Toshiba Satellite Z830 needs the quirk video_disable_backlight_sysfs_if +for proper backlight control after suspend/resume cycles. + +Toshiba Portege Z830 is simply the same laptop rebranded for certain +markets (I looked through the manual to other language sections to confirm +this) and thus also needs this quirk. + +Thanks to Hans de Goede for suggesting this fix. + +Link: https://www.spinics.net/lists/platform-driver-x86/msg34394.html +Suggested-by: Hans de Goede +Signed-off-by: Arvid Norlander +Reviewed-by: Hans de Goede +Tested-by: Arvid Norlander +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/acpi/acpi_video.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c +index eb04b2f828ee..cf6c9ffe04a2 100644 +--- a/drivers/acpi/acpi_video.c ++++ b/drivers/acpi/acpi_video.c +@@ -498,6 +498,22 @@ static const struct dmi_system_id video_dmi_table[] = { + DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE R830"), + }, + }, ++ { ++ .callback = video_disable_backlight_sysfs_if, ++ .ident = "Toshiba Satellite Z830", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE Z830"), ++ }, ++ }, ++ { ++ .callback = video_disable_backlight_sysfs_if, ++ .ident = "Toshiba Portege Z830", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE Z830"), ++ }, ++ }, + /* + * Some machine's _DOD IDs don't have bit 31(Device ID Scheme) set + * but the IDs actually follow the Device ID Scheme. +-- +2.35.1 + diff --git a/queue-5.10/alsa-dmaengine-increment-buffer-pointer-atomically.patch b/queue-5.10/alsa-dmaengine-increment-buffer-pointer-atomically.patch new file mode 100644 index 00000000000..4625d350174 --- /dev/null +++ b/queue-5.10/alsa-dmaengine-increment-buffer-pointer-atomically.patch @@ -0,0 +1,49 @@ +From 4fd957d4bcceec3ce3a8d4ba00e550f0968b91c9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 18:58:13 +0200 +Subject: ALSA: dmaengine: increment buffer pointer atomically + +From: Andreas Pape + +[ Upstream commit d1c442019594692c64a70a86ad88eb5b6db92216 ] + +Setting pointer and afterwards checking for wraparound leads +to the possibility of returning the inconsistent pointer position. + +This patch increments buffer pointer atomically to avoid this issue. + +Fixes: e7f73a1613567a ("ASoC: Add dmaengine PCM helper functions") +Signed-off-by: Andreas Pape +Signed-off-by: Eugeniu Rosca +Link: https://lore.kernel.org/r/1664211493-11789-1-git-send-email-erosca@de.adit-jv.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/core/pcm_dmaengine.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/sound/core/pcm_dmaengine.c b/sound/core/pcm_dmaengine.c +index 4d0e8fe535a1..be58505889a3 100644 +--- a/sound/core/pcm_dmaengine.c ++++ b/sound/core/pcm_dmaengine.c +@@ -130,12 +130,14 @@ EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_set_config_from_dai_data); + + static void dmaengine_pcm_dma_complete(void *arg) + { ++ unsigned int new_pos; + struct snd_pcm_substream *substream = arg; + struct dmaengine_pcm_runtime_data *prtd = substream_to_prtd(substream); + +- prtd->pos += snd_pcm_lib_period_bytes(substream); +- if (prtd->pos >= snd_pcm_lib_buffer_bytes(substream)) +- prtd->pos = 0; ++ new_pos = prtd->pos + snd_pcm_lib_period_bytes(substream); ++ if (new_pos >= snd_pcm_lib_buffer_bytes(substream)) ++ new_pos = 0; ++ prtd->pos = new_pos; + + snd_pcm_period_elapsed(substream); + } +-- +2.35.1 + diff --git a/queue-5.10/alsa-hda-beep-simplify-keep-power-at-enable-behavior.patch b/queue-5.10/alsa-hda-beep-simplify-keep-power-at-enable-behavior.patch new file mode 100644 index 00000000000..9491a9a7f64 --- /dev/null +++ b/queue-5.10/alsa-hda-beep-simplify-keep-power-at-enable-behavior.patch @@ -0,0 +1,135 @@ +From ef4f4622b126b262cb136a278d24197bc1dc8a70 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 11:23:06 +0200 +Subject: ALSA: hda: beep: Simplify keep-power-at-enable behavior + +From: Takashi Iwai + +[ Upstream commit 4c8d695cb9bc5f6fd298a586602947b2fc099a64 ] + +The recent fix for IDT codecs to keep the power up while the beep is +enabled can be better integrated into the beep helper code. +This patch cleans up the code with refactoring. + +Fixes: 414d38ba8710 ("ALSA: hda/sigmatel: Keep power up while beep is enabled") +Link: https://lore.kernel.org/r/20220906092306.26183-1-tiwai@suse.de +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/pci/hda/hda_beep.c | 15 +++++++++++++-- + sound/pci/hda/hda_beep.h | 1 + + sound/pci/hda/patch_sigmatel.c | 25 ++----------------------- + 3 files changed, 16 insertions(+), 25 deletions(-) + +diff --git a/sound/pci/hda/hda_beep.c b/sound/pci/hda/hda_beep.c +index 53a2b89f8983..e63621bcb214 100644 +--- a/sound/pci/hda/hda_beep.c ++++ b/sound/pci/hda/hda_beep.c +@@ -118,6 +118,12 @@ static int snd_hda_beep_event(struct input_dev *dev, unsigned int type, + return 0; + } + ++static void turn_on_beep(struct hda_beep *beep) ++{ ++ if (beep->keep_power_at_enable) ++ snd_hda_power_up_pm(beep->codec); ++} ++ + static void turn_off_beep(struct hda_beep *beep) + { + cancel_work_sync(&beep->beep_work); +@@ -125,6 +131,8 @@ static void turn_off_beep(struct hda_beep *beep) + /* turn off beep */ + generate_tone(beep, 0); + } ++ if (beep->keep_power_at_enable) ++ snd_hda_power_down_pm(beep->codec); + } + + /** +@@ -140,7 +148,9 @@ int snd_hda_enable_beep_device(struct hda_codec *codec, int enable) + enable = !!enable; + if (beep->enabled != enable) { + beep->enabled = enable; +- if (!enable) ++ if (enable) ++ turn_on_beep(beep); ++ else + turn_off_beep(beep); + return 1; + } +@@ -167,7 +177,8 @@ static int beep_dev_disconnect(struct snd_device *device) + input_unregister_device(beep->dev); + else + input_free_device(beep->dev); +- turn_off_beep(beep); ++ if (beep->enabled) ++ turn_off_beep(beep); + return 0; + } + +diff --git a/sound/pci/hda/hda_beep.h b/sound/pci/hda/hda_beep.h +index a25358a4807a..db76e3ddba65 100644 +--- a/sound/pci/hda/hda_beep.h ++++ b/sound/pci/hda/hda_beep.h +@@ -25,6 +25,7 @@ struct hda_beep { + unsigned int enabled:1; + unsigned int linear_tone:1; /* linear tone for IDT/STAC codec */ + unsigned int playing:1; ++ unsigned int keep_power_at_enable:1; /* set by driver */ + struct work_struct beep_work; /* scheduled task for beep event */ + struct mutex mutex; + void (*power_hook)(struct hda_beep *beep, bool on); +diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c +index b848e435b93f..6fc0c4e77cd1 100644 +--- a/sound/pci/hda/patch_sigmatel.c ++++ b/sound/pci/hda/patch_sigmatel.c +@@ -4308,6 +4308,8 @@ static int stac_parse_auto_config(struct hda_codec *codec) + if (codec->beep) { + /* IDT/STAC codecs have linear beep tone parameter */ + codec->beep->linear_tone = spec->linear_tone_beep; ++ /* keep power up while beep is enabled */ ++ codec->beep->keep_power_at_enable = 1; + /* if no beep switch is available, make its own one */ + caps = query_amp_caps(codec, nid, HDA_OUTPUT); + if (!(caps & AC_AMPCAP_MUTE)) { +@@ -4448,28 +4450,6 @@ static int stac_suspend(struct hda_codec *codec) + stac_shutup(codec); + return 0; + } +- +-static int stac_check_power_status(struct hda_codec *codec, hda_nid_t nid) +-{ +-#ifdef CONFIG_SND_HDA_INPUT_BEEP +- struct sigmatel_spec *spec = codec->spec; +-#endif +- int ret = snd_hda_gen_check_power_status(codec, nid); +- +-#ifdef CONFIG_SND_HDA_INPUT_BEEP +- if (nid == spec->gen.beep_nid && codec->beep) { +- if (codec->beep->enabled != spec->beep_power_on) { +- spec->beep_power_on = codec->beep->enabled; +- if (spec->beep_power_on) +- snd_hda_power_up_pm(codec); +- else +- snd_hda_power_down_pm(codec); +- } +- ret |= spec->beep_power_on; +- } +-#endif +- return ret; +-} + #else + #define stac_suspend NULL + #endif /* CONFIG_PM */ +@@ -4482,7 +4462,6 @@ static const struct hda_codec_ops stac_patch_ops = { + .unsol_event = snd_hda_jack_unsol_event, + #ifdef CONFIG_PM + .suspend = stac_suspend, +- .check_power_status = stac_check_power_status, + #endif + .reboot_notify = stac_shutup, + }; +-- +2.35.1 + diff --git a/queue-5.10/alsa-hda-hdmi-don-t-skip-notification-handling-durin.patch b/queue-5.10/alsa-hda-hdmi-don-t-skip-notification-handling-durin.patch new file mode 100644 index 00000000000..b94f17d8a49 --- /dev/null +++ b/queue-5.10/alsa-hda-hdmi-don-t-skip-notification-handling-durin.patch @@ -0,0 +1,63 @@ +From de00fc8208ac637deb36e87a3838b7bc81b69097 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 1 Oct 2022 09:48:10 +0200 +Subject: ALSA: hda/hdmi: Don't skip notification handling during PM operation + +From: Takashi Iwai + +[ Upstream commit 5226c7b9784eee215e3914f440b3c2e1764f67a8 ] + +The HDMI driver skips the notification handling from the graphics +driver when the codec driver is being in the PM operation. This +behavior was introduced by the commit eb399d3c99d8 ("ALSA: hda - Skip +ELD notification during PM process"). This skip may cause a problem, +as we may miss the ELD update when the connection/disconnection +happens right at the runtime-PM operation of the audio codec. + +Although this workaround was valid at that time, it's no longer true; +the fix was required just because the ELD update procedure needed to +wake up the audio codec, which had lead to a runtime-resume during a +runtime-suspend. Meanwhile, the ELD update procedure doesn't need a +codec wake up any longer since the commit 788d441a164c ("ALSA: hda - +Use component ops for i915 HDMI/DP audio jack handling"); i.e. there +is no much reason for skipping the notification. + +Let's drop those checks for addressing the missing notification. + +Fixes: 788d441a164c ("ALSA: hda - Use component ops for i915 HDMI/DP audio jack handling") +Reported-by: Brent Lu +Link: https://lore.kernel.org/r/20220927135807.4097052-1-brent.lu@intel.com +Link: https://lore.kernel.org/r/20221001074809.7461-1-tiwai@suse.de +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/pci/hda/patch_hdmi.c | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c +index c3fcf478037f..b1c57c65f6cd 100644 +--- a/sound/pci/hda/patch_hdmi.c ++++ b/sound/pci/hda/patch_hdmi.c +@@ -2684,9 +2684,6 @@ static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) + */ + if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) + return; +- /* ditto during suspend/resume process itself */ +- if (snd_hdac_is_in_pm(&codec->core)) +- return; + + check_presence_and_report(codec, pin_nid, dev_id); + } +@@ -2870,9 +2867,6 @@ static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) + */ + if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) + return; +- /* ditto during suspend/resume process itself */ +- if (snd_hdac_is_in_pm(&codec->core)) +- return; + + snd_hdac_i915_set_bclk(&codec->bus->core); + check_presence_and_report(codec, pin_nid, dev_id); +-- +2.35.1 + diff --git a/queue-5.10/alsa-usb-audio-add-quirk-to-enable-avid-mbox-3-suppo.patch b/queue-5.10/alsa-usb-audio-add-quirk-to-enable-avid-mbox-3-suppo.patch new file mode 100644 index 00000000000..d3837a1ddb5 --- /dev/null +++ b/queue-5.10/alsa-usb-audio-add-quirk-to-enable-avid-mbox-3-suppo.patch @@ -0,0 +1,430 @@ +From db5fbfbb1ae1d24a8543fc2e9552d48c893432f0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 18 Aug 2022 17:14:33 -0300 +Subject: ALSA: usb-audio: Add quirk to enable Avid Mbox 3 support + +From: Conner Knox + +[ Upstream commit b01104fc62b6194c852124f6c6df1c0a5c031fc1 ] + +Add support for Avid Mbox3 USB audio interface at 48kHz + +Signed-off-by: Conner Knox +Link: https://lore.kernel.org/r/20220818201433.16360-1-mbarriolinares@gmail.com +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/quirks-table.h | 76 ++++++++++ + sound/usb/quirks.c | 302 +++++++++++++++++++++++++++++++++++++++ + 2 files changed, 378 insertions(+) + +diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h +index 1ac91c46da3c..a7f065567190 100644 +--- a/sound/usb/quirks-table.h ++++ b/sound/usb/quirks-table.h +@@ -3021,6 +3021,82 @@ AU0828_DEVICE(0x2040, 0x7270, "Hauppauge", "HVR-950Q"), + } + } + }, ++/* DIGIDESIGN MBOX 3 */ ++{ ++ USB_DEVICE(0x0dba, 0x5000), ++ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { ++ .vendor_name = "Digidesign", ++ .product_name = "Mbox 3", ++ .ifnum = QUIRK_ANY_INTERFACE, ++ .type = QUIRK_COMPOSITE, ++ .data = (const struct snd_usb_audio_quirk[]) { ++ { ++ .ifnum = 0, ++ .type = QUIRK_IGNORE_INTERFACE ++ }, ++ { ++ .ifnum = 1, ++ .type = QUIRK_IGNORE_INTERFACE ++ }, ++ { ++ .ifnum = 2, ++ .type = QUIRK_AUDIO_FIXED_ENDPOINT, ++ .data = &(const struct audioformat) { ++ .formats = SNDRV_PCM_FMTBIT_S24_3LE, ++ .channels = 4, ++ .iface = 2, ++ .altsetting = 1, ++ .altset_idx = 1, ++ .attributes = 0x00, ++ .endpoint = 0x01, ++ .ep_attr = USB_ENDPOINT_XFER_ISOC | ++ USB_ENDPOINT_SYNC_ASYNC, ++ .rates = SNDRV_PCM_RATE_48000, ++ .rate_min = 48000, ++ .rate_max = 48000, ++ .nr_rates = 1, ++ .rate_table = (unsigned int[]) { ++ 48000 ++ } ++ } ++ }, ++ { ++ .ifnum = 3, ++ .type = QUIRK_AUDIO_FIXED_ENDPOINT, ++ .data = &(const struct audioformat) { ++ .formats = SNDRV_PCM_FMTBIT_S24_3LE, ++ .channels = 4, ++ .iface = 3, ++ .altsetting = 1, ++ .altset_idx = 1, ++ .endpoint = 0x81, ++ .attributes = 0x00, ++ .ep_attr = USB_ENDPOINT_XFER_ISOC | ++ USB_ENDPOINT_SYNC_ASYNC, ++ .maxpacksize = 0x009c, ++ .rates = SNDRV_PCM_RATE_48000, ++ .rate_min = 48000, ++ .rate_max = 48000, ++ .nr_rates = 1, ++ .rate_table = (unsigned int[]) { ++ 48000 ++ } ++ } ++ }, ++ { ++ .ifnum = 4, ++ .type = QUIRK_MIDI_FIXED_ENDPOINT, ++ .data = &(const struct snd_usb_midi_endpoint_info) { ++ .out_cables = 0x0001, ++ .in_cables = 0x0001 ++ } ++ }, ++ { ++ .ifnum = -1 ++ } ++ } ++ } ++}, + { + /* Tascam US122 MKII - playback-only support */ + USB_DEVICE_VENDOR_SPEC(0x0644, 0x8021), +diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c +index 41f5d8242478..b571a9c9c319 100644 +--- a/sound/usb/quirks.c ++++ b/sound/usb/quirks.c +@@ -1024,6 +1024,304 @@ static int snd_usb_axefx3_boot_quirk(struct usb_device *dev) + return 0; + } + ++static void mbox3_setup_48_24_magic(struct usb_device *dev) ++{ ++ /* The Mbox 3 is "little endian" */ ++ /* max volume is: 0x0000. */ ++ /* min volume is: 0x0080 (shown in little endian form) */ ++ ++ ++ /* Load 48000Hz rate into buffer */ ++ u8 com_buff[4] = {0x80, 0xbb, 0x00, 0x00}; ++ ++ /* Set 48000Hz sample rate */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 0x01, 0x21, 0x0100, 0x0001, &com_buff, 4); //Is this really needed? ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 0x01, 0x21, 0x0100, 0x8101, &com_buff, 4); ++ ++ /* Deactivate Tuner */ ++ /* on = 0x01*/ ++ /* off = 0x00*/ ++ com_buff[0] = 0x00; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 0x01, 0x21, 0x0003, 0x2001, &com_buff, 1); ++ ++ /* Set clock source to Internal (as opposed to S/PDIF) */ ++ com_buff[0] = 0x01; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0100, 0x8001, &com_buff, 1); ++ ++ /* Mute the hardware loopbacks to start the device in a known state. */ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* Analogue input 1 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0110, 0x4001, &com_buff, 2); ++ /* Analogue input 1 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0111, 0x4001, &com_buff, 2); ++ /* Analogue input 2 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0114, 0x4001, &com_buff, 2); ++ /* Analogue input 2 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0115, 0x4001, &com_buff, 2); ++ /* Analogue input 3 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0118, 0x4001, &com_buff, 2); ++ /* Analogue input 3 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0119, 0x4001, &com_buff, 2); ++ /* Analogue input 4 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x011c, 0x4001, &com_buff, 2); ++ /* Analogue input 4 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x011d, 0x4001, &com_buff, 2); ++ ++ /* Set software sends to output */ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x00; ++ /* Analogue software return 1 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0100, 0x4001, &com_buff, 2); ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* Analogue software return 1 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0101, 0x4001, &com_buff, 2); ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* Analogue software return 2 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0104, 0x4001, &com_buff, 2); ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x00; ++ /* Analogue software return 2 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0105, 0x4001, &com_buff, 2); ++ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* Analogue software return 3 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0108, 0x4001, &com_buff, 2); ++ /* Analogue software return 3 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0109, 0x4001, &com_buff, 2); ++ /* Analogue software return 4 left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x010c, 0x4001, &com_buff, 2); ++ /* Analogue software return 4 right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x010d, 0x4001, &com_buff, 2); ++ ++ /* Return to muting sends */ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* Analogue fx return left channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0120, 0x4001, &com_buff, 2); ++ /* Analogue fx return right channel: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0121, 0x4001, &com_buff, 2); ++ ++ /* Analogue software input 1 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0100, 0x4201, &com_buff, 2); ++ /* Analogue software input 2 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0101, 0x4201, &com_buff, 2); ++ /* Analogue software input 3 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0102, 0x4201, &com_buff, 2); ++ /* Analogue software input 4 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0103, 0x4201, &com_buff, 2); ++ /* Analogue input 1 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0104, 0x4201, &com_buff, 2); ++ /* Analogue input 2 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0105, 0x4201, &com_buff, 2); ++ /* Analogue input 3 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0106, 0x4201, &com_buff, 2); ++ /* Analogue input 4 fx send: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0107, 0x4201, &com_buff, 2); ++ ++ /* Toggle allowing host control */ ++ com_buff[0] = 0x02; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 3, 0x21, 0x0000, 0x2001, &com_buff, 1); ++ ++ /* Do not dim fx returns */ ++ com_buff[0] = 0x00; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 3, 0x21, 0x0002, 0x2001, &com_buff, 1); ++ ++ /* Do not set fx returns to mono */ ++ com_buff[0] = 0x00; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 3, 0x21, 0x0001, 0x2001, &com_buff, 1); ++ ++ /* Mute the S/PDIF hardware loopback ++ * same odd volume logic here as above ++ */ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* S/PDIF hardware input 1 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0112, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 1 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0113, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 2 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0116, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 2 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0117, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 3 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x011a, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 3 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x011b, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 4 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x011e, 0x4001, &com_buff, 2); ++ /* S/PDIF hardware input 4 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x011f, 0x4001, &com_buff, 2); ++ /* S/PDIF software return 1 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0102, 0x4001, &com_buff, 2); ++ /* S/PDIF software return 1 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0103, 0x4001, &com_buff, 2); ++ /* S/PDIF software return 2 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0106, 0x4001, &com_buff, 2); ++ /* S/PDIF software return 2 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0107, 0x4001, &com_buff, 2); ++ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x00; ++ /* S/PDIF software return 3 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x010a, 0x4001, &com_buff, 2); ++ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* S/PDIF software return 3 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x010b, 0x4001, &com_buff, 2); ++ /* S/PDIF software return 4 left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x010e, 0x4001, &com_buff, 2); ++ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x00; ++ /* S/PDIF software return 4 right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x010f, 0x4001, &com_buff, 2); ++ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x80; ++ /* S/PDIF fx returns left channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0122, 0x4001, &com_buff, 2); ++ /* S/PDIF fx returns right channel */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0123, 0x4001, &com_buff, 2); ++ ++ /* Set the dropdown "Effect" to the first option */ ++ /* Room1 = 0x00 */ ++ /* Room2 = 0x01 */ ++ /* Room3 = 0x02 */ ++ /* Hall 1 = 0x03 */ ++ /* Hall 2 = 0x04 */ ++ /* Plate = 0x05 */ ++ /* Delay = 0x06 */ ++ /* Echo = 0x07 */ ++ com_buff[0] = 0x00; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0200, 0x4301, &com_buff, 1); /* max is 0xff */ ++ /* min is 0x00 */ ++ ++ ++ /* Set the effect duration to 0 */ ++ /* max is 0xffff */ ++ /* min is 0x0000 */ ++ com_buff[0] = 0x00; ++ com_buff[1] = 0x00; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0400, 0x4301, &com_buff, 2); ++ ++ /* Set the effect volume and feedback to 0 */ ++ /* max is 0xff */ ++ /* min is 0x00 */ ++ com_buff[0] = 0x00; ++ /* feedback: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0500, 0x4301, &com_buff, 1); ++ /* volume: */ ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 1, 0x21, 0x0300, 0x4301, &com_buff, 1); ++ ++ /* Set soft button hold duration */ ++ /* 0x03 = 250ms */ ++ /* 0x05 = 500ms DEFAULT */ ++ /* 0x08 = 750ms */ ++ /* 0x0a = 1sec */ ++ com_buff[0] = 0x05; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 3, 0x21, 0x0005, 0x2001, &com_buff, 1); ++ ++ /* Use dim LEDs for button of state */ ++ com_buff[0] = 0x00; ++ snd_usb_ctl_msg(dev, usb_sndctrlpipe(dev, 0), ++ 3, 0x21, 0x0004, 0x2001, &com_buff, 1); ++} ++ ++#define MBOX3_DESCRIPTOR_SIZE 464 ++ ++static int snd_usb_mbox3_boot_quirk(struct usb_device *dev) ++{ ++ struct usb_host_config *config = dev->actconfig; ++ int err; ++ int descriptor_size; ++ ++ descriptor_size = le16_to_cpu(get_cfg_desc(config)->wTotalLength); ++ ++ if (descriptor_size != MBOX3_DESCRIPTOR_SIZE) { ++ dev_err(&dev->dev, "Invalid descriptor size=%d.\n", descriptor_size); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&dev->dev, "device initialised!\n"); ++ ++ err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, ++ &dev->descriptor, sizeof(dev->descriptor)); ++ config = dev->actconfig; ++ if (err < 0) ++ dev_dbg(&dev->dev, "error usb_get_descriptor: %d\n", err); ++ ++ err = usb_reset_configuration(dev); ++ if (err < 0) ++ dev_dbg(&dev->dev, "error usb_reset_configuration: %d\n", err); ++ dev_dbg(&dev->dev, "mbox3_boot: new boot length = %d\n", ++ le16_to_cpu(get_cfg_desc(config)->wTotalLength)); ++ ++ mbox3_setup_48_24_magic(dev); ++ dev_info(&dev->dev, "Digidesign Mbox 3: 24bit 48kHz"); ++ ++ return 0; /* Successful boot */ ++} + + #define MICROBOOK_BUF_SIZE 128 + +@@ -1344,6 +1642,10 @@ int snd_usb_apply_boot_quirk(struct usb_device *dev, + case USB_ID(0x0dba, 0x3000): + /* Digidesign Mbox 2 */ + return snd_usb_mbox2_boot_quirk(dev); ++ case USB_ID(0x0dba, 0x5000): ++ /* Digidesign Mbox 3 */ ++ return snd_usb_mbox3_boot_quirk(dev); ++ + + case USB_ID(0x1235, 0x0010): /* Focusrite Novation Saffire 6 USB */ + case USB_ID(0x1235, 0x0018): /* Focusrite Novation Twitch */ +-- +2.35.1 + diff --git a/queue-5.10/arm-9244-1-dump-fix-wrong-pg_level-in-walk_pmd.patch b/queue-5.10/arm-9244-1-dump-fix-wrong-pg_level-in-walk_pmd.patch new file mode 100644 index 00000000000..37787cbe6b9 --- /dev/null +++ b/queue-5.10/arm-9244-1-dump-fix-wrong-pg_level-in-walk_pmd.patch @@ -0,0 +1,36 @@ +From da071bbb8a8dd8e231f7030cc4c3af1a9aa20c0c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 05:25:51 +0100 +Subject: ARM: 9244/1: dump: Fix wrong pg_level in walk_pmd() + +From: Wang Kefeng + +[ Upstream commit 2ccd19b3ffac07cc7e75a2bd1ed779728bb67197 ] + +After ARM supports p4d page tables, the pg_level for note_page() +in walk_pmd() should be 4, not 3, fix it. + +Fixes: 84e6ffb2c49c ("arm: add support for folded p4d page tables") +Signed-off-by: Kefeng Wang +Signed-off-by: Russell King (Oracle) +Signed-off-by: Sasha Levin +--- + arch/arm/mm/dump.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c +index c18d23a5e5f1..9b9023a92d46 100644 +--- a/arch/arm/mm/dump.c ++++ b/arch/arm/mm/dump.c +@@ -342,7 +342,7 @@ static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start) + addr = start + i * PMD_SIZE; + domain = get_domain_name(pmd); + if (pmd_none(*pmd) || pmd_large(*pmd) || !pmd_present(*pmd)) +- note_page(st, addr, 3, pmd_val(*pmd), domain); ++ note_page(st, addr, 4, pmd_val(*pmd), domain); + else + walk_pte(st, pmd, addr, domain); + +-- +2.35.1 + diff --git a/queue-5.10/arm-9247-1-mm-set-readonly-for-mt_memory_ro-with-arm.patch b/queue-5.10/arm-9247-1-mm-set-readonly-for-mt_memory_ro-with-arm.patch new file mode 100644 index 00000000000..0a12f89177a --- /dev/null +++ b/queue-5.10/arm-9247-1-mm-set-readonly-for-mt_memory_ro-with-arm.patch @@ -0,0 +1,46 @@ +From add7bf9658b3cfb8a917dbe49b4b2cb6c8a4c136 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 12:10:49 +0100 +Subject: ARM: 9247/1: mm: set readonly for MT_MEMORY_RO with ARM_LPAE + +From: Wang Kefeng + +[ Upstream commit 14ca1a4690750bb54e1049e49f3140ef48958a6e ] + +MT_MEMORY_RO is introduced by commit 598f0a99fa8a ("ARM: 9210/1: +Mark the FDT_FIXED sections as shareable"), which is a readonly +memory type for FDT area, but there are some different between +ARM_LPAE and non-ARM_LPAE, we need to setup PMD_SECT_AP2 and +L_PMD_SECT_RDONLY for MT_MEMORY_RO when ARM_LAPE enabled. + +non-ARM_LPAE 0xff800000-0xffa00000 2M PGD KERNEL ro NX SHD +ARM_LPAE 0xff800000-0xffc00000 4M PMD RW NX SHD +ARM_LPAE+fix 0xff800000-0xffc00000 4M PMD ro NX SHD + +Fixes: 598f0a99fa8a ("ARM: 9210/1: Mark the FDT_FIXED sections as shareable") +Signed-off-by: Kefeng Wang +Signed-off-by: Russell King (Oracle) +Signed-off-by: Sasha Levin +--- + arch/arm/mm/mmu.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c +index 86f213f1b44b..0d0c3bf23914 100644 +--- a/arch/arm/mm/mmu.c ++++ b/arch/arm/mm/mmu.c +@@ -300,7 +300,11 @@ static struct mem_type mem_types[] __ro_after_init = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_XN | L_PTE_RDONLY, + .prot_l1 = PMD_TYPE_TABLE, ++#ifdef CONFIG_ARM_LPAE ++ .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2, ++#else + .prot_sect = PMD_TYPE_SECT, ++#endif + .domain = DOMAIN_KERNEL, + }, + [MT_ROM] = { +-- +2.35.1 + diff --git a/queue-5.10/arm-decompressor-include-.data.rel.ro.local.patch b/queue-5.10/arm-decompressor-include-.data.rel.ro.local.patch new file mode 100644 index 00000000000..6964e7eeec0 --- /dev/null +++ b/queue-5.10/arm-decompressor-include-.data.rel.ro.local.patch @@ -0,0 +1,50 @@ +From ac78531ae562e537148a7b26287c383d6cdc2dc3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 15:41:03 -0700 +Subject: ARM: decompressor: Include .data.rel.ro.local + +From: Kees Cook + +[ Upstream commit 1b64daf413acd86c2c13f5443f6b4ef3690c8061 ] + +The .data.rel.ro.local section has the same semantics as .data.rel.ro +here, so include it in the .rodata section of the decompressor. +Additionally since the .printk_index section isn't usable outside of +the core kernel, discard it in the decompressor. Avoids these warnings: + +arm-linux-gnueabi-ld: warning: orphan section `.data.rel.ro.local' from `arch/arm/boot/compressed/fdt_rw.o' being placed in section `.data.rel.ro.local' +arm-linux-gnueabi-ld: warning: orphan section `.printk_index' from `arch/arm/boot/compressed/fdt_rw.o' being placed in section `.printk_index' + +Reported-by: kernel test robot +Link: https://lore.kernel.org/linux-mm/202209080545.qMIVj7YM-lkp@intel.com +Cc: Russell King +Cc: linux-arm-kernel@lists.infradead.org +Signed-off-by: Kees Cook +Signed-off-by: Sasha Levin +--- + arch/arm/boot/compressed/vmlinux.lds.S | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S +index 1bcb68ac4b01..3fcb3e62dc56 100644 +--- a/arch/arm/boot/compressed/vmlinux.lds.S ++++ b/arch/arm/boot/compressed/vmlinux.lds.S +@@ -23,6 +23,7 @@ SECTIONS + *(.ARM.extab*) + *(.note.*) + *(.rel.*) ++ *(.printk_index) + /* + * Discard any r/w data - this produces a link error if we have any, + * which is required for PIC decompression. Local data generates +@@ -57,6 +58,7 @@ SECTIONS + *(.rodata) + *(.rodata.*) + *(.data.rel.ro) ++ *(.data.rel.ro.*) + } + .piggydata : { + *(.piggydata) +-- +2.35.1 + diff --git a/queue-5.10/arm-drop-cmdline_-dependency-on-atags.patch b/queue-5.10/arm-drop-cmdline_-dependency-on-atags.patch new file mode 100644 index 00000000000..964ad78a1b3 --- /dev/null +++ b/queue-5.10/arm-drop-cmdline_-dependency-on-atags.patch @@ -0,0 +1,45 @@ +From c9c41ee64ab806d92db5d88908dd6938c75d30d6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 27 Sep 2022 15:28:26 +0200 +Subject: ARM: Drop CMDLINE_* dependency on ATAGS + +From: Geert Uytterhoeven + +[ Upstream commit 136f4b1ec7c962ee37a787e095fd37b058d72bd3 ] + +On arm32, the configuration options to specify the kernel command line +type depend on ATAGS. However, the actual CMDLINE cofiguration option +does not depend on ATAGS, and the code that handles this is not specific +to ATAGS (see drivers/of/fdt.c:early_init_dt_scan_chosen()). + +Hence users who desire to override the kernel command line on arm32 must +enable support for ATAGS, even on a pure-DT system. Other architectures +(arm64, loongarch, microblaze, nios2, powerpc, and riscv) do not impose +such a restriction. + +Hence drop the dependency on ATAGS. + +Fixes: bd51e2f595580fb6 ("ARM: 7506/1: allow for ATAGS to be configured out when DT support is selected") +Signed-off-by: Geert Uytterhoeven +Acked-by: Ard Biesheuvel +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index b587ecc6f949..985ab0b091a6 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1791,7 +1791,6 @@ config CMDLINE + choice + prompt "Kernel command line type" if CMDLINE != "" + default CMDLINE_FROM_BOOTLOADER +- depends on ATAGS + + config CMDLINE_FROM_BOOTLOADER + bool "Use bootloader kernel arguments if available" +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-exynos-correct-s5k6a3-reset-polarity-on-mida.patch b/queue-5.10/arm-dts-exynos-correct-s5k6a3-reset-polarity-on-mida.patch new file mode 100644 index 00000000000..91b663586cc --- /dev/null +++ b/queue-5.10/arm-dts-exynos-correct-s5k6a3-reset-polarity-on-mida.patch @@ -0,0 +1,42 @@ +From 07de551f669e558ab15a10190c77be5e61e0c531 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 12:43:53 +0200 +Subject: ARM: dts: exynos: correct s5k6a3 reset polarity on Midas family + +From: Dmitry Torokhov + +[ Upstream commit 3ba2d4bb9592bf7a6a3fe3dbe711ecfc3d004bab ] + +According to s5k6a3 driver code, the reset line for the chip appears to +be active low. This also matches the typical polarity of reset lines in +general. Let's fix it up as having correct polarity in DTS is important +when the driver will be switched over to gpiod API. + +Fixes: b4fec64758ab ("ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board") +Signed-off-by: Dmitry Torokhov +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Linus Walleij +Link: https://lore.kernel.org/r/20220913164104.203957-1-dmitry.torokhov@gmail.com +Link: https://lore.kernel.org/r/20220926104354.118578-2-krzysztof.kozlowski@linaro.org' +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/exynos4412-midas.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi +index 06450066b178..255a13666edc 100644 +--- a/arch/arm/boot/dts/exynos4412-midas.dtsi ++++ b/arch/arm/boot/dts/exynos4412-midas.dtsi +@@ -588,7 +588,7 @@ + clocks = <&camera 1>; + clock-names = "extclk"; + samsung,camclk-out = <1>; +- gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; + + port { + is_s5k6a3_ep: endpoint { +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-exynos-fix-polarity-of-vbus-gpio-of-origen.patch b/queue-5.10/arm-dts-exynos-fix-polarity-of-vbus-gpio-of-origen.patch new file mode 100644 index 00000000000..74603356ad5 --- /dev/null +++ b/queue-5.10/arm-dts-exynos-fix-polarity-of-vbus-gpio-of-origen.patch @@ -0,0 +1,39 @@ +From 9a6ac08c76c8c8230936ecb1ebd4aca4dbc638ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 27 Sep 2022 15:05:03 -0700 +Subject: ARM: dts: exynos: fix polarity of VBUS GPIO of Origen + +From: Dmitry Torokhov + +[ Upstream commit a08137bd1e0a7ce951dce9ce4a83e39d379b6e1b ] + +EHCI Oxynos (drivers/usb/host/ehci-exynos.c) drives VBUS GPIO high when +trying to power up the bus, therefore the GPIO in DTS must be marked as +"active high". This will be important when EHCI driver is converted to +gpiod API that respects declared polarities. + +Fixes: 4e8991def565 ("ARM: dts: exynos: Enable AX88760 USB hub on Origen board") +Signed-off-by: Dmitry Torokhov +Link: https://lore.kernel.org/r/20220927220504.3744878-1-dmitry.torokhov@gmail.com +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/exynos4412-origen.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts +index c2e793b69e7d..e2d76ea4404e 100644 +--- a/arch/arm/boot/dts/exynos4412-origen.dts ++++ b/arch/arm/boot/dts/exynos4412-origen.dts +@@ -95,7 +95,7 @@ + }; + + &ehci { +- samsung,vbus-gpio = <&gpx3 5 1>; ++ samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; + phy-names = "hsic0", "hsic1"; +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx6dl-add-missing-properties-for-sram.patch b/queue-5.10/arm-dts-imx6dl-add-missing-properties-for-sram.patch new file mode 100644 index 00000000000..441b154ed19 --- /dev/null +++ b/queue-5.10/arm-dts-imx6dl-add-missing-properties-for-sram.patch @@ -0,0 +1,38 @@ +From e2dc8f6c44349d86578d1cd437a761aac5b25068 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 07:53:32 +0200 +Subject: ARM: dts: imx6dl: add missing properties for sram + +From: Alexander Stein + +[ Upstream commit f5848b95633d598bacf0500e0108dc5961af88c0 ] + +All 3 properties are required by sram.yaml. Fixes the dtbs_check warning: +sram@900000: '#address-cells' is a required property +sram@900000: '#size-cells' is a required property +sram@900000: 'ranges' is a required property + +Signed-off-by: Alexander Stein +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6dl.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi +index fdd81fdc3f35..cd3183c36488 100644 +--- a/arch/arm/boot/dts/imx6dl.dtsi ++++ b/arch/arm/boot/dts/imx6dl.dtsi +@@ -84,6 +84,9 @@ + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; ++ ranges = <0 0x00900000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx6q-add-missing-properties-for-sram.patch b/queue-5.10/arm-dts-imx6q-add-missing-properties-for-sram.patch new file mode 100644 index 00000000000..7541b077977 --- /dev/null +++ b/queue-5.10/arm-dts-imx6q-add-missing-properties-for-sram.patch @@ -0,0 +1,38 @@ +From d9050f235a30871daa927399fbaa7c5aec1837ac Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 07:53:31 +0200 +Subject: ARM: dts: imx6q: add missing properties for sram + +From: Alexander Stein + +[ Upstream commit b11d083c5dcec7c42fe982c854706d404ddd3a5f ] + +All 3 properties are required by sram.yaml. Fixes the dtbs_check warning: +sram@900000: '#address-cells' is a required property +sram@900000: '#size-cells' is a required property +sram@900000: 'ranges' is a required property + +Signed-off-by: Alexander Stein +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6q.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi +index 5277e3903291..afec1677e6ba 100644 +--- a/arch/arm/boot/dts/imx6q.dtsi ++++ b/arch/arm/boot/dts/imx6q.dtsi +@@ -163,6 +163,9 @@ + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x40000>; ++ ranges = <0 0x00900000 0x40000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx6qp-add-missing-properties-for-sram.patch b/queue-5.10/arm-dts-imx6qp-add-missing-properties-for-sram.patch new file mode 100644 index 00000000000..f8968a46268 --- /dev/null +++ b/queue-5.10/arm-dts-imx6qp-add-missing-properties-for-sram.patch @@ -0,0 +1,47 @@ +From e5b93de4b5c76f0401004756f6239adb8410ada6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 07:53:33 +0200 +Subject: ARM: dts: imx6qp: add missing properties for sram + +From: Alexander Stein + +[ Upstream commit 088fe5237435ee2f7ed4450519b2ef58b94c832f ] + +All 3 properties are required by sram.yaml. Fixes the dtbs_check warning: +sram@940000: '#address-cells' is a required property +sram@940000: '#size-cells' is a required property +sram@940000: 'ranges' is a required property + +Signed-off-by: Alexander Stein +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6qp.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi +index b310f13a53f2..4d23c92aa8a6 100644 +--- a/arch/arm/boot/dts/imx6qp.dtsi ++++ b/arch/arm/boot/dts/imx6qp.dtsi +@@ -9,12 +9,18 @@ + ocram2: sram@940000 { + compatible = "mmio-sram"; + reg = <0x00940000 0x20000>; ++ ranges = <0 0x00940000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocram3: sram@960000 { + compatible = "mmio-sram"; + reg = <0x00960000 0x20000>; ++ ranges = <0 0x00960000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx6sl-add-missing-properties-for-sram.patch b/queue-5.10/arm-dts-imx6sl-add-missing-properties-for-sram.patch new file mode 100644 index 00000000000..257beb94c4d --- /dev/null +++ b/queue-5.10/arm-dts-imx6sl-add-missing-properties-for-sram.patch @@ -0,0 +1,38 @@ +From 86225d41186d7bc9a05df721d3e16986b3b7bbdf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 07:53:34 +0200 +Subject: ARM: dts: imx6sl: add missing properties for sram + +From: Alexander Stein + +[ Upstream commit 60c9213a1d9941a8b33db570796c3f9be8984974 ] + +All 3 properties are required by sram.yaml. Fixes the dtbs_check warning: +sram@900000: '#address-cells' is a required property +sram@900000: '#size-cells' is a required property +sram@900000: 'ranges' is a required property + +Signed-off-by: Alexander Stein +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6sl.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi +index 91a8c54d5e11..c184a6d5bc42 100644 +--- a/arch/arm/boot/dts/imx6sl.dtsi ++++ b/arch/arm/boot/dts/imx6sl.dtsi +@@ -114,6 +114,9 @@ + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; ++ ranges = <0 0x00900000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx6sll-add-missing-properties-for-sram.patch b/queue-5.10/arm-dts-imx6sll-add-missing-properties-for-sram.patch new file mode 100644 index 00000000000..ca5beb8d725 --- /dev/null +++ b/queue-5.10/arm-dts-imx6sll-add-missing-properties-for-sram.patch @@ -0,0 +1,38 @@ +From 75975feee39c54a11921c99fe173b372a72cff34 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 07:53:35 +0200 +Subject: ARM: dts: imx6sll: add missing properties for sram + +From: Alexander Stein + +[ Upstream commit 7492a83ed9b7a151e2dd11d64b06da7a7f0fa7f9 ] + +All 3 properties are required by sram.yaml. Fixes the dtbs_check warning: +sram@900000: '#address-cells' is a required property +sram@900000: '#size-cells' is a required property +sram@900000: 'ranges' is a required property + +Signed-off-by: Alexander Stein +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6sll.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi +index 0b622201a1f3..bf5b262b91f9 100644 +--- a/arch/arm/boot/dts/imx6sll.dtsi ++++ b/arch/arm/boot/dts/imx6sll.dtsi +@@ -115,6 +115,9 @@ + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; ++ ranges = <0 0x00900000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + }; + + intc: interrupt-controller@a01000 { +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx6sx-add-missing-properties-for-sram.patch b/queue-5.10/arm-dts-imx6sx-add-missing-properties-for-sram.patch new file mode 100644 index 00000000000..a21dba97eca --- /dev/null +++ b/queue-5.10/arm-dts-imx6sx-add-missing-properties-for-sram.patch @@ -0,0 +1,47 @@ +From 70b0a93670dfd0536d85f5382413be11544763d8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 07:53:36 +0200 +Subject: ARM: dts: imx6sx: add missing properties for sram + +From: Alexander Stein + +[ Upstream commit 415432c008b2bce8138841356ba444631cabaa50 ] + +All 3 properties are required by sram.yaml. Fixes the dtbs_check warning: +sram@900000: '#address-cells' is a required property +sram@900000: '#size-cells' is a required property +sram@900000: 'ranges' is a required property + +Signed-off-by: Alexander Stein +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi +index dfdca1804f9f..c399919943c3 100644 +--- a/arch/arm/boot/dts/imx6sx.dtsi ++++ b/arch/arm/boot/dts/imx6sx.dtsi +@@ -161,12 +161,18 @@ + ocram_s: sram@8f8000 { + compatible = "mmio-sram"; + reg = <0x008f8000 0x4000>; ++ ranges = <0 0x008f8000 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; ++ ranges = <0 0x00900000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch b/queue-5.10/arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch new file mode 100644 index 00000000000..4ad97ad527a --- /dev/null +++ b/queue-5.10/arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch @@ -0,0 +1,60 @@ +From 3c5144d6b3fd61ac5ac871ef21e0b0fb77428dc0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Jul 2022 18:16:22 +0800 +Subject: ARM: dts: imx7d-sdb: config the max pressure for tsc2046 + +From: Haibo Chen + +[ Upstream commit e7c4ebe2f9cd68588eb24ba4ed122e696e2d5272 ] + +Use the general touchscreen method to config the max pressure for +touch tsc2046(data sheet suggest 8 bit pressure), otherwise, for +ABS_PRESSURE, when config the same max and min value, weston will +meet the following issue, + +[17:19:39.183] event1 - ADS7846 Touchscreen: is tagged by udev as: Touchscreen +[17:19:39.183] event1 - ADS7846 Touchscreen: kernel bug: device has min == max on ABS_PRESSURE +[17:19:39.183] event1 - ADS7846 Touchscreen: was rejected +[17:19:39.183] event1 - not using input device '/dev/input/event1' + +This will then cause the APP weston-touch-calibrator can't list touch devices. + +root@imx6ul7d:~# weston-touch-calibrator +could not load cursor 'dnd-move' +could not load cursor 'dnd-copy' +could not load cursor 'dnd-none' +No devices listed. + +And accroding to binding Doc, "ti,x-max", "ti,y-max", "ti,pressure-max" +belong to the deprecated properties, so remove them. Also for "ti,x-min", +"ti,y-min", "ti,x-plate-ohms", the value set in dts equal to the default +value in driver, so are redundant, also remove here. + +Signed-off-by: Haibo Chen +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx7d-sdb.dts | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts +index 6823b9f1a2a3..6d562ebe9029 100644 +--- a/arch/arm/boot/dts/imx7d-sdb.dts ++++ b/arch/arm/boot/dts/imx7d-sdb.dts +@@ -199,12 +199,7 @@ + interrupt-parent = <&gpio2>; + interrupts = <29 0>; + pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; +- ti,x-min = /bits/ 16 <0>; +- ti,x-max = /bits/ 16 <0>; +- ti,y-min = /bits/ 16 <0>; +- ti,y-max = /bits/ 16 <0>; +- ti,pressure-max = /bits/ 16 <0>; +- ti,x-plate-ohms = /bits/ 16 <400>; ++ touchscreen-max-pressure = <255>; + wakeup-source; + }; + }; +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-kirkwood-lsxl-fix-serial-line.patch b/queue-5.10/arm-dts-kirkwood-lsxl-fix-serial-line.patch new file mode 100644 index 00000000000..dd9f7ecb0cd --- /dev/null +++ b/queue-5.10/arm-dts-kirkwood-lsxl-fix-serial-line.patch @@ -0,0 +1,50 @@ +From aebd6142cc7e1dc26b2693466d327df938ab57c5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Aug 2022 02:10:24 +0200 +Subject: ARM: dts: kirkwood: lsxl: fix serial line + +From: Michael Walle + +[ Upstream commit 04eabc6ac10fda9424606d9a7ab6ab9a5d95350a ] + +Commit 327e15428977 ("ARM: dts: kirkwood: consolidate common pinctrl +settings") unknowingly broke the serial output on this board. Before +this commit, the pinmux was still configured by the bootloader and the +kernel didn't reconfigured it again. This was an oversight by the +initial board support where the pinmux for the serial line was never +configured by the kernel. But with this commit, the serial line will be +reconfigured to the wrong pins. This is especially confusing, because +the output still works, but the input doesn't. Presumingly, the input is +reconfigured to MPP10, but the output is connected to both MPP11 and +MPP5. + +Override the pinmux in the board device tree. + +Fixes: 327e15428977 ("ARM: dts: kirkwood: consolidate common pinctrl settings") +Signed-off-by: Michael Walle +Reviewed-by: Andrew Lunn +Signed-off-by: Gregory CLEMENT +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/kirkwood-lsxl.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi +index 7b151acb9984..321a40a98ed2 100644 +--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi ++++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi +@@ -10,6 +10,11 @@ + + ocp@f1000000 { + pinctrl: pin-controller@10000 { ++ /* Non-default UART pins */ ++ pmx_uart0: pmx-uart0 { ++ marvell,pins = "mpp4", "mpp5"; ++ }; ++ + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp10"; + marvell,function = "gpo"; +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-kirkwood-lsxl-remove-first-ethernet-port.patch b/queue-5.10/arm-dts-kirkwood-lsxl-remove-first-ethernet-port.patch new file mode 100644 index 00000000000..f6cef7a9c4c --- /dev/null +++ b/queue-5.10/arm-dts-kirkwood-lsxl-remove-first-ethernet-port.patch @@ -0,0 +1,53 @@ +From 34bc10827d7be3f3e7892f52246d4bbef47d62a3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Aug 2022 02:10:25 +0200 +Subject: ARM: dts: kirkwood: lsxl: remove first ethernet port + +From: Michael Walle + +[ Upstream commit 2d528eda7c96ce5c70f895854ecd5684bd5d80b9 ] + +Both the Linkstation LS-CHLv2 and the LS-XHL have only one ethernet +port. This has always been wrong, i.e. the board code used to set up +both ports, but the driver will play nice and return -ENODEV if the +assiciated PHY is not found. Nevertheless, it is wrong. Remove it. + +Fixes: 876e23333511 ("ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes") +Signed-off-by: Michael Walle +Reviewed-by: Andrew Lunn +Signed-off-by: Gregory CLEMENT +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/kirkwood-lsxl.dtsi | 11 ----------- + 1 file changed, 11 deletions(-) + +diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi +index 321a40a98ed2..88b70ba1c8fe 100644 +--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi ++++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi +@@ -218,22 +218,11 @@ + &mdio { + status = "okay"; + +- ethphy0: ethernet-phy@0 { +- reg = <0>; +- }; +- + ethphy1: ethernet-phy@8 { + reg = <8>; + }; + }; + +-ð0 { +- status = "okay"; +- ethernet0-port@0 { +- phy-handle = <ðphy0>; +- }; +-}; +- + ð1 { + status = "okay"; + ethernet1-port@0 { +-- +2.35.1 + diff --git a/queue-5.10/arm-dts-turris-omnia-fix-mpp26-pin-name-and-comment.patch b/queue-5.10/arm-dts-turris-omnia-fix-mpp26-pin-name-and-comment.patch new file mode 100644 index 00000000000..cf508421334 --- /dev/null +++ b/queue-5.10/arm-dts-turris-omnia-fix-mpp26-pin-name-and-comment.patch @@ -0,0 +1,53 @@ +From b249076dd0d28c20919f1bea909124d696412bcf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Jul 2022 14:56:10 +0200 +Subject: ARM: dts: turris-omnia: Fix mpp26 pin name and comment +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marek Behún + +[ Upstream commit 49e93898f0dc177e645c22d0664813567fd9ec00 ] + +There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, +which is routed to CN11 pin header, is documented as SPI CS1, but +MPP[26] pin does not support this function. Instead it controls chip +select 2 if in "spi0" mode. + +Fix the name of the pin node in pinctrl node and fix the comment in SPI +node. + +Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") +Signed-off-by: Marek Behún +Signed-off-by: Gregory CLEMENT +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts +index fde4c302f08e..92e08486ec81 100644 +--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts ++++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts +@@ -307,7 +307,7 @@ + marvell,function = "spi0"; + }; + +- spi0cs1_pins: spi0cs1-pins { ++ spi0cs2_pins: spi0cs2-pins { + marvell,pins = "mpp26"; + marvell,function = "spi0"; + }; +@@ -342,7 +342,7 @@ + }; + }; + +- /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ ++ /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ + }; + + &uart0 { +-- +2.35.1 + diff --git a/queue-5.10/arm-orion-fix-include-path.patch b/queue-5.10/arm-orion-fix-include-path.patch new file mode 100644 index 00000000000..737887eb4c3 --- /dev/null +++ b/queue-5.10/arm-orion-fix-include-path.patch @@ -0,0 +1,39 @@ +From 552f40f6f625268de16d6aa070d515afd167d003 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 23 Sep 2022 21:55:50 +0200 +Subject: ARM: orion: fix include path + +From: Arnd Bergmann + +[ Upstream commit 63872304bdb3decd5454f4dd210c25395278ed13 ] + +Now that CONFIG_ARCH_MULTIPLATFORM can be disabled anywhere, +there is a build failure for plat-orion: + +arch/arm/plat-orion/irq.c:19:10: fatal error: plat/irq.h: No such file or directory + +Make the include path unconditional. + +Reported-by: kernel test robot +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/plat-orion/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile +index 4e3f25de13c1..830b0be038c6 100644 +--- a/arch/arm/plat-orion/Makefile ++++ b/arch/arm/plat-orion/Makefile +@@ -2,7 +2,7 @@ + # + # Makefile for the linux kernel. + # +-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include ++ccflags-y := -I$(srctree)/$(src)/include + + orion-gpio-$(CONFIG_GPIOLIB) += gpio.o + obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-imx8mq-librem5-add-bq25895-as-max17055-s-p.patch b/queue-5.10/arm64-dts-imx8mq-librem5-add-bq25895-as-max17055-s-p.patch new file mode 100644 index 00000000000..9f8b133c947 --- /dev/null +++ b/queue-5.10/arm64-dts-imx8mq-librem5-add-bq25895-as-max17055-s-p.patch @@ -0,0 +1,36 @@ +From db4a90eea827c579b681491690b59c256dd62d72 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 10:42:13 +0200 +Subject: arm64: dts: imx8mq-librem5: Add bq25895 as max17055's power supply + +From: Sebastian Krzyszkowiak + +[ Upstream commit 6effe295e1a87408033c29dbcea9d5a5c8b937d5 ] + +This allows the userspace to notice that there's not enough +current provided to charge the battery, and also fixes issues +with 0% SOC values being considered invalid. + +Signed-off-by: Sebastian Krzyszkowiak +Signed-off-by: Martin Kepplinger +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +index e3c6d1272198..325ea100969a 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +@@ -899,6 +899,7 @@ + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gauge>; ++ power-supplies = <&bq25895>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + maxim,rsns-microohm = <5000>; +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-qcom-fix-ipq8074-pcie-phy-nodes.patch b/queue-5.10/arm64-dts-qcom-fix-ipq8074-pcie-phy-nodes.patch new file mode 100644 index 00000000000..6e4d54e7acb --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-fix-ipq8074-pcie-phy-nodes.patch @@ -0,0 +1,105 @@ +From 80763571c2d254f14c943d127dc4f57de7c3d7c0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Sep 2021 11:42:51 +0800 +Subject: arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes + +From: Shawn Guo + +[ Upstream commit 942bcd33ed455ad40b71a59901bd926bbf4a500e ] + +IPQ8074 PCIe PHY nodes are broken in the many ways: + +- '#address-cells', '#size-cells' and 'ranges' are missing. +- Child phy/lane node is missing, and the child properties like + '#phy-cells' and 'clocks' are mistakenly put into parent node. +- The clocks properties for parent node are missing. + +Fix them to get the nodes comply with the bindings schema. + +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org +Stable-dep-of: ed22cc93abae ("arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size") +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++------ + 1 file changed, 36 insertions(+), 10 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index 99e2488b92dc..e8b3ecb591dd 100644 +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -167,34 +167,60 @@ + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + }; + +- pcie_phy0: phy@86000 { ++ pcie_qmp0: phy@86000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x00086000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy0_pipe_clk"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; + ++ clocks = <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>; ++ clock-names = "aux", "cfg_ahb"; + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; ++ ++ pcie_phy0: phy@86200 { ++ reg = <0x86200 0x16c>, ++ <0x86400 0x200>, ++ <0x86800 0x4f4>; ++ #phy-cells = <0>; ++ #clock-cells = <0>; ++ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "pipe0"; ++ clock-output-names = "pcie_0_pipe_clk"; ++ }; + }; + +- pcie_phy1: phy@8e000 { ++ pcie_qmp1: phy@8e000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x0008e000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy1_pipe_clk"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; + ++ clocks = <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>; ++ clock-names = "aux", "cfg_ahb"; + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; ++ ++ pcie_phy1: phy@8e200 { ++ reg = <0x8e200 0x16c>, ++ <0x8e400 0x200>, ++ <0x8e800 0x4f4>; ++ #phy-cells = <0>; ++ #clock-cells = <0>; ++ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "pipe0"; ++ clock-output-names = "pcie_1_pipe_clk"; ++ }; + }; + + tlmm: pinctrl@1000000 { +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-qcom-ipq8074-fix-pcie-phy-serdes-size.patch b/queue-5.10/arm64-dts-qcom-ipq8074-fix-pcie-phy-serdes-size.patch new file mode 100644 index 00000000000..81f5a298d0f --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-ipq8074-fix-pcie-phy-serdes-size.patch @@ -0,0 +1,47 @@ +From 33e91a10eb2ab48d69ac64438186f8d86de96d16 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 Sep 2022 16:34:30 +0200 +Subject: arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size + +From: Johan Hovold + +[ Upstream commit ed22cc93abae68f9d3fc4957c20a1d902cf28882 ] + +The size of the PCIe PHY serdes register region is 0x1c4 and the +corresponding 'reg' property should specifically not include the +adjacent regions that are defined in the child node (e.g. tx and rx). + +Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") +Signed-off-by: Johan Hovold +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220915143431.19842-1-johan+linaro@kernel.org +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +index e8b3ecb591dd..ebf9ad93656d 100644 +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -169,7 +169,7 @@ + + pcie_qmp0: phy@86000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x00086000 0x1000>; ++ reg = <0x00086000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +@@ -197,7 +197,7 @@ + + pcie_qmp1: phy@8e000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x0008e000 0x1000>; ++ reg = <0x0008e000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch b/queue-5.10/arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch new file mode 100644 index 00000000000..59d3004e869 --- /dev/null +++ b/queue-5.10/arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch @@ -0,0 +1,44 @@ +From d2c595840ed4c36751bfcfea73e21f6e390e165d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Jul 2022 13:37:47 +0200 +Subject: arm64: dts: qcom: sdm845: narrow LLCC address space + +From: Krzysztof Kozlowski + +[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ] + +The Last Level Cache Controller (LLCC) device does not need to access +entire LLCC address space. Currently driver uses only hardware info and +status registers which both reside in LLCC0_COMMON range (offset +0x30000, size 0x1000). Narrow the address space to allow binding other +drivers to rest of LLCC address space. + +Cc: Rajendra Nayak +Cc: Sibi Sankar +Reported-by: Steev Klimaszewski +Suggested-by: Sibi Sankar +Signed-off-by: Krzysztof Kozlowski +Tested-by: Steev Klimaszewski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi +index 9beb3c34fcdb..068fad00e615 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi +@@ -1796,7 +1796,7 @@ + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; +- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; ++ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; +-- +2.35.1 + diff --git a/queue-5.10/arm64-dts-uniphier-add-usb-device-support-for-pxs3-r.patch b/queue-5.10/arm64-dts-uniphier-add-usb-device-support-for-pxs3-r.patch new file mode 100644 index 00000000000..8032377c251 --- /dev/null +++ b/queue-5.10/arm64-dts-uniphier-add-usb-device-support-for-pxs3-r.patch @@ -0,0 +1,162 @@ +From d8fd9703c6fa6d8dc90b7aee4c3b1ab05599d2f4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 13:23:18 +0900 +Subject: arm64: dts: uniphier: Add USB-device support for PXs3 reference board + +From: Kunihiko Hayashi + +[ Upstream commit 19fee1a1096d21ab1f1e712148b5417bda2939a2 ] + +PXs3 reference board can change each USB port 0 and 1 to device mode +with jumpers. Prepare devicetree sources for USB port 0 and 1. + +This specifies dr_mode, pinctrl, and some quirks and removes nodes for +unused phys and vbus-supply properties. + +Signed-off-by: Kunihiko Hayashi +Link: https://lore.kernel.org/r/20220913042321.4817-8-hayashi.kunihiko@socionext.com' +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/uniphier-pinctrl.dtsi | 10 +++++ + arch/arm64/boot/dts/socionext/Makefile | 4 +- + .../socionext/uniphier-pxs3-ref-gadget0.dts | 41 +++++++++++++++++++ + .../socionext/uniphier-pxs3-ref-gadget1.dts | 40 ++++++++++++++++++ + 4 files changed, 94 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts + create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts + +diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi +index c0fd029b37e5..f909ec2e5333 100644 +--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi ++++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi +@@ -196,11 +196,21 @@ + function = "usb0"; + }; + ++ pinctrl_usb0_device: usb0-device { ++ groups = "usb0_device"; ++ function = "usb0"; ++ }; ++ + pinctrl_usb1: usb1 { + groups = "usb1"; + function = "usb1"; + }; + ++ pinctrl_usb1_device: usb1-device { ++ groups = "usb1_device"; ++ function = "usb1"; ++ }; ++ + pinctrl_usb2: usb2 { + groups = "usb2"; + function = "usb2"; +diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile +index dda3da33614b..33989a9643ac 100644 +--- a/arch/arm64/boot/dts/socionext/Makefile ++++ b/arch/arm64/boot/dts/socionext/Makefile +@@ -5,4 +5,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ld20-akebi96.dtb \ + uniphier-ld20-global.dtb \ + uniphier-ld20-ref.dtb \ +- uniphier-pxs3-ref.dtb ++ uniphier-pxs3-ref.dtb \ ++ uniphier-pxs3-ref-gadget0.dtb \ ++ uniphier-pxs3-ref-gadget1.dtb +diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts +new file mode 100644 +index 000000000000..7069f51bc120 +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts +@@ -0,0 +1,41 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++// ++// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #0) ++// ++// Copyright (C) 2021 Socionext Inc. ++// Author: Kunihiko Hayashi ++ ++/dts-v1/; ++#include "uniphier-pxs3-ref.dts" ++ ++/ { ++ model = "UniPhier PXs3 Reference Board (USB-Device #0)"; ++}; ++ ++/* I2C3 pinctrl is shared with USB*VBUSIN */ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++&usb0 { ++ status = "okay"; ++ dr_mode = "peripheral"; ++ pinctrl-0 = <&pinctrl_usb0_device>; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,usb2_gadget_lpm_disable; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phys = <&usb0_hsphy0>, <&usb0_ssphy0>; ++}; ++ ++&usb0_hsphy0 { ++ /delete-property/ vbus-supply; ++}; ++ ++&usb0_ssphy0 { ++ /delete-property/ vbus-supply; ++}; ++ ++/delete-node/ &usb0_hsphy1; ++/delete-node/ &usb0_ssphy1; +diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts +new file mode 100644 +index 000000000000..a3cfa8113ffb +--- /dev/null ++++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts +@@ -0,0 +1,40 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++// ++// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #1) ++// ++// Copyright (C) 2021 Socionext Inc. ++// Author: Kunihiko Hayashi ++ ++/dts-v1/; ++#include "uniphier-pxs3-ref.dts" ++ ++/ { ++ model = "UniPhier PXs3 Reference Board (USB-Device #1)"; ++}; ++ ++/* I2C3 pinctrl is shared with USB*VBUSIN */ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++&usb1 { ++ status = "okay"; ++ dr_mode = "peripheral"; ++ pinctrl-0 = <&pinctrl_usb1_device>; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,usb2_gadget_lpm_disable; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phys = <&usb1_hsphy0>, <&usb1_ssphy0>; ++}; ++ ++&usb1_hsphy0 { ++ /delete-property/ vbus-supply; ++}; ++ ++&usb1_ssphy0 { ++ /delete-property/ vbus-supply; ++}; ++ ++/delete-node/ &usb1_hsphy1; +-- +2.35.1 + diff --git a/queue-5.10/arm64-ftrace-fix-module-plts-with-mcount.patch b/queue-5.10/arm64-ftrace-fix-module-plts-with-mcount.patch new file mode 100644 index 00000000000..d61cf982a90 --- /dev/null +++ b/queue-5.10/arm64-ftrace-fix-module-plts-with-mcount.patch @@ -0,0 +1,127 @@ +From e063093d27aca6c5baf369e86f5a6944eb073cc0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 14:45:25 +0100 +Subject: arm64: ftrace: fix module PLTs with mcount + +From: Mark Rutland + +[ Upstream commit 8cfb08575c6d4585f1ce0deeb189e5c824776b04 ] + +Li Huafei reports that mcount-based ftrace with module PLTs was broken +by commit: + + a6253579977e4c6f ("arm64: ftrace: consistently handle PLTs.") + +When a module PLTs are used and a module is loaded sufficiently far away +from the kernel, we'll create PLTs for any branches which are +out-of-range. These are separate from the special ftrace trampoline +PLTs, which the module PLT code doesn't directly manipulate. + +When mcount is in use this is a problem, as each mcount callsite in a +module will be initialized to point to a module PLT, but since commit +a6253579977e4c6f ftrace_make_nop() will assume that the callsite has +been initialized to point to the special ftrace trampoline PLT, and +ftrace_find_callable_addr() rejects other cases. + +This means that when ftrace tries to initialize a callsite via +ftrace_make_nop(), the call to ftrace_find_callable_addr() will find +that the `_mcount` stub is out-of-range and is not handled by the ftrace +PLT, resulting in a splat: + +| ftrace_test: loading out-of-tree module taints kernel. +| ftrace: no module PLT for _mcount +| ------------[ ftrace bug ]------------ +| ftrace failed to modify +| [] 0xffff800029180014 +| actual: 44:00:00:94 +| Initializing ftrace call sites +| ftrace record flags: 2000000 +| (0) +| expected tramp: ffff80000802eb3c +| ------------[ cut here ]------------ +| WARNING: CPU: 3 PID: 157 at kernel/trace/ftrace.c:2120 ftrace_bug+0x94/0x270 +| Modules linked in: +| CPU: 3 PID: 157 Comm: insmod Tainted: G O 6.0.0-rc6-00151-gcd722513a189-dirty #22 +| Hardware name: linux,dummy-virt (DT) +| pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) +| pc : ftrace_bug+0x94/0x270 +| lr : ftrace_bug+0x21c/0x270 +| sp : ffff80000b2bbaf0 +| x29: ffff80000b2bbaf0 x28: 0000000000000000 x27: ffff0000c4d38000 +| x26: 0000000000000001 x25: ffff800009d7e000 x24: ffff0000c4d86e00 +| x23: 0000000002000000 x22: ffff80000a62b000 x21: ffff8000098ebea8 +| x20: ffff0000c4d38000 x19: ffff80000aa24158 x18: ffffffffffffffff +| x17: 0000000000000000 x16: 0a0d2d2d2d2d2d2d x15: ffff800009aa9118 +| x14: 0000000000000000 x13: 6333626532303830 x12: 3030303866666666 +| x11: 203a706d61727420 x10: 6465746365707865 x9 : 3362653230383030 +| x8 : c0000000ffffefff x7 : 0000000000017fe8 x6 : 000000000000bff4 +| x5 : 0000000000057fa8 x4 : 0000000000000000 x3 : 0000000000000001 +| x2 : ad2cb14bb5438900 x1 : 0000000000000000 x0 : 0000000000000022 +| Call trace: +| ftrace_bug+0x94/0x270 +| ftrace_process_locs+0x308/0x430 +| ftrace_module_init+0x44/0x60 +| load_module+0x15b4/0x1ce8 +| __do_sys_init_module+0x1ec/0x238 +| __arm64_sys_init_module+0x24/0x30 +| invoke_syscall+0x54/0x118 +| el0_svc_common.constprop.4+0x84/0x100 +| do_el0_svc+0x3c/0xd0 +| el0_svc+0x1c/0x50 +| el0t_64_sync_handler+0x90/0xb8 +| el0t_64_sync+0x15c/0x160 +| ---[ end trace 0000000000000000 ]--- +| ---------test_init----------- + +Fix this by reverting to the old behaviour of ignoring the old +instruction when initialising an mcount callsite in a module, which was +the behaviour prior to commit a6253579977e4c6f. + +Signed-off-by: Mark Rutland +Fixes: a6253579977e ("arm64: ftrace: consistently handle PLTs.") +Reported-by: Li Huafei +Link: https://lore.kernel.org/linux-arm-kernel/20220929094134.99512-1-lihuafei1@huawei.com +Cc: Ard Biesheuvel +Cc: Will Deacon +Link: https://lore.kernel.org/r/20220929134525.798593-1-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/ftrace.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c +index 3724bab278b2..402a24f845b9 100644 +--- a/arch/arm64/kernel/ftrace.c ++++ b/arch/arm64/kernel/ftrace.c +@@ -216,11 +216,26 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, + unsigned long pc = rec->ip; + u32 old = 0, new; + ++ new = aarch64_insn_gen_nop(); ++ ++ /* ++ * When using mcount, callsites in modules may have been initalized to ++ * call an arbitrary module PLT (which redirects to the _mcount stub) ++ * rather than the ftrace PLT we'll use at runtime (which redirects to ++ * the ftrace trampoline). We can ignore the old PLT when initializing ++ * the callsite. ++ * ++ * Note: 'mod' is only set at module load time. ++ */ ++ if (!IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS) && ++ IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && mod) { ++ return aarch64_insn_patch_text_nosync((void *)pc, new); ++ } ++ + if (!ftrace_find_callable_addr(rec, mod, &addr)) + return -EINVAL; + + old = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK); +- new = aarch64_insn_gen_nop(); + + return ftrace_modify_code(pc, old, new, true); + } +-- +2.35.1 + diff --git a/queue-5.10/asoc-da7219-fix-an-error-handling-path-in-da7219_reg.patch b/queue-5.10/asoc-da7219-fix-an-error-handling-path-in-da7219_reg.patch new file mode 100644 index 00000000000..48c50c2d2d7 --- /dev/null +++ b/queue-5.10/asoc-da7219-fix-an-error-handling-path-in-da7219_reg.patch @@ -0,0 +1,58 @@ +From 4f92408ecf1c6b9f580b79ad790f1d5c2411d4a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 21:44:57 +0200 +Subject: ASoC: da7219: Fix an error handling path in + da7219_register_dai_clks() + +From: Christophe JAILLET + +[ Upstream commit abb4e4349afe7eecdb0499582f1c777031e3a7c8 ] + +If clk_hw_register() fails, the corresponding clk should not be +unregistered. + +To handle errors from loops, clean up partial iterations before doing the +goto. So add a clk_hw_unregister(). +Then use a while (--i >= 0) loop in the unwind section. + +Fixes: 78013a1cf297 ("ASoC: da7219: Fix clock handling around codec level probe") +Reported-by: Dan Carpenter +Signed-off-by: Christophe JAILLET +Reviewed-by: Dan Carpenter +Link: https://lore.kernel.org/r/e4acceab57a0d9e477a8d5890a45c5309e553e7c.1663875789.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/da7219.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c +index 5f8c96dea094..f9e58d6509a8 100644 +--- a/sound/soc/codecs/da7219.c ++++ b/sound/soc/codecs/da7219.c +@@ -2194,6 +2194,7 @@ static int da7219_register_dai_clks(struct snd_soc_component *component) + dai_clk_lookup = clkdev_hw_create(dai_clk_hw, init.name, + "%s", dev_name(dev)); + if (!dai_clk_lookup) { ++ clk_hw_unregister(dai_clk_hw); + ret = -ENOMEM; + goto err; + } else { +@@ -2215,12 +2216,12 @@ static int da7219_register_dai_clks(struct snd_soc_component *component) + return 0; + + err: +- do { ++ while (--i >= 0) { + if (da7219->dai_clks_lookup[i]) + clkdev_drop(da7219->dai_clks_lookup[i]); + + clk_hw_unregister(&da7219->dai_clks_hw[i]); +- } while (i-- > 0); ++ } + + if (np) + kfree(da7219->clk_hw_data); +-- +2.35.1 + diff --git a/queue-5.10/asoc-eureka-tlv320-hold-reference-returned-from-of_f.patch b/queue-5.10/asoc-eureka-tlv320-hold-reference-returned-from-of_f.patch new file mode 100644 index 00000000000..ddf0964d626 --- /dev/null +++ b/queue-5.10/asoc-eureka-tlv320-hold-reference-returned-from-of_f.patch @@ -0,0 +1,69 @@ +From 029742c43476c401ed9123de0d1074d1dbd9d3d3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 14 Sep 2022 21:43:54 +0800 +Subject: ASoC: eureka-tlv320: Hold reference returned from of_find_xxx API + +From: Liang He + +[ Upstream commit bfb735a3ceff0bab6473bac275da96f9b2a06dec ] + +In eukrea_tlv320_probe(), we need to hold the reference returned +from of_find_compatible_node() which has increased the refcount +and then call of_node_put() with it when done. + +Fixes: 66f232908de2 ("ASoC: eukrea-tlv320: Add DT support.") +Co-authored-by: Kelin Wang +Signed-off-by: Liang He +Link: https://lore.kernel.org/r/20220914134354.3995587-1-windhl@126.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/fsl/eukrea-tlv320.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/fsl/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c +index e13271ea84de..29cf9234984d 100644 +--- a/sound/soc/fsl/eukrea-tlv320.c ++++ b/sound/soc/fsl/eukrea-tlv320.c +@@ -86,7 +86,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev) + int ret; + int int_port = 0, ext_port; + struct device_node *np = pdev->dev.of_node; +- struct device_node *ssi_np = NULL, *codec_np = NULL; ++ struct device_node *ssi_np = NULL, *codec_np = NULL, *tmp_np = NULL; + + eukrea_tlv320.dev = &pdev->dev; + if (np) { +@@ -143,7 +143,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev) + } + + if (machine_is_eukrea_cpuimx27() || +- of_find_compatible_node(NULL, NULL, "fsl,imx21-audmux")) { ++ (tmp_np = of_find_compatible_node(NULL, NULL, "fsl,imx21-audmux"))) { + imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, + IMX_AUDMUX_V1_PCR_SYN | + IMX_AUDMUX_V1_PCR_TFSDIR | +@@ -158,10 +158,11 @@ static int eukrea_tlv320_probe(struct platform_device *pdev) + IMX_AUDMUX_V1_PCR_SYN | + IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0) + ); ++ of_node_put(tmp_np); + } else if (machine_is_eukrea_cpuimx25sd() || + machine_is_eukrea_cpuimx35sd() || + machine_is_eukrea_cpuimx51sd() || +- of_find_compatible_node(NULL, NULL, "fsl,imx31-audmux")) { ++ (tmp_np = of_find_compatible_node(NULL, NULL, "fsl,imx31-audmux"))) { + if (!np) + ext_port = machine_is_eukrea_cpuimx25sd() ? + 4 : 3; +@@ -178,6 +179,7 @@ static int eukrea_tlv320_probe(struct platform_device *pdev) + IMX_AUDMUX_V2_PTCR_SYN, + IMX_AUDMUX_V2_PDCR_RXDSEL(int_port) + ); ++ of_node_put(tmp_np); + } else { + if (np) { + /* The eukrea,asoc-tlv320 driver was explicitly +-- +2.35.1 + diff --git a/queue-5.10/asoc-mt6660-fix-pm-disable-depth-imbalance-in-mt6660.patch b/queue-5.10/asoc-mt6660-fix-pm-disable-depth-imbalance-in-mt6660.patch new file mode 100644 index 00000000000..002a818e76e --- /dev/null +++ b/queue-5.10/asoc-mt6660-fix-pm-disable-depth-imbalance-in-mt6660.patch @@ -0,0 +1,51 @@ +From 35e7a73f05ec88fe2d64f735414290447146f835 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 00:01:16 +0800 +Subject: ASoC: mt6660: Fix PM disable depth imbalance in mt6660_i2c_probe + +From: Zhang Qilong + +[ Upstream commit b73f11e895e140537e7f8c7251211ccd3ce0782b ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. We fix it by moving +pm_runtime_enable to the endding of mt6660_i2c_probe. + +Fixes:f289e55c6eeb4 ("ASoC: Add MediaTek MT6660 Speaker Amp Driver") + +Signed-off-by: Zhang Qilong +Link: https://lore.kernel.org/r/20220928160116.125020-5-zhangqilong3@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/mt6660.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/codecs/mt6660.c b/sound/soc/codecs/mt6660.c +index d1797003c83d..e18a58868273 100644 +--- a/sound/soc/codecs/mt6660.c ++++ b/sound/soc/codecs/mt6660.c +@@ -504,13 +504,17 @@ static int mt6660_i2c_probe(struct i2c_client *client, + dev_err(chip->dev, "read chip revision fail\n"); + goto probe_fail; + } +- pm_runtime_set_active(chip->dev); +- pm_runtime_enable(chip->dev); + + ret = devm_snd_soc_register_component(chip->dev, + &mt6660_component_driver, + &mt6660_codec_dai, 1); ++ if (!ret) { ++ pm_runtime_set_active(chip->dev); ++ pm_runtime_enable(chip->dev); ++ } ++ + return ret; ++ + probe_fail: + _mt6660_chip_power_on(chip, 0); + mutex_destroy(&chip->io_lock); +-- +2.35.1 + diff --git a/queue-5.10/asoc-rsnd-add-check-for-rsnd_mod_power_on.patch b/queue-5.10/asoc-rsnd-add-check-for-rsnd_mod_power_on.patch new file mode 100644 index 00000000000..0b7f5eba435 --- /dev/null +++ b/queue-5.10/asoc-rsnd-add-check-for-rsnd_mod_power_on.patch @@ -0,0 +1,116 @@ +From f5754d8fc53fab9b4efea29aaee16c4e7cd5a63d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 09:30:30 +0800 +Subject: ASoC: rsnd: Add check for rsnd_mod_power_on + +From: Jiasheng Jiang + +[ Upstream commit 376be51caf8871419bbcbb755e1e615d30dc3153 ] + +As rsnd_mod_power_on() can return negative numbers, +it should be better to check the return value and +deal with the exception. + +Fixes: e7d850dd10f4 ("ASoC: rsnd: use mod base common method on SSI-parent") +Signed-off-by: Jiasheng Jiang +Acked-by: Kuninori Morimoto +Link: https://lore.kernel.org/r/20220902013030.3691266-1-jiasheng@iscas.ac.cn +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/sh/rcar/ctu.c | 6 +++++- + sound/soc/sh/rcar/dvc.c | 6 +++++- + sound/soc/sh/rcar/mix.c | 6 +++++- + sound/soc/sh/rcar/src.c | 5 ++++- + sound/soc/sh/rcar/ssi.c | 4 +++- + 5 files changed, 22 insertions(+), 5 deletions(-) + +diff --git a/sound/soc/sh/rcar/ctu.c b/sound/soc/sh/rcar/ctu.c +index 7647b3d4c0ba..25a8cfc27433 100644 +--- a/sound/soc/sh/rcar/ctu.c ++++ b/sound/soc/sh/rcar/ctu.c +@@ -171,7 +171,11 @@ static int rsnd_ctu_init(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) + { +- rsnd_mod_power_on(mod); ++ int ret; ++ ++ ret = rsnd_mod_power_on(mod); ++ if (ret < 0) ++ return ret; + + rsnd_ctu_activation(mod); + +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 8d91c0eb0880..53b2ad01222b 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -186,7 +186,11 @@ static int rsnd_dvc_init(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) + { +- rsnd_mod_power_on(mod); ++ int ret; ++ ++ ret = rsnd_mod_power_on(mod); ++ if (ret < 0) ++ return ret; + + rsnd_dvc_activation(mod); + +diff --git a/sound/soc/sh/rcar/mix.c b/sound/soc/sh/rcar/mix.c +index a3e0370f5704..c6fe2595c373 100644 +--- a/sound/soc/sh/rcar/mix.c ++++ b/sound/soc/sh/rcar/mix.c +@@ -146,7 +146,11 @@ static int rsnd_mix_init(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) + { +- rsnd_mod_power_on(mod); ++ int ret; ++ ++ ret = rsnd_mod_power_on(mod); ++ if (ret < 0) ++ return ret; + + rsnd_mix_activation(mod); + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 585ffba0244b..fd52e26a3808 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -454,11 +454,14 @@ static int rsnd_src_init(struct rsnd_mod *mod, + struct rsnd_priv *priv) + { + struct rsnd_src *src = rsnd_mod_to_src(mod); ++ int ret; + + /* reset sync convert_rate */ + src->sync.val = 0; + +- rsnd_mod_power_on(mod); ++ ret = rsnd_mod_power_on(mod); ++ if (ret < 0) ++ return ret; + + rsnd_src_activation(mod); + +diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c +index 042207c11651..2ead44779d46 100644 +--- a/sound/soc/sh/rcar/ssi.c ++++ b/sound/soc/sh/rcar/ssi.c +@@ -518,7 +518,9 @@ static int rsnd_ssi_init(struct rsnd_mod *mod, + + ssi->usrcnt++; + +- rsnd_mod_power_on(mod); ++ ret = rsnd_mod_power_on(mod); ++ if (ret < 0) ++ return ret; + + rsnd_ssi_config_init(mod, io); + +-- +2.35.1 + diff --git a/queue-5.10/asoc-sof-pci-change-dmi-match-info-to-support-all-ch.patch b/queue-5.10/asoc-sof-pci-change-dmi-match-info-to-support-all-ch.patch new file mode 100644 index 00000000000..33dbfea88c0 --- /dev/null +++ b/queue-5.10/asoc-sof-pci-change-dmi-match-info-to-support-all-ch.patch @@ -0,0 +1,45 @@ +From a53ba7f0f2e30a2045456d651ca47f9fcd2898a6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 13:44:29 +0200 +Subject: ASoC: SOF: pci: Change DMI match info to support all Chrome platforms + +From: Jairaj Arava + +[ Upstream commit c1c1fc8103f794a10c5c15e3c17879caf4f42c8f ] + +In some Chrome platforms if OEM's use their own string as SYS_VENDOR than +"Google", it leads to firmware load failure from intel/sof/community path. + +Hence, changing SYS_VENDOR to PRODUCT_FAMILY in which "Google" is used +as common prefix and is supported in all Chrome platforms. + +Reviewed-by: Ranjani Sridharan +Reviewed-by: Chao Song +Reviewed-by: Curtis Malainey +Signed-off-by: Jairaj Arava +Signed-off-by: Curtis Malainey +Signed-off-by: Sathyanarayana Nujella +Signed-off-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20220919114429.42700-1-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/sof/sof-pci-dev.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c +index 75657a25dbc0..fe9feaab6a0a 100644 +--- a/sound/soc/sof/sof-pci-dev.c ++++ b/sound/soc/sof/sof-pci-dev.c +@@ -75,7 +75,7 @@ static const struct dmi_system_id community_key_platforms[] = { + { + .ident = "Google Chromebooks", + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Google"), ++ DMI_MATCH(DMI_PRODUCT_FAMILY, "Google"), + } + }, + {}, +-- +2.35.1 + diff --git a/queue-5.10/asoc-tas2764-allow-mono-streams.patch b/queue-5.10/asoc-tas2764-allow-mono-streams.patch new file mode 100644 index 00000000000..81b1412cfb1 --- /dev/null +++ b/queue-5.10/asoc-tas2764-allow-mono-streams.patch @@ -0,0 +1,43 @@ +From bc7e257eea70646f77089e9c4eb67a933ca1cf12 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 16:02:37 +0200 +Subject: ASoC: tas2764: Allow mono streams +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Martin PoviÅ¡er + +[ Upstream commit 23204d928a27146d13e11c9383632775345ecca8 ] + +The part is a mono speaker amp, but it can do downmix and switch between +left and right channel, so the right channel range is 1 to 2. + +(This mirrors commit bf54d97a835d ("ASoC: tas2770: Allow mono streams") +which was a fix to the tas2770 driver.) + +Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764") +Signed-off-by: Martin PoviÅ¡er +Link: https://lore.kernel.org/r/20220825140241.53963-2-povik+lin@cutebit.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/tas2764.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c +index 37588804a6b5..bde92f080459 100644 +--- a/sound/soc/codecs/tas2764.c ++++ b/sound/soc/codecs/tas2764.c +@@ -485,7 +485,7 @@ static struct snd_soc_dai_driver tas2764_dai_driver[] = { + .id = 0, + .playback = { + .stream_name = "ASI1 Playback", +- .channels_min = 2, ++ .channels_min = 1, + .channels_max = 2, + .rates = TAS2764_RATES, + .formats = TAS2764_FORMATS, +-- +2.35.1 + diff --git a/queue-5.10/asoc-tas2764-drop-conflicting-set_bias_level-power-s.patch b/queue-5.10/asoc-tas2764-drop-conflicting-set_bias_level-power-s.patch new file mode 100644 index 00000000000..da2a75dd52f --- /dev/null +++ b/queue-5.10/asoc-tas2764-drop-conflicting-set_bias_level-power-s.patch @@ -0,0 +1,83 @@ +From 88a87e75db2322a342d3e3974baf6aeb303ecdd0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 16:02:38 +0200 +Subject: ASoC: tas2764: Drop conflicting set_bias_level power setting +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Martin PoviÅ¡er + +[ Upstream commit 09273f38832406db19a8907a934687cc10660a6b ] + +The driver is setting the PWR_CTRL field in both the set_bias_level +callback and on DAPM events of the DAC widget (and also in the +mute_stream method). Drop the set_bias_level callback altogether as the +power setting it does is in conflict with the other code paths. + +(This mirrors commit c8a6ae3fe1c8 ("ASoC: tas2770: Drop conflicting +set_bias_level power setting") which was a fix to the tas2770 driver.) + +Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764") +Signed-off-by: Martin PoviÅ¡er +Link: https://lore.kernel.org/r/20220825140241.53963-3-povik+lin@cutebit.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/tas2764.c | 33 --------------------------------- + 1 file changed, 33 deletions(-) + +diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c +index bde92f080459..6b6e30b072f2 100644 +--- a/sound/soc/codecs/tas2764.c ++++ b/sound/soc/codecs/tas2764.c +@@ -50,38 +50,6 @@ static void tas2764_reset(struct tas2764_priv *tas2764) + usleep_range(1000, 2000); + } + +-static int tas2764_set_bias_level(struct snd_soc_component *component, +- enum snd_soc_bias_level level) +-{ +- struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); +- +- switch (level) { +- case SND_SOC_BIAS_ON: +- snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_ACTIVE); +- break; +- case SND_SOC_BIAS_STANDBY: +- case SND_SOC_BIAS_PREPARE: +- snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_MUTE); +- break; +- case SND_SOC_BIAS_OFF: +- snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_SHUTDOWN); +- break; +- +- default: +- dev_err(tas2764->dev, +- "wrong power level setting %d\n", level); +- return -EINVAL; +- } +- +- return 0; +-} +- + #ifdef CONFIG_PM + static int tas2764_codec_suspend(struct snd_soc_component *component) + { +@@ -549,7 +517,6 @@ static const struct snd_soc_component_driver soc_component_driver_tas2764 = { + .probe = tas2764_codec_probe, + .suspend = tas2764_codec_suspend, + .resume = tas2764_codec_resume, +- .set_bias_level = tas2764_set_bias_level, + .controls = tas2764_snd_controls, + .num_controls = ARRAY_SIZE(tas2764_snd_controls), + .dapm_widgets = tas2764_dapm_widgets, +-- +2.35.1 + diff --git a/queue-5.10/asoc-tas2764-fix-mute-unmute.patch b/queue-5.10/asoc-tas2764-fix-mute-unmute.patch new file mode 100644 index 00000000000..b5c0ce8e4f1 --- /dev/null +++ b/queue-5.10/asoc-tas2764-fix-mute-unmute.patch @@ -0,0 +1,139 @@ +From b9d1bc57f865c27c1c7da6f4e74e495baeccd217 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 16:02:39 +0200 +Subject: ASoC: tas2764: Fix mute/unmute +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Martin PoviÅ¡er + +[ Upstream commit f5ad67f13623548e5aff847f89700c178aaf2a98 ] + +Because the PWR_CTRL field is modeled as the power state of the DAC +widget, and at the same time it is used to implement mute/unmute, we +need some additional book-keeping to have the right end result no matter +the sequence of calls. Without this fix, one permanently mutes an +ongoing stream by toggling the associated speaker pin control. + +(This mirrors commit 1e5907bcb3a3 ("ASoC: tas2770: Fix handling of +mute/unmute") which was a fix to the tas2770 driver.) + +Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764") +Signed-off-by: Martin PoviÅ¡er +Link: https://lore.kernel.org/r/20220825140241.53963-4-povik+lin@cutebit.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/tas2764.c | 57 +++++++++++++++++++++----------------- + 1 file changed, 32 insertions(+), 25 deletions(-) + +diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c +index 6b6e30b072f2..8b262e7f5275 100644 +--- a/sound/soc/codecs/tas2764.c ++++ b/sound/soc/codecs/tas2764.c +@@ -34,6 +34,9 @@ struct tas2764_priv { + + int v_sense_slot; + int i_sense_slot; ++ ++ bool dac_powered; ++ bool unmuted; + }; + + static void tas2764_reset(struct tas2764_priv *tas2764) +@@ -50,6 +53,26 @@ static void tas2764_reset(struct tas2764_priv *tas2764) + usleep_range(1000, 2000); + } + ++static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764) ++{ ++ struct snd_soc_component *component = tas2764->component; ++ unsigned int val; ++ int ret; ++ ++ if (tas2764->dac_powered) ++ val = tas2764->unmuted ? ++ TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE; ++ else ++ val = TAS2764_PWR_CTRL_SHUTDOWN; ++ ++ ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, ++ TAS2764_PWR_CTRL_MASK, val); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ + #ifdef CONFIG_PM + static int tas2764_codec_suspend(struct snd_soc_component *component) + { +@@ -82,9 +105,7 @@ static int tas2764_codec_resume(struct snd_soc_component *component) + usleep_range(1000, 2000); + } + +- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_ACTIVE); ++ ret = tas2764_update_pwr_ctrl(tas2764); + + if (ret < 0) + return ret; +@@ -118,14 +139,12 @@ static int tas2764_dac_event(struct snd_soc_dapm_widget *w, + + switch (event) { + case SND_SOC_DAPM_POST_PMU: +- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_MUTE); ++ tas2764->dac_powered = true; ++ ret = tas2764_update_pwr_ctrl(tas2764); + break; + case SND_SOC_DAPM_PRE_PMD: +- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_SHUTDOWN); ++ tas2764->dac_powered = false; ++ ret = tas2764_update_pwr_ctrl(tas2764); + break; + default: + dev_err(tas2764->dev, "Unsupported event\n"); +@@ -170,17 +189,11 @@ static const struct snd_soc_dapm_route tas2764_audio_map[] = { + + static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction) + { +- struct snd_soc_component *component = dai->component; +- int ret; +- +- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- mute ? TAS2764_PWR_CTRL_MUTE : 0); ++ struct tas2764_priv *tas2764 = ++ snd_soc_component_get_drvdata(dai->component); + +- if (ret < 0) +- return ret; +- +- return 0; ++ tas2764->unmuted = !mute; ++ return tas2764_update_pwr_ctrl(tas2764); + } + + static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth) +@@ -494,12 +507,6 @@ static int tas2764_codec_probe(struct snd_soc_component *component) + if (ret < 0) + return ret; + +- ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, +- TAS2764_PWR_CTRL_MASK, +- TAS2764_PWR_CTRL_MUTE); +- if (ret < 0) +- return ret; +- + return 0; + } + +-- +2.35.1 + diff --git a/queue-5.10/asoc-wm5102-fix-pm-disable-depth-imbalance-in-wm5102.patch b/queue-5.10/asoc-wm5102-fix-pm-disable-depth-imbalance-in-wm5102.patch new file mode 100644 index 00000000000..93114e4bf6d --- /dev/null +++ b/queue-5.10/asoc-wm5102-fix-pm-disable-depth-imbalance-in-wm5102.patch @@ -0,0 +1,51 @@ +From ce3580caaba7899d5df0f2c4b12cde54408673af Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 00:01:15 +0800 +Subject: ASoC: wm5102: Fix PM disable depth imbalance in wm5102_probe + +From: Zhang Qilong + +[ Upstream commit fcbb60820cd3008bb44334a0395e5e57ccb77329 ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. We fix it by moving +pm_runtime_enable to the endding of wm5102_probe. + +Fixes:93e8791dd34ca ("ASoC: wm5102: Initial driver") + +Signed-off-by: Zhang Qilong +Link: https://lore.kernel.org/r/20220928160116.125020-4-zhangqilong3@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wm5102.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c +index 2ed3fa67027d..b7f5e5391fdb 100644 +--- a/sound/soc/codecs/wm5102.c ++++ b/sound/soc/codecs/wm5102.c +@@ -2083,9 +2083,6 @@ static int wm5102_probe(struct platform_device *pdev) + regmap_update_bits(arizona->regmap, wm5102_digital_vu[i], + WM5102_DIG_VU, WM5102_DIG_VU); + +- pm_runtime_enable(&pdev->dev); +- pm_runtime_idle(&pdev->dev); +- + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 Compressed IRQ", wm5102_adsp2_irq, + wm5102); +@@ -2118,6 +2115,9 @@ static int wm5102_probe(struct platform_device *pdev) + goto err_spk_irqs; + } + ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_idle(&pdev->dev); ++ + return ret; + + err_spk_irqs: +-- +2.35.1 + diff --git a/queue-5.10/asoc-wm5110-fix-pm-disable-depth-imbalance-in-wm5110.patch b/queue-5.10/asoc-wm5110-fix-pm-disable-depth-imbalance-in-wm5110.patch new file mode 100644 index 00000000000..d2e8ac96223 --- /dev/null +++ b/queue-5.10/asoc-wm5110-fix-pm-disable-depth-imbalance-in-wm5110.patch @@ -0,0 +1,51 @@ +From 32d8f6fb126ee591b4cfa6566ee03d4770f2e66a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 00:01:14 +0800 +Subject: ASoC: wm5110: Fix PM disable depth imbalance in wm5110_probe + +From: Zhang Qilong + +[ Upstream commit 86b46bf1feb83898d89a2b4a8d08d21e9ea277a7 ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. We fix it by moving +pm_runtime_enable to the endding of wm5110_probe. + +Fixes:5c6af635fd772 ("ASoC: wm5110: Add audio CODEC driver") + +Signed-off-by: Zhang Qilong +Link: https://lore.kernel.org/r/20220928160116.125020-3-zhangqilong3@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wm5110.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c +index d0cef982215d..c158f8b1e8e4 100644 +--- a/sound/soc/codecs/wm5110.c ++++ b/sound/soc/codecs/wm5110.c +@@ -2452,9 +2452,6 @@ static int wm5110_probe(struct platform_device *pdev) + regmap_update_bits(arizona->regmap, wm5110_digital_vu[i], + WM5110_DIG_VU, WM5110_DIG_VU); + +- pm_runtime_enable(&pdev->dev); +- pm_runtime_idle(&pdev->dev); +- + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 Compressed IRQ", wm5110_adsp2_irq, + wm5110); +@@ -2487,6 +2484,9 @@ static int wm5110_probe(struct platform_device *pdev) + goto err_spk_irqs; + } + ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_idle(&pdev->dev); ++ + return ret; + + err_spk_irqs: +-- +2.35.1 + diff --git a/queue-5.10/asoc-wm8997-fix-pm-disable-depth-imbalance-in-wm8997.patch b/queue-5.10/asoc-wm8997-fix-pm-disable-depth-imbalance-in-wm8997.patch new file mode 100644 index 00000000000..9d45f7155d2 --- /dev/null +++ b/queue-5.10/asoc-wm8997-fix-pm-disable-depth-imbalance-in-wm8997.patch @@ -0,0 +1,51 @@ +From dd8fda4497b5b7337a69bc65f126b9ff7cb7be85 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 00:01:13 +0800 +Subject: ASoC: wm8997: Fix PM disable depth imbalance in wm8997_probe + +From: Zhang Qilong + +[ Upstream commit 41a736ac20602f64773e80f0f5b32cde1830a44a ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. We fix it by moving +pm_runtime_enable to the endding of wm8997_probe + +Fixes:40843aea5a9bd ("ASoC: wm8997: Initial CODEC driver") + +Signed-off-by: Zhang Qilong +Link: https://lore.kernel.org/r/20220928160116.125020-2-zhangqilong3@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wm8997.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/codecs/wm8997.c b/sound/soc/codecs/wm8997.c +index 229f2986cd96..07378714b013 100644 +--- a/sound/soc/codecs/wm8997.c ++++ b/sound/soc/codecs/wm8997.c +@@ -1156,9 +1156,6 @@ static int wm8997_probe(struct platform_device *pdev) + regmap_update_bits(arizona->regmap, wm8997_digital_vu[i], + WM8997_DIG_VU, WM8997_DIG_VU); + +- pm_runtime_enable(&pdev->dev); +- pm_runtime_idle(&pdev->dev); +- + arizona_init_common(arizona); + + ret = arizona_init_vol_limit(arizona); +@@ -1177,6 +1174,9 @@ static int wm8997_probe(struct platform_device *pdev) + goto err_spk_irqs; + } + ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_idle(&pdev->dev); ++ + return ret; + + err_spk_irqs: +-- +2.35.1 + diff --git a/queue-5.10/ata-fix-ata_id_has_devslp.patch b/queue-5.10/ata-fix-ata_id_has_devslp.patch new file mode 100644 index 00000000000..5201cea3d38 --- /dev/null +++ b/queue-5.10/ata-fix-ata_id_has_devslp.patch @@ -0,0 +1,57 @@ +From 674133063d2a287ac3d2ccb6a722228b9adaa28a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 14:28:33 +0200 +Subject: ata: fix ata_id_has_devslp() + +From: Niklas Cassel + +[ Upstream commit 9c6e09a434e1317e09b78b3b69cd384022ec9a03 ] + +ACS-5 section +7.13.6.36 Word 78: Serial ATA features supported +states that: + +If word 76 is not 0000h or FFFFh, word 78 reports the features supported +by the device. If this word is not supported, the word shall be cleared +to zero. + +(This text also exists in really old ACS standards, e.g. ACS-3.) + +Additionally, move the macro to the other ATA_ID_FEATURE_SUPP macros +(which already have this check), thus making it more likely that the +next ATA_ID_FEATURE_SUPP macro that is added will include this check. + +Fixes: 65fe1f0f66a5 ("ahci: implement aggressive SATA device sleep support") +Signed-off-by: Niklas Cassel +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + include/linux/ata.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/include/linux/ata.h b/include/linux/ata.h +index 734cc646ce35..8b884cd3a232 100644 +--- a/include/linux/ata.h ++++ b/include/linux/ata.h +@@ -565,6 +565,10 @@ struct ata_bmdma_prd { + ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ + ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ + ((id)[ATA_ID_FEATURE_SUPP] & (1 << 2))) ++#define ata_id_has_devslp(id) \ ++ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ ++ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ ++ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 8))) + #define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10)) + #define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11)) + #define ata_id_u32(id,n) \ +@@ -577,7 +581,6 @@ struct ata_bmdma_prd { + + #define ata_id_cdb_intr(id) (((id)[ATA_ID_CONFIG] & 0x60) == 0x20) + #define ata_id_has_da(id) ((id)[ATA_ID_SATA_CAPABILITY_2] & (1 << 4)) +-#define ata_id_has_devslp(id) ((id)[ATA_ID_FEATURE_SUPP] & (1 << 8)) + #define ata_id_has_ncq_autosense(id) \ + ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7)) + +-- +2.35.1 + diff --git a/queue-5.10/ata-fix-ata_id_has_dipm.patch b/queue-5.10/ata-fix-ata_id_has_dipm.patch new file mode 100644 index 00000000000..8067017b412 --- /dev/null +++ b/queue-5.10/ata-fix-ata_id_has_dipm.patch @@ -0,0 +1,76 @@ +From da867f34d487e1c760be5728a5df381bc90a97ad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 14:28:35 +0200 +Subject: ata: fix ata_id_has_dipm() + +From: Niklas Cassel + +[ Upstream commit 630624cb1b5826d753ac8e01a0e42de43d66dedf ] + +ACS-5 section +7.13.6.36 Word 78: Serial ATA features supported +states that: + +If word 76 is not 0000h or FFFFh, word 78 reports the features supported +by the device. If this word is not supported, the word shall be cleared +to zero. + +(This text also exists in really old ACS standards, e.g. ACS-3.) + +The problem with ata_id_has_dipm() is that the while it performs a +check against 0 and 0xffff, it performs the check against +ATA_ID_FEATURE_SUPP (word 78), the same word where the feature bit +is stored. + +Fix this by performing the check against ATA_ID_SATA_CAPABILITY +(word 76), like required by the spec. The feature bit check itself +is of course still performed against ATA_ID_FEATURE_SUPP (word 78). + +Additionally, move the macro to the other ATA_ID_FEATURE_SUPP macros +(which already have this check), thus making it more likely that the +next ATA_ID_FEATURE_SUPP macro that is added will include this check. + +Fixes: ca77329fb713 ("[libata] Link power management infrastructure") +Signed-off-by: Niklas Cassel +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + include/linux/ata.h | 15 ++++----------- + 1 file changed, 4 insertions(+), 11 deletions(-) + +diff --git a/include/linux/ata.h b/include/linux/ata.h +index 94f7872da983..6d2d31b03b4d 100644 +--- a/include/linux/ata.h ++++ b/include/linux/ata.h +@@ -573,6 +573,10 @@ struct ata_bmdma_prd { + ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ + ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ + ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7))) ++#define ata_id_has_dipm(id) \ ++ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ ++ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ ++ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 3))) + #define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10)) + #define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11)) + #define ata_id_u32(id,n) \ +@@ -596,17 +600,6 @@ static inline bool ata_id_has_hipm(const u16 *id) + return val & (1 << 9); + } + +-static inline bool ata_id_has_dipm(const u16 *id) +-{ +- u16 val = id[ATA_ID_FEATURE_SUPP]; +- +- if (val == 0 || val == 0xffff) +- return false; +- +- return val & (1 << 3); +-} +- +- + static inline bool ata_id_has_fua(const u16 *id) + { + if ((id[ATA_ID_CFSSE] & 0xC000) != 0x4000) +-- +2.35.1 + diff --git a/queue-5.10/ata-fix-ata_id_has_ncq_autosense.patch b/queue-5.10/ata-fix-ata_id_has_ncq_autosense.patch new file mode 100644 index 00000000000..75dde5a6450 --- /dev/null +++ b/queue-5.10/ata-fix-ata_id_has_ncq_autosense.patch @@ -0,0 +1,58 @@ +From 0a8598c7a43e6700ad0ad4d70a4d70b4b4126944 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 14:28:34 +0200 +Subject: ata: fix ata_id_has_ncq_autosense() + +From: Niklas Cassel + +[ Upstream commit a5fb6bf853148974dbde092ec1bde553bea5e49f ] + +ACS-5 section +7.13.6.36 Word 78: Serial ATA features supported +states that: + +If word 76 is not 0000h or FFFFh, word 78 reports the features supported +by the device. If this word is not supported, the word shall be cleared +to zero. + +(This text also exists in really old ACS standards, e.g. ACS-3.) + +Additionally, move the macro to the other ATA_ID_FEATURE_SUPP macros +(which already have this check), thus making it more likely that the +next ATA_ID_FEATURE_SUPP macro that is added will include this check. + +Fixes: 5b01e4b9efa0 ("libata: Implement NCQ autosense") +Signed-off-by: Niklas Cassel +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + include/linux/ata.h | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/include/linux/ata.h b/include/linux/ata.h +index 8b884cd3a232..94f7872da983 100644 +--- a/include/linux/ata.h ++++ b/include/linux/ata.h +@@ -569,6 +569,10 @@ struct ata_bmdma_prd { + ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ + ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ + ((id)[ATA_ID_FEATURE_SUPP] & (1 << 8))) ++#define ata_id_has_ncq_autosense(id) \ ++ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ ++ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ ++ ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7))) + #define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10)) + #define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11)) + #define ata_id_u32(id,n) \ +@@ -581,8 +585,6 @@ struct ata_bmdma_prd { + + #define ata_id_cdb_intr(id) (((id)[ATA_ID_CONFIG] & 0x60) == 0x20) + #define ata_id_has_da(id) ((id)[ATA_ID_SATA_CAPABILITY_2] & (1 << 4)) +-#define ata_id_has_ncq_autosense(id) \ +- ((id)[ATA_ID_FEATURE_SUPP] & (1 << 7)) + + static inline bool ata_id_has_hipm(const u16 *id) + { +-- +2.35.1 + diff --git a/queue-5.10/ata-fix-ata_id_sense_reporting_enabled-and-ata_id_ha.patch b/queue-5.10/ata-fix-ata_id_sense_reporting_enabled-and-ata_id_ha.patch new file mode 100644 index 00000000000..eefbf3206d7 --- /dev/null +++ b/queue-5.10/ata-fix-ata_id_sense_reporting_enabled-and-ata_id_ha.patch @@ -0,0 +1,72 @@ +From 1c95e1dc938f13593d6a8ba9b6c2dced04b6a194 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 14:28:32 +0200 +Subject: ata: fix ata_id_sense_reporting_enabled() and + ata_id_has_sense_reporting() + +From: Niklas Cassel + +[ Upstream commit 690aa8c3ae308bc696ec8b1b357b995193927083 ] + +ACS-5 section +7.13.6.41 Words 85..87, 120: Commands and feature sets supported or enabled +states that: + +If bit 15 of word 86 is set to one, bit 14 of word 119 is set to one, +and bit 15 of word 119 is cleared to zero, then word 119 is valid. + +If bit 15 of word 86 is set to one, bit 14 of word 120 is set to one, +and bit 15 of word 120 is cleared to zero, then word 120 is valid. + +(This text also exists in really old ACS standards, e.g. ACS-3.) + +Currently, ata_id_sense_reporting_enabled() and +ata_id_has_sense_reporting() both check bit 15 of word 86, +but neither of them check that bit 14 of word 119 is set to one, +or that bit 15 of word 119 is cleared to zero. + +Additionally, make ata_id_sense_reporting_enabled() return false +if !ata_id_has_sense_reporting(), similar to how e.g. +ata_id_flush_ext_enabled() returns false if !ata_id_has_flush_ext(). + +Fixes: e87fd28cf9a2 ("libata: Implement support for sense data reporting") +Signed-off-by: Niklas Cassel +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + include/linux/ata.h | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +diff --git a/include/linux/ata.h b/include/linux/ata.h +index 6e67aded28f8..734cc646ce35 100644 +--- a/include/linux/ata.h ++++ b/include/linux/ata.h +@@ -770,16 +770,21 @@ static inline bool ata_id_has_read_log_dma_ext(const u16 *id) + + static inline bool ata_id_has_sense_reporting(const u16 *id) + { +- if (!(id[ATA_ID_CFS_ENABLE_2] & (1 << 15))) ++ if (!(id[ATA_ID_CFS_ENABLE_2] & BIT(15))) ++ return false; ++ if ((id[ATA_ID_COMMAND_SET_3] & (BIT(15) | BIT(14))) != BIT(14)) + return false; +- return id[ATA_ID_COMMAND_SET_3] & (1 << 6); ++ return id[ATA_ID_COMMAND_SET_3] & BIT(6); + } + + static inline bool ata_id_sense_reporting_enabled(const u16 *id) + { +- if (!(id[ATA_ID_CFS_ENABLE_2] & (1 << 15))) ++ if (!ata_id_has_sense_reporting(id)) ++ return false; ++ /* ata_id_has_sense_reporting() == true, word 86 must have bit 15 set */ ++ if ((id[ATA_ID_COMMAND_SET_4] & (BIT(15) | BIT(14))) != BIT(14)) + return false; +- return id[ATA_ID_COMMAND_SET_4] & (1 << 6); ++ return id[ATA_ID_COMMAND_SET_4] & BIT(6); + } + + /** +-- +2.35.1 + diff --git a/queue-5.10/ata-libahci_platform-sanity-check-the-dt-child-nodes.patch b/queue-5.10/ata-libahci_platform-sanity-check-the-dt-child-nodes.patch new file mode 100644 index 00000000000..1bc5f900594 --- /dev/null +++ b/queue-5.10/ata-libahci_platform-sanity-check-the-dt-child-nodes.patch @@ -0,0 +1,67 @@ +From a00a4dcd79416e93245bd690eb095c18a63695cd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 22:36:06 +0300 +Subject: ata: libahci_platform: Sanity check the DT child nodes number + +From: Serge Semin + +[ Upstream commit 3c132ea6508b34956e5ed88d04936983ec230601 ] + +Having greater than AHCI_MAX_PORTS (32) ports detected isn't that critical +from the further AHCI-platform initialization point of view since +exceeding the ports upper limit will cause allocating more resources than +will be used afterwards. But detecting too many child DT-nodes doesn't +seem right since it's very unlikely to have it on an ordinary platform. In +accordance with the AHCI specification there can't be more than 32 ports +implemented at least due to having the CAP.NP field of 5 bits wide and the +PI register of dword size. Thus if such situation is found the DTB must +have been corrupted and the data read from it shouldn't be reliable. Let's +consider that as an erroneous situation and halt further resources +allocation. + +Note it's logically more correct to have the nports set only after the +initialization value is checked for being sane. So while at it let's make +sure nports is assigned with a correct value. + +Signed-off-by: Serge Semin +Reviewed-by: Hannes Reinecke +Signed-off-by: Damien Le Moal +Signed-off-by: Sasha Levin +--- + drivers/ata/libahci_platform.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c +index 0910441321f7..64d6da0a5303 100644 +--- a/drivers/ata/libahci_platform.c ++++ b/drivers/ata/libahci_platform.c +@@ -451,14 +451,24 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, + } + } + +- hpriv->nports = child_nodes = of_get_child_count(dev->of_node); ++ /* ++ * Too many sub-nodes most likely means having something wrong with ++ * the firmware. ++ */ ++ child_nodes = of_get_child_count(dev->of_node); ++ if (child_nodes > AHCI_MAX_PORTS) { ++ rc = -EINVAL; ++ goto err_out; ++ } + + /* + * If no sub-node was found, we still need to set nports to + * one in order to be able to use the + * ahci_platform_[en|dis]able_[phys|regulators] functions. + */ +- if (!child_nodes) ++ if (child_nodes) ++ hpriv->nports = child_nodes; ++ else + hpriv->nports = 1; + + hpriv->phys = devm_kcalloc(dev, hpriv->nports, sizeof(*hpriv->phys), GFP_KERNEL); +-- +2.35.1 + diff --git a/queue-5.10/bcache-fix-set_at_max_writeback_rate-for-multiple-at.patch b/queue-5.10/bcache-fix-set_at_max_writeback_rate-for-multiple-at.patch new file mode 100644 index 00000000000..f3092e4b00b --- /dev/null +++ b/queue-5.10/bcache-fix-set_at_max_writeback_rate-for-multiple-at.patch @@ -0,0 +1,136 @@ +From 535c383fd584c806b624b341831778b5db7779d6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 00:16:47 +0800 +Subject: bcache: fix set_at_max_writeback_rate() for multiple attached devices + +From: Coly Li + +[ Upstream commit d2d05b88035d2d51a5bb6c5afec88a0880c73df4 ] + +Inside set_at_max_writeback_rate() the calculation in following if() +check is wrong, + if (atomic_inc_return(&c->idle_counter) < + atomic_read(&c->attached_dev_nr) * 6) + +Because each attached backing device has its own writeback thread +running and increasing c->idle_counter, the counter increates much +faster than expected. The correct calculation should be, + (counter / dev_nr) < dev_nr * 6 +which equals to, + counter < dev_nr * dev_nr * 6 + +This patch fixes the above mistake with correct calculation, and helper +routine idle_counter_exceeded() is added to make code be more clear. + +Reported-by: Mingzhe Zou +Signed-off-by: Coly Li +Acked-by: Mingzhe Zou +Link: https://lore.kernel.org/r/20220919161647.81238-6-colyli@suse.de +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + drivers/md/bcache/writeback.c | 73 +++++++++++++++++++++++++---------- + 1 file changed, 52 insertions(+), 21 deletions(-) + +diff --git a/drivers/md/bcache/writeback.c b/drivers/md/bcache/writeback.c +index a878b959fbcd..3aa73da2c67b 100644 +--- a/drivers/md/bcache/writeback.c ++++ b/drivers/md/bcache/writeback.c +@@ -119,6 +119,53 @@ static void __update_writeback_rate(struct cached_dev *dc) + dc->writeback_rate_target = target; + } + ++static bool idle_counter_exceeded(struct cache_set *c) ++{ ++ int counter, dev_nr; ++ ++ /* ++ * If c->idle_counter is overflow (idel for really long time), ++ * reset as 0 and not set maximum rate this time for code ++ * simplicity. ++ */ ++ counter = atomic_inc_return(&c->idle_counter); ++ if (counter <= 0) { ++ atomic_set(&c->idle_counter, 0); ++ return false; ++ } ++ ++ dev_nr = atomic_read(&c->attached_dev_nr); ++ if (dev_nr == 0) ++ return false; ++ ++ /* ++ * c->idle_counter is increased by writeback thread of all ++ * attached backing devices, in order to represent a rough ++ * time period, counter should be divided by dev_nr. ++ * Otherwise the idle time cannot be larger with more backing ++ * device attached. ++ * The following calculation equals to checking ++ * (counter / dev_nr) < (dev_nr * 6) ++ */ ++ if (counter < (dev_nr * dev_nr * 6)) ++ return false; ++ ++ return true; ++} ++ ++/* ++ * Idle_counter is increased every time when update_writeback_rate() is ++ * called. If all backing devices attached to the same cache set have ++ * identical dc->writeback_rate_update_seconds values, it is about 6 ++ * rounds of update_writeback_rate() on each backing device before ++ * c->at_max_writeback_rate is set to 1, and then max wrteback rate set ++ * to each dc->writeback_rate.rate. ++ * In order to avoid extra locking cost for counting exact dirty cached ++ * devices number, c->attached_dev_nr is used to calculate the idle ++ * throushold. It might be bigger if not all cached device are in write- ++ * back mode, but it still works well with limited extra rounds of ++ * update_writeback_rate(). ++ */ + static bool set_at_max_writeback_rate(struct cache_set *c, + struct cached_dev *dc) + { +@@ -129,21 +176,8 @@ static bool set_at_max_writeback_rate(struct cache_set *c, + /* Don't set max writeback rate if gc is running */ + if (!c->gc_mark_valid) + return false; +- /* +- * Idle_counter is increased everytime when update_writeback_rate() is +- * called. If all backing devices attached to the same cache set have +- * identical dc->writeback_rate_update_seconds values, it is about 6 +- * rounds of update_writeback_rate() on each backing device before +- * c->at_max_writeback_rate is set to 1, and then max wrteback rate set +- * to each dc->writeback_rate.rate. +- * In order to avoid extra locking cost for counting exact dirty cached +- * devices number, c->attached_dev_nr is used to calculate the idle +- * throushold. It might be bigger if not all cached device are in write- +- * back mode, but it still works well with limited extra rounds of +- * update_writeback_rate(). +- */ +- if (atomic_inc_return(&c->idle_counter) < +- atomic_read(&c->attached_dev_nr) * 6) ++ ++ if (!idle_counter_exceeded(c)) + return false; + + if (atomic_read(&c->at_max_writeback_rate) != 1) +@@ -157,13 +191,10 @@ static bool set_at_max_writeback_rate(struct cache_set *c, + dc->writeback_rate_change = 0; + + /* +- * Check c->idle_counter and c->at_max_writeback_rate agagain in case +- * new I/O arrives during before set_at_max_writeback_rate() returns. +- * Then the writeback rate is set to 1, and its new value should be +- * decided via __update_writeback_rate(). ++ * In case new I/O arrives during before ++ * set_at_max_writeback_rate() returns. + */ +- if ((atomic_read(&c->idle_counter) < +- atomic_read(&c->attached_dev_nr) * 6) || ++ if (!idle_counter_exceeded(c) || + !atomic_read(&c->at_max_writeback_rate)) + return false; + +-- +2.35.1 + diff --git a/queue-5.10/blk-throttle-prevent-overflow-while-calculating-wait.patch b/queue-5.10/blk-throttle-prevent-overflow-while-calculating-wait.patch new file mode 100644 index 00000000000..3a208083571 --- /dev/null +++ b/queue-5.10/blk-throttle-prevent-overflow-while-calculating-wait.patch @@ -0,0 +1,51 @@ +From 681b35acf5996eef3244ea197b5b6efb9dfea475 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 29 Aug 2022 10:22:38 +0800 +Subject: blk-throttle: prevent overflow while calculating wait time + +From: Yu Kuai + +[ Upstream commit 8d6bbaada2e0a65f9012ac4c2506460160e7237a ] + +There is a problem found by code review in tg_with_in_bps_limit() that +'bps_limit * jiffy_elapsed_rnd' might overflow. Fix the problem by +calling mul_u64_u64_div_u64() instead. + +Signed-off-by: Yu Kuai +Acked-by: Tejun Heo +Link: https://lore.kernel.org/r/20220829022240.3348319-3-yukuai1@huaweicloud.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + block/blk-throttle.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/block/blk-throttle.c b/block/blk-throttle.c +index c53a254171a2..c526fdd0a7b9 100644 +--- a/block/blk-throttle.c ++++ b/block/blk-throttle.c +@@ -944,7 +944,7 @@ static bool tg_with_in_bps_limit(struct throtl_grp *tg, struct bio *bio, + u64 bps_limit, unsigned long *wait) + { + bool rw = bio_data_dir(bio); +- u64 bytes_allowed, extra_bytes, tmp; ++ u64 bytes_allowed, extra_bytes; + unsigned long jiffy_elapsed, jiffy_wait, jiffy_elapsed_rnd; + unsigned int bio_size = throtl_bio_data_size(bio); + +@@ -961,10 +961,8 @@ static bool tg_with_in_bps_limit(struct throtl_grp *tg, struct bio *bio, + jiffy_elapsed_rnd = tg->td->throtl_slice; + + jiffy_elapsed_rnd = roundup(jiffy_elapsed_rnd, tg->td->throtl_slice); +- +- tmp = bps_limit * jiffy_elapsed_rnd; +- do_div(tmp, HZ); +- bytes_allowed = tmp; ++ bytes_allowed = mul_u64_u64_div_u64(bps_limit, (u64)jiffy_elapsed_rnd, ++ (u64)HZ); + + if (tg->bytes_disp[rw] + bio_size <= bytes_allowed) { + if (wait) +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-btusb-fine-tune-mt7663-mechanism.patch b/queue-5.10/bluetooth-btusb-fine-tune-mt7663-mechanism.patch new file mode 100644 index 00000000000..fa0bbdbc498 --- /dev/null +++ b/queue-5.10/bluetooth-btusb-fine-tune-mt7663-mechanism.patch @@ -0,0 +1,75 @@ +From 1dd674d88d1d77eba07fb11dc7554af815340e91 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 2 Feb 2021 18:26:17 +0800 +Subject: Bluetooth: btusb: Fine-tune mt7663 mechanism. + +From: Mark Chen + +[ Upstream commit 48c13301e6baba5fd0960b412af519c0baa98011 ] + +Fine-tune read register for mt7663/mt7921. +For mediatek chip spcific wmt protocol, we add more delay to send EP0 +In-Token. + +Signed-off-by: Mark Chen +Signed-off-by: Marcel Holtmann +Stable-dep-of: fd3f106677ba ("Bluetooth: btusb: mediatek: fix WMT failure during runtime suspend") +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btusb.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c +index a699e6166aef..eb6e33d168d8 100644 +--- a/drivers/bluetooth/btusb.c ++++ b/drivers/bluetooth/btusb.c +@@ -2816,6 +2816,7 @@ enum { + enum { + BTMTK_WMT_INVALID, + BTMTK_WMT_PATCH_UNDONE, ++ BTMTK_WMT_PATCH_PROGRESS, + BTMTK_WMT_PATCH_DONE, + BTMTK_WMT_ON_UNDONE, + BTMTK_WMT_ON_DONE, +@@ -2831,7 +2832,7 @@ struct btmtk_wmt_hdr { + + struct btmtk_hci_wmt_cmd { + struct btmtk_wmt_hdr hdr; +- u8 data[256]; ++ u8 data[1000]; + } __packed; + + struct btmtk_hci_wmt_evt { +@@ -2934,7 +2935,7 @@ static void btusb_mtk_wmt_recv(struct urb *urb) + * to generate the event. Otherwise, the WMT event cannot return from + * the device successfully. + */ +- udelay(100); ++ udelay(500); + + usb_anchor_urb(urb, &data->ctrl_anchor); + err = usb_submit_urb(urb, GFP_ATOMIC); +@@ -3238,9 +3239,9 @@ static int btusb_mtk_reg_read(struct btusb_data *data, u32 reg, u32 *val) + return err; + } + +-static int btusb_mtk_id_get(struct btusb_data *data, u32 *id) ++static int btusb_mtk_id_get(struct btusb_data *data, u32 reg, u32 *id) + { +- return btusb_mtk_reg_read(data, 0x80000008, id); ++ return btusb_mtk_reg_read(data, reg, id); + } + + static int btusb_mtk_setup(struct hci_dev *hdev) +@@ -3258,7 +3259,7 @@ static int btusb_mtk_setup(struct hci_dev *hdev) + + calltime = ktime_get(); + +- err = btusb_mtk_id_get(data, &dev_id); ++ err = btusb_mtk_id_get(data, 0x80000008, &dev_id); + if (err < 0) { + bt_dev_err(hdev, "Failed to get device id (%d)", err); + return err; +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-btusb-fix-excessive-stack-usage.patch b/queue-5.10/bluetooth-btusb-fix-excessive-stack-usage.patch new file mode 100644 index 00000000000..faf0ead60d3 --- /dev/null +++ b/queue-5.10/bluetooth-btusb-fix-excessive-stack-usage.patch @@ -0,0 +1,115 @@ +From d75da669221fca80dcfb4769b558d8f87e566fd8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 4 Feb 2021 16:47:07 +0100 +Subject: Bluetooth: btusb: fix excessive stack usage + +From: Arnd Bergmann + +[ Upstream commit 10888140f09c3472146dc206accd0cfa051d0ed4 ] + +Enlarging the size of 'struct btmtk_hci_wmt_cmd' makes it no longer +fit on the kernel stack, as seen from this compiler warning: + +drivers/bluetooth/btusb.c:3365:12: error: stack frame size of 1036 bytes in function 'btusb_mtk_hci_wmt_sync' [-Werror,-Wframe-larger-than=] + +Change the function to dynamically allocate the buffer instead. +As there are other sleeping functions called from the same location, +using GFP_KERNEL should be fine here, and the runtime overhead should +not matter as this is rarely called. + +Unfortunately, I could not figure out why the message size is +increased in the previous patch. Using dynamic allocation means +any size is possible now, but there is still a range check that +limits the total size (including the five-byte header) to 255 +bytes, so whatever was intended there is now undone. + +Fixes: 48c13301e6ba ("Bluetooth: btusb: Fine-tune mt7663 mechanism.") +Signed-off-by: Arnd Bergmann +Signed-off-by: Marcel Holtmann +Stable-dep-of: fd3f106677ba ("Bluetooth: btusb: mediatek: fix WMT failure during runtime suspend") +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btusb.c | 24 +++++++++++++++--------- + 1 file changed, 15 insertions(+), 9 deletions(-) + +diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c +index eb6e33d168d8..80a3d5019950 100644 +--- a/drivers/bluetooth/btusb.c ++++ b/drivers/bluetooth/btusb.c +@@ -2832,7 +2832,7 @@ struct btmtk_wmt_hdr { + + struct btmtk_hci_wmt_cmd { + struct btmtk_wmt_hdr hdr; +- u8 data[1000]; ++ u8 data[]; + } __packed; + + struct btmtk_hci_wmt_evt { +@@ -3011,7 +3011,7 @@ static int btusb_mtk_hci_wmt_sync(struct hci_dev *hdev, + struct btmtk_hci_wmt_evt_funcc *wmt_evt_funcc; + u32 hlen, status = BTMTK_WMT_INVALID; + struct btmtk_hci_wmt_evt *wmt_evt; +- struct btmtk_hci_wmt_cmd wc; ++ struct btmtk_hci_wmt_cmd *wc; + struct btmtk_wmt_hdr *hdr; + int err; + +@@ -3020,20 +3020,24 @@ static int btusb_mtk_hci_wmt_sync(struct hci_dev *hdev, + if (hlen > 255) + return -EINVAL; + +- hdr = (struct btmtk_wmt_hdr *)&wc; ++ wc = kzalloc(hlen, GFP_KERNEL); ++ if (!wc) ++ return -ENOMEM; ++ ++ hdr = &wc->hdr; + hdr->dir = 1; + hdr->op = wmt_params->op; + hdr->dlen = cpu_to_le16(wmt_params->dlen + 1); + hdr->flag = wmt_params->flag; +- memcpy(wc.data, wmt_params->data, wmt_params->dlen); ++ memcpy(wc->data, wmt_params->data, wmt_params->dlen); + + set_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags); + +- err = __hci_cmd_send(hdev, 0xfc6f, hlen, &wc); ++ err = __hci_cmd_send(hdev, 0xfc6f, hlen, wc); + + if (err < 0) { + clear_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags); +- return err; ++ goto err_free_wc; + } + + /* Submit control IN URB on demand to process the WMT event */ +@@ -3055,13 +3059,14 @@ static int btusb_mtk_hci_wmt_sync(struct hci_dev *hdev, + if (err == -EINTR) { + bt_dev_err(hdev, "Execution of wmt command interrupted"); + clear_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags); +- return err; ++ goto err_free_wc; + } + + if (err) { + bt_dev_err(hdev, "Execution of wmt command timed out"); + clear_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags); +- return -ETIMEDOUT; ++ err = -ETIMEDOUT; ++ goto err_free_wc; + } + + /* Parse and handle the return WMT event */ +@@ -3097,7 +3102,8 @@ static int btusb_mtk_hci_wmt_sync(struct hci_dev *hdev, + err_free_skb: + kfree_skb(data->evt_skb); + data->evt_skb = NULL; +- ++err_free_wc: ++ kfree(wc); + return err; + } + +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-btusb-mediatek-fix-wmt-failure-during-runt.patch b/queue-5.10/bluetooth-btusb-mediatek-fix-wmt-failure-during-runt.patch new file mode 100644 index 00000000000..a4f62381382 --- /dev/null +++ b/queue-5.10/bluetooth-btusb-mediatek-fix-wmt-failure-during-runt.patch @@ -0,0 +1,62 @@ +From fc0452655082897551f10199aad7266e5328d4f6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Aug 2022 08:49:07 +0800 +Subject: Bluetooth: btusb: mediatek: fix WMT failure during runtime suspend + +From: Sean Wang + +[ Upstream commit fd3f106677bac70437dc12e76c827294ed495a44 ] + +WMT cmd/event doesn't follow up the generic HCI cmd/event handling, it +needs constantly polling control pipe until the host received the WMT +event, thus, we should require to specifically acquire PM counter on the +USB to prevent the interface from entering auto suspended while WMT +cmd/event in progress. + +Fixes: a1c49c434e15 ("Bluetooth: btusb: Add protocol support for MediaTek MT7668U USB devices") +Co-developed-by: Jing Cai +Signed-off-by: Jing Cai +Signed-off-by: Sean Wang +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/btusb.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c +index 80a3d5019950..6efd981979bd 100644 +--- a/drivers/bluetooth/btusb.c ++++ b/drivers/bluetooth/btusb.c +@@ -3033,15 +3033,29 @@ static int btusb_mtk_hci_wmt_sync(struct hci_dev *hdev, + + set_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags); + ++ /* WMT cmd/event doesn't follow up the generic HCI cmd/event handling, ++ * it needs constantly polling control pipe until the host received the ++ * WMT event, thus, we should require to specifically acquire PM counter ++ * on the USB to prevent the interface from entering auto suspended ++ * while WMT cmd/event in progress. ++ */ ++ err = usb_autopm_get_interface(data->intf); ++ if (err < 0) ++ goto err_free_wc; ++ + err = __hci_cmd_send(hdev, 0xfc6f, hlen, wc); + + if (err < 0) { + clear_bit(BTUSB_TX_WAIT_VND_EVT, &data->flags); ++ usb_autopm_put_interface(data->intf); + goto err_free_wc; + } + + /* Submit control IN URB on demand to process the WMT event */ + err = btusb_mtk_submit_wmt_recv_urb(hdev); ++ ++ usb_autopm_put_interface(data->intf); ++ + if (err < 0) + return err; + +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-hci_-ldisc-serdev-check-percpu_init_rwsem-.patch b/queue-5.10/bluetooth-hci_-ldisc-serdev-check-percpu_init_rwsem-.patch new file mode 100644 index 00000000000..2d537b12790 --- /dev/null +++ b/queue-5.10/bluetooth-hci_-ldisc-serdev-check-percpu_init_rwsem-.patch @@ -0,0 +1,93 @@ +From 54886a3483de2ef5cadc47de18d50750625f34bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 29 Aug 2022 23:58:12 +0900 +Subject: Bluetooth: hci_{ldisc,serdev}: check percpu_init_rwsem() failure + +From: Tetsuo Handa + +[ Upstream commit 3124d320c22f3f4388d9ac5c8f37eaad0cefd6b1 ] + +syzbot is reporting NULL pointer dereference at hci_uart_tty_close() [1], +for rcu_sync_enter() is called without rcu_sync_init() due to +hci_uart_tty_open() ignoring percpu_init_rwsem() failure. + +While we are at it, fix that hci_uart_register_device() ignores +percpu_init_rwsem() failure and hci_uart_unregister_device() does not +call percpu_free_rwsem(). + +Link: https://syzkaller.appspot.com/bug?extid=576dfca25381fb6fbc5f [1] +Reported-by: syzbot +Signed-off-by: Tetsuo Handa +Fixes: 67d2f8781b9f00d1 ("Bluetooth: hci_ldisc: Allow sleeping while proto locks are held.") +Fixes: d73e172816652772 ("Bluetooth: hci_serdev: Init hci_uart proto_lock to avoid oops") +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + drivers/bluetooth/hci_ldisc.c | 7 +++++-- + drivers/bluetooth/hci_serdev.c | 10 +++++++--- + 2 files changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c +index 637c5b8c2aa1..726d5c83c550 100644 +--- a/drivers/bluetooth/hci_ldisc.c ++++ b/drivers/bluetooth/hci_ldisc.c +@@ -490,6 +490,11 @@ static int hci_uart_tty_open(struct tty_struct *tty) + BT_ERR("Can't allocate control structure"); + return -ENFILE; + } ++ if (percpu_init_rwsem(&hu->proto_lock)) { ++ BT_ERR("Can't allocate semaphore structure"); ++ kfree(hu); ++ return -ENOMEM; ++ } + + tty->disc_data = hu; + hu->tty = tty; +@@ -502,8 +507,6 @@ static int hci_uart_tty_open(struct tty_struct *tty) + INIT_WORK(&hu->init_ready, hci_uart_init_work); + INIT_WORK(&hu->write_work, hci_uart_write_work); + +- percpu_init_rwsem(&hu->proto_lock); +- + /* Flush any pending characters in the driver */ + tty_driver_flush_buffer(tty); + +diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c +index e9a44ab3812d..f2e2e553d4de 100644 +--- a/drivers/bluetooth/hci_serdev.c ++++ b/drivers/bluetooth/hci_serdev.c +@@ -301,11 +301,12 @@ int hci_uart_register_device(struct hci_uart *hu, + + serdev_device_set_client_ops(hu->serdev, &hci_serdev_client_ops); + ++ if (percpu_init_rwsem(&hu->proto_lock)) ++ return -ENOMEM; ++ + err = serdev_device_open(hu->serdev); + if (err) +- return err; +- +- percpu_init_rwsem(&hu->proto_lock); ++ goto err_rwsem; + + err = p->open(hu); + if (err) +@@ -375,6 +376,8 @@ int hci_uart_register_device(struct hci_uart *hu, + p->close(hu); + err_open: + serdev_device_close(hu->serdev); ++err_rwsem: ++ percpu_free_rwsem(&hu->proto_lock); + return err; + } + EXPORT_SYMBOL_GPL(hci_uart_register_device); +@@ -396,5 +399,6 @@ void hci_uart_unregister_device(struct hci_uart *hu) + clear_bit(HCI_UART_PROTO_READY, &hu->flags); + serdev_device_close(hu->serdev); + } ++ percpu_free_rwsem(&hu->proto_lock); + } + EXPORT_SYMBOL_GPL(hci_uart_unregister_device); +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-hci_core-fix-not-handling-link-timeouts-pr.patch b/queue-5.10/bluetooth-hci_core-fix-not-handling-link-timeouts-pr.patch new file mode 100644 index 00000000000..fe2a5082970 --- /dev/null +++ b/queue-5.10/bluetooth-hci_core-fix-not-handling-link-timeouts-pr.patch @@ -0,0 +1,104 @@ +From 72cf5a4074e140ab08d5ef7ffbdc2c5e5ad38fff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 15:44:42 -0700 +Subject: Bluetooth: hci_core: Fix not handling link timeouts propertly + +From: Luiz Augusto von Dentz + +[ Upstream commit 116523c8fac05d1d26f748fee7919a4ec5df67ea ] + +Change that introduced the use of __check_timeout did not account for +link types properly, it always assumes ACL_LINK is used thus causing +hdev->acl_last_tx to be used even in case of LE_LINK and then again +uses ACL_LINK with hci_link_tx_to. + +To fix this __check_timeout now takes the link type as parameter and +then procedure to use the right last_tx based on the link type and pass +it to hci_link_tx_to. + +Fixes: 1b1d29e51499 ("Bluetooth: Make use of __check_timeout on hci_sched_le") +Signed-off-by: Luiz Augusto von Dentz +Tested-by: David Beinder +Signed-off-by: Sasha Levin +--- + net/bluetooth/hci_core.c | 34 +++++++++++++++++++++++----------- + 1 file changed, 23 insertions(+), 11 deletions(-) + +diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c +index 2cb0cf035476..866eb22432de 100644 +--- a/net/bluetooth/hci_core.c ++++ b/net/bluetooth/hci_core.c +@@ -4482,15 +4482,27 @@ static inline int __get_blocks(struct hci_dev *hdev, struct sk_buff *skb) + return DIV_ROUND_UP(skb->len - HCI_ACL_HDR_SIZE, hdev->block_len); + } + +-static void __check_timeout(struct hci_dev *hdev, unsigned int cnt) ++static void __check_timeout(struct hci_dev *hdev, unsigned int cnt, u8 type) + { +- if (!hci_dev_test_flag(hdev, HCI_UNCONFIGURED)) { +- /* ACL tx timeout must be longer than maximum +- * link supervision timeout (40.9 seconds) */ +- if (!cnt && time_after(jiffies, hdev->acl_last_tx + +- HCI_ACL_TX_TIMEOUT)) +- hci_link_tx_to(hdev, ACL_LINK); ++ unsigned long last_tx; ++ ++ if (hci_dev_test_flag(hdev, HCI_UNCONFIGURED)) ++ return; ++ ++ switch (type) { ++ case LE_LINK: ++ last_tx = hdev->le_last_tx; ++ break; ++ default: ++ last_tx = hdev->acl_last_tx; ++ break; + } ++ ++ /* tx timeout must be longer than maximum link supervision timeout ++ * (40.9 seconds) ++ */ ++ if (!cnt && time_after(jiffies, last_tx + HCI_ACL_TX_TIMEOUT)) ++ hci_link_tx_to(hdev, type); + } + + /* Schedule SCO */ +@@ -4548,7 +4560,7 @@ static void hci_sched_acl_pkt(struct hci_dev *hdev) + struct sk_buff *skb; + int quote; + +- __check_timeout(hdev, cnt); ++ __check_timeout(hdev, cnt, ACL_LINK); + + while (hdev->acl_cnt && + (chan = hci_chan_sent(hdev, ACL_LINK, "e))) { +@@ -4591,8 +4603,6 @@ static void hci_sched_acl_blk(struct hci_dev *hdev) + int quote; + u8 type; + +- __check_timeout(hdev, cnt); +- + BT_DBG("%s", hdev->name); + + if (hdev->dev_type == HCI_AMP) +@@ -4600,6 +4610,8 @@ static void hci_sched_acl_blk(struct hci_dev *hdev) + else + type = ACL_LINK; + ++ __check_timeout(hdev, cnt, type); ++ + while (hdev->block_cnt > 0 && + (chan = hci_chan_sent(hdev, type, "e))) { + u32 priority = (skb_peek(&chan->data_q))->priority; +@@ -4673,7 +4685,7 @@ static void hci_sched_le(struct hci_dev *hdev) + + cnt = hdev->le_pkts ? hdev->le_cnt : hdev->acl_cnt; + +- __check_timeout(hdev, cnt); ++ __check_timeout(hdev, cnt, LE_LINK); + + tmp = cnt; + while (cnt && (chan = hci_chan_sent(hdev, LE_LINK, "e))) { +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-hci_sysfs-fix-attempting-to-call-device_ad.patch b/queue-5.10/bluetooth-hci_sysfs-fix-attempting-to-call-device_ad.patch new file mode 100644 index 00000000000..c5649ef1f3f --- /dev/null +++ b/queue-5.10/bluetooth-hci_sysfs-fix-attempting-to-call-device_ad.patch @@ -0,0 +1,67 @@ +From 7d27a7c442f756f8b4885eb8e8e4c5ef1b0a544e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 10:56:59 -0700 +Subject: Bluetooth: hci_sysfs: Fix attempting to call device_add multiple + times + +From: Luiz Augusto von Dentz + +[ Upstream commit 448a496f760664d3e2e79466aa1787e6abc922b5 ] + +device_add shall not be called multiple times as stated in its +documentation: + + 'Do not call this routine or device_register() more than once for + any device structure' + +Syzkaller reports a bug as follows [1]: +------------[ cut here ]------------ +kernel BUG at lib/list_debug.c:33! +invalid opcode: 0000 [#1] PREEMPT SMP KASAN +[...] +Call Trace: + + __list_add include/linux/list.h:69 [inline] + list_add_tail include/linux/list.h:102 [inline] + kobj_kset_join lib/kobject.c:164 [inline] + kobject_add_internal+0x18f/0x8f0 lib/kobject.c:214 + kobject_add_varg lib/kobject.c:358 [inline] + kobject_add+0x150/0x1c0 lib/kobject.c:410 + device_add+0x368/0x1e90 drivers/base/core.c:3452 + hci_conn_add_sysfs+0x9b/0x1b0 net/bluetooth/hci_sysfs.c:53 + hci_le_cis_estabilished_evt+0x57c/0xae0 net/bluetooth/hci_event.c:6799 + hci_le_meta_evt+0x2b8/0x510 net/bluetooth/hci_event.c:7110 + hci_event_func net/bluetooth/hci_event.c:7440 [inline] + hci_event_packet+0x63d/0xfd0 net/bluetooth/hci_event.c:7495 + hci_rx_work+0xae7/0x1230 net/bluetooth/hci_core.c:4007 + process_one_work+0x991/0x1610 kernel/workqueue.c:2289 + worker_thread+0x665/0x1080 kernel/workqueue.c:2436 + kthread+0x2e4/0x3a0 kernel/kthread.c:376 + ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:306 + + +Link: https://syzkaller.appspot.com/bug?id=da3246e2d33afdb92d66bc166a0934c5b146404a +Signed-off-by: Luiz Augusto von Dentz +Tested-by: Hawkins Jiawei +Signed-off-by: Sasha Levin +--- + net/bluetooth/hci_sysfs.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/net/bluetooth/hci_sysfs.c b/net/bluetooth/hci_sysfs.c +index b69d88b88d2e..ccd2c377bf83 100644 +--- a/net/bluetooth/hci_sysfs.c ++++ b/net/bluetooth/hci_sysfs.c +@@ -48,6 +48,9 @@ void hci_conn_add_sysfs(struct hci_conn *conn) + + BT_DBG("conn %p", conn); + ++ if (device_is_registered(&conn->dev)) ++ return; ++ + dev_set_name(&conn->dev, "%s:%d", hdev->name, conn->handle); + + if (device_add(&conn->dev) < 0) { +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-l2cap-fix-user-after-free.patch b/queue-5.10/bluetooth-l2cap-fix-user-after-free.patch new file mode 100644 index 00000000000..30736aa1186 --- /dev/null +++ b/queue-5.10/bluetooth-l2cap-fix-user-after-free.patch @@ -0,0 +1,61 @@ +From 7988adc19903b064f2e106d45b6d26d7ad8730a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 13:27:13 -0700 +Subject: Bluetooth: L2CAP: Fix user-after-free + +From: Luiz Augusto von Dentz + +[ Upstream commit 35fcbc4243aad7e7d020b7c1dfb14bb888b20a4f ] + +This uses l2cap_chan_hold_unless_zero() after calling +__l2cap_get_chan_blah() to prevent the following trace: + +Bluetooth: l2cap_core.c:static void l2cap_chan_destroy(struct kref +*kref) +Bluetooth: chan 0000000023c4974d +Bluetooth: parent 00000000ae861c08 +================================================================== +BUG: KASAN: use-after-free in __mutex_waiter_is_first +kernel/locking/mutex.c:191 [inline] +BUG: KASAN: use-after-free in __mutex_lock_common +kernel/locking/mutex.c:671 [inline] +BUG: KASAN: use-after-free in __mutex_lock+0x278/0x400 +kernel/locking/mutex.c:729 +Read of size 8 at addr ffff888006a49b08 by task kworker/u3:2/389 + +Link: https://lore.kernel.org/lkml/20220622082716.478486-1-lee.jones@linaro.org +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sungwoo Kim +Signed-off-by: Sasha Levin +--- + net/bluetooth/l2cap_core.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c +index 8d5029c81ee7..83dd76e9196f 100644 +--- a/net/bluetooth/l2cap_core.c ++++ b/net/bluetooth/l2cap_core.c +@@ -4305,6 +4305,12 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn, + } + } + ++ chan = l2cap_chan_hold_unless_zero(chan); ++ if (!chan) { ++ err = -EBADSLT; ++ goto unlock; ++ } ++ + err = 0; + + l2cap_chan_lock(chan); +@@ -4334,6 +4340,7 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn, + } + + l2cap_chan_unlock(chan); ++ l2cap_chan_put(chan); + + unlock: + mutex_unlock(&conn->chan_lock); +-- +2.35.1 + diff --git a/queue-5.10/bluetooth-l2cap-initialize-delayed-works-at-l2cap_ch.patch b/queue-5.10/bluetooth-l2cap-initialize-delayed-works-at-l2cap_ch.patch new file mode 100644 index 00000000000..3d70b69ca12 --- /dev/null +++ b/queue-5.10/bluetooth-l2cap-initialize-delayed-works-at-l2cap_ch.patch @@ -0,0 +1,82 @@ +From 1e58815e3f93c16d31f15a722005daaa78693b8d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 00:32:56 +0900 +Subject: Bluetooth: L2CAP: initialize delayed works at l2cap_chan_create() + +From: Tetsuo Handa + +[ Upstream commit 2d2cb3066f2c90cd8ca540b36ba7a55e7f2406e0 ] + +syzbot is reporting cancel_delayed_work() without INIT_DELAYED_WORK() at +l2cap_chan_del() [1], for CONF_NOT_COMPLETE flag (which meant to prevent +l2cap_chan_del() from calling cancel_delayed_work()) is cleared by timer +which fires before l2cap_chan_del() is called by closing file descriptor +created by socket(AF_BLUETOOTH, SOCK_STREAM, BTPROTO_L2CAP). + +l2cap_bredr_sig_cmd(L2CAP_CONF_REQ) and l2cap_bredr_sig_cmd(L2CAP_CONF_RSP) +are calling l2cap_ertm_init(chan), and they call l2cap_chan_ready() (which +clears CONF_NOT_COMPLETE flag) only when l2cap_ertm_init(chan) succeeded. + +l2cap_sock_init() does not call l2cap_ertm_init(chan), and it instead sets +CONF_NOT_COMPLETE flag by calling l2cap_chan_set_defaults(). However, when +connect() is requested, "command 0x0409 tx timeout" happens after 2 seconds + from connect() request, and CONF_NOT_COMPLETE flag is cleared after 4 +seconds from connect() request, for l2cap_conn_start() from +l2cap_info_timeout() callback scheduled by + + schedule_delayed_work(&conn->info_timer, L2CAP_INFO_TIMEOUT); + +in l2cap_connect() is calling l2cap_chan_ready(). + +Fix this problem by initializing delayed works used by L2CAP_MODE_ERTM +mode as soon as l2cap_chan_create() allocates a channel, like I did in +commit be8597239379f0f5 ("Bluetooth: initialize skb_queue_head at +l2cap_chan_create()"). + +Link: https://syzkaller.appspot.com/bug?extid=83672956c7aa6af698b3 [1] +Reported-by: syzbot +Signed-off-by: Tetsuo Handa +Signed-off-by: Luiz Augusto von Dentz +Signed-off-by: Sasha Levin +--- + net/bluetooth/l2cap_core.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c +index 0c38af2ff209..8d5029c81ee7 100644 +--- a/net/bluetooth/l2cap_core.c ++++ b/net/bluetooth/l2cap_core.c +@@ -61,6 +61,9 @@ static void l2cap_send_disconn_req(struct l2cap_chan *chan, int err); + + static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control, + struct sk_buff_head *skbs, u8 event); ++static void l2cap_retrans_timeout(struct work_struct *work); ++static void l2cap_monitor_timeout(struct work_struct *work); ++static void l2cap_ack_timeout(struct work_struct *work); + + static inline u8 bdaddr_type(u8 link_type, u8 bdaddr_type) + { +@@ -476,6 +479,9 @@ struct l2cap_chan *l2cap_chan_create(void) + write_unlock(&chan_list_lock); + + INIT_DELAYED_WORK(&chan->chan_timer, l2cap_chan_timeout); ++ INIT_DELAYED_WORK(&chan->retrans_timer, l2cap_retrans_timeout); ++ INIT_DELAYED_WORK(&chan->monitor_timer, l2cap_monitor_timeout); ++ INIT_DELAYED_WORK(&chan->ack_timer, l2cap_ack_timeout); + + chan->state = BT_OPEN; + +@@ -3316,10 +3322,6 @@ int l2cap_ertm_init(struct l2cap_chan *chan) + chan->rx_state = L2CAP_RX_STATE_RECV; + chan->tx_state = L2CAP_TX_STATE_XMIT; + +- INIT_DELAYED_WORK(&chan->retrans_timer, l2cap_retrans_timeout); +- INIT_DELAYED_WORK(&chan->monitor_timer, l2cap_monitor_timeout); +- INIT_DELAYED_WORK(&chan->ack_timer, l2cap_ack_timeout); +- + skb_queue_head_init(&chan->srej_q); + + err = l2cap_seq_list_init(&chan->srej_list, chan->tx_win); +-- +2.35.1 + diff --git a/queue-5.10/bnx2x-fix-potential-memory-leak-in-bnx2x_tpa_stop.patch b/queue-5.10/bnx2x-fix-potential-memory-leak-in-bnx2x_tpa_stop.patch new file mode 100644 index 00000000000..b242d2b0310 --- /dev/null +++ b/queue-5.10/bnx2x-fix-potential-memory-leak-in-bnx2x_tpa_stop.patch @@ -0,0 +1,40 @@ +From 05d00512b14842fc30407776c0e36085e0e5a5f6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 14:28:43 +0800 +Subject: bnx2x: fix potential memory leak in bnx2x_tpa_stop() + +From: Jianglei Nie + +[ Upstream commit b43f9acbb8942b05252be83ac25a81cec70cc192 ] + +bnx2x_tpa_stop() allocates a memory chunk from new_data with +bnx2x_frag_alloc(). The new_data should be freed when gets some error. +But when "pad + len > fp->rx_buf_size" is true, bnx2x_tpa_stop() returns +without releasing the new_data, which will lead to a memory leak. + +We should free the new_data with bnx2x_frag_free() when "pad + len > +fp->rx_buf_size" is true. + +Fixes: 07b0f00964def8af9321cfd6c4a7e84f6362f728 ("bnx2x: fix possible panic under memory stress") +Signed-off-by: Jianglei Nie +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c +index 198e041d8410..4f669e7c7558 100644 +--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c ++++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c +@@ -788,6 +788,7 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp, + BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n", + pad, len, fp->rx_buf_size); + bnx2x_panic(); ++ bnx2x_frag_free(fp, new_data); + return; + } + #endif +-- +2.35.1 + diff --git a/queue-5.10/bpf-btf-fix-truncated-last_member_type_id-in-btf_str.patch b/queue-5.10/bpf-btf-fix-truncated-last_member_type_id-in-btf_str.patch new file mode 100644 index 00000000000..2fc50ebeb3f --- /dev/null +++ b/queue-5.10/bpf-btf-fix-truncated-last_member_type_id-in-btf_str.patch @@ -0,0 +1,47 @@ +From c5a7c634bfac2bc3eba37d3e09675dc8aef9a0e1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 10 Sep 2022 11:01:20 +0000 +Subject: bpf: btf: fix truncated last_member_type_id in btf_struct_resolve + +From: Lorenz Bauer + +[ Upstream commit a37a32583e282d8d815e22add29bc1e91e19951a ] + +When trying to finish resolving a struct member, btf_struct_resolve +saves the member type id in a u16 temporary variable. This truncates +the 32 bit type id value if it exceeds UINT16_MAX. + +As a result, structs that have members with type ids > UINT16_MAX and +which need resolution will fail with a message like this: + + [67414] STRUCT ff_device size=120 vlen=12 + effect_owners type_id=67434 bits_offset=960 Member exceeds struct_size + +Fix this by changing the type of last_member_type_id to u32. + +Fixes: a0791f0df7d2 ("bpf: fix BTF limits") +Reviewed-by: Stanislav Fomichev +Signed-off-by: Lorenz Bauer +Link: https://lore.kernel.org/r/20220910110120.339242-1-oss@lmb.io +Signed-off-by: Alexei Starovoitov +Signed-off-by: Sasha Levin +--- + kernel/bpf/btf.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/bpf/btf.c b/kernel/bpf/btf.c +index dc497eaf2266..9232938e3f96 100644 +--- a/kernel/bpf/btf.c ++++ b/kernel/bpf/btf.c +@@ -2913,7 +2913,7 @@ static int btf_struct_resolve(struct btf_verifier_env *env, + if (v->next_member) { + const struct btf_type *last_member_type; + const struct btf_member *last_member; +- u16 last_member_type_id; ++ u32 last_member_type_id; + + last_member = btf_type_member(v->t) + v->next_member - 1; + last_member_type_id = last_member->type; +-- +2.35.1 + diff --git a/queue-5.10/bpf-ensure-correct-locking-around-vulnerable-functio.patch b/queue-5.10/bpf-ensure-correct-locking-around-vulnerable-functio.patch new file mode 100644 index 00000000000..e149649d377 --- /dev/null +++ b/queue-5.10/bpf-ensure-correct-locking-around-vulnerable-functio.patch @@ -0,0 +1,43 @@ +From fdf5207076076c40c9a444151f1e7910840a4787 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Sep 2022 14:38:55 +0100 +Subject: bpf: Ensure correct locking around vulnerable function find_vpid() + +From: Lee Jones + +[ Upstream commit 83c10cc362d91c0d8d25e60779ee52fdbbf3894d ] + +The documentation for find_vpid() clearly states: + + "Must be called with the tasklist_lock or rcu_read_lock() held." + +Presently we do neither for find_vpid() instance in bpf_task_fd_query(). +Add proper rcu_read_lock/unlock() to fix the issue. + +Fixes: 41bdc4b40ed6f ("bpf: introduce bpf subcommand BPF_TASK_FD_QUERY") +Signed-off-by: Lee Jones +Signed-off-by: Daniel Borkmann +Acked-by: Yonghong Song +Link: https://lore.kernel.org/bpf/20220912133855.1218900-1-lee@kernel.org +Signed-off-by: Sasha Levin +--- + kernel/bpf/syscall.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c +index 419dbc3d060e..aaad2dce2be6 100644 +--- a/kernel/bpf/syscall.c ++++ b/kernel/bpf/syscall.c +@@ -3915,7 +3915,9 @@ static int bpf_task_fd_query(const union bpf_attr *attr, + if (attr->task_fd_query.flags != 0) + return -EINVAL; + ++ rcu_read_lock(); + task = get_pid_task(find_vpid(pid), PIDTYPE_PID); ++ rcu_read_unlock(); + if (!task) + return -ENOENT; + +-- +2.35.1 + diff --git a/queue-5.10/bpftool-clear-errno-after-libcap-s-checks.patch b/queue-5.10/bpftool-clear-errno-after-libcap-s-checks.patch new file mode 100644 index 00000000000..4c21c344e8b --- /dev/null +++ b/queue-5.10/bpftool-clear-errno-after-libcap-s-checks.patch @@ -0,0 +1,70 @@ +From 0c7d04576e9c581d53007f1d9c5f73fda8930825 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Aug 2022 17:22:05 +0100 +Subject: bpftool: Clear errno after libcap's checks + +From: Quentin Monnet + +[ Upstream commit cea558855c39b7f1f02ff50dcf701ca6596bc964 ] + +When bpftool is linked against libcap, the library runs a "constructor" +function to compute the number of capabilities of the running kernel +[0], at the beginning of the execution of the program. As part of this, +it performs multiple calls to prctl(). Some of these may fail, and set +errno to a non-zero value: + + # strace -e prctl ./bpftool version + prctl(PR_CAPBSET_READ, CAP_MAC_OVERRIDE) = 1 + prctl(PR_CAPBSET_READ, 0x30 /* CAP_??? */) = -1 EINVAL (Invalid argument) + prctl(PR_CAPBSET_READ, CAP_CHECKPOINT_RESTORE) = 1 + prctl(PR_CAPBSET_READ, 0x2c /* CAP_??? */) = -1 EINVAL (Invalid argument) + prctl(PR_CAPBSET_READ, 0x2a /* CAP_??? */) = -1 EINVAL (Invalid argument) + prctl(PR_CAPBSET_READ, 0x29 /* CAP_??? */) = -1 EINVAL (Invalid argument) + ** fprintf added at the top of main(): we have errno == 1 + ./bpftool v7.0.0 + using libbpf v1.0 + features: libbfd, libbpf_strict, skeletons + +++ exited with 0 +++ + +This has been addressed in libcap 2.63 [1], but until this version is +available everywhere, we can fix it on bpftool side. + +Let's clean errno at the beginning of the main() function, to make sure +that these checks do not interfere with the batch mode, where we error +out if errno is set after a bpftool command. + + [0] https://git.kernel.org/pub/scm/libs/libcap/libcap.git/tree/libcap/cap_alloc.c?h=libcap-2.65#n20 + [1] https://git.kernel.org/pub/scm/libs/libcap/libcap.git/commit/?id=f25a1b7e69f7b33e6afb58b3e38f3450b7d2d9a0 + +Signed-off-by: Quentin Monnet +Signed-off-by: Daniel Borkmann +Link: https://lore.kernel.org/bpf/20220815162205.45043-1-quentin@isovalent.com +Signed-off-by: Sasha Levin +--- + tools/bpf/bpftool/main.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/tools/bpf/bpftool/main.c b/tools/bpf/bpftool/main.c +index 1854d6b97860..4fd4e3462ebc 100644 +--- a/tools/bpf/bpftool/main.c ++++ b/tools/bpf/bpftool/main.c +@@ -398,6 +398,16 @@ int main(int argc, char **argv) + + setlinebuf(stdout); + ++#ifdef USE_LIBCAP ++ /* Libcap < 2.63 hooks before main() to compute the number of ++ * capabilities of the running kernel, and doing so it calls prctl() ++ * which may fail and set errno to non-zero. ++ * Let's reset errno to make sure this does not interfere with the ++ * batch mode. ++ */ ++ errno = 0; ++#endif ++ + last_do_help = do_help; + pretty_output = false; + json_output = false; +-- +2.35.1 + diff --git a/queue-5.10/bpftool-fix-a-wrong-type-cast-in-btf_dumper_int.patch b/queue-5.10/bpftool-fix-a-wrong-type-cast-in-btf_dumper_int.patch new file mode 100644 index 00000000000..9dbeed66bd2 --- /dev/null +++ b/queue-5.10/bpftool-fix-a-wrong-type-cast-in-btf_dumper_int.patch @@ -0,0 +1,40 @@ +From 2dd04fa26dd5ccb03ddae46733977164837b7b31 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 15:59:00 -0700 +Subject: bpftool: Fix a wrong type cast in btf_dumper_int + +From: Lam Thai + +[ Upstream commit 7184aef9c0f7a81db8fd18d183ee42481d89bf35 ] + +When `data` points to a boolean value, casting it to `int *` is problematic +and could lead to a wrong value being passed to `jsonw_bool`. Change the +cast to `bool *` instead. + +Fixes: b12d6ec09730 ("bpf: btf: add btf print functionality") +Signed-off-by: Lam Thai +Signed-off-by: Andrii Nakryiko +Reviewed-by: Quentin Monnet +Acked-by: John Fastabend +Link: https://lore.kernel.org/bpf/20220824225859.9038-1-lamthai@arista.com +Signed-off-by: Sasha Levin +--- + tools/bpf/bpftool/btf_dumper.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/bpf/bpftool/btf_dumper.c b/tools/bpf/bpftool/btf_dumper.c +index 0e9310727281..13be48763199 100644 +--- a/tools/bpf/bpftool/btf_dumper.c ++++ b/tools/bpf/bpftool/btf_dumper.c +@@ -416,7 +416,7 @@ static int btf_dumper_int(const struct btf_type *t, __u8 bit_offset, + *(char *)data); + break; + case BTF_INT_BOOL: +- jsonw_bool(jw, *(int *)data); ++ jsonw_bool(jw, *(bool *)data); + break; + default: + /* shouldn't happen */ +-- +2.35.1 + diff --git a/queue-5.10/btrfs-add-kcsan-annotations-for-unlocked-access-to-b.patch b/queue-5.10/btrfs-add-kcsan-annotations-for-unlocked-access-to-b.patch new file mode 100644 index 00000000000..df3925eda76 --- /dev/null +++ b/queue-5.10/btrfs-add-kcsan-annotations-for-unlocked-access-to-b.patch @@ -0,0 +1,90 @@ +From 438159f7b94039cb4e8a1c77ed00c1474fd1c45c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Sep 2022 18:32:23 +0200 +Subject: btrfs: add KCSAN annotations for unlocked access to block_rsv->full + +From: David Sterba + +[ Upstream commit 748f553c3c4c4f175c6c834358632aff802d72cf ] + +KCSAN reports that there's unlocked access mixed with locked access, +which is technically correct but is not a bug. To avoid false alerts at +least from KCSAN, add annotation and use a wrapper whenever ->full is +accessed for read outside of lock. + +It is used as a fast check and only advisory. In the worst case the +block reserve is found !full and becomes full in the meantime, but +properly handled. + +Depending on the value of ->full, btrfs_block_rsv_release decides +where to return the reservation, and block_rsv_release_bytes handles a +NULL pointer for block_rsv and if it's not NULL then it double checks +the full status under a lock. + +Link: https://lore.kernel.org/linux-btrfs/CAAwBoOJDjei5Hnem155N_cJwiEkVwJYvgN-tQrwWbZQGhFU=cA@mail.gmail.com/ +Link: https://lore.kernel.org/linux-btrfs/YvHU/vsXd7uz5V6j@hungrycats.org +Reported-by: Zygo Blaxell +Signed-off-by: David Sterba +Signed-off-by: Sasha Levin +--- + fs/btrfs/block-rsv.c | 2 +- + fs/btrfs/block-rsv.h | 9 +++++++++ + fs/btrfs/transaction.c | 4 ++-- + 3 files changed, 12 insertions(+), 3 deletions(-) + +diff --git a/fs/btrfs/block-rsv.c b/fs/btrfs/block-rsv.c +index bc920afe23bf..692a1739bef6 100644 +--- a/fs/btrfs/block-rsv.c ++++ b/fs/btrfs/block-rsv.c +@@ -285,7 +285,7 @@ u64 btrfs_block_rsv_release(struct btrfs_fs_info *fs_info, + */ + if (block_rsv == delayed_rsv) + target = global_rsv; +- else if (block_rsv != global_rsv && !delayed_rsv->full) ++ else if (block_rsv != global_rsv && !btrfs_block_rsv_full(delayed_rsv)) + target = delayed_rsv; + + if (target && block_rsv->space_info != target->space_info) +diff --git a/fs/btrfs/block-rsv.h b/fs/btrfs/block-rsv.h +index 0b6ae5302837..f0431547acf2 100644 +--- a/fs/btrfs/block-rsv.h ++++ b/fs/btrfs/block-rsv.h +@@ -90,4 +90,13 @@ static inline void btrfs_unuse_block_rsv(struct btrfs_fs_info *fs_info, + btrfs_block_rsv_release(fs_info, block_rsv, 0, NULL); + } + ++/* ++ * Fast path to check if the reserve is full, may be carefully used outside of ++ * locks. ++ */ ++static inline bool btrfs_block_rsv_full(const struct btrfs_block_rsv *rsv) ++{ ++ return data_race(rsv->full); ++} ++ + #endif /* BTRFS_BLOCK_RSV_H */ +diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c +index 8daa9e4eb1d2..3cfa7cce266e 100644 +--- a/fs/btrfs/transaction.c ++++ b/fs/btrfs/transaction.c +@@ -608,7 +608,7 @@ start_transaction(struct btrfs_root *root, unsigned int num_items, + */ + num_bytes = btrfs_calc_insert_metadata_size(fs_info, num_items); + if (flush == BTRFS_RESERVE_FLUSH_ALL && +- delayed_refs_rsv->full == 0) { ++ btrfs_block_rsv_full(delayed_refs_rsv) == 0) { + delayed_refs_bytes = num_bytes; + num_bytes <<= 1; + } +@@ -633,7 +633,7 @@ start_transaction(struct btrfs_root *root, unsigned int num_items, + if (rsv->space_info->force_alloc) + do_chunk_alloc = true; + } else if (num_items == 0 && flush == BTRFS_RESERVE_FLUSH_ALL && +- !delayed_refs_rsv->full) { ++ !btrfs_block_rsv_full(delayed_refs_rsv)) { + /* + * Some people call with btrfs_start_transaction(root, 0) + * because they can be throttled, but have some other mechanism +-- +2.35.1 + diff --git a/queue-5.10/btrfs-check-superblock-to-ensure-the-fs-was-not-modi.patch b/queue-5.10/btrfs-check-superblock-to-ensure-the-fs-was-not-modi.patch new file mode 100644 index 00000000000..f75024f9118 --- /dev/null +++ b/queue-5.10/btrfs-check-superblock-to-ensure-the-fs-was-not-modi.patch @@ -0,0 +1,254 @@ +From c51682ccc8cdebf7af7fa6f95508f6e3f87ab104 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 20:16:22 +0800 +Subject: btrfs: check superblock to ensure the fs was not modified at thaw + time + +From: Qu Wenruo + +[ Upstream commit a05d3c9153145283ce9c58a1d7a9056fbb85f6a1 ] + +[BACKGROUND] +There is an incident report that, one user hibernated the system, with +one btrfs on removable device still mounted. + +Then by some incident, the btrfs got mounted and modified by another +system/OS, then back to the hibernated system. + +After resuming from the hibernation, new write happened into the victim btrfs. + +Now the fs is completely broken, since the underlying btrfs is no longer +the same one before the hibernation, and the user lost their data due to +various transid mismatch. + +[REPRODUCER] +We can emulate the situation using the following small script: + + truncate -s 1G $dev + mkfs.btrfs -f $dev + mount $dev $mnt + fsstress -w -d $mnt -n 500 + sync + xfs_freeze -f $mnt + cp $dev $dev.backup + + # There is no way to mount the same cloned fs on the same system, + # as the conflicting fsid will be rejected by btrfs. + # Thus here we have to wipe the fs using a different btrfs. + mkfs.btrfs -f $dev.backup + + dd if=$dev.backup of=$dev bs=1M + xfs_freeze -u $mnt + fsstress -w -d $mnt -n 20 + umount $mnt + btrfs check $dev + +The final fsck will fail due to some tree blocks has incorrect fsid. + +This is enough to emulate the problem hit by the unfortunate user. + +[ENHANCEMENT] +Although such case should not be that common, it can still happen from +time to time. + +From the view of btrfs, we can detect any unexpected super block change, +and if there is any unexpected change, we just mark the fs read-only, +and thaw the fs. + +By this we can limit the damage to minimal, and I hope no one would lose +their data by this anymore. + +Suggested-by: Goffredo Baroncelli +Link: https://lore.kernel.org/linux-btrfs/83bf3b4b-7f4c-387a-b286-9251e3991e34@bluemole.com/ +Reviewed-by: Anand Jain +Signed-off-by: Qu Wenruo +Signed-off-by: David Sterba +Signed-off-by: Sasha Levin +--- + fs/btrfs/disk-io.c | 25 ++++++++++++++----- + fs/btrfs/disk-io.h | 4 +++- + fs/btrfs/super.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ + fs/btrfs/volumes.c | 2 +- + 4 files changed, 83 insertions(+), 8 deletions(-) + +diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c +index f2abd8bfd4a0..8af0d722ab9a 100644 +--- a/fs/btrfs/disk-io.c ++++ b/fs/btrfs/disk-io.c +@@ -2400,8 +2400,8 @@ static int btrfs_read_roots(struct btrfs_fs_info *fs_info) + * 1, 2 2nd and 3rd backup copy + * -1 skip bytenr check + */ +-static int validate_super(struct btrfs_fs_info *fs_info, +- struct btrfs_super_block *sb, int mirror_num) ++int btrfs_validate_super(struct btrfs_fs_info *fs_info, ++ struct btrfs_super_block *sb, int mirror_num) + { + u64 nodesize = btrfs_super_nodesize(sb); + u64 sectorsize = btrfs_super_sectorsize(sb); +@@ -2576,7 +2576,7 @@ static int validate_super(struct btrfs_fs_info *fs_info, + */ + static int btrfs_validate_mount_super(struct btrfs_fs_info *fs_info) + { +- return validate_super(fs_info, fs_info->super_copy, 0); ++ return btrfs_validate_super(fs_info, fs_info->super_copy, 0); + } + + /* +@@ -2590,7 +2590,7 @@ static int btrfs_validate_write_super(struct btrfs_fs_info *fs_info, + { + int ret; + +- ret = validate_super(fs_info, sb, -1); ++ ret = btrfs_validate_super(fs_info, sb, -1); + if (ret < 0) + goto out; + if (!btrfs_supported_super_csum(btrfs_super_csum_type(sb))) { +@@ -3500,7 +3500,7 @@ static void btrfs_end_super_write(struct bio *bio) + } + + struct btrfs_super_block *btrfs_read_dev_one_super(struct block_device *bdev, +- int copy_num) ++ int copy_num, bool drop_cache) + { + struct btrfs_super_block *super; + struct page *page; +@@ -3511,6 +3511,19 @@ struct btrfs_super_block *btrfs_read_dev_one_super(struct block_device *bdev, + if (bytenr + BTRFS_SUPER_INFO_SIZE >= i_size_read(bdev->bd_inode)) + return ERR_PTR(-EINVAL); + ++ if (drop_cache) { ++ /* This should only be called with the primary sb. */ ++ ASSERT(copy_num == 0); ++ ++ /* ++ * Drop the page of the primary superblock, so later read will ++ * always read from the device. ++ */ ++ invalidate_inode_pages2_range(mapping, ++ bytenr >> PAGE_SHIFT, ++ (bytenr + BTRFS_SUPER_INFO_SIZE) >> PAGE_SHIFT); ++ } ++ + page = read_cache_page_gfp(mapping, bytenr >> PAGE_SHIFT, GFP_NOFS); + if (IS_ERR(page)) + return ERR_CAST(page); +@@ -3542,7 +3555,7 @@ struct btrfs_super_block *btrfs_read_dev_super(struct block_device *bdev) + * later supers, using BTRFS_SUPER_MIRROR_MAX instead + */ + for (i = 0; i < 1; i++) { +- super = btrfs_read_dev_one_super(bdev, i); ++ super = btrfs_read_dev_one_super(bdev, i, false); + if (IS_ERR(super)) + continue; + +diff --git a/fs/btrfs/disk-io.h b/fs/btrfs/disk-io.h +index 182540bdcea0..a1bcd388dfec 100644 +--- a/fs/btrfs/disk-io.h ++++ b/fs/btrfs/disk-io.h +@@ -54,10 +54,12 @@ int __cold open_ctree(struct super_block *sb, + struct btrfs_fs_devices *fs_devices, + char *options); + void __cold close_ctree(struct btrfs_fs_info *fs_info); ++int btrfs_validate_super(struct btrfs_fs_info *fs_info, ++ struct btrfs_super_block *sb, int mirror_num); + int write_all_supers(struct btrfs_fs_info *fs_info, int max_mirrors); + struct btrfs_super_block *btrfs_read_dev_super(struct block_device *bdev); + struct btrfs_super_block *btrfs_read_dev_one_super(struct block_device *bdev, +- int copy_num); ++ int copy_num, bool drop_cache); + int btrfs_commit_super(struct btrfs_fs_info *fs_info); + struct btrfs_root *btrfs_read_tree_root(struct btrfs_root *tree_root, + struct btrfs_key *key); +diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c +index 8bf8cdb62a3a..97b06c24e443 100644 +--- a/fs/btrfs/super.c ++++ b/fs/btrfs/super.c +@@ -2400,11 +2400,71 @@ static int btrfs_freeze(struct super_block *sb) + return btrfs_commit_transaction(trans); + } + ++static int check_dev_super(struct btrfs_device *dev) ++{ ++ struct btrfs_fs_info *fs_info = dev->fs_info; ++ struct btrfs_super_block *sb; ++ int ret = 0; ++ ++ /* This should be called with fs still frozen. */ ++ ASSERT(test_bit(BTRFS_FS_FROZEN, &fs_info->flags)); ++ ++ /* Missing dev, no need to check. */ ++ if (!dev->bdev) ++ return 0; ++ ++ /* Only need to check the primary super block. */ ++ sb = btrfs_read_dev_one_super(dev->bdev, 0, true); ++ if (IS_ERR(sb)) ++ return PTR_ERR(sb); ++ ++ /* Btrfs_validate_super() includes fsid check against super->fsid. */ ++ ret = btrfs_validate_super(fs_info, sb, 0); ++ if (ret < 0) ++ goto out; ++ ++ if (btrfs_super_generation(sb) != fs_info->last_trans_committed) { ++ btrfs_err(fs_info, "transid mismatch, has %llu expect %llu", ++ btrfs_super_generation(sb), ++ fs_info->last_trans_committed); ++ ret = -EUCLEAN; ++ goto out; ++ } ++out: ++ btrfs_release_disk_super(sb); ++ return ret; ++} ++ + static int btrfs_unfreeze(struct super_block *sb) + { + struct btrfs_fs_info *fs_info = btrfs_sb(sb); ++ struct btrfs_device *device; ++ int ret = 0; + ++ /* ++ * Make sure the fs is not changed by accident (like hibernation then ++ * modified by other OS). ++ * If we found anything wrong, we mark the fs error immediately. ++ * ++ * And since the fs is frozen, no one can modify the fs yet, thus ++ * we don't need to hold device_list_mutex. ++ */ ++ list_for_each_entry(device, &fs_info->fs_devices->devices, dev_list) { ++ ret = check_dev_super(device); ++ if (ret < 0) { ++ btrfs_handle_fs_error(fs_info, ret, ++ "super block on devid %llu got modified unexpectedly", ++ device->devid); ++ break; ++ } ++ } + clear_bit(BTRFS_FS_FROZEN, &fs_info->flags); ++ ++ /* ++ * We still return 0, to allow VFS layer to unfreeze the fs even the ++ * above checks failed. Since the fs is either fine or read-only, we're ++ * safe to continue, without causing further damage. ++ */ + return 0; + } + +diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c +index d4d89e0738ff..e14bd23cc75c 100644 +--- a/fs/btrfs/volumes.c ++++ b/fs/btrfs/volumes.c +@@ -2069,7 +2069,7 @@ void btrfs_scratch_superblocks(struct btrfs_fs_info *fs_info, + struct page *page; + int ret; + +- disk_super = btrfs_read_dev_one_super(bdev, copy_num); ++ disk_super = btrfs_read_dev_one_super(bdev, copy_num, false); + if (IS_ERR(disk_super)) + continue; + +-- +2.35.1 + diff --git a/queue-5.10/btrfs-scrub-try-to-fix-super-block-errors.patch b/queue-5.10/btrfs-scrub-try-to-fix-super-block-errors.patch new file mode 100644 index 00000000000..0e8697b07ca --- /dev/null +++ b/queue-5.10/btrfs-scrub-try-to-fix-super-block-errors.patch @@ -0,0 +1,147 @@ +From 9a26a717dda4ecbcc7644a5dd14e8501200d3bf9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 2 Aug 2022 14:53:03 +0800 +Subject: btrfs: scrub: try to fix super block errors + +From: Qu Wenruo + +[ Upstream commit f9eab5f0bba76742af654f33d517bf62a0db8f12 ] + +[BUG] +The following script shows that, although scrub can detect super block +errors, it never tries to fix it: + + mkfs.btrfs -f -d raid1 -m raid1 $dev1 $dev2 + xfs_io -c "pwrite 67108864 4k" $dev2 + + mount $dev1 $mnt + btrfs scrub start -B $dev2 + btrfs scrub start -Br $dev2 + umount $mnt + +The first scrub reports the super error correctly: + + scrub done for f3289218-abd3-41ac-a630-202f766c0859 + Scrub started: Tue Aug 2 14:44:11 2022 + Status: finished + Duration: 0:00:00 + Total to scrub: 1.26GiB + Rate: 0.00B/s + Error summary: super=1 + Corrected: 0 + Uncorrectable: 0 + Unverified: 0 + +But the second read-only scrub still reports the same super error: + + Scrub started: Tue Aug 2 14:44:11 2022 + Status: finished + Duration: 0:00:00 + Total to scrub: 1.26GiB + Rate: 0.00B/s + Error summary: super=1 + Corrected: 0 + Uncorrectable: 0 + Unverified: 0 + +[CAUSE] +The comments already shows that super block can be easily fixed by +committing a transaction: + + /* + * If we find an error in a super block, we just report it. + * They will get written with the next transaction commit + * anyway + */ + +But the truth is, such assumption is not always true, and since scrub +should try to repair every error it found (except for read-only scrub), +we should really actively commit a transaction to fix this. + +[FIX] +Just commit a transaction if we found any super block errors, after +everything else is done. + +We cannot do this just after scrub_supers(), as +btrfs_commit_transaction() will try to pause and wait for the running +scrub, thus we can not call it with scrub_lock hold. + +Signed-off-by: Qu Wenruo +Reviewed-by: David Sterba +Signed-off-by: David Sterba +Signed-off-by: Sasha Levin +--- + fs/btrfs/scrub.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/fs/btrfs/scrub.c b/fs/btrfs/scrub.c +index 0392c556af60..88b9a5394561 100644 +--- a/fs/btrfs/scrub.c ++++ b/fs/btrfs/scrub.c +@@ -3811,6 +3811,7 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start, + int ret; + struct btrfs_device *dev; + unsigned int nofs_flag; ++ bool need_commit = false; + + if (btrfs_fs_closing(fs_info)) + return -EAGAIN; +@@ -3924,6 +3925,12 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start, + */ + nofs_flag = memalloc_nofs_save(); + if (!is_dev_replace) { ++ u64 old_super_errors; ++ ++ spin_lock(&sctx->stat_lock); ++ old_super_errors = sctx->stat.super_errors; ++ spin_unlock(&sctx->stat_lock); ++ + btrfs_info(fs_info, "scrub: started on devid %llu", devid); + /* + * by holding device list mutex, we can +@@ -3932,6 +3939,16 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start, + mutex_lock(&fs_info->fs_devices->device_list_mutex); + ret = scrub_supers(sctx, dev); + mutex_unlock(&fs_info->fs_devices->device_list_mutex); ++ ++ spin_lock(&sctx->stat_lock); ++ /* ++ * Super block errors found, but we can not commit transaction ++ * at current context, since btrfs_commit_transaction() needs ++ * to pause the current running scrub (hold by ourselves). ++ */ ++ if (sctx->stat.super_errors > old_super_errors && !sctx->readonly) ++ need_commit = true; ++ spin_unlock(&sctx->stat_lock); + } + + if (!ret) +@@ -3958,6 +3975,25 @@ int btrfs_scrub_dev(struct btrfs_fs_info *fs_info, u64 devid, u64 start, + scrub_workers_put(fs_info); + scrub_put_ctx(sctx); + ++ /* ++ * We found some super block errors before, now try to force a ++ * transaction commit, as scrub has finished. ++ */ ++ if (need_commit) { ++ struct btrfs_trans_handle *trans; ++ ++ trans = btrfs_start_transaction(fs_info->tree_root, 0); ++ if (IS_ERR(trans)) { ++ ret = PTR_ERR(trans); ++ btrfs_err(fs_info, ++ "scrub: failed to start transaction to fix super block errors: %d", ret); ++ return ret; ++ } ++ ret = btrfs_commit_transaction(trans); ++ if (ret < 0) ++ btrfs_err(fs_info, ++ "scrub: failed to commit transaction to fix super block errors: %d", ret); ++ } + return ret; + out: + scrub_workers_put(fs_info); +-- +2.35.1 + diff --git a/queue-5.10/can-bcm-check-the-result-of-can_send-in-bcm_can_tx.patch b/queue-5.10/can-bcm-check-the-result-of-can_send-in-bcm_can_tx.patch new file mode 100644 index 00000000000..5c1bdd2cdb3 --- /dev/null +++ b/queue-5.10/can-bcm-check-the-result-of-can_send-in-bcm_can_tx.patch @@ -0,0 +1,53 @@ +From 62dd67415357926a744a1368f11af0e4b5ae51a2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 Sep 2022 09:55:56 +0800 +Subject: can: bcm: check the result of can_send() in bcm_can_tx() + +From: Ziyang Xuan + +[ Upstream commit 3fd7bfd28cfd68ae80a2fe92ea1615722cc2ee6e ] + +If can_send() fail, it should not update frames_abs counter +in bcm_can_tx(). Add the result check for can_send() in bcm_can_tx(). + +Suggested-by: Marc Kleine-Budde +Suggested-by: Oliver Hartkopp +Signed-off-by: Ziyang Xuan +Link: https://lore.kernel.org/all/9851878e74d6d37aee2f1ee76d68361a46f89458.1663206163.git.william.xuanziyang@huawei.com +Acked-by: Oliver Hartkopp +Signed-off-by: Marc Kleine-Budde +Signed-off-by: Sasha Levin +--- + net/can/bcm.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/net/can/bcm.c b/net/can/bcm.c +index e918a0f3cda2..afa82adaf6cd 100644 +--- a/net/can/bcm.c ++++ b/net/can/bcm.c +@@ -274,6 +274,7 @@ static void bcm_can_tx(struct bcm_op *op) + struct sk_buff *skb; + struct net_device *dev; + struct canfd_frame *cf = op->frames + op->cfsiz * op->currframe; ++ int err; + + /* no target device? => exit */ + if (!op->ifindex) +@@ -298,11 +299,11 @@ static void bcm_can_tx(struct bcm_op *op) + /* send with loopback */ + skb->dev = dev; + can_skb_set_owner(skb, op->sk); +- can_send(skb, 1); ++ err = can_send(skb, 1); ++ if (!err) ++ op->frames_abs++; + +- /* update statistics */ + op->currframe++; +- op->frames_abs++; + + /* reached last frame? */ + if (op->currframe >= op->nframes) +-- +2.35.1 + diff --git a/queue-5.10/can-rx-offload-can_rx_offload_init_queue-fix-typo.patch b/queue-5.10/can-rx-offload-can_rx_offload_init_queue-fix-typo.patch new file mode 100644 index 00000000000..3eb6524c119 --- /dev/null +++ b/queue-5.10/can-rx-offload-can_rx_offload_init_queue-fix-typo.patch @@ -0,0 +1,39 @@ +From 7cd0eb7815455bd37b0d559d76a98e8ad03200b5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Aug 2022 21:38:00 +0200 +Subject: can: rx-offload: can_rx_offload_init_queue(): fix typo +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marc Kleine-Budde + +[ Upstream commit 766108d91246530d31b42765046f7ec2d1e42581 ] + +Fix typo "rounted" -> "rounded". + +Link: https://lore.kernel.org/all/20220811093617.1861938-2-mkl@pengutronix.de +Fixes: d254586c3453 ("can: rx-offload: Add support for HW fifo based irq offloading") +Reported-by: Uwe Kleine-König +Signed-off-by: Marc Kleine-Budde +Signed-off-by: Sasha Levin +--- + drivers/net/can/dev/rx-offload.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/can/dev/rx-offload.c b/drivers/net/can/dev/rx-offload.c +index 6e95193b215b..cee6ceae2158 100644 +--- a/drivers/net/can/dev/rx-offload.c ++++ b/drivers/net/can/dev/rx-offload.c +@@ -307,7 +307,7 @@ static int can_rx_offload_init_queue(struct net_device *dev, + { + offload->dev = dev; + +- /* Limit queue len to 4x the weight (rounted to next power of two) */ ++ /* Limit queue len to 4x the weight (rounded to next power of two) */ + offload->skb_queue_len_max = 2 << fls(weight); + offload->skb_queue_len_max *= 4; + skb_queue_head_init(&offload->skb_queue); +-- +2.35.1 + diff --git a/queue-5.10/cgroup-cpuset-enable-update_tasks_cpumask-on-top_cpu.patch b/queue-5.10/cgroup-cpuset-enable-update_tasks_cpumask-on-top_cpu.patch new file mode 100644 index 00000000000..1ff8bdfe3bc --- /dev/null +++ b/queue-5.10/cgroup-cpuset-enable-update_tasks_cpumask-on-top_cpu.patch @@ -0,0 +1,71 @@ +From 0065d144fa31dcc53966cd1d95583e3f8a2878de Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 16:57:36 -0400 +Subject: cgroup/cpuset: Enable update_tasks_cpumask() on top_cpuset + +From: Waiman Long + +[ Upstream commit ec5fbdfb99d18482619ac42605cb80fbb56068ee ] + +Previously, update_tasks_cpumask() is not supposed to be called with +top cpuset. With cpuset partition that takes CPUs away from the top +cpuset, adjusting the cpus_mask of the tasks in the top cpuset is +necessary. Percpu kthreads, however, are ignored. + +Fixes: ee8dde0cd2ce ("cpuset: Add new v2 cpuset.sched.partition flag") +Signed-off-by: Waiman Long +Signed-off-by: Tejun Heo +Signed-off-by: Sasha Levin +--- + kernel/cgroup/cpuset.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c +index b7830f1f1f3a..43270b07b2e0 100644 +--- a/kernel/cgroup/cpuset.c ++++ b/kernel/cgroup/cpuset.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1059,10 +1060,18 @@ static void update_tasks_cpumask(struct cpuset *cs) + { + struct css_task_iter it; + struct task_struct *task; ++ bool top_cs = cs == &top_cpuset; + + css_task_iter_start(&cs->css, 0, &it); +- while ((task = css_task_iter_next(&it))) ++ while ((task = css_task_iter_next(&it))) { ++ /* ++ * Percpu kthreads in top_cpuset are ignored ++ */ ++ if (top_cs && (task->flags & PF_KTHREAD) && ++ kthread_is_per_cpu(task)) ++ continue; + set_cpus_allowed_ptr(task, cs->effective_cpus); ++ } + css_task_iter_end(&it); + } + +@@ -2016,12 +2025,7 @@ static int update_prstate(struct cpuset *cs, int new_prs) + update_flag(CS_CPU_EXCLUSIVE, cs, 0); + } + +- /* +- * Update cpumask of parent's tasks except when it is the top +- * cpuset as some system daemons cannot be mapped to other CPUs. +- */ +- if (parent != &top_cpuset) +- update_tasks_cpumask(parent); ++ update_tasks_cpumask(parent); + + if (parent->child_ecpus_count) + update_sibling_cpumasks(parent, cs, &tmpmask); +-- +2.35.1 + diff --git a/queue-5.10/cgroup-honor-caller-s-cgroup-ns-when-resolving-path.patch b/queue-5.10/cgroup-honor-caller-s-cgroup-ns-when-resolving-path.patch new file mode 100644 index 00000000000..1b09409bb3a --- /dev/null +++ b/queue-5.10/cgroup-honor-caller-s-cgroup-ns-when-resolving-path.patch @@ -0,0 +1,49 @@ +From 9d8503d8acddd2f9ecb8fa58ac2b1c2a0d49b791 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 18:52:35 +0200 +Subject: cgroup: Honor caller's cgroup NS when resolving path +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michal Koutný + +[ Upstream commit 74e4b956eb1cac0e4c10c240339b1bbfbc9a4c48 ] + +cgroup_get_from_path() is not widely used function. Its callers presume +the path is resolved under cgroup namespace. (There is one caller +currently and resolving in init NS won't make harm (netfilter). However, +future users may be subject to different effects when resolving +globally.) +Since, there's currently no use for the global resolution, modify the +existing function to take cgroup NS into account. + +Fixes: a79a908fd2b0 ("cgroup: introduce cgroup namespaces") +Signed-off-by: Michal Koutný +Signed-off-by: Tejun Heo +Signed-off-by: Sasha Levin +--- + kernel/cgroup/cgroup.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c +index f0da7cfe5a34..312a63f328ec 100644 +--- a/kernel/cgroup/cgroup.c ++++ b/kernel/cgroup/cgroup.c +@@ -6476,8 +6476,12 @@ struct cgroup *cgroup_get_from_path(const char *path) + { + struct kernfs_node *kn; + struct cgroup *cgrp = ERR_PTR(-ENOENT); ++ struct cgroup *root_cgrp; + +- kn = kernfs_walk_and_get(cgrp_dfl_root.cgrp.kn, path); ++ spin_lock_irq(&css_set_lock); ++ root_cgrp = current_cgns_cgroup_from_root(&cgrp_dfl_root); ++ kn = kernfs_walk_and_get(root_cgrp->kn, path); ++ spin_unlock_irq(&css_set_lock); + if (!kn) + goto out; + +-- +2.35.1 + diff --git a/queue-5.10/cgroup-reduce-dependency-on-cgroup_mutex.patch b/queue-5.10/cgroup-reduce-dependency-on-cgroup_mutex.patch new file mode 100644 index 00000000000..6e71d76cdd7 --- /dev/null +++ b/queue-5.10/cgroup-reduce-dependency-on-cgroup_mutex.patch @@ -0,0 +1,114 @@ +From 5bb3078936faa526a813cb7a10de42467cb6bc43 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 24 Oct 2021 23:19:14 -0700 +Subject: cgroup: reduce dependency on cgroup_mutex + +From: Shakeel Butt + +[ Upstream commit be288169712f3dea0bc6b50c00b3ab53d85f1435 ] + +Currently cgroup_get_from_path() and cgroup_get_from_id() grab +cgroup_mutex before traversing the default hierarchy to find the +kernfs_node corresponding to the path/id and then extract the linked +cgroup. Since cgroup_mutex is still held, it is guaranteed that the +cgroup will be alive and the reference can be taken on it. + +However similar guarantee can be provided without depending on the +cgroup_mutex and potentially reducing avenues of cgroup_mutex contentions. +The kernfs_node's priv pointer is RCU protected pointer and with just +rcu read lock we can grab the reference on the cgroup without +cgroup_mutex. So, remove cgroup_mutex from them. + +Signed-off-by: Shakeel Butt +Signed-off-by: Tejun Heo +Stable-dep-of: 74e4b956eb1c ("cgroup: Honor caller's cgroup NS when resolving path") +Signed-off-by: Sasha Levin +--- + kernel/cgroup/cgroup.c | 51 ++++++++++++++++++++++++------------------ + 1 file changed, 29 insertions(+), 22 deletions(-) + +diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c +index c420b048466b..f0da7cfe5a34 100644 +--- a/kernel/cgroup/cgroup.c ++++ b/kernel/cgroup/cgroup.c +@@ -5932,17 +5932,20 @@ struct cgroup *cgroup_get_from_id(u64 id) + struct kernfs_node *kn; + struct cgroup *cgrp = NULL; + +- mutex_lock(&cgroup_mutex); + kn = kernfs_find_and_get_node_by_id(cgrp_dfl_root.kf_root, id); + if (!kn) +- goto out_unlock; ++ goto out; ++ ++ rcu_read_lock(); + +- cgrp = kn->priv; +- if (cgroup_is_dead(cgrp) || !cgroup_tryget(cgrp)) ++ cgrp = rcu_dereference(*(void __rcu __force **)&kn->priv); ++ if (cgrp && !cgroup_tryget(cgrp)) + cgrp = NULL; ++ ++ rcu_read_unlock(); ++ + kernfs_put(kn); +-out_unlock: +- mutex_unlock(&cgroup_mutex); ++out: + return cgrp; + } + EXPORT_SYMBOL_GPL(cgroup_get_from_id); +@@ -6466,30 +6469,34 @@ struct cgroup_subsys_state *css_from_id(int id, struct cgroup_subsys *ss) + * + * Find the cgroup at @path on the default hierarchy, increment its + * reference count and return it. Returns pointer to the found cgroup on +- * success, ERR_PTR(-ENOENT) if @path doesn't exist and ERR_PTR(-ENOTDIR) +- * if @path points to a non-directory. ++ * success, ERR_PTR(-ENOENT) if @path doesn't exist or if the cgroup has already ++ * been released and ERR_PTR(-ENOTDIR) if @path points to a non-directory. + */ + struct cgroup *cgroup_get_from_path(const char *path) + { + struct kernfs_node *kn; +- struct cgroup *cgrp; +- +- mutex_lock(&cgroup_mutex); ++ struct cgroup *cgrp = ERR_PTR(-ENOENT); + + kn = kernfs_walk_and_get(cgrp_dfl_root.cgrp.kn, path); +- if (kn) { +- if (kernfs_type(kn) == KERNFS_DIR) { +- cgrp = kn->priv; +- cgroup_get_live(cgrp); +- } else { +- cgrp = ERR_PTR(-ENOTDIR); +- } +- kernfs_put(kn); +- } else { +- cgrp = ERR_PTR(-ENOENT); ++ if (!kn) ++ goto out; ++ ++ if (kernfs_type(kn) != KERNFS_DIR) { ++ cgrp = ERR_PTR(-ENOTDIR); ++ goto out_kernfs; + } + +- mutex_unlock(&cgroup_mutex); ++ rcu_read_lock(); ++ ++ cgrp = rcu_dereference(*(void __rcu __force **)&kn->priv); ++ if (!cgrp || !cgroup_tryget(cgrp)) ++ cgrp = ERR_PTR(-ENOENT); ++ ++ rcu_read_unlock(); ++ ++out_kernfs: ++ kernfs_put(kn); ++out: + return cgrp; + } + EXPORT_SYMBOL_GPL(cgroup_get_from_path); +-- +2.35.1 + diff --git a/queue-5.10/clk-ast2600-bclk-comes-from-epll.patch b/queue-5.10/clk-ast2600-bclk-comes-from-epll.patch new file mode 100644 index 00000000000..b18fbb249fa --- /dev/null +++ b/queue-5.10/clk-ast2600-bclk-comes-from-epll.patch @@ -0,0 +1,38 @@ +From 027475606dc6b7186aa7c2941d23d911bcfc6f9b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Apr 2022 13:34:26 +0930 +Subject: clk: ast2600: BCLK comes from EPLL + +From: Joel Stanley + +[ Upstream commit b8c1dc9c00b252b3be853720a71b05ed451ddd9f ] + +This correction was made in the u-boot SDK recently. There are no +in-tree users of this clock so the impact is minimal. + +Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") +Link: https://github.com/AspeedTech-BMC/u-boot/commit/8ad54a5ae15f27fea5e894cc2539a20d90019717 +Signed-off-by: Joel Stanley +Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.au +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-ast2600.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c +index 24dab2312bc6..9c3305bcb27a 100644 +--- a/drivers/clk/clk-ast2600.c ++++ b/drivers/clk/clk-ast2600.c +@@ -622,7 +622,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) + regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */ + + /* P-Bus (BCLK) clock divider */ +- hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, ++ hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, + ast2600_div_table, + &aspeed_g6_clk_lock); +-- +2.35.1 + diff --git a/queue-5.10/clk-baikal-t1-add-sata-internal-ref-clock-buffer.patch b/queue-5.10/clk-baikal-t1-add-sata-internal-ref-clock-buffer.patch new file mode 100644 index 00000000000..2c1bec85f03 --- /dev/null +++ b/queue-5.10/clk-baikal-t1-add-sata-internal-ref-clock-buffer.patch @@ -0,0 +1,234 @@ +From 7a9d5dedd10bf1771b90ca5b1806f0a3362304c3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 01:53:58 +0300 +Subject: clk: baikal-t1: Add SATA internal ref clock buffer + +From: Serge Semin + +[ Upstream commit 081a9b7c74eae4e12b2cb1b86720f836a8f29247 ] + +It turns out the internal SATA reference clock signal will stay +unavailable for the SATA interface consumer until the buffer on it's way +is ungated. So aside with having the actual clock divider enabled we need +to ungate a buffer placed on the signal way to the SATA controller (most +likely some rudiment from the initial SoC release). Seeing the switch flag +is placed in the same register as the SATA-ref clock divider at a +non-standard ffset, let's implement it as a separate clock controller with +the set-rate propagation to the parental clock divider wrapper. As such +we'll be able to disable/enable and still change the original clock source +rate. + +Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") +Signed-off-by: Serge Semin +Link: https://lore.kernel.org/r/20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/baikal-t1/ccu-div.c | 64 +++++++++++++++++++++++++++++ + drivers/clk/baikal-t1/ccu-div.h | 4 ++ + drivers/clk/baikal-t1/clk-ccu-div.c | 18 +++++++- + 3 files changed, 85 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c +index bbfa3526ee10..a6642f3d33d4 100644 +--- a/drivers/clk/baikal-t1/ccu-div.c ++++ b/drivers/clk/baikal-t1/ccu-div.c +@@ -34,6 +34,7 @@ + #define CCU_DIV_CTL_CLKDIV_MASK(_width) \ + GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD) + #define CCU_DIV_CTL_LOCK_SHIFTED BIT(27) ++#define CCU_DIV_CTL_GATE_REF_BUF BIT(28) + #define CCU_DIV_CTL_LOCK_NORMAL BIT(31) + + #define CCU_DIV_RST_DELAY_US 1 +@@ -170,6 +171,40 @@ static int ccu_div_gate_is_enabled(struct clk_hw *hw) + return !!(val & CCU_DIV_CTL_EN); + } + ++static int ccu_div_buf_enable(struct clk_hw *hw) ++{ ++ struct ccu_div *div = to_ccu_div(hw); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&div->lock, flags); ++ regmap_update_bits(div->sys_regs, div->reg_ctl, ++ CCU_DIV_CTL_GATE_REF_BUF, 0); ++ spin_unlock_irqrestore(&div->lock, flags); ++ ++ return 0; ++} ++ ++static void ccu_div_buf_disable(struct clk_hw *hw) ++{ ++ struct ccu_div *div = to_ccu_div(hw); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&div->lock, flags); ++ regmap_update_bits(div->sys_regs, div->reg_ctl, ++ CCU_DIV_CTL_GATE_REF_BUF, CCU_DIV_CTL_GATE_REF_BUF); ++ spin_unlock_irqrestore(&div->lock, flags); ++} ++ ++static int ccu_div_buf_is_enabled(struct clk_hw *hw) ++{ ++ struct ccu_div *div = to_ccu_div(hw); ++ u32 val = 0; ++ ++ regmap_read(div->sys_regs, div->reg_ctl, &val); ++ ++ return !(val & CCU_DIV_CTL_GATE_REF_BUF); ++} ++ + static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { +@@ -323,6 +358,7 @@ static const struct ccu_div_dbgfs_bit ccu_div_bits[] = { + CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN), + CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST), + CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV), ++ CCU_DIV_DBGFS_BIT_ATTR("div_buf", CCU_DIV_CTL_GATE_REF_BUF), + CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL) + }; + +@@ -441,6 +477,9 @@ static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry) + continue; + } + ++ if (!strcmp("div_buf", name)) ++ continue; ++ + bits[didx] = ccu_div_bits[bidx]; + bits[didx].div = div; + +@@ -477,6 +516,21 @@ static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry) + &ccu_div_dbgfs_fixed_clkdiv_fops); + } + ++static void ccu_div_buf_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ struct ccu_div *div = to_ccu_div(hw); ++ struct ccu_div_dbgfs_bit *bit; ++ ++ bit = kmalloc(sizeof(*bit), GFP_KERNEL); ++ if (!bit) ++ return; ++ ++ *bit = ccu_div_bits[3]; ++ bit->div = div; ++ debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit, ++ &ccu_div_dbgfs_bit_fops); ++} ++ + static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry) + { + struct ccu_div *div = to_ccu_div(hw); +@@ -489,6 +543,7 @@ static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry) + + #define ccu_div_var_debug_init NULL + #define ccu_div_gate_debug_init NULL ++#define ccu_div_buf_debug_init NULL + #define ccu_div_fixed_debug_init NULL + + #endif /* !CONFIG_DEBUG_FS */ +@@ -520,6 +575,13 @@ static const struct clk_ops ccu_div_gate_ops = { + .debug_init = ccu_div_gate_debug_init + }; + ++static const struct clk_ops ccu_div_buf_ops = { ++ .enable = ccu_div_buf_enable, ++ .disable = ccu_div_buf_disable, ++ .is_enabled = ccu_div_buf_is_enabled, ++ .debug_init = ccu_div_buf_debug_init ++}; ++ + static const struct clk_ops ccu_div_fixed_ops = { + .recalc_rate = ccu_div_fixed_recalc_rate, + .round_rate = ccu_div_fixed_round_rate, +@@ -566,6 +628,8 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init) + } else if (div_init->type == CCU_DIV_GATE) { + hw_init.ops = &ccu_div_gate_ops; + div->divider = div_init->divider; ++ } else if (div_init->type == CCU_DIV_BUF) { ++ hw_init.ops = &ccu_div_buf_ops; + } else if (div_init->type == CCU_DIV_FIXED) { + hw_init.ops = &ccu_div_fixed_ops; + div->divider = div_init->divider; +diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h +index b6a9c8e45318..4eb49ff4803c 100644 +--- a/drivers/clk/baikal-t1/ccu-div.h ++++ b/drivers/clk/baikal-t1/ccu-div.h +@@ -15,8 +15,10 @@ + + /* + * CCU Divider private clock IDs ++ * @CCU_SYS_SATA_CLK: CCU SATA internal clock + * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock + */ ++#define CCU_SYS_SATA_CLK -1 + #define CCU_SYS_XGMAC_CLK -2 + + /* +@@ -37,11 +39,13 @@ + * enum ccu_div_type - CCU Divider types + * @CCU_DIV_VAR: Clocks gate with variable divider. + * @CCU_DIV_GATE: Clocks gate with fixed divider. ++ * @CCU_DIV_BUF: Clock gate with no divider. + * @CCU_DIV_FIXED: Ungateable clock with fixed divider. + */ + enum ccu_div_type { + CCU_DIV_VAR, + CCU_DIV_GATE, ++ CCU_DIV_BUF, + CCU_DIV_FIXED + }; + +diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c +index 3953ae5664be..90f4fda406ee 100644 +--- a/drivers/clk/baikal-t1/clk-ccu-div.c ++++ b/drivers/clk/baikal-t1/clk-ccu-div.c +@@ -76,6 +76,16 @@ + .divider = _divider \ + } + ++#define CCU_DIV_BUF_INFO(_id, _name, _pname, _base, _flags) \ ++ { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _pname, \ ++ .base = _base, \ ++ .type = CCU_DIV_BUF, \ ++ .flags = _flags \ ++ } ++ + #define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \ + { \ + .id = _id, \ +@@ -188,11 +198,14 @@ static const struct ccu_div_rst_map axi_rst_map[] = { + * for the SoC devices registers IO-operations. + */ + static const struct ccu_div_info sys_info[] = { +- CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk", ++ CCU_DIV_VAR_INFO(CCU_SYS_SATA_CLK, "sys_sata_clk", + "sata_clk", CCU_SYS_SATA_REF_BASE, 4, + CLK_SET_RATE_GATE, + CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED | + CCU_DIV_RESET_DOMAIN), ++ CCU_DIV_BUF_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk", ++ "sys_sata_clk", CCU_SYS_SATA_REF_BASE, ++ CLK_SET_RATE_PARENT), + CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk", + "pcie_clk", CCU_SYS_APB_BASE, 5, + CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN), +@@ -398,6 +411,9 @@ static int ccu_div_clk_register(struct ccu_div_data *data) + init.base = info->base; + init.sys_regs = data->sys_regs; + init.divider = info->divider; ++ } else if (init.type == CCU_DIV_BUF) { ++ init.base = info->base; ++ init.sys_regs = data->sys_regs; + } else { + init.divider = info->divider; + } +-- +2.35.1 + diff --git a/queue-5.10/clk-baikal-t1-add-shared-xgmac-ref-ptp-clocks-intern.patch b/queue-5.10/clk-baikal-t1-add-shared-xgmac-ref-ptp-clocks-intern.patch new file mode 100644 index 00000000000..11430e9ec41 --- /dev/null +++ b/queue-5.10/clk-baikal-t1-add-shared-xgmac-ref-ptp-clocks-intern.patch @@ -0,0 +1,84 @@ +From c2124e08c619fe5f0b337f7fca9d685a275e337b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 01:53:57 +0300 +Subject: clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent + +From: Serge Semin + +[ Upstream commit e2eef312762e0b5a5a70d29fe59a245c0a3cffa0 ] + +Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC +PTP clocks are generated by two different wrappers with the same constant +divider thus each producing a 156.25 MHz signal. But for some reason both +of these clock sources are gated by a single switch-flag in the CCU +registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks +handled independently we need to define a shared parental gate so the base +clock signal would be switched off only if both of the child-clocks are +disabled. + +Note the ID is intentionally set to -2 since we are going to add a one +more internal clock identifier in the next commit. + +Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") +Signed-off-by: Serge Semin +Link: https://lore.kernel.org/r/20220929225402.9696-4-Sergey.Semin@baikalelectronics.ru +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/baikal-t1/ccu-div.c | 1 + + drivers/clk/baikal-t1/ccu-div.h | 6 ++++++ + drivers/clk/baikal-t1/clk-ccu-div.c | 8 +++++--- + 3 files changed, 12 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c +index 4062092d67f9..bbfa3526ee10 100644 +--- a/drivers/clk/baikal-t1/ccu-div.c ++++ b/drivers/clk/baikal-t1/ccu-div.c +@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init) + goto err_free_div; + } + parent_data.fw_name = div_init->parent_name; ++ parent_data.name = div_init->parent_name; + hw_init.parent_data = &parent_data; + hw_init.num_parents = 1; + +diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h +index 795665caefbd..b6a9c8e45318 100644 +--- a/drivers/clk/baikal-t1/ccu-div.h ++++ b/drivers/clk/baikal-t1/ccu-div.h +@@ -13,6 +13,12 @@ + #include + #include + ++/* ++ * CCU Divider private clock IDs ++ * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock ++ */ ++#define CCU_SYS_XGMAC_CLK -2 ++ + /* + * CCU Divider private flags + * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1. +diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c +index ea77eec40ddd..3953ae5664be 100644 +--- a/drivers/clk/baikal-t1/clk-ccu-div.c ++++ b/drivers/clk/baikal-t1/clk-ccu-div.c +@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = { + "eth_clk", CCU_SYS_GMAC1_BASE, 5), + CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk", + "eth_clk", 10), +- CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk", +- "eth_clk", CCU_SYS_XGMAC_BASE, 8), ++ CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk", ++ "eth_clk", CCU_SYS_XGMAC_BASE, 1), ++ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk", ++ "sys_xgmac_clk", 8), + CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk", +- "eth_clk", 8), ++ "sys_xgmac_clk", 8), + CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk", + "eth_clk", CCU_SYS_USB_BASE, 10), + CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk", +-- +2.35.1 + diff --git a/queue-5.10/clk-baikal-t1-fix-invalid-xgmac-ptp-clock-divider.patch b/queue-5.10/clk-baikal-t1-fix-invalid-xgmac-ptp-clock-divider.patch new file mode 100644 index 00000000000..622fb976bf7 --- /dev/null +++ b/queue-5.10/clk-baikal-t1-fix-invalid-xgmac-ptp-clock-divider.patch @@ -0,0 +1,38 @@ +From bc82b02cb740fbca2a50fe4d6c4f56e6c9082eb4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 01:53:56 +0300 +Subject: clk: baikal-t1: Fix invalid xGMAC PTP clock divider + +From: Serge Semin + +[ Upstream commit 3c742088686ce922704aec5b11d09bcc5a396589 ] + +Most likely due to copy-paste mistake the divider has been set to 10 while +according to the SoC reference manual it's supposed to be 8 thus having +PTP clock frequency of 156.25 MHz. + +Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") +Signed-off-by: Serge Semin +Link: https://lore.kernel.org/r/20220929225402.9696-3-Sergey.Semin@baikalelectronics.ru +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/baikal-t1/clk-ccu-div.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c +index f141fda12b09..ea77eec40ddd 100644 +--- a/drivers/clk/baikal-t1/clk-ccu-div.c ++++ b/drivers/clk/baikal-t1/clk-ccu-div.c +@@ -207,7 +207,7 @@ static const struct ccu_div_info sys_info[] = { + CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk", + "eth_clk", CCU_SYS_XGMAC_BASE, 8), + CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk", +- "eth_clk", 10), ++ "eth_clk", 8), + CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk", + "eth_clk", CCU_SYS_USB_BASE, 10), + CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk", +-- +2.35.1 + diff --git a/queue-5.10/clk-bcm2835-fix-bcm2835_clock_rate_from_divisor-decl.patch b/queue-5.10/clk-bcm2835-fix-bcm2835_clock_rate_from_divisor-decl.patch new file mode 100644 index 00000000000..be5e7cda9f2 --- /dev/null +++ b/queue-5.10/clk-bcm2835-fix-bcm2835_clock_rate_from_divisor-decl.patch @@ -0,0 +1,43 @@ +From e20500ceb230f766aa3f5913ac30620f558e7879 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 16:10:37 +0200 +Subject: clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration + +From: Stefan Wahren + +[ Upstream commit 0b919a3728691c172312dee99ba654055ccd8c84 ] + +The return value of bcm2835_clock_rate_from_divisor is always unsigned +and also all caller expect this. So fix the declaration accordingly. + +Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") +Signed-off-by: Stefan Wahren +Link: https://lore.kernel.org/r/20220904141037.38816-1-stefan.wahren@i2se.com +Reviewed-by: Ivan T. Ivanov +Reviewed-by: Florian Fainelli +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/bcm/clk-bcm2835.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c +index 178886823b90..f306b959297d 100644 +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -968,9 +968,9 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw, + return div; + } + +-static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, +- unsigned long parent_rate, +- u32 div) ++static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, ++ unsigned long parent_rate, ++ u32 div) + { + const struct bcm2835_clock_data *data = clock->data; + u64 temp; +-- +2.35.1 + diff --git a/queue-5.10/clk-bcm2835-make-peripheral-pllc-critical.patch b/queue-5.10/clk-bcm2835-make-peripheral-pllc-critical.patch new file mode 100644 index 00000000000..499d7ef561b --- /dev/null +++ b/queue-5.10/clk-bcm2835-make-peripheral-pllc-critical.patch @@ -0,0 +1,50 @@ +From 10bc7b200a590fd4cccdbfeb24aecf258b219ba1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 10:45:09 +0200 +Subject: clk: bcm2835: Make peripheral PLLC critical +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Maxime Ripard + +[ Upstream commit 6c5422851d8be8c7451e968fd2e6da41b6109e17 ] + +When testing for a series affecting the VEC, it was discovered that +turning off and on the VEC clock is crashing the system. + +It turns out that, when disabling the VEC clock, it's the only child of +the PLLC-per clock which will also get disabled. The source of the crash +is PLLC-per being disabled. + +It's likely that some other device might not take a clock reference that +it actually needs, but it's unclear which at this point. Let's make +PLLC-per critical so that we don't have that crash. + +Reported-by: Noralf Trønnes +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20220926084509.12233-1-maxime@cerno.tech +Reviewed-by: Stefan Wahren +Acked-by: Noralf Trønnes +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/bcm/clk-bcm2835.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c +index f306b959297d..b7f89873fcf5 100644 +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -1786,7 +1786,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .load_mask = CM_PLLC_LOADPER, + .hold_mask = CM_PLLC_HOLDPER, + .fixed_divider = 1, +- .flags = CLK_SET_RATE_PARENT), ++ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + + /* + * PLLD is the display PLL, used to drive DSI display panels. +-- +2.35.1 + diff --git a/queue-5.10/clk-berlin-add-of_node_put-for-of_get_parent.patch b/queue-5.10/clk-berlin-add-of_node_put-for-of_get_parent.patch new file mode 100644 index 00000000000..5ddcef3c113 --- /dev/null +++ b/queue-5.10/clk-berlin-add-of_node_put-for-of_get_parent.patch @@ -0,0 +1,77 @@ +From aa2c7dba542303fa8e796ed3b7cca84549c7bd9d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Jul 2022 16:49:00 +0800 +Subject: clk: berlin: Add of_node_put() for of_get_parent() + +From: Liang He + +[ Upstream commit 37c381b812dcbfde9c3f1f3d3e75fdfc1b40d5bc ] + +In berlin2_clock_setup() and berlin2q_clock_setup(), we need to +call of_node_put() for the reference returned by of_get_parent() +which has increased the refcount. We should call *_put() in fail +path or when it is not used anymore. + +Fixes: 26b3b6b959b2 ("clk: berlin: prepare simple-mfd conversion") +Signed-off-by: Liang He +Link: https://lore.kernel.org/r/20220708084900.311684-1-windhl@126.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/berlin/bg2.c | 5 ++++- + drivers/clk/berlin/bg2q.c | 6 +++++- + 2 files changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c +index bccdfa00fd37..67a9edbba29c 100644 +--- a/drivers/clk/berlin/bg2.c ++++ b/drivers/clk/berlin/bg2.c +@@ -500,12 +500,15 @@ static void __init berlin2_clock_setup(struct device_node *np) + int n, ret; + + clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL); +- if (!clk_data) ++ if (!clk_data) { ++ of_node_put(parent_np); + return; ++ } + clk_data->num = MAX_CLKS; + hws = clk_data->hws; + + gbase = of_iomap(parent_np, 0); ++ of_node_put(parent_np); + if (!gbase) + return; + +diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c +index e9518d35f262..dd2784bb75b6 100644 +--- a/drivers/clk/berlin/bg2q.c ++++ b/drivers/clk/berlin/bg2q.c +@@ -286,19 +286,23 @@ static void __init berlin2q_clock_setup(struct device_node *np) + int n, ret; + + clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL); +- if (!clk_data) ++ if (!clk_data) { ++ of_node_put(parent_np); + return; ++ } + clk_data->num = MAX_CLKS; + hws = clk_data->hws; + + gbase = of_iomap(parent_np, 0); + if (!gbase) { ++ of_node_put(parent_np); + pr_err("%pOF: Unable to map global base\n", np); + return; + } + + /* BG2Q CPU PLL is not part of global registers */ + cpupll_base = of_iomap(parent_np, 1); ++ of_node_put(parent_np); + if (!cpupll_base) { + pr_err("%pOF: Unable to map cpupll base\n", np); + iounmap(gbase); +-- +2.35.1 + diff --git a/queue-5.10/clk-generalize-devm_clk_get-a-bit.patch b/queue-5.10/clk-generalize-devm_clk_get-a-bit.patch new file mode 100644 index 00000000000..f25db7a7a38 --- /dev/null +++ b/queue-5.10/clk-generalize-devm_clk_get-a-bit.patch @@ -0,0 +1,124 @@ +From 2e8aa64321308cb222564b49311dffe42d4e98a3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 May 2022 09:57:35 +0200 +Subject: clk: generalize devm_clk_get() a bit +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit abae8e57e49aa75f6db76aa866c775721523908f ] + +Allow to add an exit hook to devm managed clocks. Also use +clk_get_optional() in devm_clk_get_optional instead of open coding it. +The generalisation will be used in the next commit to add some more +devm_clk helpers. + +Reviewed-by: Jonathan Cameron +Reviewed-by: Alexandru Ardelean +Signed-off-by: Uwe Kleine-König +Link: https://lore.kernel.org/r/20220520075737.758761-3-u.kleine-koenig@pengutronix.de +Signed-off-by: Stephen Boyd +Stable-dep-of: 10a2199caf43 ("hwrng: imx-rngc - Moving IRQ handler registering after imx_rngc_irq_mask_clear()") +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-devres.c | 66 +++++++++++++++++++++++++++++----------- + 1 file changed, 49 insertions(+), 17 deletions(-) + +diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c +index f9d5b7334341..c822f4ef1584 100644 +--- a/drivers/clk/clk-devres.c ++++ b/drivers/clk/clk-devres.c +@@ -4,39 +4,71 @@ + #include + #include + ++struct devm_clk_state { ++ struct clk *clk; ++ void (*exit)(struct clk *clk); ++}; ++ + static void devm_clk_release(struct device *dev, void *res) + { +- clk_put(*(struct clk **)res); ++ struct devm_clk_state *state = *(struct devm_clk_state **)res; ++ ++ if (state->exit) ++ state->exit(state->clk); ++ ++ clk_put(state->clk); + } + +-struct clk *devm_clk_get(struct device *dev, const char *id) ++static struct clk *__devm_clk_get(struct device *dev, const char *id, ++ struct clk *(*get)(struct device *dev, const char *id), ++ int (*init)(struct clk *clk), ++ void (*exit)(struct clk *clk)) + { +- struct clk **ptr, *clk; ++ struct devm_clk_state *state; ++ struct clk *clk; ++ int ret; + +- ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL); +- if (!ptr) ++ state = devres_alloc(devm_clk_release, sizeof(*state), GFP_KERNEL); ++ if (!state) + return ERR_PTR(-ENOMEM); + +- clk = clk_get(dev, id); +- if (!IS_ERR(clk)) { +- *ptr = clk; +- devres_add(dev, ptr); +- } else { +- devres_free(ptr); ++ clk = get(dev, id); ++ if (IS_ERR(clk)) { ++ ret = PTR_ERR(clk); ++ goto err_clk_get; + } + ++ if (init) { ++ ret = init(clk); ++ if (ret) ++ goto err_clk_init; ++ } ++ ++ state->clk = clk; ++ state->exit = exit; ++ ++ devres_add(dev, state); ++ + return clk; ++ ++err_clk_init: ++ ++ clk_put(clk); ++err_clk_get: ++ ++ devres_free(state); ++ return ERR_PTR(ret); ++} ++ ++struct clk *devm_clk_get(struct device *dev, const char *id) ++{ ++ return __devm_clk_get(dev, id, clk_get, NULL, NULL); + } + EXPORT_SYMBOL(devm_clk_get); + + struct clk *devm_clk_get_optional(struct device *dev, const char *id) + { +- struct clk *clk = devm_clk_get(dev, id); +- +- if (clk == ERR_PTR(-ENOENT)) +- return NULL; +- +- return clk; ++ return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL); + } + EXPORT_SYMBOL(devm_clk_get_optional); + +-- +2.35.1 + diff --git a/queue-5.10/clk-mediatek-mt8183-mfgcfg-propagate-rate-changes-to.patch b/queue-5.10/clk-mediatek-mt8183-mfgcfg-propagate-rate-changes-to.patch new file mode 100644 index 00000000000..10a16d8b695 --- /dev/null +++ b/queue-5.10/clk-mediatek-mt8183-mfgcfg-propagate-rate-changes-to.patch @@ -0,0 +1,44 @@ +From bfa692c994af6a49f47027509ef9abe959a3a3e2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 27 Sep 2022 12:11:20 +0200 +Subject: clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent + +From: Chen-Yu Tsai + +[ Upstream commit 9f94f545f258b15bfa6357eb62e1e307b712851e ] + +The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its +rate change requests to its parent, so that DVFS for the GPU can work +properly. + +Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") +Signed-off-by: Chen-Yu Tsai +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Sasha Levin +--- + drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +index 37b4162c5882..3a33014eee7f 100644 +--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c ++++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +@@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs = { + .sta_ofs = 0x0, + }; + +-#define GATE_MFG(_id, _name, _parent, _shift) \ +- GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ +- &mtk_clk_gate_ops_setclr) ++#define GATE_MFG(_id, _name, _parent, _shift) \ ++ GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ ++ &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) + + static const struct mtk_gate mfg_clks[] = { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0) +-- +2.35.1 + diff --git a/queue-5.10/clk-meson-hold-reference-returned-by-of_get_parent.patch b/queue-5.10/clk-meson-hold-reference-returned-by-of_get_parent.patch new file mode 100644 index 00000000000..7074d916df6 --- /dev/null +++ b/queue-5.10/clk-meson-hold-reference-returned-by-of_get_parent.patch @@ -0,0 +1,99 @@ +From 16116ac9ef30f94f1a274d879948324d28758540 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 22:10:38 +0800 +Subject: clk: meson: Hold reference returned by of_get_parent() + +From: Liang He + +[ Upstream commit 89ab396d712f7c91fe94f55cff23460426f5fc81 ] + +We should hold the reference returned by of_get_parent() and use it +to call of_node_put() for refcount balance. + +Fixes: 88e2da81241e ("clk: meson: aoclk: refactor common code into dedicated file") +Fixes: 6682bd4d443f ("clk: meson: factorise meson64 peripheral clock controller drivers") +Fixes: bb6eddd1d28c ("clk: meson: meson8b: use the HHI syscon if available") + +Signed-off-by: Liang He +Link: https://lore.kernel.org/r/20220628141038.168383-1-windhl@126.com +Reviewed-by: Neil Armstrong +Reviewed-by: Martin Blumenstingl +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/meson/meson-aoclk.c | 5 ++++- + drivers/clk/meson/meson-eeclk.c | 5 ++++- + drivers/clk/meson/meson8b.c | 5 ++++- + 3 files changed, 12 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c +index 3a6d84cd6601..67d8a0d30221 100644 +--- a/drivers/clk/meson/meson-aoclk.c ++++ b/drivers/clk/meson/meson-aoclk.c +@@ -36,6 +36,7 @@ int meson_aoclkc_probe(struct platform_device *pdev) + struct meson_aoclk_reset_controller *rstc; + struct meson_aoclk_data *data; + struct device *dev = &pdev->dev; ++ struct device_node *np; + struct regmap *regmap; + int ret, clkid; + +@@ -47,7 +48,9 @@ int meson_aoclkc_probe(struct platform_device *pdev) + if (!rstc) + return -ENOMEM; + +- regmap = syscon_node_to_regmap(of_get_parent(dev->of_node)); ++ np = of_get_parent(dev->of_node); ++ regmap = syscon_node_to_regmap(np); ++ of_node_put(np); + if (IS_ERR(regmap)) { + dev_err(dev, "failed to get regmap\n"); + return PTR_ERR(regmap); +diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c +index a7cb1e7aedc4..18ae38787268 100644 +--- a/drivers/clk/meson/meson-eeclk.c ++++ b/drivers/clk/meson/meson-eeclk.c +@@ -17,6 +17,7 @@ int meson_eeclkc_probe(struct platform_device *pdev) + { + const struct meson_eeclkc_data *data; + struct device *dev = &pdev->dev; ++ struct device_node *np; + struct regmap *map; + int ret, i; + +@@ -25,7 +26,9 @@ int meson_eeclkc_probe(struct platform_device *pdev) + return -EINVAL; + + /* Get the hhi system controller node */ +- map = syscon_node_to_regmap(of_get_parent(dev->of_node)); ++ np = of_get_parent(dev->of_node); ++ map = syscon_node_to_regmap(np); ++ of_node_put(np); + if (IS_ERR(map)) { + dev_err(dev, + "failed to get HHI regmap\n"); +diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c +index 862f0756b50f..1da9d212f8b7 100644 +--- a/drivers/clk/meson/meson8b.c ++++ b/drivers/clk/meson/meson8b.c +@@ -3735,13 +3735,16 @@ static void __init meson8b_clkc_init_common(struct device_node *np, + struct clk_hw_onecell_data *clk_hw_onecell_data) + { + struct meson8b_clk_reset *rstc; ++ struct device_node *parent_np; + const char *notifier_clk_name; + struct clk *notifier_clk; + void __iomem *clk_base; + struct regmap *map; + int i, ret; + +- map = syscon_node_to_regmap(of_get_parent(np)); ++ parent_np = of_get_parent(np); ++ map = syscon_node_to_regmap(parent_np); ++ of_node_put(parent_np); + if (IS_ERR(map)) { + pr_info("failed to get HHI regmap - Trying obsolete regs\n"); + +-- +2.35.1 + diff --git a/queue-5.10/clk-oxnas-hold-reference-returned-by-of_get_parent.patch b/queue-5.10/clk-oxnas-hold-reference-returned-by-of_get_parent.patch new file mode 100644 index 00000000000..fb52fdbc6e7 --- /dev/null +++ b/queue-5.10/clk-oxnas-hold-reference-returned-by-of_get_parent.patch @@ -0,0 +1,49 @@ +From c9c2771130d43915a6a4eccbf40e2c10f03aa212 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 22:31:55 +0800 +Subject: clk: oxnas: Hold reference returned by of_get_parent() + +From: Liang He + +[ Upstream commit 1d6aa08c54cd0e005210ab8e3b1e92ede70f8a4f ] + +In oxnas_stdclk_probe(), we need to hold the reference returned by +of_get_parent() and use it to call of_node_put() for refcount +balance. + +Fixes: 0bbd72b4c64f ("clk: Add Oxford Semiconductor OXNAS Standard Clocks") +Signed-off-by: Liang He +Link: https://lore.kernel.org/r/20220628143155.170550-1-windhl@126.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-oxnas.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c +index 78d5ea669fea..2fe36f579ac5 100644 +--- a/drivers/clk/clk-oxnas.c ++++ b/drivers/clk/clk-oxnas.c +@@ -207,7 +207,7 @@ static const struct of_device_id oxnas_stdclk_dt_ids[] = { + + static int oxnas_stdclk_probe(struct platform_device *pdev) + { +- struct device_node *np = pdev->dev.of_node; ++ struct device_node *np = pdev->dev.of_node, *parent_np; + const struct oxnas_stdclk_data *data; + const struct of_device_id *id; + struct regmap *regmap; +@@ -219,7 +219,9 @@ static int oxnas_stdclk_probe(struct platform_device *pdev) + return -ENODEV; + data = id->data; + +- regmap = syscon_node_to_regmap(of_get_parent(np)); ++ parent_np = of_get_parent(np); ++ regmap = syscon_node_to_regmap(parent_np); ++ of_node_put(parent_np); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "failed to have parent regmap\n"); + return PTR_ERR(regmap); +-- +2.35.1 + diff --git a/queue-5.10/clk-provide-new-devm_clk-helpers-for-prepared-and-en.patch b/queue-5.10/clk-provide-new-devm_clk-helpers-for-prepared-and-en.patch new file mode 100644 index 00000000000..25643f6a758 --- /dev/null +++ b/queue-5.10/clk-provide-new-devm_clk-helpers-for-prepared-and-en.patch @@ -0,0 +1,214 @@ +From 5cdb42187f1e07e14a09a565710d05bf335f0a31 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 20 May 2022 09:57:36 +0200 +Subject: clk: Provide new devm_clk helpers for prepared and enabled clocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit 7ef9651e9792b08eb310c6beb202cbc947f43cab ] + +When a driver keeps a clock prepared (or enabled) during the whole +lifetime of the driver, these helpers allow to simplify the drivers. + +Reviewed-by: Jonathan Cameron +Reviewed-by: Alexandru Ardelean +Signed-off-by: Uwe Kleine-König +Link: https://lore.kernel.org/r/20220520075737.758761-4-u.kleine-koenig@pengutronix.de +Signed-off-by: Stephen Boyd +Stable-dep-of: 10a2199caf43 ("hwrng: imx-rngc - Moving IRQ handler registering after imx_rngc_irq_mask_clear()") +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-devres.c | 27 ++++++++++ + include/linux/clk.h | 109 +++++++++++++++++++++++++++++++++++++++ + 2 files changed, 136 insertions(+) + +diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c +index c822f4ef1584..43ccd20e0298 100644 +--- a/drivers/clk/clk-devres.c ++++ b/drivers/clk/clk-devres.c +@@ -66,12 +66,39 @@ struct clk *devm_clk_get(struct device *dev, const char *id) + } + EXPORT_SYMBOL(devm_clk_get); + ++struct clk *devm_clk_get_prepared(struct device *dev, const char *id) ++{ ++ return __devm_clk_get(dev, id, clk_get, clk_prepare, clk_unprepare); ++} ++EXPORT_SYMBOL_GPL(devm_clk_get_prepared); ++ ++struct clk *devm_clk_get_enabled(struct device *dev, const char *id) ++{ ++ return __devm_clk_get(dev, id, clk_get, ++ clk_prepare_enable, clk_disable_unprepare); ++} ++EXPORT_SYMBOL_GPL(devm_clk_get_enabled); ++ + struct clk *devm_clk_get_optional(struct device *dev, const char *id) + { + return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL); + } + EXPORT_SYMBOL(devm_clk_get_optional); + ++struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id) ++{ ++ return __devm_clk_get(dev, id, clk_get_optional, ++ clk_prepare, clk_unprepare); ++} ++EXPORT_SYMBOL_GPL(devm_clk_get_optional_prepared); ++ ++struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id) ++{ ++ return __devm_clk_get(dev, id, clk_get_optional, ++ clk_prepare_enable, clk_disable_unprepare); ++} ++EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled); ++ + struct clk_bulk_devres { + struct clk_bulk_data *clks; + int num_clks; +diff --git a/include/linux/clk.h b/include/linux/clk.h +index 7fd6a1febcf4..1814eabb7c20 100644 +--- a/include/linux/clk.h ++++ b/include/linux/clk.h +@@ -418,6 +418,47 @@ int __must_check devm_clk_bulk_get_all(struct device *dev, + */ + struct clk *devm_clk_get(struct device *dev, const char *id); + ++/** ++ * devm_clk_get_prepared - devm_clk_get() + clk_prepare() ++ * @dev: device for clock "consumer" ++ * @id: clock consumer ID ++ * ++ * Context: May sleep. ++ * ++ * Return: a struct clk corresponding to the clock producer, or ++ * valid IS_ERR() condition containing errno. The implementation ++ * uses @dev and @id to determine the clock consumer, and thereby ++ * the clock producer. (IOW, @id may be identical strings, but ++ * clk_get may return different clock producers depending on @dev.) ++ * ++ * The returned clk (if valid) is prepared. Drivers must however assume ++ * that the clock is not enabled. ++ * ++ * The clock will automatically be unprepared and freed when the device ++ * is unbound from the bus. ++ */ ++struct clk *devm_clk_get_prepared(struct device *dev, const char *id); ++ ++/** ++ * devm_clk_get_enabled - devm_clk_get() + clk_prepare_enable() ++ * @dev: device for clock "consumer" ++ * @id: clock consumer ID ++ * ++ * Context: May sleep. ++ * ++ * Return: a struct clk corresponding to the clock producer, or ++ * valid IS_ERR() condition containing errno. The implementation ++ * uses @dev and @id to determine the clock consumer, and thereby ++ * the clock producer. (IOW, @id may be identical strings, but ++ * clk_get may return different clock producers depending on @dev.) ++ * ++ * The returned clk (if valid) is prepared and enabled. ++ * ++ * The clock will automatically be disabled, unprepared and freed ++ * when the device is unbound from the bus. ++ */ ++struct clk *devm_clk_get_enabled(struct device *dev, const char *id); ++ + /** + * devm_clk_get_optional - lookup and obtain a managed reference to an optional + * clock producer. +@@ -429,6 +470,50 @@ struct clk *devm_clk_get(struct device *dev, const char *id); + */ + struct clk *devm_clk_get_optional(struct device *dev, const char *id); + ++/** ++ * devm_clk_get_optional_prepared - devm_clk_get_optional() + clk_prepare() ++ * @dev: device for clock "consumer" ++ * @id: clock consumer ID ++ * ++ * Context: May sleep. ++ * ++ * Return: a struct clk corresponding to the clock producer, or ++ * valid IS_ERR() condition containing errno. The implementation ++ * uses @dev and @id to determine the clock consumer, and thereby ++ * the clock producer. If no such clk is found, it returns NULL ++ * which serves as a dummy clk. That's the only difference compared ++ * to devm_clk_get_prepared(). ++ * ++ * The returned clk (if valid) is prepared. Drivers must however ++ * assume that the clock is not enabled. ++ * ++ * The clock will automatically be unprepared and freed when the ++ * device is unbound from the bus. ++ */ ++struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id); ++ ++/** ++ * devm_clk_get_optional_enabled - devm_clk_get_optional() + ++ * clk_prepare_enable() ++ * @dev: device for clock "consumer" ++ * @id: clock consumer ID ++ * ++ * Context: May sleep. ++ * ++ * Return: a struct clk corresponding to the clock producer, or ++ * valid IS_ERR() condition containing errno. The implementation ++ * uses @dev and @id to determine the clock consumer, and thereby ++ * the clock producer. If no such clk is found, it returns NULL ++ * which serves as a dummy clk. That's the only difference compared ++ * to devm_clk_get_enabled(). ++ * ++ * The returned clk (if valid) is prepared and enabled. ++ * ++ * The clock will automatically be disabled, unprepared and freed ++ * when the device is unbound from the bus. ++ */ ++struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id); ++ + /** + * devm_get_clk_from_child - lookup and obtain a managed reference to a + * clock producer from child node. +@@ -773,12 +858,36 @@ static inline struct clk *devm_clk_get(struct device *dev, const char *id) + return NULL; + } + ++static inline struct clk *devm_clk_get_prepared(struct device *dev, ++ const char *id) ++{ ++ return NULL; ++} ++ ++static inline struct clk *devm_clk_get_enabled(struct device *dev, ++ const char *id) ++{ ++ return NULL; ++} ++ + static inline struct clk *devm_clk_get_optional(struct device *dev, + const char *id) + { + return NULL; + } + ++static inline struct clk *devm_clk_get_optional_prepared(struct device *dev, ++ const char *id) ++{ ++ return NULL; ++} ++ ++static inline struct clk *devm_clk_get_optional_enabled(struct device *dev, ++ const char *id) ++{ ++ return NULL; ++} ++ + static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, + struct clk_bulk_data *clks) + { +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch b/queue-5.10/clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch new file mode 100644 index 00000000000..25cd7d289de --- /dev/null +++ b/queue-5.10/clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch @@ -0,0 +1,73 @@ +From 4f43a797b5e79816361b2e41b09d3320ce3c4125 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 00:06:21 +0200 +Subject: clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src + +From: Robert Marko + +[ Upstream commit 43a56cbf2a38170b02db29654607575b1b4b5bc0 ] + +While working on IPQ8074 APSS driver it was discovered that IPQ6018 and +IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is +currently broken. + +More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux +clock. +However after debugging why it was always stuck at 800Mhz, it was figured +out that its not regmap_mux compatible at all. +It is a simple mux but it uses RCG2 register layout and control bits, so +utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not +having to provide a dummy frequency table. + +While we are here, use ARRAY_SIZE for number of parents. + +Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. + +Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") +Signed-off-by: Robert Marko +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/apss-ipq6018.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c +index d78ff2f310bf..be952d417ded 100644 +--- a/drivers/clk/qcom/apss-ipq6018.c ++++ b/drivers/clk/qcom/apss-ipq6018.c +@@ -16,7 +16,7 @@ + #include "clk-regmap.h" + #include "clk-branch.h" + #include "clk-alpha-pll.h" +-#include "clk-regmap-mux.h" ++#include "clk-rcg.h" + + enum { + P_XO, +@@ -33,16 +33,15 @@ static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_APSS_PLL_EARLY, 5 }, + }; + +-static struct clk_regmap_mux apcs_alias0_clk_src = { +- .reg = 0x0050, +- .width = 3, +- .shift = 7, ++static struct clk_rcg2 apcs_alias0_clk_src = { ++ .cmd_rcgr = 0x0050, ++ .hid_width = 5, + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_clk_src", + .parent_data = parents_apcs_alias0_clk_src, +- .num_parents = 2, +- .ops = &clk_regmap_mux_closest_ops, ++ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), ++ .ops = &clk_rcg2_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }; +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-apss-ipq6018-mark-apcs_alias0_core_clk-as-c.patch b/queue-5.10/clk-qcom-apss-ipq6018-mark-apcs_alias0_core_clk-as-c.patch new file mode 100644 index 00000000000..a5c2d1bfcd9 --- /dev/null +++ b/queue-5.10/clk-qcom-apss-ipq6018-mark-apcs_alias0_core_clk-as-c.patch @@ -0,0 +1,42 @@ +From 2c9d4503a0052593a9b5cf82a85820a26083d504 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 00:06:22 +0200 +Subject: clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as critical + +From: Robert Marko + +[ Upstream commit 86e78995c93ee182433f965babfccd48417d4dcf ] + +While fixing up the driver I noticed that my IPQ8074 board was hanging +after CPUFreq switched the frequency during boot, WDT would eventually +reset it. + +So mark apcs_alias0_core_clk as critical since its the clock feeding the +CPU cluster and must never be disabled. + +Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") +Signed-off-by: Robert Marko +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220818220628.339366-3-robimarko@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/apss-ipq6018.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c +index be952d417ded..f2f502e2d5a4 100644 +--- a/drivers/clk/qcom/apss-ipq6018.c ++++ b/drivers/clk/qcom/apss-ipq6018.c +@@ -56,7 +56,7 @@ static struct clk_branch apcs_alias0_core_clk = { + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch b/queue-5.10/clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch new file mode 100644 index 00000000000..6aa91d045e6 --- /dev/null +++ b/queue-5.10/clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch @@ -0,0 +1,64 @@ +From 16ec9ef8bb1218cdbee8476d90b89fbc0e5646f1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 00:06:20 +0200 +Subject: clk: qcom: clk-rcg2: add rcg2 mux ops + +From: Christian Marangi + +[ Upstream commit c5d2c96b3a7bd8987fad9957510034130037fccf ] + +An RCG may act as a mux that switch between 2 parents. +This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds +the CPU cluster clock just switches between XO and the PLL that feeds it. + +Add the required ops to add support for this special configuration and use +the generic mux function to determine the rate. + +This way we dont have to keep a essentially dummy frequency table to use +RCG2 as a mux. + +Signed-off-by: Christian Marangi +Signed-off-by: Robert Marko +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com +Stable-dep-of: 43a56cbf2a38 ("clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/clk-rcg.h | 1 + + drivers/clk/qcom/clk-rcg2.c | 7 +++++++ + 2 files changed, 8 insertions(+) + +diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h +index 86d2b8b90173..51d86f7af7e4 100644 +--- a/drivers/clk/qcom/clk-rcg.h ++++ b/drivers/clk/qcom/clk-rcg.h +@@ -155,6 +155,7 @@ struct clk_rcg2 { + + extern const struct clk_ops clk_rcg2_ops; + extern const struct clk_ops clk_rcg2_floor_ops; ++extern const struct clk_ops clk_rcg2_mux_closest_ops; + extern const struct clk_ops clk_edp_pixel_ops; + extern const struct clk_ops clk_byte_ops; + extern const struct clk_ops clk_byte2_ops; +diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c +index 71a0d30cf44d..8d95bd35be56 100644 +--- a/drivers/clk/qcom/clk-rcg2.c ++++ b/drivers/clk/qcom/clk-rcg2.c +@@ -388,6 +388,13 @@ const struct clk_ops clk_rcg2_floor_ops = { + }; + EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); + ++const struct clk_ops clk_rcg2_mux_closest_ops = { ++ .determine_rate = __clk_mux_determine_rate_closest, ++ .get_parent = clk_rcg2_get_parent, ++ .set_parent = clk_rcg2_set_parent, ++}; ++EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops); ++ + struct frac_entry { + int num; + int den; +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-gcc-sdm660-move-parent-tables-after-plls.patch b/queue-5.10/clk-qcom-gcc-sdm660-move-parent-tables-after-plls.patch new file mode 100644 index 00000000000..d67fb6a0577 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-sdm660-move-parent-tables-after-plls.patch @@ -0,0 +1,245 @@ +From 08db360111814e0d3316ac6b0c437164c45c1275 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 26 Aug 2021 11:49:14 -0700 +Subject: clk: qcom: gcc-sdm660: Move parent tables after PLLs + +From: Stephen Boyd + +[ Upstream commit a61ca021fe28ab7163ca879fc3532c3cca25063c ] + +In the next patch we're going to change these tables to reference the +PLL structures directly. Let's move them here so the diff is easier to +read. No functional change in this patch. + +Signed-off-by: Stephen Boyd +Stable-dep-of: 6956c18f4ad9 ("clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clock") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sdm660.c | 204 +++++++++++++++++----------------- + 1 file changed, 102 insertions(+), 102 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c +index 31258795e7b8..aac1d4024ab7 100644 +--- a/drivers/clk/qcom/gcc-sdm660.c ++++ b/drivers/clk/qcom/gcc-sdm660.c +@@ -37,108 +37,6 @@ enum { + P_GPLL1_EARLY_DIV, + }; + +-static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL0_EARLY_DIV, 6 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll0_early_div", +-}; +- +-static const struct parent_map gcc_parent_map_xo_gpll0[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll0[] = { +- "xo", +- "gpll0", +-}; +- +-static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_SLEEP_CLK, 5 }, +- { P_GPLL0_EARLY_DIV, 6 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "sleep_clk", +- "gpll0_early_div", +-}; +- +-static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { +- { P_XO, 0 }, +- { P_SLEEP_CLK, 5 }, +-}; +- +-static const char * const gcc_parent_names_xo_sleep_clk[] = { +- "xo", +- "sleep_clk", +-}; +- +-static const struct parent_map gcc_parent_map_xo_gpll4[] = { +- { P_XO, 0 }, +- { P_GPLL4, 5 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll4[] = { +- "xo", +- "gpll4", +-}; +- +-static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL0_EARLY_DIV, 3 }, +- { P_GPLL1, 4 }, +- { P_GPLL4, 5 }, +- { P_GPLL1_EARLY_DIV, 6 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { +- "xo", +- "gpll0", +- "gpll0_early_div", +- "gpll1", +- "gpll4", +- "gpll1_early_div", +-}; +- +-static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL4, 5 }, +- { P_GPLL0_EARLY_DIV, 6 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll4", +- "gpll0_early_div", +-}; +- +-static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { +- { P_XO, 0 }, +- { P_GPLL0, 1 }, +- { P_GPLL0_EARLY_DIV, 2 }, +- { P_GPLL4, 5 }, +-}; +- +-static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = { +- "xo", +- "gpll0", +- "gpll0_early_div", +- "gpll4", +-}; +- + static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, +@@ -251,6 +149,108 @@ static struct clk_alpha_pll_postdiv gpll4 = { + }, + }; + ++static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_EARLY_DIV, 6 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = { ++ "xo", ++ "gpll0", ++ "gpll0_early_div", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_gpll0[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll0[] = { ++ "xo", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_SLEEP_CLK, 5 }, ++ { P_GPLL0_EARLY_DIV, 6 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = { ++ "xo", ++ "gpll0", ++ "sleep_clk", ++ "gpll0_early_div", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { ++ { P_XO, 0 }, ++ { P_SLEEP_CLK, 5 }, ++}; ++ ++static const char * const gcc_parent_names_xo_sleep_clk[] = { ++ "xo", ++ "sleep_clk", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_gpll4[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 5 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll4[] = { ++ "xo", ++ "gpll4", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_EARLY_DIV, 3 }, ++ { P_GPLL1, 4 }, ++ { P_GPLL4, 5 }, ++ { P_GPLL1_EARLY_DIV, 6 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { ++ "xo", ++ "gpll0", ++ "gpll0_early_div", ++ "gpll1", ++ "gpll4", ++ "gpll1_early_div", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 5 }, ++ { P_GPLL0_EARLY_DIV, 6 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = { ++ "xo", ++ "gpll0", ++ "gpll4", ++ "gpll0_early_div", ++}; ++ ++static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_EARLY_DIV, 2 }, ++ { P_GPLL4, 5 }, ++}; ++ ++static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = { ++ "xo", ++ "gpll0", ++ "gpll0_early_div", ++ "gpll4", ++}; ++ + static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-gcc-sdm660-replace-usage-of-parent_names.patch b/queue-5.10/clk-qcom-gcc-sdm660-replace-usage-of-parent_names.patch new file mode 100644 index 00000000000..be296b3b755 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-sdm660-replace-usage-of-parent_names.patch @@ -0,0 +1,1130 @@ +From 7b567a29852bc2e5980324cb784174c90c39e56a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 Aug 2021 13:45:17 -0700 +Subject: clk: qcom: gcc-sdm660: Replace usage of parent_names + +From: Bjorn Andersson + +[ Upstream commit da09577ab562e2700f0aba3f17cc741717ca9e38 ] + +Using parent_data and parent_hws, instead of parent_names, does protect +against some cases of incompletely defined clock trees. While it turns +out that the bug being chased this time was totally unrelated, this +patch converts the SDM660 GCC driver to avoid such issues. + +The "xo" fixed_factor clock is unused within the gcc driver, but +referenced from the DSI PHY. So it's left in place until the DSI driver +is updated. + +Tested-by: Marijn Suijten +Reviewed-by: AngeloGioacchino Del Regno +Reviewed-by: Marijn Suijten +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org +[sboyd@kernel.org: Reduce diff by moving enum and tables back to +original position in previous patch] +Signed-off-by: Stephen Boyd +Stable-dep-of: 6956c18f4ad9 ("clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clock") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sdm660.c | 370 ++++++++++++++++++---------------- + 1 file changed, 194 insertions(+), 176 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c +index aac1d4024ab7..b8e59b4f0bde 100644 +--- a/drivers/clk/qcom/gcc-sdm660.c ++++ b/drivers/clk/qcom/gcc-sdm660.c +@@ -42,7 +42,9 @@ static struct clk_fixed_factor xo = { + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "xo", +- .parent_names = (const char *[]){ "xo_board" }, ++ .parent_data = &(const struct clk_parent_data) { ++ .fw_name = "xo" ++ }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +@@ -56,7 +58,9 @@ static struct clk_alpha_pll gpll0_early = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_early", +- .parent_names = (const char *[]){ "xo" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "xo", ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, +@@ -68,7 +72,9 @@ static struct clk_fixed_factor gpll0_early_div = { + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_early_div", +- .parent_names = (const char *[]){ "gpll0_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll0_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +@@ -79,7 +85,9 @@ static struct clk_alpha_pll_postdiv gpll0 = { + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", +- .parent_names = (const char *[]){ "gpll0_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll0_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +@@ -93,7 +101,9 @@ static struct clk_alpha_pll gpll1_early = { + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_early", +- .parent_names = (const char *[]){ "xo" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "xo", ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, +@@ -105,7 +115,9 @@ static struct clk_fixed_factor gpll1_early_div = { + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll1_early_div", +- .parent_names = (const char *[]){ "gpll1_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll1_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +@@ -116,7 +128,9 @@ static struct clk_alpha_pll_postdiv gpll1 = { + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll1", +- .parent_names = (const char *[]){ "gpll1_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll1_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +@@ -130,7 +144,9 @@ static struct clk_alpha_pll gpll4_early = { + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_early", +- .parent_names = (const char *[]){ "xo" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "xo", ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, +@@ -143,7 +159,9 @@ static struct clk_alpha_pll_postdiv gpll4 = { + .clkr.hw.init = &(struct clk_init_data) + { + .name = "gpll4", +- .parent_names = (const char *[]) { "gpll4_early" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gpll4_early.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ops, + }, +@@ -155,10 +173,10 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = { + { P_GPLL0_EARLY_DIV, 6 }, + }; + +-static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll0_early_div", ++static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_early_div.hw }, + }; + + static const struct parent_map gcc_parent_map_xo_gpll0[] = { +@@ -166,9 +184,9 @@ static const struct parent_map gcc_parent_map_xo_gpll0[] = { + { P_GPLL0, 1 }, + }; + +-static const char * const gcc_parent_names_xo_gpll0[] = { +- "xo", +- "gpll0", ++static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll0.clkr.hw }, + }; + + static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { +@@ -178,11 +196,11 @@ static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div + { P_GPLL0_EARLY_DIV, 6 }, + }; + +-static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "sleep_clk", +- "gpll0_early_div", ++static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll0.clkr.hw }, ++ { .fw_name = "sleep_clk" }, ++ { .hw = &gpll0_early_div.hw }, + }; + + static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { +@@ -190,9 +208,9 @@ static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { + { P_SLEEP_CLK, 5 }, + }; + +-static const char * const gcc_parent_names_xo_sleep_clk[] = { +- "xo", +- "sleep_clk", ++static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = { ++ { .fw_name = "xo" }, ++ { .fw_name = "sleep_clk" }, + }; + + static const struct parent_map gcc_parent_map_xo_gpll4[] = { +@@ -200,9 +218,9 @@ static const struct parent_map gcc_parent_map_xo_gpll4[] = { + { P_GPLL4, 5 }, + }; + +-static const char * const gcc_parent_names_xo_gpll4[] = { +- "xo", +- "gpll4", ++static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll4.clkr.hw }, + }; + + static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { +@@ -214,13 +232,13 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpl + { P_GPLL1_EARLY_DIV, 6 }, + }; + +-static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { +- "xo", +- "gpll0", +- "gpll0_early_div", +- "gpll1", +- "gpll4", +- "gpll1_early_div", ++static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_early_div.hw }, ++ { .hw = &gpll1.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++ { .hw = &gpll1_early_div.hw }, + }; + + static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { +@@ -230,11 +248,11 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = + { P_GPLL0_EARLY_DIV, 6 }, + }; + +-static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = { +- "xo", +- "gpll0", +- "gpll4", +- "gpll0_early_div", ++static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++ { .hw = &gpll0_early_div.hw }, + }; + + static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { +@@ -244,11 +262,11 @@ static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = + { P_GPLL4, 5 }, + }; + +-static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = { +- "xo", +- "gpll0", +- "gpll0_early_div", +- "gpll4", ++static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = { ++ { .fw_name = "xo" }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_early_div.hw }, ++ { .hw = &gpll4.clkr.hw }, + }; + + static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { +@@ -265,7 +283,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -290,7 +308,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -304,7 +322,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -318,7 +336,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -332,7 +350,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -346,7 +364,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -360,7 +378,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -374,7 +392,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -407,7 +425,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -421,7 +439,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -435,7 +453,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -449,7 +467,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -463,7 +481,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -477,7 +495,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -491,7 +509,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -505,7 +523,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -519,7 +537,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -533,7 +551,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -547,7 +565,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -561,7 +579,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -582,7 +600,7 @@ static struct clk_rcg2 gp1_clk_src = { + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +@@ -596,7 +614,7 @@ static struct clk_rcg2 gp2_clk_src = { + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +@@ -610,7 +628,7 @@ static struct clk_rcg2 gp3_clk_src = { + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +@@ -630,7 +648,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { + .freq_tbl = ftbl_hmss_gpll0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -651,7 +669,7 @@ static struct clk_rcg2 hmss_gpll4_clk_src = { + .freq_tbl = ftbl_hmss_gpll4_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll4_clk_src", +- .parent_names = gcc_parent_names_xo_gpll4, ++ .parent_data = gcc_parent_data_xo_gpll4, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +@@ -670,7 +688,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0, ++ .parent_data = gcc_parent_data_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +@@ -689,7 +707,7 @@ static struct clk_rcg2 pdm2_clk_src = { + .freq_tbl = ftbl_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -711,7 +729,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { + .freq_tbl = ftbl_qspi_ser_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +@@ -737,7 +755,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { + .freq_tbl = ftbl_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +@@ -759,7 +777,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .freq_tbl = ftbl_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -785,7 +803,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, + .num_parents = 4, + .ops = &clk_rcg2_floor_ops, + }, +@@ -808,7 +826,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { + .freq_tbl = ftbl_ufs_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -829,7 +847,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { + .freq_tbl = ftbl_ufs_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -843,7 +861,7 @@ static struct clk_rcg2 ufs_phy_aux_clk_src = { + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_phy_aux_clk_src", +- .parent_names = gcc_parent_names_xo_sleep_clk, ++ .parent_data = gcc_parent_data_xo_sleep_clk, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +@@ -864,7 +882,7 @@ static struct clk_rcg2 ufs_unipro_core_clk_src = { + .freq_tbl = ftbl_ufs_unipro_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_unipro_core_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -885,7 +903,7 @@ static struct clk_rcg2 usb20_master_clk_src = { + .freq_tbl = ftbl_usb20_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -905,7 +923,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .freq_tbl = ftbl_usb20_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -930,7 +948,7 @@ static struct clk_rcg2 usb30_master_clk_src = { + .freq_tbl = ftbl_usb30_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -951,7 +969,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", +- .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, ++ .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +@@ -971,7 +989,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { + .freq_tbl = ftbl_usb3_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", +- .parent_names = gcc_parent_names_xo_sleep_clk, ++ .parent_data = gcc_parent_data_xo_sleep_clk, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +@@ -985,8 +1003,8 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_ufs_axi_clk", +- .parent_names = (const char *[]){ +- "ufs_axi_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &ufs_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1002,8 +1020,8 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_usb3_axi_clk", +- .parent_names = (const char *[]){ +- "usb30_master_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb30_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1071,8 +1089,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup1_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1089,8 +1107,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup1_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1107,8 +1125,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup2_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1125,8 +1143,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup2_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1143,8 +1161,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup3_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1161,8 +1179,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup3_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1179,8 +1197,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup4_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1197,8 +1215,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_qup4_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1215,8 +1233,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_uart1_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_uart1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1233,8 +1251,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", +- .parent_names = (const char *[]){ +- "blsp1_uart2_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp1_uart2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1264,8 +1282,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup1_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1282,8 +1300,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup1_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1300,8 +1318,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup2_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup2_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1318,8 +1336,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup2_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup2_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1336,8 +1354,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup3_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup3_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1354,8 +1372,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup3_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup3_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1372,8 +1390,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_i2c_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup4_i2c_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1390,8 +1408,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_spi_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_qup4_spi_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1408,8 +1426,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart1_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_uart1_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_uart1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1426,8 +1444,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart2_apps_clk", +- .parent_names = (const char *[]){ +- "blsp2_uart2_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &blsp2_uart2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1457,8 +1475,8 @@ static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb2_axi_clk", +- .parent_names = (const char *[]){ +- "usb20_master_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb20_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1474,8 +1492,8 @@ static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_axi_clk", +- .parent_names = (const char *[]){ +- "usb30_master_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb30_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1503,8 +1521,8 @@ static struct clk_branch gcc_gp1_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", +- .parent_names = (const char *[]){ +- "gp1_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1521,8 +1539,8 @@ static struct clk_branch gcc_gp2_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", +- .parent_names = (const char *[]){ +- "gp2_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1539,8 +1557,8 @@ static struct clk_branch gcc_gp3_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", +- .parent_names = (const char *[]){ +- "gp3_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1583,8 +1601,8 @@ static struct clk_branch gcc_gpu_gpll0_clk = { + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk", +- .parent_names = (const char *[]){ +- "gpll0", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1600,8 +1618,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk = { + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk", +- .parent_names = (const char *[]){ +- "gpll0_early_div", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gpll0_early_div.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1631,8 +1649,8 @@ static struct clk_branch gcc_hmss_rbcpr_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_rbcpr_clk", +- .parent_names = (const char *[]){ +- "hmss_rbcpr_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &hmss_rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1649,8 +1667,8 @@ static struct clk_branch gcc_mmss_gpll0_clk = { + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_clk", +- .parent_names = (const char *[]){ +- "gpll0", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1666,8 +1684,8 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_div_clk", +- .parent_names = (const char *[]){ +- "gpll0_early_div", ++ .parent_hws = (const struct clk_hw*[]) { ++ &gpll0_early_div.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, +@@ -1760,8 +1778,8 @@ static struct clk_branch gcc_pdm2_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", +- .parent_names = (const char *[]){ +- "pdm2_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1817,8 +1835,8 @@ static struct clk_branch gcc_qspi_ser_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ser_clk", +- .parent_names = (const char *[]){ +- "qspi_ser_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &qspi_ser_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1874,8 +1892,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", +- .parent_names = (const char *[]){ +- "sdcc1_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1892,8 +1910,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", +- .parent_names = (const char *[]){ +- "sdcc1_ice_core_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1923,8 +1941,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", +- .parent_names = (const char *[]){ +- "sdcc2_apps_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1954,8 +1972,8 @@ static struct clk_branch gcc_ufs_axi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_clk", +- .parent_names = (const char *[]){ +- "ufs_axi_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &ufs_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -1985,8 +2003,8 @@ static struct clk_branch gcc_ufs_ice_core_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_clk", +- .parent_names = (const char *[]){ +- "ufs_ice_core_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &ufs_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -2003,8 +2021,8 @@ static struct clk_branch gcc_ufs_phy_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_clk", +- .parent_names = (const char *[]){ +- "ufs_phy_aux_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &ufs_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -2060,8 +2078,8 @@ static struct clk_branch gcc_ufs_unipro_core_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_clk", +- .parent_names = (const char *[]){ +- "ufs_unipro_core_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &ufs_unipro_core_clk_src.clkr.hw, + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, +@@ -2078,8 +2096,8 @@ static struct clk_branch gcc_usb20_master_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_master_clk", +- .parent_names = (const char *[]){ +- "usb20_master_clk_src" ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb20_master_clk_src.clkr.hw, + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, +@@ -2096,8 +2114,8 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_mock_utmi_clk", +- .parent_names = (const char *[]){ +- "usb20_mock_utmi_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -2127,8 +2145,8 @@ static struct clk_branch gcc_usb30_master_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk", +- .parent_names = (const char *[]){ +- "usb30_master_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb30_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -2145,8 +2163,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk", +- .parent_names = (const char *[]){ +- "usb30_mock_utmi_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb30_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +@@ -2189,8 +2207,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk", +- .parent_names = (const char *[]){ +- "usb3_phy_aux_clk_src", ++ .parent_hws = (const struct clk_hw*[]) { ++ &usb3_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-gcc-sdm660-use-array_size-for-num_parents.patch b/queue-5.10/clk-qcom-gcc-sdm660-use-array_size-for-num_parents.patch new file mode 100644 index 00000000000..f8184bef256 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-sdm660-use-array_size-for-num_parents.patch @@ -0,0 +1,389 @@ +From 023dc6f51709ee0a0b7d491cd86c580fb7a758cf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 29 Aug 2021 22:48:19 +0200 +Subject: clk: qcom: gcc-sdm660: Use ARRAY_SIZE for num_parents + +From: Marijn Suijten + +[ Upstream commit 00ff818888fd436b687dbef457ea5a9135c60b15 ] + +Where possible, use ARRAY_SIZE to determine the number of parents in +clk_parent_data instead of hardcoding a number that relies on an array +defined hundreds of lines above. + +Signed-off-by: Marijn Suijten +Link: https://lore.kernel.org/r/20210829204822.289829-2-marijn.suijten@somainline.org +Signed-off-by: Stephen Boyd +Stable-dep-of: 6956c18f4ad9 ("clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clock") +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sdm660.c | 80 +++++++++++++++++------------------ + 1 file changed, 40 insertions(+), 40 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c +index b8e59b4f0bde..95712cf38bab 100644 +--- a/drivers/clk/qcom/gcc-sdm660.c ++++ b/drivers/clk/qcom/gcc-sdm660.c +@@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -309,7 +309,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -323,7 +323,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -337,7 +337,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -379,7 +379,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -393,7 +393,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -454,7 +454,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -468,7 +468,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -482,7 +482,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -496,7 +496,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -510,7 +510,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -524,7 +524,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -538,7 +538,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -552,7 +552,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -566,7 +566,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -580,7 +580,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -601,7 +601,7 @@ static struct clk_rcg2 gp1_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -615,7 +615,7 @@ static struct clk_rcg2 gp2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -629,7 +629,7 @@ static struct clk_rcg2 gp3_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -649,7 +649,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -670,7 +670,7 @@ static struct clk_rcg2 hmss_gpll4_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll4_clk_src", + .parent_data = gcc_parent_data_xo_gpll4, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4), + .ops = &clk_rcg2_ops, + }, + }; +@@ -689,7 +689,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", + .parent_data = gcc_parent_data_xo_gpll0, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0), + .ops = &clk_rcg2_ops, + }, + }; +@@ -708,7 +708,7 @@ static struct clk_rcg2 pdm2_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -730,7 +730,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, +- .num_parents = 6, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -756,7 +756,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -778,7 +778,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -804,7 +804,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, +- .num_parents = 4, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4), + .ops = &clk_rcg2_floor_ops, + }, + }; +@@ -827,7 +827,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -848,7 +848,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -862,7 +862,7 @@ static struct clk_rcg2 ufs_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_phy_aux_clk_src", + .parent_data = gcc_parent_data_xo_sleep_clk, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), + .ops = &clk_rcg2_ops, + }, + }; +@@ -883,7 +883,7 @@ static struct clk_rcg2 ufs_unipro_core_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_unipro_core_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -904,7 +904,7 @@ static struct clk_rcg2 usb20_master_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -924,7 +924,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -949,7 +949,7 @@ static struct clk_rcg2 usb30_master_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -970,7 +970,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), + .ops = &clk_rcg2_ops, + }, + }; +@@ -990,7 +990,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", + .parent_data = gcc_parent_data_xo_sleep_clk, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), + .ops = &clk_rcg2_ops, + }, + }; +-- +2.35.1 + diff --git a/queue-5.10/clk-qcom-gcc-sdm660-use-floor-ops-for-sdcc1-clock.patch b/queue-5.10/clk-qcom-gcc-sdm660-use-floor-ops-for-sdcc1-clock.patch new file mode 100644 index 00000000000..e9ebea762c5 --- /dev/null +++ b/queue-5.10/clk-qcom-gcc-sdm660-use-floor-ops-for-sdcc1-clock.patch @@ -0,0 +1,46 @@ +From 6a2334df85eec46ed28495ea50e595590668b866 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 14 Jul 2022 22:38:22 +0200 +Subject: clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clock + +From: Marijn Suijten + +[ Upstream commit 6956c18f4ad9200aa945f7ea37d65a05afc49d51 ] + +In commit 3f905469c8ce ("clk: qcom: gcc: Use floor ops for SDCC clocks") +floor ops were applied to SDCC2 only, but flooring is also required on +the SDCC1 apps clock which is used by the eMMC card on Sony's Nile +platform, and otherwise result in the typicial "Card appears +overclocked" warnings observed on many other platforms before: + + mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz + mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz + mmc0: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz + +Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") +Signed-off-by: Marijn Suijten +Tested-by: Alexey Minnekhanov +Reviewed-by: Stephen Boyd +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220714203822.186448-1-marijn.suijten@somainline.org +Signed-off-by: Sasha Levin +--- + drivers/clk/qcom/gcc-sdm660.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c +index 95712cf38bab..905705559f59 100644 +--- a/drivers/clk/qcom/gcc-sdm660.c ++++ b/drivers/clk/qcom/gcc-sdm660.c +@@ -757,7 +757,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { + .name = "sdcc1_apps_clk_src", + .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div), +- .ops = &clk_rcg2_ops, ++ .ops = &clk_rcg2_floor_ops, + }, + }; + +-- +2.35.1 + diff --git a/queue-5.10/clk-qoriq-hold-reference-returned-by-of_get_parent.patch b/queue-5.10/clk-qoriq-hold-reference-returned-by-of_get_parent.patch new file mode 100644 index 00000000000..37f83f16ed0 --- /dev/null +++ b/queue-5.10/clk-qoriq-hold-reference-returned-by-of_get_parent.patch @@ -0,0 +1,56 @@ +From 0b206a6549301b7016b957f463f94593bd5087ff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 22:38:51 +0800 +Subject: clk: qoriq: Hold reference returned by of_get_parent() + +From: Liang He + +[ Upstream commit a8ea4273bc26256ce3cce83164f0f51c5bf6e127 ] + +In legacy_init_clockgen(), we need to hold the reference returned +by of_get_parent() and use it to call of_node_put() for refcount +balance. + +Beside, in create_sysclk(), we need to call of_node_put() on 'sysclk' +also for refcount balance. + +Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver") +Signed-off-by: Liang He +Link: https://lore.kernel.org/r/20220628143851.171299-1-windhl@126.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-qoriq.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c +index 46101c6a20f2..585b9ac11881 100644 +--- a/drivers/clk/clk-qoriq.c ++++ b/drivers/clk/clk-qoriq.c +@@ -1038,8 +1038,13 @@ static void __init _clockgen_init(struct device_node *np, bool legacy); + */ + static void __init legacy_init_clockgen(struct device_node *np) + { +- if (!clockgen.node) +- _clockgen_init(of_get_parent(np), true); ++ if (!clockgen.node) { ++ struct device_node *parent_np; ++ ++ parent_np = of_get_parent(np); ++ _clockgen_init(parent_np, true); ++ of_node_put(parent_np); ++ } + } + + /* Legacy node */ +@@ -1134,6 +1139,7 @@ static struct clk * __init create_sysclk(const char *name) + sysclk = of_get_child_by_name(clockgen.node, "sysclk"); + if (sysclk) { + clk = sysclk_from_fixed(sysclk, name); ++ of_node_put(sysclk); + if (!IS_ERR(clk)) + return clk; + } +-- +2.35.1 + diff --git a/queue-5.10/clk-sprd-hold-reference-returned-by-of_get_parent.patch b/queue-5.10/clk-sprd-hold-reference-returned-by-of_get_parent.patch new file mode 100644 index 00000000000..a0320095af6 --- /dev/null +++ b/queue-5.10/clk-sprd-hold-reference-returned-by-of_get_parent.patch @@ -0,0 +1,52 @@ +From 5ff3433d613304dbc9076a2827965b55724d0a08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Jul 2022 08:47:29 +0800 +Subject: clk: sprd: Hold reference returned by of_get_parent() + +From: Liang He + +[ Upstream commit 91e6455bf715fb1558a0bf8f645ec1c131254a3c ] + +We should hold the reference returned by of_get_parent() and use it +to call of_node_put() for refcount balance. + +Fixes: f95e8c7923d1 ("clk: sprd: support to get regmap from parent node") +Signed-off-by: Liang He +Link: https://lore.kernel.org/r/20220704004729.272481-1-windhl@126.com +Reviewed-by: Orson Zhai +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/sprd/common.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c +index d620bbbcdfc8..ce81e4087a8f 100644 +--- a/drivers/clk/sprd/common.c ++++ b/drivers/clk/sprd/common.c +@@ -41,7 +41,7 @@ int sprd_clk_regmap_init(struct platform_device *pdev, + { + void __iomem *base; + struct device *dev = &pdev->dev; +- struct device_node *node = dev->of_node; ++ struct device_node *node = dev->of_node, *np; + struct regmap *regmap; + + if (of_find_property(node, "sprd,syscon", NULL)) { +@@ -50,9 +50,10 @@ int sprd_clk_regmap_init(struct platform_device *pdev, + pr_err("%s: failed to get syscon regmap\n", __func__); + return PTR_ERR(regmap); + } +- } else if (of_device_is_compatible(of_get_parent(dev->of_node), +- "syscon")) { +- regmap = device_node_to_regmap(of_get_parent(dev->of_node)); ++ } else if (of_device_is_compatible(np = of_get_parent(node), "syscon") || ++ (of_node_put(np), 0)) { ++ regmap = device_node_to_regmap(np); ++ of_node_put(np); + if (IS_ERR(regmap)) { + dev_err(dev, "failed to get regmap from its parent.\n"); + return PTR_ERR(regmap); +-- +2.35.1 + diff --git a/queue-5.10/clk-tegra-fix-refcount-leak-in-tegra114_clock_init.patch b/queue-5.10/clk-tegra-fix-refcount-leak-in-tegra114_clock_init.patch new file mode 100644 index 00000000000..324fc212c0d --- /dev/null +++ b/queue-5.10/clk-tegra-fix-refcount-leak-in-tegra114_clock_init.patch @@ -0,0 +1,37 @@ +From e487b2edcd8e31b18b2967bcb411638de6f1ca24 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 18:38:34 +0400 +Subject: clk: tegra: Fix refcount leak in tegra114_clock_init + +From: Miaoqian Lin + +[ Upstream commit db16a80c76ea395766913082b1e3f939dde29b2c ] + +of_find_matching_node() returns a node pointer with refcount +incremented, we should use of_node_put() on it when not need anymore. +Add missing of_node_put() to avoid refcount leak. + +Fixes: 2cb5efefd6f7 ("clk: tegra: Implement clocks for Tegra114") +Signed-off-by: Miaoqian Lin +Link: https://lore.kernel.org/r/20220523143834.7587-1-linmq006@gmail.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/tegra/clk-tegra114.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c +index bc9e47a4cb60..4e2b26e3e573 100644 +--- a/drivers/clk/tegra/clk-tegra114.c ++++ b/drivers/clk/tegra/clk-tegra114.c +@@ -1317,6 +1317,7 @@ static void __init tegra114_clock_init(struct device_node *np) + } + + pmc_base = of_iomap(node, 0); ++ of_node_put(node); + if (!pmc_base) { + pr_err("Can't map pmc registers\n"); + WARN_ON(1); +-- +2.35.1 + diff --git a/queue-5.10/clk-tegra-fix-refcount-leak-in-tegra210_clock_init.patch b/queue-5.10/clk-tegra-fix-refcount-leak-in-tegra210_clock_init.patch new file mode 100644 index 00000000000..4230bd4ccf1 --- /dev/null +++ b/queue-5.10/clk-tegra-fix-refcount-leak-in-tegra210_clock_init.patch @@ -0,0 +1,37 @@ +From c4f25573aee4cc4b57a461b333fb25371e42e16d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 18:26:08 +0400 +Subject: clk: tegra: Fix refcount leak in tegra210_clock_init + +From: Miaoqian Lin + +[ Upstream commit 56c78cb1f00a9dde8cd762131ce8f4c5eb046fbb ] + +of_find_matching_node() returns a node pointer with refcount +incremented, we should use of_node_put() on it when not need anymore. +Add missing of_node_put() to avoid refcount leak. + +Fixes: 6b301a059eb2 ("clk: tegra: Add support for Tegra210 clocks") +Signed-off-by: Miaoqian Lin +Link: https://lore.kernel.org/r/20220523142608.65074-1-linmq006@gmail.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/tegra/clk-tegra210.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c +index 68cbb98af567..1a0016d07f88 100644 +--- a/drivers/clk/tegra/clk-tegra210.c ++++ b/drivers/clk/tegra/clk-tegra210.c +@@ -3697,6 +3697,7 @@ static void __init tegra210_clock_init(struct device_node *np) + } + + pmc_base = of_iomap(node, 0); ++ of_node_put(node); + if (!pmc_base) { + pr_err("Can't map pmc registers\n"); + WARN_ON(1); +-- +2.35.1 + diff --git a/queue-5.10/clk-tegra20-fix-refcount-leak-in-tegra20_clock_init.patch b/queue-5.10/clk-tegra20-fix-refcount-leak-in-tegra20_clock_init.patch new file mode 100644 index 00000000000..49f8a5f491e --- /dev/null +++ b/queue-5.10/clk-tegra20-fix-refcount-leak-in-tegra20_clock_init.patch @@ -0,0 +1,37 @@ +From daf72ae502b9f4f98375a10cdbf5ba2964bae4ed Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 19:28:11 +0400 +Subject: clk: tegra20: Fix refcount leak in tegra20_clock_init + +From: Miaoqian Lin + +[ Upstream commit 4e343bafe03ff68a62f48f8235cf98f2c685468b ] + +of_find_matching_node() returns a node pointer with refcount +incremented, we should use of_node_put() on it when not need anymore. +Add missing of_node_put() to avoid refcount leak. + +Fixes: 37c26a906527 ("clk: tegra: add clock support for Tegra20") +Signed-off-by: Miaoqian Lin +Link: https://lore.kernel.org/r/20220523152811.19692-1-linmq006@gmail.com +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/tegra/clk-tegra20.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c +index 3efc651b42e3..d60ee6e318a5 100644 +--- a/drivers/clk/tegra/clk-tegra20.c ++++ b/drivers/clk/tegra/clk-tegra20.c +@@ -1128,6 +1128,7 @@ static void __init tegra20_clock_init(struct device_node *np) + } + + pmc_base = of_iomap(node, 0); ++ of_node_put(node); + if (!pmc_base) { + pr_err("Can't map pmc registers\n"); + BUG(); +-- +2.35.1 + diff --git a/queue-5.10/clk-ti-dra7-atl-fix-reference-leak-in-of_dra7_atl_cl.patch b/queue-5.10/clk-ti-dra7-atl-fix-reference-leak-in-of_dra7_atl_cl.patch new file mode 100644 index 00000000000..b05891c992e --- /dev/null +++ b/queue-5.10/clk-ti-dra7-atl-fix-reference-leak-in-of_dra7_atl_cl.patch @@ -0,0 +1,60 @@ +From aed144cc347b782e7aff4955c06c30fbf4ca6e5e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 2 Jun 2022 07:08:36 +0400 +Subject: clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe + +From: Miaoqian Lin + +[ Upstream commit 9c59a01caba26ec06fefd6ca1f22d5fd1de57d63 ] + +pm_runtime_get_sync() will increment pm usage counter. +Forgetting to putting operation will result in reference leak. +Add missing pm_runtime_put_sync in some error paths. + +Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") +Signed-off-by: Miaoqian Lin +Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.com +Reviewed-by: Tony Lindgren +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/ti/clk-dra7-atl.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c +index 8d4c08b034bd..e2e59d78c173 100644 +--- a/drivers/clk/ti/clk-dra7-atl.c ++++ b/drivers/clk/ti/clk-dra7-atl.c +@@ -251,14 +251,16 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) + if (rc) { + pr_err("%s: failed to lookup atl clock %d\n", __func__, + i); +- return -EINVAL; ++ ret = -EINVAL; ++ goto pm_put; + } + + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) { + pr_err("%s: failed to get atl clock %d from provider\n", + __func__, i); +- return PTR_ERR(clk); ++ ret = PTR_ERR(clk); ++ goto pm_put; + } + + cdesc = to_atl_desc(__clk_get_hw(clk)); +@@ -291,8 +293,9 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev) + if (cdesc->enabled) + atl_clk_enable(__clk_get_hw(clk)); + } +- pm_runtime_put_sync(cinfo->dev); + ++pm_put: ++ pm_runtime_put_sync(cinfo->dev); + return ret; + } + +-- +2.35.1 + diff --git a/queue-5.10/clk-vc5-fix-5p49v6901-outputs-disabling-when-enablin.patch b/queue-5.10/clk-vc5-fix-5p49v6901-outputs-disabling-when-enablin.patch new file mode 100644 index 00000000000..f02baeafcdf --- /dev/null +++ b/queue-5.10/clk-vc5-fix-5p49v6901-outputs-disabling-when-enablin.patch @@ -0,0 +1,55 @@ +From d5215500d2b0ce588f6f52f71b40fc67d36ad573 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 01:53:55 +0300 +Subject: clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD + +From: Serge Semin + +[ Upstream commit c388cc804016cf0f65afdc2362b120aa594ff3e6 ] + +We have discovered random glitches during the system boot up procedure. +The problem investigation led us to the weird outcomes: when none of the +Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the +glitches disappeared. It was a mystery since the SoC external clock +domains were fed with different 5P49V6901 outputs. The driver code didn't +seem like bogus either. We almost despaired to find out a root cause when +the solution has been found for a more modern revision of the chip. It +turned out the 5P49V6901 clock generator stopped its output for a short +period of time during the VC5_OUT_DIV_CONTROL register writing. The same +problem was found for the 5P49V6965 revision of the chip and was +successfully fixed in commit fc336ae622df ("clk: vc5: fix output disabling +when enabling a FOD") by enabling the "bypass_sync" flag hidden inside +"Unused Factory Reserved Register". Even though the 5P49V6901 registers +description and programming guide doesn't provide any intel regarding that +flag, setting it up anyway in the officially unused register completely +eliminated the denoted glitches. Thus let's activate the functionality +submitted in commit fc336ae622df ("clk: vc5: fix output disabling when +enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove the +ports implicit inter-dependency. + +Fixes: dbf6b16f5683 ("clk: vc5: Add support for IDT VersaClock 5P49V6901") +Signed-off-by: Serge Semin +Reviewed-by: Luca Ceresoli +Link: https://lore.kernel.org/r/20220929225402.9696-2-Sergey.Semin@baikalelectronics.ru +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/clk-versaclock5.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c +index 4e741f94baf0..eb597ea7bb87 100644 +--- a/drivers/clk/clk-versaclock5.c ++++ b/drivers/clk/clk-versaclock5.c +@@ -1116,7 +1116,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = { + .model = IDT_VC6_5P49V6901, + .clk_fod_cnt = 4, + .clk_out_cnt = 5, +- .flags = VC5_HAS_PFD_FREQ_DBL, ++ .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, + }; + + static const struct vc5_chip_info idt_5p49v6965_info = { +-- +2.35.1 + diff --git a/queue-5.10/clk-zynqmp-fix-stack-out-of-bounds-in-strncpy.patch b/queue-5.10/clk-zynqmp-fix-stack-out-of-bounds-in-strncpy.patch new file mode 100644 index 00000000000..c5dbf6c1c5e --- /dev/null +++ b/queue-5.10/clk-zynqmp-fix-stack-out-of-bounds-in-strncpy.patch @@ -0,0 +1,118 @@ +From 8d535fe70d7d56e46a9cda73f119c8bfc1196221 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 10 May 2022 12:31:54 +0530 +Subject: clk: zynqmp: Fix stack-out-of-bounds in strncpy` + +From: Ian Nam + +[ Upstream commit dd80fb2dbf1cd8751efbe4e53e54056f56a9b115 ] + +"BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68" + +Linux-ATF interface is using 16 bytes of SMC payload. In case clock name is +longer than 15 bytes, string terminated NULL character will not be received +by Linux. Add explicit NULL character at last byte to fix issues when clock +name is longer. + +This fixes below bug reported by KASAN: + + ================================================================== + BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68 + Read of size 1 at addr ffff0008c89a7410 by task swapper/0/1 + + CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.4.0-00396-g81ef9e7-dirty #3 + Hardware name: Xilinx Versal vck190 Eval board revA (QSPI) (DT) + Call trace: + dump_backtrace+0x0/0x1e8 + show_stack+0x14/0x20 + dump_stack+0xd4/0x108 + print_address_description.isra.0+0xbc/0x37c + __kasan_report+0x144/0x198 + kasan_report+0xc/0x18 + __asan_load1+0x5c/0x68 + strncpy+0x30/0x68 + zynqmp_clock_probe+0x238/0x7b8 + platform_drv_probe+0x6c/0xc8 + really_probe+0x14c/0x418 + driver_probe_device+0x74/0x130 + __device_attach_driver+0xc4/0xe8 + bus_for_each_drv+0xec/0x150 + __device_attach+0x160/0x1d8 + device_initial_probe+0x10/0x18 + bus_probe_device+0xe0/0xf0 + device_add+0x528/0x950 + of_device_add+0x5c/0x80 + of_platform_device_create_pdata+0x120/0x168 + of_platform_bus_create+0x244/0x4e0 + of_platform_populate+0x50/0xe8 + zynqmp_firmware_probe+0x370/0x3a8 + platform_drv_probe+0x6c/0xc8 + really_probe+0x14c/0x418 + driver_probe_device+0x74/0x130 + device_driver_attach+0x94/0xa0 + __driver_attach+0x70/0x108 + bus_for_each_dev+0xe4/0x158 + driver_attach+0x30/0x40 + bus_add_driver+0x21c/0x2b8 + driver_register+0xbc/0x1d0 + __platform_driver_register+0x7c/0x88 + zynqmp_firmware_driver_init+0x1c/0x24 + do_one_initcall+0xa4/0x234 + kernel_init_freeable+0x1b0/0x24c + kernel_init+0x10/0x110 + ret_from_fork+0x10/0x18 + + The buggy address belongs to the page: + page:ffff0008f9be1c88 refcount:0 mapcount:0 mapping:0000000000000000 index:0x0 + raw: 0008d00000000000 ffff0008f9be1c90 ffff0008f9be1c90 0000000000000000 + raw: 0000000000000000 0000000000000000 00000000ffffffff + page dumped because: kasan: bad access detected + + addr ffff0008c89a7410 is located in stack of task swapper/0/1 at offset 112 in frame: + zynqmp_clock_probe+0x0/0x7b8 + + this frame has 3 objects: + [32, 44) 'response' + [64, 80) 'ret_payload' + [96, 112) 'name' + + Memory state around the buggy address: + ffff0008c89a7300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + ffff0008c89a7380: 00 00 00 00 f1 f1 f1 f1 00 04 f2 f2 00 00 f2 f2 + >ffff0008c89a7400: 00 00 f3 f3 00 00 00 00 00 00 00 00 00 00 00 00 + ^ + ffff0008c89a7480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + ffff0008c89a7500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + ================================================================== + +Signed-off-by: Ian Nam +Signed-off-by: Shubhrajyoti Datta +Link: https://lore.kernel.org/r/20220510070154.29528-3-shubhrajyoti.datta@xilinx.com +Acked-by: Michal Simek +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/zynqmp/clkc.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c +index db8d0d7161ce..9c82ae240c40 100644 +--- a/drivers/clk/zynqmp/clkc.c ++++ b/drivers/clk/zynqmp/clkc.c +@@ -687,6 +687,13 @@ static void zynqmp_get_clock_info(void) + FIELD_PREP(CLK_ATTR_NODE_INDEX, i); + + zynqmp_pm_clock_get_name(clock[i].clk_id, &name); ++ ++ /* ++ * Terminate with NULL character in case name provided by firmware ++ * is longer and truncated due to size limit. ++ */ ++ name.name[sizeof(name.name) - 1] = '\0'; ++ + if (!strcmp(name.name, RESERVED_CLK_NAME)) + continue; + strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN); +-- +2.35.1 + diff --git a/queue-5.10/clk-zynqmp-pll-rectify-rate-rounding-in-zynqmp_pll_r.patch b/queue-5.10/clk-zynqmp-pll-rectify-rate-rounding-in-zynqmp_pll_r.patch new file mode 100644 index 00000000000..333fcfdcf8f --- /dev/null +++ b/queue-5.10/clk-zynqmp-pll-rectify-rate-rounding-in-zynqmp_pll_r.patch @@ -0,0 +1,92 @@ +From 43366d3dd6ed4fa8c6c3f6cb58418cff8eb88771 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 22:20:30 +0800 +Subject: clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate + +From: Quanyang Wang + +[ Upstream commit 30eaf02149ecc3c5815e45d27187bf09e925071d ] + +The function zynqmp_pll_round_rate is used to find a most appropriate +PLL frequency which the hardware can generate according to the desired +frequency. For example, if the desired frequency is 297MHz, considering +the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz) +of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5). + +There are two problems with the current code of zynqmp_pll_round_rate: + +1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate +when the parameter "rate" is an integer multiple of *prate, in other words, +if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which +is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz +and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and +just return 660MHz, and this will cause clk_calc_new_rates failure since +zynqmp_pll_round_rate returns an invalid rate out of its boundaries. + +2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk +that zynqmp_pll_round_rate returns an invalid rate because the function +DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent +clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz, +this function will return 1499999985Hz by using the formula below: + value = *prate * DIV_ROUND_CLOSEST(rate, *prate)). +This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN. +because DIV_ROUND_CLOSEST makes some loss in the fractional part. + +Signed-off-by: Quanyang Wang +Link: https://lore.kernel.org/r/20220826142030.213805-1-quanyang.wang@windriver.com +Reviewed-by: Shubhrajyoti Datta +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +--- + drivers/clk/zynqmp/pll.c | 31 +++++++++++++++---------------- + 1 file changed, 15 insertions(+), 16 deletions(-) + +diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c +index abe6afbf3407..2ae7f9129b07 100644 +--- a/drivers/clk/zynqmp/pll.c ++++ b/drivers/clk/zynqmp/pll.c +@@ -99,26 +99,25 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) + { + u32 fbdiv; +- long rate_div, f; ++ u32 mult, div; + +- /* Enable the fractional mode if needed */ +- rate_div = (rate * FRAC_DIV) / *prate; +- f = rate_div % FRAC_DIV; +- if (f) { +- if (rate > PS_PLL_VCO_MAX) { +- fbdiv = rate / PS_PLL_VCO_MAX; +- rate = rate / (fbdiv + 1); +- } +- if (rate < PS_PLL_VCO_MIN) { +- fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); +- rate = rate * fbdiv; +- } +- return rate; ++ /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */ ++ if (rate > PS_PLL_VCO_MAX) { ++ div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX); ++ rate = rate / div; ++ } ++ if (rate < PS_PLL_VCO_MIN) { ++ mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); ++ rate = rate * mult; + } + + fbdiv = DIV_ROUND_CLOSEST(rate, *prate); +- fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); +- return *prate * fbdiv; ++ if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { ++ fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); ++ rate = *prate * fbdiv; ++ } ++ ++ return rate; + } + + /** +-- +2.35.1 + diff --git a/queue-5.10/crypto-akcipher-default-implementation-for-setting-a.patch b/queue-5.10/crypto-akcipher-default-implementation-for-setting-a.patch new file mode 100644 index 00000000000..cbf9061318a --- /dev/null +++ b/queue-5.10/crypto-akcipher-default-implementation-for-setting-a.patch @@ -0,0 +1,70 @@ +From 2e65eda9eb8ed8046c587099032b0fb46866a8ae Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 31 Aug 2022 19:37:06 +0100 +Subject: crypto: akcipher - default implementation for setting a private key + +From: Ignat Korchagin + +[ Upstream commit bc155c6c188c2f0c5749993b1405673d25a80389 ] + +Changes from v1: + * removed the default implementation from set_pub_key: it is assumed that + an implementation must always have this callback defined as there are + no use case for an algorithm, which doesn't need a public key + +Many akcipher implementations (like ECDSA) support only signature +verifications, so they don't have all callbacks defined. + +Commit 78a0324f4a53 ("crypto: akcipher - default implementations for +request callbacks") introduced default callbacks for sign/verify +operations, which just return an error code. + +However, these are not enough, because before calling sign the caller would +likely call set_priv_key first on the instantiated transform (as the +in-kernel testmgr does). This function does not have a default stub, so the +kernel crashes, when trying to set a private key on an akcipher, which +doesn't support signature generation. + +I've noticed this, when trying to add a KAT vector for ECDSA signature to +the testmgr. + +With this patch the testmgr returns an error in dmesg (as it should) +instead of crashing the kernel NULL ptr dereference. + +Fixes: 78a0324f4a53 ("crypto: akcipher - default implementations for request callbacks") +Signed-off-by: Ignat Korchagin +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + crypto/akcipher.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/crypto/akcipher.c b/crypto/akcipher.c +index f866085c8a4a..ab975a420e1e 100644 +--- a/crypto/akcipher.c ++++ b/crypto/akcipher.c +@@ -120,6 +120,12 @@ static int akcipher_default_op(struct akcipher_request *req) + return -ENOSYS; + } + ++static int akcipher_default_set_key(struct crypto_akcipher *tfm, ++ const void *key, unsigned int keylen) ++{ ++ return -ENOSYS; ++} ++ + int crypto_register_akcipher(struct akcipher_alg *alg) + { + struct crypto_alg *base = &alg->base; +@@ -132,6 +138,8 @@ int crypto_register_akcipher(struct akcipher_alg *alg) + alg->encrypt = akcipher_default_op; + if (!alg->decrypt) + alg->decrypt = akcipher_default_op; ++ if (!alg->set_priv_key) ++ alg->set_priv_key = akcipher_default_set_key; + + akcipher_prepare_alg(alg); + return crypto_register_alg(base); +-- +2.35.1 + diff --git a/queue-5.10/crypto-cavium-prevent-integer-overflow-loading-firmw.patch b/queue-5.10/crypto-cavium-prevent-integer-overflow-loading-firmw.patch new file mode 100644 index 00000000000..67eb80865d3 --- /dev/null +++ b/queue-5.10/crypto-cavium-prevent-integer-overflow-loading-firmw.patch @@ -0,0 +1,56 @@ +From 16d35d51a753eb2ec15e0d860e5fa2d912b5ac12 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 09:43:27 +0300 +Subject: crypto: cavium - prevent integer overflow loading firmware + +From: Dan Carpenter + +[ Upstream commit 2526d6bf27d15054bb0778b2f7bc6625fd934905 ] + +The "code_length" value comes from the firmware file. If your firmware +is untrusted realistically there is probably very little you can do to +protect yourself. Still we try to limit the damage as much as possible. +Also Smatch marks any data read from the filesystem as untrusted and +prints warnings if it not capped correctly. + +The "ntohl(ucode->code_length) * 2" multiplication can have an +integer overflow. + +Fixes: 9e2c7d99941d ("crypto: cavium - Add Support for Octeon-tx CPT Engine") +Signed-off-by: Dan Carpenter +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/cavium/cpt/cptpf_main.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/cavium/cpt/cptpf_main.c b/drivers/crypto/cavium/cpt/cptpf_main.c +index 781949027451..d9362199423f 100644 +--- a/drivers/crypto/cavium/cpt/cptpf_main.c ++++ b/drivers/crypto/cavium/cpt/cptpf_main.c +@@ -254,6 +254,7 @@ static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae) + const struct firmware *fw_entry; + struct device *dev = &cpt->pdev->dev; + struct ucode_header *ucode; ++ unsigned int code_length; + struct microcode *mcode; + int j, ret = 0; + +@@ -264,11 +265,12 @@ static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae) + ucode = (struct ucode_header *)fw_entry->data; + mcode = &cpt->mcode[cpt->next_mc_idx]; + memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ); +- mcode->code_size = ntohl(ucode->code_length) * 2; +- if (!mcode->code_size) { ++ code_length = ntohl(ucode->code_length); ++ if (code_length == 0 || code_length >= INT_MAX / 2) { + ret = -EINVAL; + goto fw_release; + } ++ mcode->code_size = code_length * 2; + + mcode->is_ae = is_ae; + mcode->core_mask = 0ULL; +-- +2.35.1 + diff --git a/queue-5.10/crypto-ccp-release-dma-channels-before-dmaengine-unr.patch b/queue-5.10/crypto-ccp-release-dma-channels-before-dmaengine-unr.patch new file mode 100644 index 00000000000..89fdad3e2e0 --- /dev/null +++ b/queue-5.10/crypto-ccp-release-dma-channels-before-dmaengine-unr.patch @@ -0,0 +1,54 @@ +From 3b8fdc8cc0cce01932b038a1b5988d93b1732226 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 22:47:12 +0800 +Subject: crypto: ccp - Release dma channels before dmaengine unrgister + +From: Koba Ko + +[ Upstream commit 68dbe80f5b510c66c800b9e8055235c5b07e37d1 ] + +A warning is shown during shutdown, + +__dma_async_device_channel_unregister called while 2 clients hold a reference +WARNING: CPU: 15 PID: 1 at drivers/dma/dmaengine.c:1110 __dma_async_device_channel_unregister+0xb7/0xc0 + +Call dma_release_channel for occupied channles before dma_async_device_unregister. + +Fixes: 54cce8ecb925 ("crypto: ccp - ccp_dmaengine_unregister release dma channels") +Reported-by: kernel test robot +Signed-off-by: Koba Ko +Acked-by: Tom Lendacky +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/ccp/ccp-dmaengine.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/ccp/ccp-dmaengine.c b/drivers/crypto/ccp/ccp-dmaengine.c +index b3eea329f840..b9299defb431 100644 +--- a/drivers/crypto/ccp/ccp-dmaengine.c ++++ b/drivers/crypto/ccp/ccp-dmaengine.c +@@ -642,6 +642,10 @@ static void ccp_dma_release(struct ccp_device *ccp) + for (i = 0; i < ccp->cmd_q_count; i++) { + chan = ccp->ccp_dma_chan + i; + dma_chan = &chan->dma_chan; ++ ++ if (dma_chan->client_count) ++ dma_release_channel(dma_chan); ++ + tasklet_kill(&chan->cleanup_tasklet); + list_del_rcu(&dma_chan->device_node); + } +@@ -767,8 +771,8 @@ void ccp_dmaengine_unregister(struct ccp_device *ccp) + if (!dmaengine) + return; + +- dma_async_device_unregister(dma_dev); + ccp_dma_release(ccp); ++ dma_async_device_unregister(dma_dev); + + kmem_cache_destroy(ccp->dma_desc_cache); + kmem_cache_destroy(ccp->dma_cmd_cache); +-- +2.35.1 + diff --git a/queue-5.10/crypto-hisilicon-zip-fix-mismatch-in-get-set-sgl_sge.patch b/queue-5.10/crypto-hisilicon-zip-fix-mismatch-in-get-set-sgl_sge.patch new file mode 100644 index 00000000000..429a97bbb79 --- /dev/null +++ b/queue-5.10/crypto-hisilicon-zip-fix-mismatch-in-get-set-sgl_sge.patch @@ -0,0 +1,53 @@ +From 16963043ab1e18a4c9d3b32c7f9851545c137bef Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Jul 2022 10:07:58 +0800 +Subject: crypto: hisilicon/zip - fix mismatch in get/set sgl_sge_nr + +From: Ye Weihua + +[ Upstream commit d74f9340097a881869c4c22ca376654cc2516ecc ] + +KASAN reported this Bug: + + [17619.659757] BUG: KASAN: global-out-of-bounds in param_get_int+0x34/0x60 + [17619.673193] Read of size 4 at addr fffff01332d7ed00 by task read_all/1507958 + ... + [17619.698934] The buggy address belongs to the variable: + [17619.708371] sgl_sge_nr+0x0/0xffffffffffffa300 [hisi_zip] + +There is a mismatch in hisi_zip when get/set the variable sgl_sge_nr. +The type of sgl_sge_nr is u16, and get/set sgl_sge_nr by +param_get/set_int. + +Replacing param_get/set_int to param_get/set_ushort can fix this bug. + +Fixes: f081fda293ffb ("crypto: hisilicon - add sgl_sge_nr module param for zip") +Signed-off-by: Ye Weihua +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/hisilicon/zip/zip_crypto.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/hisilicon/zip/zip_crypto.c b/drivers/crypto/hisilicon/zip/zip_crypto.c +index 08b4660b014c..5db7cdea994a 100644 +--- a/drivers/crypto/hisilicon/zip/zip_crypto.c ++++ b/drivers/crypto/hisilicon/zip/zip_crypto.c +@@ -107,12 +107,12 @@ static int sgl_sge_nr_set(const char *val, const struct kernel_param *kp) + if (ret || n == 0 || n > HISI_ACC_SGL_SGE_NR_MAX) + return -EINVAL; + +- return param_set_int(val, kp); ++ return param_set_ushort(val, kp); + } + + static const struct kernel_param_ops sgl_sge_nr_ops = { + .set = sgl_sge_nr_set, +- .get = param_get_int, ++ .get = param_get_ushort, + }; + + static u16 sgl_sge_nr = HZIP_SGL_SGE_NR; +-- +2.35.1 + diff --git a/queue-5.10/crypto-inside-secure-change-swab-to-swab32.patch b/queue-5.10/crypto-inside-secure-change-swab-to-swab32.patch new file mode 100644 index 00000000000..9526e55e357 --- /dev/null +++ b/queue-5.10/crypto-inside-secure-change-swab-to-swab32.patch @@ -0,0 +1,65 @@ +From 46e415c334a287ae2caea9f0d447353aa2862969 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 10:51:28 +0800 +Subject: crypto: inside-secure - Change swab to swab32 + +From: Peter Harliman Liem + +[ Upstream commit 664593407e936b6438fbfaaf98876910fd31cf9a ] + +The use of swab() is causing failures in 64-bit arch, as it +translates to __swab64() instead of the intended __swab32(). +It eventually causes wrong results in xcbcmac & cmac algo. + +Fixes: 78cf1c8bfcb8 ("crypto: inside-secure - Move ipad/opad into safexcel_context") +Signed-off-by: Peter Harliman Liem +Acked-by: Antoine Tenart +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/inside-secure/safexcel_hash.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/crypto/inside-secure/safexcel_hash.c b/drivers/crypto/inside-secure/safexcel_hash.c +index 56d5ccb5cc00..1c9af02eb63b 100644 +--- a/drivers/crypto/inside-secure/safexcel_hash.c ++++ b/drivers/crypto/inside-secure/safexcel_hash.c +@@ -381,7 +381,7 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring, + u32 x; + + x = ipad[i] ^ ipad[i + 4]; +- cache[i] ^= swab(x); ++ cache[i] ^= swab32(x); + } + } + cache_len = AES_BLOCK_SIZE; +@@ -819,7 +819,7 @@ static int safexcel_ahash_final(struct ahash_request *areq) + u32 *result = (void *)areq->result; + + /* K3 */ +- result[i] = swab(ctx->base.ipad.word[i + 4]); ++ result[i] = swab32(ctx->base.ipad.word[i + 4]); + } + areq->result[0] ^= 0x80; // 10- padding + crypto_cipher_encrypt_one(ctx->kaes, areq->result, areq->result); +@@ -2104,7 +2104,7 @@ static int safexcel_xcbcmac_setkey(struct crypto_ahash *tfm, const u8 *key, + crypto_cipher_encrypt_one(ctx->kaes, (u8 *)key_tmp + AES_BLOCK_SIZE, + "\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3"); + for (i = 0; i < 3 * AES_BLOCK_SIZE / sizeof(u32); i++) +- ctx->base.ipad.word[i] = swab(key_tmp[i]); ++ ctx->base.ipad.word[i] = swab32(key_tmp[i]); + + crypto_cipher_clear_flags(ctx->kaes, CRYPTO_TFM_REQ_MASK); + crypto_cipher_set_flags(ctx->kaes, crypto_ahash_get_flags(tfm) & +@@ -2187,7 +2187,7 @@ static int safexcel_cmac_setkey(struct crypto_ahash *tfm, const u8 *key, + return ret; + + for (i = 0; i < len / sizeof(u32); i++) +- ctx->base.ipad.word[i + 8] = swab(aes.key_enc[i]); ++ ctx->base.ipad.word[i + 8] = swab32(aes.key_enc[i]); + + /* precompute the CMAC key material */ + crypto_cipher_clear_flags(ctx->kaes, CRYPTO_TFM_REQ_MASK); +-- +2.35.1 + diff --git a/queue-5.10/crypto-marvell-octeontx-prevent-integer-overflows.patch b/queue-5.10/crypto-marvell-octeontx-prevent-integer-overflows.patch new file mode 100644 index 00000000000..786df6f4cf7 --- /dev/null +++ b/queue-5.10/crypto-marvell-octeontx-prevent-integer-overflows.patch @@ -0,0 +1,79 @@ +From 564f4fb52fb27de4f4690c4fad85c88c14e6dc08 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 09:43:19 +0300 +Subject: crypto: marvell/octeontx - prevent integer overflows + +From: Dan Carpenter + +[ Upstream commit caca37cf6c749ff0303f68418cfe7b757a4e0697 ] + +The "code_length" value comes from the firmware file. If your firmware +is untrusted realistically there is probably very little you can do to +protect yourself. Still we try to limit the damage as much as possible. +Also Smatch marks any data read from the filesystem as untrusted and +prints warnings if it not capped correctly. + +The "code_length * 2" can overflow. The round_up(ucode_size, 16) + +sizeof() expression can overflow too. Prevent these overflows. + +Fixes: d9110b0b01ff ("crypto: marvell - add support for OCTEON TX CPT engine") +Signed-off-by: Dan Carpenter +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + .../crypto/marvell/octeontx/otx_cptpf_ucode.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c +index 40b482198ebc..a765eefb18c2 100644 +--- a/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c ++++ b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c +@@ -286,6 +286,7 @@ static int process_tar_file(struct device *dev, + struct tar_ucode_info_t *tar_info; + struct otx_cpt_ucode_hdr *ucode_hdr; + int ucode_type, ucode_size; ++ unsigned int code_length; + + /* + * If size is less than microcode header size then don't report +@@ -303,7 +304,13 @@ static int process_tar_file(struct device *dev, + if (get_ucode_type(ucode_hdr, &ucode_type)) + return 0; + +- ucode_size = ntohl(ucode_hdr->code_length) * 2; ++ code_length = ntohl(ucode_hdr->code_length); ++ if (code_length >= INT_MAX / 2) { ++ dev_err(dev, "Invalid code_length %u\n", code_length); ++ return -EINVAL; ++ } ++ ++ ucode_size = code_length * 2; + if (!ucode_size || (size < round_up(ucode_size, 16) + + sizeof(struct otx_cpt_ucode_hdr) + OTX_CPT_UCODE_SIGN_LEN)) { + dev_err(dev, "Ucode %s invalid size\n", filename); +@@ -886,6 +893,7 @@ static int ucode_load(struct device *dev, struct otx_cpt_ucode *ucode, + { + struct otx_cpt_ucode_hdr *ucode_hdr; + const struct firmware *fw; ++ unsigned int code_length; + int ret; + + set_ucode_filename(ucode, ucode_filename); +@@ -896,7 +904,13 @@ static int ucode_load(struct device *dev, struct otx_cpt_ucode *ucode, + ucode_hdr = (struct otx_cpt_ucode_hdr *) fw->data; + memcpy(ucode->ver_str, ucode_hdr->ver_str, OTX_CPT_UCODE_VER_STR_SZ); + ucode->ver_num = ucode_hdr->ver_num; +- ucode->size = ntohl(ucode_hdr->code_length) * 2; ++ code_length = ntohl(ucode_hdr->code_length); ++ if (code_length >= INT_MAX / 2) { ++ dev_err(dev, "Ucode invalid code_length %u\n", code_length); ++ ret = -EINVAL; ++ goto release_fw; ++ } ++ ucode->size = code_length * 2; + if (!ucode->size || (fw->size < round_up(ucode->size, 16) + + sizeof(struct otx_cpt_ucode_hdr) + OTX_CPT_UCODE_SIGN_LEN)) { + dev_err(dev, "Ucode %s invalid size\n", ucode_filename); +-- +2.35.1 + diff --git a/queue-5.10/crypto-qat-fix-dma-transfer-direction.patch b/queue-5.10/crypto-qat-fix-dma-transfer-direction.patch new file mode 100644 index 00000000000..c892052f787 --- /dev/null +++ b/queue-5.10/crypto-qat-fix-dma-transfer-direction.patch @@ -0,0 +1,156 @@ +From a4e9eb48c20908c4cdf409138c13b377aad9cdc3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 11:49:12 +0100 +Subject: crypto: qat - fix DMA transfer direction + +From: Damian Muszynski + +[ Upstream commit cf5bb835b7c8a5fee7f26455099cca7feb57f5e9 ] + +When CONFIG_DMA_API_DEBUG is selected, while running the crypto self +test on the QAT crypto algorithms, the function add_dma_entry() reports +a warning similar to the one below, saying that overlapping mappings +are not supported. This occurs in tests where the input and the output +scatter list point to the same buffers (i.e. two different scatter lists +which point to the same chunks of memory). + +The logic that implements the mapping uses the flag DMA_BIDIRECTIONAL +for both the input and the output scatter lists which leads to +overlapped write mappings. These are not supported by the DMA layer. + +Fix by specifying the correct DMA transfer directions when mapping +buffers. For in-place operations where the input scatter list +matches the output scatter list, buffers are mapped once with +DMA_BIDIRECTIONAL, otherwise input buffers are mapped using the flag +DMA_TO_DEVICE and output buffers are mapped with DMA_FROM_DEVICE. +Overlapping a read mapping with a write mapping is a valid case in +dma-coherent devices like QAT. +The function that frees and unmaps the buffers, qat_alg_free_bufl() +has been changed accordingly to the changes to the mapping function. + + DMA-API: 4xxx 0000:06:00.0: cacheline tracking EEXIST, overlapping mappings aren't supported + WARNING: CPU: 53 PID: 4362 at kernel/dma/debug.c:570 add_dma_entry+0x1e9/0x270 + ... + Call Trace: + dma_map_page_attrs+0x82/0x2d0 + ? preempt_count_add+0x6a/0xa0 + qat_alg_sgl_to_bufl+0x45b/0x990 [intel_qat] + qat_alg_aead_dec+0x71/0x250 [intel_qat] + crypto_aead_decrypt+0x3d/0x70 + test_aead_vec_cfg+0x649/0x810 + ? number+0x310/0x3a0 + ? vsnprintf+0x2a3/0x550 + ? scnprintf+0x42/0x70 + ? valid_sg_divisions.constprop.0+0x86/0xa0 + ? test_aead_vec+0xdf/0x120 + test_aead_vec+0xdf/0x120 + alg_test_aead+0x185/0x400 + alg_test+0x3d8/0x500 + ? crypto_acomp_scomp_free_ctx+0x30/0x30 + ? __schedule+0x32a/0x12a0 + ? ttwu_queue_wakelist+0xbf/0x110 + ? _raw_spin_unlock_irqrestore+0x23/0x40 + ? try_to_wake_up+0x83/0x570 + ? _raw_spin_unlock_irqrestore+0x23/0x40 + ? __set_cpus_allowed_ptr_locked+0xea/0x1b0 + ? crypto_acomp_scomp_free_ctx+0x30/0x30 + cryptomgr_test+0x27/0x50 + kthread+0xe6/0x110 + ? kthread_complete_and_exit+0x20/0x20 + ret_from_fork+0x1f/0x30 + +Fixes: d370cec ("crypto: qat - Intel(R) QAT crypto interface") +Link: https://lore.kernel.org/linux-crypto/20220223080400.139367-1-gilad@benyossef.com/ +Signed-off-by: Damian Muszynski +Signed-off-by: Giovanni Cabiddu +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/qat/qat_common/qat_algs.c | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c +index 2e2c2ac53609..5b71768fc0c7 100644 +--- a/drivers/crypto/qat/qat_common/qat_algs.c ++++ b/drivers/crypto/qat/qat_common/qat_algs.c +@@ -624,11 +624,14 @@ static void qat_alg_free_bufl(struct qat_crypto_instance *inst, + dma_addr_t blpout = qat_req->buf.bloutp; + size_t sz = qat_req->buf.sz; + size_t sz_out = qat_req->buf.sz_out; ++ int bl_dma_dir; + int i; + ++ bl_dma_dir = blp != blpout ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; ++ + for (i = 0; i < bl->num_bufs; i++) + dma_unmap_single(dev, bl->bufers[i].addr, +- bl->bufers[i].len, DMA_BIDIRECTIONAL); ++ bl->bufers[i].len, bl_dma_dir); + + dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE); + +@@ -642,7 +645,7 @@ static void qat_alg_free_bufl(struct qat_crypto_instance *inst, + for (i = bufless; i < blout->num_bufs; i++) { + dma_unmap_single(dev, blout->bufers[i].addr, + blout->bufers[i].len, +- DMA_BIDIRECTIONAL); ++ DMA_FROM_DEVICE); + } + dma_unmap_single(dev, blpout, sz_out, DMA_TO_DEVICE); + +@@ -666,6 +669,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + struct scatterlist *sg; + size_t sz_out, sz = struct_size(bufl, bufers, n); + int node = dev_to_node(&GET_DEV(inst->accel_dev)); ++ int bufl_dma_dir; + + if (unlikely(!n)) + return -EINVAL; +@@ -683,6 +687,8 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + qat_req->buf.sgl_src_valid = true; + } + ++ bufl_dma_dir = sgl != sglout ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; ++ + for_each_sg(sgl, sg, n, i) + bufl->bufers[i].addr = DMA_MAPPING_ERROR; + +@@ -694,7 +700,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + + bufl->bufers[y].addr = dma_map_single(dev, sg_virt(sg), + sg->length, +- DMA_BIDIRECTIONAL); ++ bufl_dma_dir); + bufl->bufers[y].len = sg->length; + if (unlikely(dma_mapping_error(dev, bufl->bufers[y].addr))) + goto err_in; +@@ -737,7 +743,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + + bufers[y].addr = dma_map_single(dev, sg_virt(sg), + sg->length, +- DMA_BIDIRECTIONAL); ++ DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(dev, bufers[y].addr))) + goto err_out; + bufers[y].len = sg->length; +@@ -767,7 +773,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + if (!dma_mapping_error(dev, buflout->bufers[i].addr)) + dma_unmap_single(dev, buflout->bufers[i].addr, + buflout->bufers[i].len, +- DMA_BIDIRECTIONAL); ++ DMA_FROM_DEVICE); + + if (!qat_req->buf.sgl_dst_valid) + kfree(buflout); +@@ -781,7 +787,7 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + if (!dma_mapping_error(dev, bufl->bufers[i].addr)) + dma_unmap_single(dev, bufl->bufers[i].addr, + bufl->bufers[i].len, +- DMA_BIDIRECTIONAL); ++ bufl_dma_dir); + + if (!qat_req->buf.sgl_src_valid) + kfree(bufl); +-- +2.35.1 + diff --git a/queue-5.10/crypto-qat-fix-use-of-dma_map_single.patch b/queue-5.10/crypto-qat-fix-use-of-dma_map_single.patch new file mode 100644 index 00000000000..d06da3311f0 --- /dev/null +++ b/queue-5.10/crypto-qat-fix-use-of-dma_map_single.patch @@ -0,0 +1,115 @@ +From fbce69dbf425a389a8ba88b65a7819992fc00c14 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Mar 2021 14:35:02 +0800 +Subject: crypto: qat - fix use of 'dma_map_single' + +From: Hui Tang + +[ Upstream commit 7cc05071f930a631040fea16a41f9d78771edc49 ] + +DMA_TO_DEVICE synchronisation must be done after the last modification +of the memory region by the software and before it is handed off to +the device. + +Signed-off-by: Hui Tang +Reported-by: kernel test robot +Reported-by: Dan Carpenter +Signed-off-by: Herbert Xu +Stable-dep-of: cf5bb835b7c8 ("crypto: qat - fix DMA transfer direction") +Signed-off-by: Sasha Levin +--- + drivers/crypto/qat/qat_common/qat_algs.c | 27 ++++++++++++------------ + 1 file changed, 14 insertions(+), 13 deletions(-) + +diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c +index 06abe1e2074e..8625e299d445 100644 +--- a/drivers/crypto/qat/qat_common/qat_algs.c ++++ b/drivers/crypto/qat/qat_common/qat_algs.c +@@ -669,8 +669,8 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + int n = sg_nents(sgl); + struct qat_alg_buf_list *bufl; + struct qat_alg_buf_list *buflout = NULL; +- dma_addr_t blp; +- dma_addr_t bloutp; ++ dma_addr_t blp = DMA_MAPPING_ERROR; ++ dma_addr_t bloutp = DMA_MAPPING_ERROR; + struct scatterlist *sg; + size_t sz_out, sz = struct_size(bufl, bufers, n + 1); + +@@ -685,10 +685,6 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + for_each_sg(sgl, sg, n, i) + bufl->bufers[i].addr = DMA_MAPPING_ERROR; + +- blp = dma_map_single(dev, bufl, sz, DMA_TO_DEVICE); +- if (unlikely(dma_mapping_error(dev, blp))) +- goto err_in; +- + for_each_sg(sgl, sg, n, i) { + int y = sg_nctr; + +@@ -704,6 +700,9 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + sg_nctr++; + } + bufl->num_bufs = sg_nctr; ++ blp = dma_map_single(dev, bufl, sz, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(dev, blp))) ++ goto err_in; + qat_req->buf.bl = bufl; + qat_req->buf.blp = blp; + qat_req->buf.sz = sz; +@@ -723,9 +722,6 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + for_each_sg(sglout, sg, n, i) + bufers[i].addr = DMA_MAPPING_ERROR; + +- bloutp = dma_map_single(dev, buflout, sz_out, DMA_TO_DEVICE); +- if (unlikely(dma_mapping_error(dev, bloutp))) +- goto err_out; + for_each_sg(sglout, sg, n, i) { + int y = sg_nctr; + +@@ -742,6 +738,9 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + } + buflout->num_bufs = sg_nctr; + buflout->num_mapped_bufs = sg_nctr; ++ bloutp = dma_map_single(dev, buflout, sz_out, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(dev, bloutp))) ++ goto err_out; + qat_req->buf.blout = buflout; + qat_req->buf.bloutp = bloutp; + qat_req->buf.sz_out = sz_out; +@@ -753,17 +752,21 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + return 0; + + err_out: ++ if (!dma_mapping_error(dev, bloutp)) ++ dma_unmap_single(dev, bloutp, sz_out, DMA_TO_DEVICE); ++ + n = sg_nents(sglout); + for (i = 0; i < n; i++) + if (!dma_mapping_error(dev, buflout->bufers[i].addr)) + dma_unmap_single(dev, buflout->bufers[i].addr, + buflout->bufers[i].len, + DMA_BIDIRECTIONAL); +- if (!dma_mapping_error(dev, bloutp)) +- dma_unmap_single(dev, bloutp, sz_out, DMA_TO_DEVICE); + kfree(buflout); + + err_in: ++ if (!dma_mapping_error(dev, blp)) ++ dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE); ++ + n = sg_nents(sgl); + for (i = 0; i < n; i++) + if (!dma_mapping_error(dev, bufl->bufers[i].addr)) +@@ -771,8 +774,6 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + bufl->bufers[i].len, + DMA_BIDIRECTIONAL); + +- if (!dma_mapping_error(dev, blp)) +- dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE); + kfree(bufl); + + dev_err(dev, "Failed to map buf for dma\n"); +-- +2.35.1 + diff --git a/queue-5.10/crypto-qat-use-pre-allocated-buffers-in-datapath.patch b/queue-5.10/crypto-qat-use-pre-allocated-buffers-in-datapath.patch new file mode 100644 index 00000000000..d58134eba92 --- /dev/null +++ b/queue-5.10/crypto-qat-use-pre-allocated-buffers-in-datapath.patch @@ -0,0 +1,208 @@ +From 9899a99a30307c24f612590bdb534ca327dbeb55 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 9 May 2022 14:34:08 +0100 +Subject: crypto: qat - use pre-allocated buffers in datapath + +From: Giovanni Cabiddu + +[ Upstream commit e0831e7af4e03f2715de102e18e9179ec0a81562 ] + +In order to do DMAs, the QAT device requires that the scatterlist +structures are mapped and translated into a format that the firmware can +understand. This is defined as the composition of a scatter gather list +(SGL) descriptor header, the struct qat_alg_buf_list, plus a variable +number of flat buffer descriptors, the struct qat_alg_buf. + +The allocation and mapping of these data structures is done each time a +request is received from the skcipher and aead APIs. +In an OOM situation, this behaviour might lead to a dead-lock if an +allocation fails. + +Based on the conversation in [1], increase the size of the aead and +skcipher request contexts to include an SGL descriptor that can handle +a maximum of 4 flat buffers. +If requests exceed 4 entries buffers, memory is allocated dynamically. + +[1] https://lore.kernel.org/linux-crypto/20200722072932.GA27544@gondor.apana.org.au/ + +Cc: stable@vger.kernel.org +Fixes: d370cec32194 ("crypto: qat - Intel(R) QAT crypto interface") +Reported-by: Mikulas Patocka +Signed-off-by: Giovanni Cabiddu +Reviewed-by: Marco Chiappero +Reviewed-by: Wojciech Ziemba +Signed-off-by: Herbert Xu +Stable-dep-of: cf5bb835b7c8 ("crypto: qat - fix DMA transfer direction") +Signed-off-by: Sasha Levin +--- + drivers/crypto/qat/qat_common/qat_algs.c | 64 +++++++++++++--------- + drivers/crypto/qat/qat_common/qat_crypto.h | 24 ++++++++ + 2 files changed, 61 insertions(+), 27 deletions(-) + +diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c +index 8625e299d445..2e2c2ac53609 100644 +--- a/drivers/crypto/qat/qat_common/qat_algs.c ++++ b/drivers/crypto/qat/qat_common/qat_algs.c +@@ -34,19 +34,6 @@ + static DEFINE_MUTEX(algs_lock); + static unsigned int active_devs; + +-struct qat_alg_buf { +- u32 len; +- u32 resrvd; +- u64 addr; +-} __packed; +- +-struct qat_alg_buf_list { +- u64 resrvd; +- u32 num_bufs; +- u32 num_mapped_bufs; +- struct qat_alg_buf bufers[]; +-} __packed __aligned(64); +- + /* Common content descriptor */ + struct qat_alg_cd { + union { +@@ -644,7 +631,10 @@ static void qat_alg_free_bufl(struct qat_crypto_instance *inst, + bl->bufers[i].len, DMA_BIDIRECTIONAL); + + dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE); +- kfree(bl); ++ ++ if (!qat_req->buf.sgl_src_valid) ++ kfree(bl); ++ + if (blp != blpout) { + /* If out of place operation dma unmap only data */ + int bufless = blout->num_bufs - blout->num_mapped_bufs; +@@ -655,7 +645,9 @@ static void qat_alg_free_bufl(struct qat_crypto_instance *inst, + DMA_BIDIRECTIONAL); + } + dma_unmap_single(dev, blpout, sz_out, DMA_TO_DEVICE); +- kfree(blout); ++ ++ if (!qat_req->buf.sgl_dst_valid) ++ kfree(blout); + } + } + +@@ -672,15 +664,24 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + dma_addr_t blp = DMA_MAPPING_ERROR; + dma_addr_t bloutp = DMA_MAPPING_ERROR; + struct scatterlist *sg; +- size_t sz_out, sz = struct_size(bufl, bufers, n + 1); ++ size_t sz_out, sz = struct_size(bufl, bufers, n); ++ int node = dev_to_node(&GET_DEV(inst->accel_dev)); + + if (unlikely(!n)) + return -EINVAL; + +- bufl = kzalloc_node(sz, GFP_ATOMIC, +- dev_to_node(&GET_DEV(inst->accel_dev))); +- if (unlikely(!bufl)) +- return -ENOMEM; ++ qat_req->buf.sgl_src_valid = false; ++ qat_req->buf.sgl_dst_valid = false; ++ ++ if (n > QAT_MAX_BUFF_DESC) { ++ bufl = kzalloc_node(sz, GFP_ATOMIC, node); ++ if (unlikely(!bufl)) ++ return -ENOMEM; ++ } else { ++ bufl = &qat_req->buf.sgl_src.sgl_hdr; ++ memset(bufl, 0, sizeof(struct qat_alg_buf_list)); ++ qat_req->buf.sgl_src_valid = true; ++ } + + for_each_sg(sgl, sg, n, i) + bufl->bufers[i].addr = DMA_MAPPING_ERROR; +@@ -711,12 +712,18 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + struct qat_alg_buf *bufers; + + n = sg_nents(sglout); +- sz_out = struct_size(buflout, bufers, n + 1); ++ sz_out = struct_size(buflout, bufers, n); + sg_nctr = 0; +- buflout = kzalloc_node(sz_out, GFP_ATOMIC, +- dev_to_node(&GET_DEV(inst->accel_dev))); +- if (unlikely(!buflout)) +- goto err_in; ++ ++ if (n > QAT_MAX_BUFF_DESC) { ++ buflout = kzalloc_node(sz_out, GFP_ATOMIC, node); ++ if (unlikely(!buflout)) ++ goto err_in; ++ } else { ++ buflout = &qat_req->buf.sgl_dst.sgl_hdr; ++ memset(buflout, 0, sizeof(struct qat_alg_buf_list)); ++ qat_req->buf.sgl_dst_valid = true; ++ } + + bufers = buflout->bufers; + for_each_sg(sglout, sg, n, i) +@@ -761,7 +768,9 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + dma_unmap_single(dev, buflout->bufers[i].addr, + buflout->bufers[i].len, + DMA_BIDIRECTIONAL); +- kfree(buflout); ++ ++ if (!qat_req->buf.sgl_dst_valid) ++ kfree(buflout); + + err_in: + if (!dma_mapping_error(dev, blp)) +@@ -774,7 +783,8 @@ static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst, + bufl->bufers[i].len, + DMA_BIDIRECTIONAL); + +- kfree(bufl); ++ if (!qat_req->buf.sgl_src_valid) ++ kfree(bufl); + + dev_err(dev, "Failed to map buf for dma\n"); + return -ENOMEM; +diff --git a/drivers/crypto/qat/qat_common/qat_crypto.h b/drivers/crypto/qat/qat_common/qat_crypto.h +index 12682d1e9f5f..5f9328201ba4 100644 +--- a/drivers/crypto/qat/qat_common/qat_crypto.h ++++ b/drivers/crypto/qat/qat_common/qat_crypto.h +@@ -20,6 +20,26 @@ struct qat_crypto_instance { + atomic_t refctr; + }; + ++#define QAT_MAX_BUFF_DESC 4 ++ ++struct qat_alg_buf { ++ u32 len; ++ u32 resrvd; ++ u64 addr; ++} __packed; ++ ++struct qat_alg_buf_list { ++ u64 resrvd; ++ u32 num_bufs; ++ u32 num_mapped_bufs; ++ struct qat_alg_buf bufers[]; ++} __packed; ++ ++struct qat_alg_fixed_buf_list { ++ struct qat_alg_buf_list sgl_hdr; ++ struct qat_alg_buf descriptors[QAT_MAX_BUFF_DESC]; ++} __packed __aligned(64); ++ + struct qat_crypto_request_buffs { + struct qat_alg_buf_list *bl; + dma_addr_t blp; +@@ -27,6 +47,10 @@ struct qat_crypto_request_buffs { + dma_addr_t bloutp; + size_t sz; + size_t sz_out; ++ bool sgl_src_valid; ++ bool sgl_dst_valid; ++ struct qat_alg_fixed_buf_list sgl_src; ++ struct qat_alg_fixed_buf_list sgl_dst; + }; + + struct qat_crypto_request; +-- +2.35.1 + diff --git a/queue-5.10/crypto-sahara-don-t-sleep-when-in-softirq.patch b/queue-5.10/crypto-sahara-don-t-sleep-when-in-softirq.patch new file mode 100644 index 00000000000..348ccc15944 --- /dev/null +++ b/queue-5.10/crypto-sahara-don-t-sleep-when-in-softirq.patch @@ -0,0 +1,95 @@ +From 141ed81f41b1b504f024944e12ae72493d73dd2b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Jul 2022 12:09:28 +0800 +Subject: crypto: sahara - don't sleep when in softirq + +From: Zhengchao Shao + +[ Upstream commit 108586eba094b318e6a831f977f4ddcc403a15da ] + +Function of sahara_aes_crypt maybe could be called by function +of crypto_skcipher_encrypt during the rx softirq, so it is not +allowed to use mutex lock. + +Fixes: c0c3c89ae347 ("crypto: sahara - replace tasklets with...") +Signed-off-by: Zhengchao Shao +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/sahara.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c +index d60679c79822..2043dd061121 100644 +--- a/drivers/crypto/sahara.c ++++ b/drivers/crypto/sahara.c +@@ -25,10 +25,10 @@ + #include + #include + #include +-#include + #include + #include + #include ++#include + + #define SHA_BUFFER_LEN PAGE_SIZE + #define SAHARA_MAX_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE +@@ -195,7 +195,7 @@ struct sahara_dev { + void __iomem *regs_base; + struct clk *clk_ipg; + struct clk *clk_ahb; +- struct mutex queue_mutex; ++ spinlock_t queue_spinlock; + struct task_struct *kthread; + struct completion dma_completion; + +@@ -641,9 +641,9 @@ static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode) + + rctx->mode = mode; + +- mutex_lock(&dev->queue_mutex); ++ spin_lock_bh(&dev->queue_spinlock); + err = crypto_enqueue_request(&dev->queue, &req->base); +- mutex_unlock(&dev->queue_mutex); ++ spin_unlock_bh(&dev->queue_spinlock); + + wake_up_process(dev->kthread); + +@@ -1042,10 +1042,10 @@ static int sahara_queue_manage(void *data) + do { + __set_current_state(TASK_INTERRUPTIBLE); + +- mutex_lock(&dev->queue_mutex); ++ spin_lock_bh(&dev->queue_spinlock); + backlog = crypto_get_backlog(&dev->queue); + async_req = crypto_dequeue_request(&dev->queue); +- mutex_unlock(&dev->queue_mutex); ++ spin_unlock_bh(&dev->queue_spinlock); + + if (backlog) + backlog->complete(backlog, -EINPROGRESS); +@@ -1091,9 +1091,9 @@ static int sahara_sha_enqueue(struct ahash_request *req, int last) + rctx->first = 1; + } + +- mutex_lock(&dev->queue_mutex); ++ spin_lock_bh(&dev->queue_spinlock); + ret = crypto_enqueue_request(&dev->queue, &req->base); +- mutex_unlock(&dev->queue_mutex); ++ spin_unlock_bh(&dev->queue_spinlock); + + wake_up_process(dev->kthread); + +@@ -1454,7 +1454,7 @@ static int sahara_probe(struct platform_device *pdev) + + crypto_init_queue(&dev->queue, SAHARA_QUEUE_LENGTH); + +- mutex_init(&dev->queue_mutex); ++ spin_lock_init(&dev->queue_spinlock); + + dev_ptr = dev; + +-- +2.35.1 + diff --git a/queue-5.10/dmaengine-hisilicon-add-multi-thread-support-for-a-d.patch b/queue-5.10/dmaengine-hisilicon-add-multi-thread-support-for-a-d.patch new file mode 100644 index 00000000000..ef68d24c6d7 --- /dev/null +++ b/queue-5.10/dmaengine-hisilicon-add-multi-thread-support-for-a-d.patch @@ -0,0 +1,102 @@ +From 5daa43a5633cdd4824be2e782658550a423e4778 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 14:22:47 +0800 +Subject: dmaengine: hisilicon: Add multi-thread support for a DMA channel + +From: Jie Hai + +[ Upstream commit 2cbb95883c990d0002a77e13d3278913ab26ad79 ] + +When we get a DMA channel and try to use it in multiple threads it +will cause oops and hanging the system. + +% echo 100 > /sys/module/dmatest/parameters/threads_per_chan +% echo 100 > /sys/module/dmatest/parameters/iterations +% echo 1 > /sys/module/dmatest/parameters/run +[383493.327077] Unable to handle kernel paging request at virtual + address dead000000000108 +[383493.335103] Mem abort info: +[383493.335103] ESR = 0x96000044 +[383493.335105] EC = 0x25: DABT (current EL), IL = 32 bits +[383493.335107] SET = 0, FnV = 0 +[383493.335108] EA = 0, S1PTW = 0 +[383493.335109] FSC = 0x04: level 0 translation fault +[383493.335110] Data abort info: +[383493.335111] ISV = 0, ISS = 0x00000044 +[383493.364739] CM = 0, WnR = 1 +[383493.367793] [dead000000000108] address between user and kernel + address ranges +[383493.375021] Internal error: Oops: 96000044 [#1] PREEMPT SMP +[383493.437574] CPU: 63 PID: 27895 Comm: dma0chan0-copy2 Kdump: + loaded Tainted: GO 5.17.0-rc4+ #2 +[383493.457851] pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT + -SSBS BTYPE=--) +[383493.465331] pc : vchan_tx_submit+0x64/0xa0 +[383493.469957] lr : vchan_tx_submit+0x34/0xa0 + +This occurs because the transmission timed out, and that's due +to data race. Each thread rewrite channels's descriptor as soon as +device_issue_pending is called. It leads to the situation that +the driver thinks that it uses the right descriptor in interrupt +handler while channels's descriptor has been changed by other +thread. The descriptor which in fact reported interrupt will not +be handled any more, as well as its tx->callback. +That's why timeout reports. + +With current fixes channels' descriptor changes it's value only +when it has been used. A new descriptor is acquired from +vc->desc_issued queue that is already filled with descriptors +that are ready to be sent. Threads have no direct access to DMA +channel descriptor. In case of channel's descriptor is busy, try +to submit to HW again when a descriptor is completed. In this case, +vc->desc_issued may be empty when hisi_dma_start_transfer is called, +so delete error reporting on this. Now it is just possible to queue +a descriptor for further processing. + +Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") +Signed-off-by: Jie Hai +Acked-by: Zhou Wang +Link: https://lore.kernel.org/r/20220830062251.52993-4-haijie1@huawei.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/hisi_dma.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c +index 08ec90dd4c46..8f1651367310 100644 +--- a/drivers/dma/hisi_dma.c ++++ b/drivers/dma/hisi_dma.c +@@ -276,7 +276,6 @@ static void hisi_dma_start_transfer(struct hisi_dma_chan *chan) + + vd = vchan_next_desc(&chan->vc); + if (!vd) { +- dev_err(&hdma_dev->pdev->dev, "no issued task!\n"); + chan->desc = NULL; + return; + } +@@ -308,7 +307,7 @@ static void hisi_dma_issue_pending(struct dma_chan *c) + + spin_lock_irqsave(&chan->vc.lock, flags); + +- if (vchan_issue_pending(&chan->vc)) ++ if (vchan_issue_pending(&chan->vc) && !chan->desc) + hisi_dma_start_transfer(chan); + + spin_unlock_irqrestore(&chan->vc.lock, flags); +@@ -447,11 +446,10 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) + chan->qp_num, chan->cq_head); + if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) { + vchan_cookie_complete(&desc->vd); ++ hisi_dma_start_transfer(chan); + } else { + dev_err(&hdma_dev->pdev->dev, "task error!\n"); + } +- +- chan->desc = NULL; + } + + spin_unlock_irqrestore(&chan->vc.lock, flags); +-- +2.35.1 + diff --git a/queue-5.10/dmaengine-hisilicon-disable-channels-when-unregister.patch b/queue-5.10/dmaengine-hisilicon-disable-channels-when-unregister.patch new file mode 100644 index 00000000000..81c32d0698a --- /dev/null +++ b/queue-5.10/dmaengine-hisilicon-disable-channels-when-unregister.patch @@ -0,0 +1,72 @@ +From 963557ece690409e6c95c93bd922b657d978fca9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 14:22:45 +0800 +Subject: dmaengine: hisilicon: Disable channels when unregister hisi_dma + +From: Jie Hai + +[ Upstream commit e3bdaa04ada31f46d0586df83a2789b8913053c5 ] + +When hisi_dma is unloaded or unbinded, all of channels should be +disabled. This patch disables DMA channels when driver is unloaded +or unbinded. + +Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") +Signed-off-by: Jie Hai +Acked-by: Zhou Wang +Link: https://lore.kernel.org/r/20220830062251.52993-2-haijie1@huawei.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/hisi_dma.c | 14 +++++++++----- + 1 file changed, 9 insertions(+), 5 deletions(-) + +diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c +index 3e83769615d1..7cedf91e86a9 100644 +--- a/drivers/dma/hisi_dma.c ++++ b/drivers/dma/hisi_dma.c +@@ -185,7 +185,8 @@ static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index) + hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0); + } + +-static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan) ++static void hisi_dma_reset_or_disable_hw_chan(struct hisi_dma_chan *chan, ++ bool disable) + { + struct hisi_dma_dev *hdma_dev = chan->hdma_dev; + u32 index = chan->qp_num, tmp; +@@ -206,8 +207,11 @@ static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan) + hisi_dma_do_reset(hdma_dev, index); + hisi_dma_reset_qp_point(hdma_dev, index); + hisi_dma_pause_dma(hdma_dev, index, false); +- hisi_dma_enable_dma(hdma_dev, index, true); +- hisi_dma_unmask_irq(hdma_dev, index); ++ ++ if (!disable) { ++ hisi_dma_enable_dma(hdma_dev, index, true); ++ hisi_dma_unmask_irq(hdma_dev, index); ++ } + + ret = readl_relaxed_poll_timeout(hdma_dev->base + + HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp, +@@ -223,7 +227,7 @@ static void hisi_dma_free_chan_resources(struct dma_chan *c) + struct hisi_dma_chan *chan = to_hisi_dma_chan(c); + struct hisi_dma_dev *hdma_dev = chan->hdma_dev; + +- hisi_dma_reset_hw_chan(chan); ++ hisi_dma_reset_or_disable_hw_chan(chan, false); + vchan_free_chan_resources(&chan->vc); + + memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth); +@@ -399,7 +403,7 @@ static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) + + static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) + { +- hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]); ++ hisi_dma_reset_or_disable_hw_chan(&hdma_dev->chan[qp_index], true); + } + + static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev) +-- +2.35.1 + diff --git a/queue-5.10/dmaengine-hisilicon-fix-cq-head-update.patch b/queue-5.10/dmaengine-hisilicon-fix-cq-head-update.patch new file mode 100644 index 00000000000..dc955aa5305 --- /dev/null +++ b/queue-5.10/dmaengine-hisilicon-fix-cq-head-update.patch @@ -0,0 +1,55 @@ +From c273965fe9eabf931486fe0a17cd65b1730d0aca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 14:22:46 +0800 +Subject: dmaengine: hisilicon: Fix CQ head update + +From: Jie Hai + +[ Upstream commit 94477a79cf80e8ab55b68f14bc579a12ddea1e0b ] + +After completion of data transfer of one or multiple descriptors, +the completion status and the current head pointer to submission +queue are written into the CQ and interrupt can be generated to +inform the software. In interrupt process CQ is read and cq_head +is updated. + +hisi_dma_irq updates cq_head only when the completion status is +success. When an abnormal interrupt reports, cq_head will not update +which will cause subsequent interrupt processes read the error CQ +and never report the correct status. + +This patch updates cq_head whenever CQ is accessed. + +Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") +Signed-off-by: Jie Hai +Acked-by: Zhou Wang +Link: https://lore.kernel.org/r/20220830062251.52993-3-haijie1@huawei.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/hisi_dma.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c +index 7cedf91e86a9..08ec90dd4c46 100644 +--- a/drivers/dma/hisi_dma.c ++++ b/drivers/dma/hisi_dma.c +@@ -442,12 +442,10 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) + desc = chan->desc; + cqe = chan->cq + chan->cq_head; + if (desc) { ++ chan->cq_head = (chan->cq_head + 1) % hdma_dev->chan_depth; ++ hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, ++ chan->qp_num, chan->cq_head); + if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) { +- chan->cq_head = (chan->cq_head + 1) % +- hdma_dev->chan_depth; +- hisi_dma_chan_write(hdma_dev->base, +- HISI_DMA_CQ_HEAD_PTR, chan->qp_num, +- chan->cq_head); + vchan_cookie_complete(&desc->vd); + } else { + dev_err(&hdma_dev->pdev->dev, "task error!\n"); +-- +2.35.1 + diff --git a/queue-5.10/dmaengine-ioat-stop-mod_timer-from-resurrecting-dele.patch b/queue-5.10/dmaengine-ioat-stop-mod_timer-from-resurrecting-dele.patch new file mode 100644 index 00000000000..43917cc4b0d --- /dev/null +++ b/queue-5.10/dmaengine-ioat-stop-mod_timer-from-resurrecting-dele.patch @@ -0,0 +1,61 @@ +From 6c3153fa130ce3d3d13ca75bb93fe05a90230e33 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 09:58:42 -0700 +Subject: dmaengine: ioat: stop mod_timer from resurrecting deleted timer in + __cleanup() + +From: Dave Jiang + +[ Upstream commit 898ec89dbb55b8294695ad71694a0684e62b2a73 ] + +User reports observing timer event report channel halted but no error +observed in CHANERR register. The driver finished self-test and released +channel resources. Debug shows that __cleanup() can call +mod_timer() after the timer has been deleted and thus resurrect the +timer. While harmless, it causes suprious error message to be emitted. +Use mod_timer_pending() call to prevent deleted timer from being +resurrected. + +Fixes: 3372de5813e4 ("dmaengine: ioatdma: removal of dma_v3.c and relevant ioat3 references") +Signed-off-by: Dave Jiang +Link: https://lore.kernel.org/r/166360672197.3851724.17040290563764838369.stgit@djiang5-desk3.ch.intel.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/ioat/dma.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c +index 37ff4ec7db76..e2070df6cad2 100644 +--- a/drivers/dma/ioat/dma.c ++++ b/drivers/dma/ioat/dma.c +@@ -656,7 +656,7 @@ static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete) + if (active - i == 0) { + dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n", + __func__); +- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); ++ mod_timer_pending(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); + } + + /* microsecond delay by sysfs variable per pending descriptor */ +@@ -682,7 +682,7 @@ static void ioat_cleanup(struct ioatdma_chan *ioat_chan) + + if (chanerr & + (IOAT_CHANERR_HANDLE_MASK | IOAT_CHANERR_RECOVER_MASK)) { +- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); ++ mod_timer_pending(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); + ioat_eh(ioat_chan); + } + } +@@ -879,7 +879,7 @@ static void check_active(struct ioatdma_chan *ioat_chan) + } + + if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) +- mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); ++ mod_timer_pending(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); + } + + static void ioat_reboot_chan(struct ioatdma_chan *ioat_chan) +-- +2.35.1 + diff --git a/queue-5.10/dmaengine-ti-k3-udma-reset-udma_chan_rt-byte-counter.patch b/queue-5.10/dmaengine-ti-k3-udma-reset-udma_chan_rt-byte-counter.patch new file mode 100644 index 00000000000..616e381483e --- /dev/null +++ b/queue-5.10/dmaengine-ti-k3-udma-reset-udma_chan_rt-byte-counter.patch @@ -0,0 +1,115 @@ +From 0a90e68477f43bcea708c72752991f85ea71c229 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 2 Aug 2022 11:18:35 +0530 +Subject: dmaengine: ti: k3-udma: Reset UDMA_CHAN_RT byte counters to prevent + overflow + +From: Vaishnav Achath + +[ Upstream commit 7c94dcfa8fcff2dba53915f1dabfee49a3df8b88 ] + +UDMA_CHAN_RT_*BCNT_REG stores the real-time channel bytecount statistics. +These registers are 32-bit hardware counters and the driver uses these +counters to monitor the operational progress status for a channel, when +transferring more than 4GB of data it was observed that these counters +overflow and completion calculation of a operation gets affected and the +transfer hangs indefinitely. + +This commit adds changes to decrease the byte count for every complete +transaction so that these registers never overflow and the proper byte +count statistics is maintained for ongoing transaction by the RT counters. + +Earlier uc->bcnt used to maintain a count of the completed bytes at driver +side, since the RT counters maintain the statistics of current transaction +now, the maintenance of uc->bcnt is not necessary. + +Signed-off-by: Vaishnav Achath +Acked-by: Peter Ujfalusi +Link: https://lore.kernel.org/r/20220802054835.19482-1-vaishnav.a@ti.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/dma/ti/k3-udma.c | 25 +++++++++++++++++-------- + 1 file changed, 17 insertions(+), 8 deletions(-) + +diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c +index d3902784cae2..eacc4377e4a0 100644 +--- a/drivers/dma/ti/k3-udma.c ++++ b/drivers/dma/ti/k3-udma.c +@@ -235,8 +235,6 @@ struct udma_chan { + + struct udma_tx_drain tx_drain; + +- u32 bcnt; /* number of bytes completed since the start of the channel */ +- + /* Channel configuration parameters */ + struct udma_chan_config config; + +@@ -656,6 +654,20 @@ static void udma_reset_rings(struct udma_chan *uc) + } + } + ++static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val) ++{ ++ if (uc->desc->dir == DMA_DEV_TO_MEM) { ++ udma_rchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val); ++ udma_rchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val); ++ udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val); ++ } else { ++ udma_tchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val); ++ udma_tchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val); ++ if (!uc->bchan) ++ udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val); ++ } ++} ++ + static void udma_reset_counters(struct udma_chan *uc) + { + u32 val; +@@ -687,8 +699,6 @@ static void udma_reset_counters(struct udma_chan *uc) + val = udma_rchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG); + udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val); + } +- +- uc->bcnt = 0; + } + + static int udma_reset_chan(struct udma_chan *uc, bool hard) +@@ -1006,7 +1016,7 @@ static void udma_check_tx_completion(struct work_struct *work) + if (uc->desc) { + struct udma_desc *d = uc->desc; + +- uc->bcnt += d->residue; ++ udma_decrement_byte_counters(uc, d->residue); + udma_start(uc); + vchan_cookie_complete(&d->vd); + break; +@@ -1060,7 +1070,7 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data) + vchan_cyclic_callback(&d->vd); + } else { + if (udma_is_desc_really_done(uc, d)) { +- uc->bcnt += d->residue; ++ udma_decrement_byte_counters(uc, d->residue); + udma_start(uc); + vchan_cookie_complete(&d->vd); + } else { +@@ -1097,7 +1107,7 @@ static irqreturn_t udma_udma_irq_handler(int irq, void *data) + vchan_cyclic_callback(&d->vd); + } else { + /* TODO: figure out the real amount of data */ +- uc->bcnt += d->residue; ++ udma_decrement_byte_counters(uc, d->residue); + udma_start(uc); + vchan_cookie_complete(&d->vd); + } +@@ -2741,7 +2751,6 @@ static enum dma_status udma_tx_status(struct dma_chan *chan, + bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG); + } + +- bcnt -= uc->bcnt; + if (bcnt && !(bcnt % uc->desc->residue)) + residue = 0; + else +-- +2.35.1 + diff --git a/queue-5.10/drivers-serial-jsm-fix-some-leaks-in-probe.patch b/queue-5.10/drivers-serial-jsm-fix-some-leaks-in-probe.patch new file mode 100644 index 00000000000..287a99f0c1f --- /dev/null +++ b/queue-5.10/drivers-serial-jsm-fix-some-leaks-in-probe.patch @@ -0,0 +1,37 @@ +From 145f746b85364655b5c0c5891b300d176d50674d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 14:22:47 +0300 +Subject: drivers: serial: jsm: fix some leaks in probe + +From: Dan Carpenter + +[ Upstream commit 1d5859ef229e381f4db38dce8ed58e4bf862006b ] + +This error path needs to unwind instead of just returning directly. + +Fixes: 03a8482c17dd ("drivers: serial: jsm: Enable support for Digi Classic adapters") +Signed-off-by: Dan Carpenter +Link: https://lore.kernel.org/r/YyxFh1+lOeZ9WfKO@kili +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/jsm/jsm_driver.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/tty/serial/jsm/jsm_driver.c b/drivers/tty/serial/jsm/jsm_driver.c +index cd30da0ef083..b5b61e598b53 100644 +--- a/drivers/tty/serial/jsm/jsm_driver.c ++++ b/drivers/tty/serial/jsm/jsm_driver.c +@@ -212,7 +212,8 @@ static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent) + + break; + default: +- return -ENXIO; ++ rc = -ENXIO; ++ goto out_kfree_brd; + } + + rc = request_irq(brd->irq, brd->bd_ops->intr, IRQF_SHARED, "JSM", brd); +-- +2.35.1 + diff --git a/queue-5.10/drm-amd-display-fix-array-bounds-error-in-dc_stream_.patch b/queue-5.10/drm-amd-display-fix-array-bounds-error-in-dc_stream_.patch new file mode 100644 index 00000000000..ffe44479870 --- /dev/null +++ b/queue-5.10/drm-amd-display-fix-array-bounds-error-in-dc_stream_.patch @@ -0,0 +1,54 @@ +From 5496827f630a0e92e757181b39b66bd65b0daeb5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 27 Sep 2022 15:01:46 -0400 +Subject: drm/amd/display: fix array-bounds error in + dc_stream_remove_writeback() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Hamza Mahfooz + +[ Upstream commit 5d8c3e836fc224dfe633e41f7f2856753b39a905 ] + +Address the following error: +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function ‘dc_stream_remove_writeback’: +drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:55: error: array subscript [0, 0] is outside array bounds of ‘struct dc_writeback_info[1]’ [-Werror=array-bounds] + 527 | stream->writeback_info[j] = stream->writeback_info[i]; + | ~~~~~~~~~~~~~~~~~~~~~~^~~ +In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc.h:1269, + from ./drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:29, + from ./drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.h:29, + from drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:27: +./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_stream.h:241:34: note: while referencing ‘writeback_info’ + 241 | struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; + | + +Currently, we aren't checking to see if j remains within +writeback_info[]'s bounds. So, add a check to make sure that we aren't +overflowing the buffer. + +Reviewed-by: Aurabindo Pillai +Signed-off-by: Hamza Mahfooz +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index d48fd87d3b95..867b8b66293a 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -491,7 +491,7 @@ bool dc_stream_remove_writeback(struct dc *dc, + } + + /* remove writeback info for disabled writeback pipes from stream */ +- for (i = 0, j = 0; i < stream->num_wb_info; i++) { ++ for (i = 0, j = 0; i < stream->num_wb_info && j < MAX_DWB_PIPES; i++) { + if (stream->writeback_info[i].wb_enabled) { + if (i != j) + /* trim the array */ +-- +2.35.1 + diff --git a/queue-5.10/drm-amd-display-fix-overflow-on-min_i64-definition.patch b/queue-5.10/drm-amd-display-fix-overflow-on-min_i64-definition.patch new file mode 100644 index 00000000000..ba1e3a0329e --- /dev/null +++ b/queue-5.10/drm-amd-display-fix-overflow-on-min_i64-definition.patch @@ -0,0 +1,57 @@ +From e3a53057282804233501762a2614c772ce92fc24 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Aug 2022 17:43:26 -0300 +Subject: drm/amd/display: fix overflow on MIN_I64 definition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: David Gow + +[ Upstream commit 6ae0632d17759852c07e2d1e0a31c728eb6ba246 ] + +The definition of MIN_I64 in bw_fixed.c can cause gcc to whinge about +integer overflow, because it is treated as a positive value, which is +then negated. The temporary positive value is not necessarily +representable. + +This causes the following warning: +../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.c:30:19: +warning: integer overflow in expression ‘-9223372036854775808’ of type +‘long long int’ results in ‘-9223372036854775808’ [-Woverflow] + 30 | (int64_t)(-(1LL << 63)) + | ^ + +Writing out (-MAX_I64 - 1) works instead. + +Signed-off-by: David Gow +Signed-off-by: Tales Aparecida +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c +index 6ca288fb5fb9..2d46bc527b21 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c +@@ -26,12 +26,12 @@ + #include "bw_fixed.h" + + +-#define MIN_I64 \ +- (int64_t)(-(1LL << 63)) +- + #define MAX_I64 \ + (int64_t)((1ULL << 63) - 1) + ++#define MIN_I64 \ ++ (-MAX_I64 - 1) ++ + #define FRACTIONAL_PART_MASK \ + ((1ULL << BW_FIXED_BITS_PER_FRACTIONAL_PART) - 1) + +-- +2.35.1 + diff --git a/queue-5.10/drm-amd-display-remove-interface-for-periodic-interr.patch b/queue-5.10/drm-amd-display-remove-interface-for-periodic-interr.patch new file mode 100644 index 00000000000..a1b2b827686 --- /dev/null +++ b/queue-5.10/drm-amd-display-remove-interface-for-periodic-interr.patch @@ -0,0 +1,205 @@ +From 50f0b23d1eed3df0eb1a4ecd9febfe25a5b70c04 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 18:07:59 -0400 +Subject: drm/amd/display: Remove interface for periodic interrupt 1 + +From: Aric Cyr + +[ Upstream commit 97d8d6f075bd8f988589be02b91f6fa644d0b0b8 ] + +[why] +Only a single VLINE interrupt is available so interface should not +expose the second one which is used by DMU firmware. + +[how] +Remove references to periodic_interrupt1 and VLINE1 from DC interfaces. + +Reviewed-by: Jaehyun Chung +Acked-by: Jasdeep Dhillon +Signed-off-by: Aric Cyr +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +++------ + drivers/gpu/drm/amd/display/dc/dc_stream.h | 6 ++-- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 35 ++++++------------- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 3 +- + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 +---- + 5 files changed, 18 insertions(+), 50 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 93f5229c303e..99887bcfada0 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -2202,11 +2202,8 @@ static void copy_stream_update_to_stream(struct dc *dc, + if (update->abm_level) + stream->abm_level = *update->abm_level; + +- if (update->periodic_interrupt0) +- stream->periodic_interrupt0 = *update->periodic_interrupt0; +- +- if (update->periodic_interrupt1) +- stream->periodic_interrupt1 = *update->periodic_interrupt1; ++ if (update->periodic_interrupt) ++ stream->periodic_interrupt = *update->periodic_interrupt; + + if (update->gamut_remap) + stream->gamut_remap_matrix = *update->gamut_remap; +@@ -2288,13 +2285,8 @@ static void commit_planes_do_stream_update(struct dc *dc, + + if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { + +- if (stream_update->periodic_interrupt0 && +- dc->hwss.setup_periodic_interrupt) +- dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0); +- +- if (stream_update->periodic_interrupt1 && +- dc->hwss.setup_periodic_interrupt) +- dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1); ++ if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt) ++ dc->hwss.setup_periodic_interrupt(dc, pipe_ctx); + + if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) || + stream_update->vrr_infopacket || +diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h +index 205bedd1b196..0487c1b8957c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h +@@ -179,8 +179,7 @@ struct dc_stream_state { + /* DMCU info */ + unsigned int abm_level; + +- struct periodic_interrupt_config periodic_interrupt0; +- struct periodic_interrupt_config periodic_interrupt1; ++ struct periodic_interrupt_config periodic_interrupt; + + /* from core_stream struct */ + struct dc_context *ctx; +@@ -244,8 +243,7 @@ struct dc_stream_update { + struct dc_info_packet *hdr_static_metadata; + unsigned int *abm_level; + +- struct periodic_interrupt_config *periodic_interrupt0; +- struct periodic_interrupt_config *periodic_interrupt1; ++ struct periodic_interrupt_config *periodic_interrupt; + + struct dc_info_packet *vrr_infopacket; + struct dc_info_packet *vsc_infopacket; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 31a13daf4289..71a85c5306ed 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -3611,7 +3611,7 @@ void dcn10_calc_vupdate_position( + { + const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing; + int vline_int_offset_from_vupdate = +- pipe_ctx->stream->periodic_interrupt0.lines_offset; ++ pipe_ctx->stream->periodic_interrupt.lines_offset; + int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); + int start_position; + +@@ -3636,18 +3636,10 @@ void dcn10_calc_vupdate_position( + static void dcn10_cal_vline_position( + struct dc *dc, + struct pipe_ctx *pipe_ctx, +- enum vline_select vline, + uint32_t *start_line, + uint32_t *end_line) + { +- enum vertical_interrupt_ref_point ref_point = INVALID_POINT; +- +- if (vline == VLINE0) +- ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point; +- else if (vline == VLINE1) +- ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point; +- +- switch (ref_point) { ++ switch (pipe_ctx->stream->periodic_interrupt.ref_point) { + case START_V_UPDATE: + dcn10_calc_vupdate_position( + dc, +@@ -3656,7 +3648,9 @@ static void dcn10_cal_vline_position( + end_line); + break; + case START_V_SYNC: +- // Suppose to do nothing because vsync is 0; ++ // vsync is line 0 so start_line is just the requested line offset ++ *start_line = pipe_ctx->stream->periodic_interrupt.lines_offset; ++ *end_line = *start_line + 2; + break; + default: + ASSERT(0); +@@ -3666,24 +3660,15 @@ static void dcn10_cal_vline_position( + + void dcn10_setup_periodic_interrupt( + struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- enum vline_select vline) ++ struct pipe_ctx *pipe_ctx) + { + struct timing_generator *tg = pipe_ctx->stream_res.tg; ++ uint32_t start_line = 0; ++ uint32_t end_line = 0; + +- if (vline == VLINE0) { +- uint32_t start_line = 0; +- uint32_t end_line = 0; ++ dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line); + +- dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line); +- +- tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line); +- +- } else if (vline == VLINE1) { +- pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1( +- tg, +- pipe_ctx->stream->periodic_interrupt1.lines_offset); +- } ++ tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line); + } + + void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +index e5691e499023..81b5057d5ff1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +@@ -174,8 +174,7 @@ void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx); + void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx); + void dcn10_setup_periodic_interrupt( + struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- enum vline_select vline); ++ struct pipe_ctx *pipe_ctx); + enum dc_status dcn10_set_clock(struct dc *dc, + enum dc_clock_type clock_type, + uint32_t clk_khz, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index 64c1be818b0e..3165a66c5362 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -32,11 +32,6 @@ + #include "inc/hw/link_encoder.h" + #include "core_status.h" + +-enum vline_select { +- VLINE0, +- VLINE1 +-}; +- + struct pipe_ctx; + struct dc_state; + struct dc_stream_status; +@@ -112,8 +107,7 @@ struct hw_sequencer_funcs { + int group_index, int group_size, + struct pipe_ctx *grouped_pipes[]); + void (*setup_periodic_interrupt)(struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- enum vline_select vline); ++ struct pipe_ctx *pipe_ctx); + void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, + unsigned int vmin, unsigned int vmax, + unsigned int vmid, unsigned int vmid_frame_number); +-- +2.35.1 + diff --git a/queue-5.10/drm-amdgpu-fix-initial-connector-audio-value.patch b/queue-5.10/drm-amdgpu-fix-initial-connector-audio-value.patch new file mode 100644 index 00000000000..145f1c7bfb2 --- /dev/null +++ b/queue-5.10/drm-amdgpu-fix-initial-connector-audio-value.patch @@ -0,0 +1,64 @@ +From 689cb9fe0edd1a86005d559694e2f564f67895dc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 17:24:53 +0800 +Subject: drm/amdgpu: fix initial connector audio value + +From: hongao + +[ Upstream commit 4bb71fce58f30df3f251118291d6b0187ce531e6 ] + +This got lost somewhere along the way, This fixes +audio not working until set_property was called. + +Signed-off-by: hongao +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +index df1f9b88a53f..98d3661336a4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +@@ -1671,10 +1671,12 @@ amdgpu_connector_add(struct amdgpu_device *adev, + adev->mode_info.dither_property, + AMDGPU_FMT_DITHER_DISABLE); + +- if (amdgpu_audio != 0) ++ if (amdgpu_audio != 0) { + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); ++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; ++ } + + subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = true; +@@ -1796,6 +1798,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); ++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, +@@ -1849,6 +1852,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); ++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, +@@ -1899,6 +1903,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); ++ amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-adv7511-fix-cec-power-down-control-regist.patch b/queue-5.10/drm-bridge-adv7511-fix-cec-power-down-control-regist.patch new file mode 100644 index 00000000000..74b35062428 --- /dev/null +++ b/queue-5.10/drm-bridge-adv7511-fix-cec-power-down-control-regist.patch @@ -0,0 +1,69 @@ +From 75610d4e24ef6d083c0497a29c379aed9d324325 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 12 Jun 2022 16:48:53 +0200 +Subject: drm: bridge: adv7511: fix CEC power down control register offset +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alvin Å ipraga + +[ Upstream commit 1d22b6033ea113a4c3850dfa2c0770885c81aec8 ] + +The ADV7511_REG_CEC_CTRL = 0xE2 register is part of the main register +map - not the CEC register map. As such, we shouldn't apply an offset to +the register address. Doing so will cause us to address a bogus register +for chips with a CEC register map offset (e.g. ADV7533). + +Fixes: 3b1b975003e4 ("drm: adv7511/33: add HDMI CEC support") +Signed-off-by: Alvin Å ipraga +Reviewed-by: Robert Foss +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20220612144854.2223873-2-alvin@pqrs.dk +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/adv7511/adv7511.h | 5 +---- + drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 4 ++-- + 2 files changed, 3 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h +index a0f6ee15c248..711061bf3eb7 100644 +--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h +@@ -386,10 +386,7 @@ void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1); + #else + static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511) + { +- unsigned int offset = adv7511->type == ADV7533 ? +- ADV7533_REG_CEC_OFFSET : 0; +- +- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, ++ regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL, + ADV7511_CEC_CTRL_POWER_DOWN); + return 0; + } +diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c +index a20a45c0b353..ddd1305b82b2 100644 +--- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c ++++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c +@@ -316,7 +316,7 @@ int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511) + goto err_cec_alloc; + } + +- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0); ++ regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL, 0); + /* cec soft reset */ + regmap_write(adv7511->regmap_cec, + ADV7511_REG_CEC_SOFT_RESET + offset, 0x01); +@@ -343,7 +343,7 @@ int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511) + dev_info(dev, "Initializing CEC failed with error %d, disabling CEC\n", + ret); + err_cec_parse_dt: +- regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, ++ regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL, + ADV7511_CEC_CTRL_POWER_DOWN); + return ret == -EPROBE_DEFER ? ret : 0; + } +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-avoid-uninitialized-variable-warning.patch b/queue-5.10/drm-bridge-avoid-uninitialized-variable-warning.patch new file mode 100644 index 00000000000..1764c2e3f47 --- /dev/null +++ b/queue-5.10/drm-bridge-avoid-uninitialized-variable-warning.patch @@ -0,0 +1,49 @@ +From 1226d9edd2bace51b9b20b5e04804ca53b7eb708 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Jul 2022 13:55:40 +0300 +Subject: drm/bridge: Avoid uninitialized variable warning + +From: Dan Carpenter + +[ Upstream commit 7d1202738efda60155d98b370b3c70d336be0eea ] + +This code works, but technically it uses "num_in_bus_fmts" before it +has been initialized so it leads to static checker warnings and probably +KMEMsan warnings at run time. Initialize the variable to zero to +silence the warning. + +Fixes: f32df58acc68 ("drm/bridge: Add the necessary bits to support bus format negotiation") +Signed-off-by: Dan Carpenter +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/YrrIs3hoGcPVmXc5@kili +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_bridge.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c +index 044acd07c153..d799ec14fd7f 100644 +--- a/drivers/gpu/drm/drm_bridge.c ++++ b/drivers/gpu/drm/drm_bridge.c +@@ -753,8 +753,8 @@ static int select_bus_fmt_recursive(struct drm_bridge *first_bridge, + struct drm_connector_state *conn_state, + u32 out_bus_fmt) + { ++ unsigned int i, num_in_bus_fmts = 0; + struct drm_bridge_state *cur_state; +- unsigned int num_in_bus_fmts, i; + struct drm_bridge *prev_bridge; + u32 *in_bus_fmts; + int ret; +@@ -875,7 +875,7 @@ drm_atomic_bridge_chain_select_bus_fmts(struct drm_bridge *bridge, + struct drm_connector *conn = conn_state->connector; + struct drm_encoder *encoder = bridge->encoder; + struct drm_bridge_state *last_bridge_state; +- unsigned int i, num_out_bus_fmts; ++ unsigned int i, num_out_bus_fmts = 0; + struct drm_bridge *last_bridge; + u32 *out_bus_fmts; + int ret = 0; +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-dw_hdmi-only-trigger-hotplug-event-on-lin.patch b/queue-5.10/drm-bridge-dw_hdmi-only-trigger-hotplug-event-on-lin.patch new file mode 100644 index 00000000000..148641fbe92 --- /dev/null +++ b/queue-5.10/drm-bridge-dw_hdmi-only-trigger-hotplug-event-on-lin.patch @@ -0,0 +1,65 @@ +From 515eb9b6244fdc7e618e8f5e277fcbd341a99ed2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 20:57:33 +0200 +Subject: drm: bridge: dw_hdmi: only trigger hotplug event on link change + +From: Lucas Stach + +[ Upstream commit da09daf881082266e4075657fac53c7966de8e4d ] + +There are two events that signal a real change of the link state: HPD going +high means the sink is newly connected or wants the source to re-read the +EDID, RX sense going low is a indication that the link has been disconnected. + +Ignore the other two events that also trigger interrupts, but don't need +immediate attention: HPD going low does not necessarily mean the link has +been lost and should not trigger a immediate read of the status. RX sense +going high also does not require a detect cycle, as HPD going high is the +right point in time to read the EDID. + +Signed-off-by: Lucas Stach +Reviewed-by: Neil Armstrong (v1) +Reviewed-by: Robert Foss +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20220826185733.3213248-1-l.stach@pengutronix.de +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index b10228b9e3a9..356c7d0bd035 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -2984,6 +2984,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + { + struct dw_hdmi *hdmi = dev_id; + u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; ++ enum drm_connector_status status = connector_status_unknown; + + intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); + phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); +@@ -3022,13 +3023,15 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); + mutex_unlock(&hdmi->cec_notifier_mutex); + } +- } + +- if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { +- enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD +- ? connector_status_connected +- : connector_status_disconnected; ++ if (phy_stat & HDMI_PHY_HPD) ++ status = connector_status_connected; ++ ++ if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) ++ status = connector_status_disconnected; ++ } + ++ if (status != connector_status_unknown) { + dev_dbg(hdmi->dev, "EVENT=%s\n", + status == connector_status_connected ? + "plugin" : "plugout"); +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-megachips-fix-a-null-pointer-dereference-.patch b/queue-5.10/drm-bridge-megachips-fix-a-null-pointer-dereference-.patch new file mode 100644 index 00000000000..4bd6f3bea52 --- /dev/null +++ b/queue-5.10/drm-bridge-megachips-fix-a-null-pointer-dereference-.patch @@ -0,0 +1,52 @@ +From cb29ebb4e47ba7db84d1a320265043c40ae4a66a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 15:34:50 +0800 +Subject: drm/bridge: megachips: Fix a null pointer dereference bug + +From: Zheyu Ma + +[ Upstream commit 1ff673333d46d2c1b053ebd0c1c7c7c79e36943e ] + +When removing the module we will get the following warning: + +[ 31.911505] i2c-core: driver [stdp2690-ge-b850v3-fw] unregistered +[ 31.912484] general protection fault, probably for non-canonical address 0xdffffc0000000001: 0000 [#1] PREEMPT SMP KASAN PTI +[ 31.913338] KASAN: null-ptr-deref in range [0x0000000000000008-0x000000000000000f] +[ 31.915280] RIP: 0010:drm_bridge_remove+0x97/0x130 +[ 31.921825] Call Trace: +[ 31.922533] stdp4028_ge_b850v3_fw_remove+0x34/0x60 [megachips_stdpxxxx_ge_b850v3_fw] +[ 31.923139] i2c_device_remove+0x181/0x1f0 + +The two bridges (stdp2690, stdp4028) do not probe at the same time, so +the driver does not call ge_b850v3_resgiter() when probing, causing the +driver to try to remove the object that has not been initialized. + +Fix this by checking whether both the bridges are probed. + +Fixes: 11632d4aa2b3 ("drm/bridge: megachips: Ensure both bridges are probed before registration") +Signed-off-by: Zheyu Ma +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20220830073450.1897020-1-zheyuma97@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c +index cce98bf2a4e7..72248a565579 100644 +--- a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c ++++ b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c +@@ -296,7 +296,9 @@ static void ge_b850v3_lvds_remove(void) + * This check is to avoid both the drivers + * removing the bridge in their remove() function + */ +- if (!ge_b850v3_lvds_ptr) ++ if (!ge_b850v3_lvds_ptr || ++ !ge_b850v3_lvds_ptr->stdp2690_i2c || ++ !ge_b850v3_lvds_ptr->stdp4028_i2c) + goto out; + + drm_bridge_remove(&ge_b850v3_lvds_ptr->bridge); +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-parade-ps8640-add-support-for-aux-channel.patch b/queue-5.10/drm-bridge-parade-ps8640-add-support-for-aux-channel.patch new file mode 100644 index 00000000000..41812b47bce --- /dev/null +++ b/queue-5.10/drm-bridge-parade-ps8640-add-support-for-aux-channel.patch @@ -0,0 +1,270 @@ +From 029d0d60ff3e472d06508b3d763218ed517f9a93 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Sep 2021 11:06:17 -0700 +Subject: drm/bridge: parade-ps8640: Add support for AUX channel + +From: Philip Chen + +[ Upstream commit 13afcdd7277eff9ab5c92dc0d8d21335d132ab2f ] + +Implement the first version of AUX support, which will be useful as +we expand the driver to support varied use cases. + +Signed-off-by: Philip Chen +Reviewed-by: Sam Ravnborg +Reviewed-by: Douglas Anderson +Reviewed-by: Stephen Boyd +[dianders: whitespace fixes reported by dim apply-branch] +Signed-off-by: Douglas Anderson +Link: https://patchwork.freedesktop.org/patch/msgid/20210921110556.v6.2.I1d6ea362dc76efa77cca2b46253d31b7651eaf17@changeid +Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/parade-ps8640.c | 180 ++++++++++++++++++++++++- + 1 file changed, 179 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c +index 88c9f3404ac1..43afa848a36a 100644 +--- a/drivers/gpu/drm/bridge/parade-ps8640.c ++++ b/drivers/gpu/drm/bridge/parade-ps8640.c +@@ -13,11 +13,36 @@ + #include + + #include ++#include + #include + #include + #include + #include + ++#define PAGE0_AUXCH_CFG3 0x76 ++#define AUXCH_CFG3_RESET 0xff ++#define PAGE0_SWAUX_ADDR_7_0 0x7d ++#define PAGE0_SWAUX_ADDR_15_8 0x7e ++#define PAGE0_SWAUX_ADDR_23_16 0x7f ++#define SWAUX_ADDR_MASK GENMASK(19, 0) ++#define PAGE0_SWAUX_LENGTH 0x80 ++#define SWAUX_LENGTH_MASK GENMASK(3, 0) ++#define SWAUX_NO_PAYLOAD BIT(7) ++#define PAGE0_SWAUX_WDATA 0x81 ++#define PAGE0_SWAUX_RDATA 0x82 ++#define PAGE0_SWAUX_CTRL 0x83 ++#define SWAUX_SEND BIT(0) ++#define PAGE0_SWAUX_STATUS 0x84 ++#define SWAUX_M_MASK GENMASK(4, 0) ++#define SWAUX_STATUS_MASK GENMASK(7, 5) ++#define SWAUX_STATUS_NACK (0x1 << 5) ++#define SWAUX_STATUS_DEFER (0x2 << 5) ++#define SWAUX_STATUS_ACKM (0x3 << 5) ++#define SWAUX_STATUS_INVALID (0x4 << 5) ++#define SWAUX_STATUS_I2C_NACK (0x5 << 5) ++#define SWAUX_STATUS_I2C_DEFER (0x6 << 5) ++#define SWAUX_STATUS_TIMEOUT (0x7 << 5) ++ + #define PAGE2_GPIO_H 0xa7 + #define PS_GPIO9 BIT(1) + #define PAGE2_I2C_BYPASS 0xea +@@ -66,6 +91,7 @@ enum ps8640_vdo_control { + struct ps8640 { + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; ++ struct drm_dp_aux aux; + struct mipi_dsi_device *dsi; + struct i2c_client *page[MAX_DEVS]; + struct regmap *regmap[MAX_DEVS]; +@@ -115,6 +141,137 @@ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) + return container_of(e, struct ps8640, bridge); + } + ++static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) ++{ ++ return container_of(aux, struct ps8640, aux); ++} ++ ++static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, ++ struct drm_dp_aux_msg *msg) ++{ ++ struct ps8640 *ps_bridge = aux_to_ps8640(aux); ++ struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; ++ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; ++ unsigned int len = msg->size; ++ unsigned int data; ++ unsigned int base; ++ int ret; ++ u8 request = msg->request & ++ ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); ++ u8 *buf = msg->buffer; ++ u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; ++ u8 i; ++ bool is_native_aux = false; ++ ++ if (len > DP_AUX_MAX_PAYLOAD_BYTES) ++ return -EINVAL; ++ ++ if (msg->address & ~SWAUX_ADDR_MASK) ++ return -EINVAL; ++ ++ switch (request) { ++ case DP_AUX_NATIVE_WRITE: ++ case DP_AUX_NATIVE_READ: ++ is_native_aux = true; ++ fallthrough; ++ case DP_AUX_I2C_WRITE: ++ case DP_AUX_I2C_READ: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); ++ if (ret) { ++ DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", ++ ret); ++ return ret; ++ } ++ ++ /* Assume it's good */ ++ msg->reply = 0; ++ ++ base = PAGE0_SWAUX_ADDR_7_0; ++ addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; ++ addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; ++ addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | ++ (msg->request << 4); ++ addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : ++ ((len - 1) & SWAUX_LENGTH_MASK); ++ ++ regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, ++ ARRAY_SIZE(addr_len)); ++ ++ if (len && (request == DP_AUX_NATIVE_WRITE || ++ request == DP_AUX_I2C_WRITE)) { ++ /* Write to the internal FIFO buffer */ ++ for (i = 0; i < len; i++) { ++ ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); ++ if (ret) { ++ DRM_DEV_ERROR(dev, ++ "failed to write WDATA: %d\n", ++ ret); ++ return ret; ++ } ++ } ++ } ++ ++ regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); ++ ++ /* Zero delay loop because i2c transactions are slow already */ ++ regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, ++ !(data & SWAUX_SEND), 0, 50 * 1000); ++ ++ regmap_read(map, PAGE0_SWAUX_STATUS, &data); ++ if (ret) { ++ DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", ++ ret); ++ return ret; ++ } ++ ++ switch (data & SWAUX_STATUS_MASK) { ++ /* Ignore the DEFER cases as they are already handled in hardware */ ++ case SWAUX_STATUS_NACK: ++ case SWAUX_STATUS_I2C_NACK: ++ /* ++ * The programming guide is not clear about whether a I2C NACK ++ * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So ++ * we handle both cases together. ++ */ ++ if (is_native_aux) ++ msg->reply |= DP_AUX_NATIVE_REPLY_NACK; ++ else ++ msg->reply |= DP_AUX_I2C_REPLY_NACK; ++ ++ fallthrough; ++ case SWAUX_STATUS_ACKM: ++ len = data & SWAUX_M_MASK; ++ break; ++ case SWAUX_STATUS_INVALID: ++ return -EOPNOTSUPP; ++ case SWAUX_STATUS_TIMEOUT: ++ return -ETIMEDOUT; ++ } ++ ++ if (len && (request == DP_AUX_NATIVE_READ || ++ request == DP_AUX_I2C_READ)) { ++ /* Read from the internal FIFO buffer */ ++ for (i = 0; i < len; i++) { ++ ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); ++ if (ret) { ++ DRM_DEV_ERROR(dev, ++ "failed to read RDATA: %d\n", ++ ret); ++ return ret; ++ } ++ ++ buf[i] = data; ++ } ++ } ++ ++ return len; ++} ++ + static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + const enum ps8640_vdo_control ctrl) + { +@@ -284,18 +441,33 @@ static int ps8640_bridge_attach(struct drm_bridge *bridge, + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->lanes = DP_NUM_LANES; + ret = mipi_dsi_attach(dsi); +- if (ret) ++ if (ret) { ++ dev_err(dev, "failed to attach dsi device: %d\n", ret); + goto err_dsi_attach; ++ } ++ ++ ret = drm_dp_aux_register(&ps_bridge->aux); ++ if (ret) { ++ dev_err(dev, "failed to register DP AUX channel: %d\n", ret); ++ goto err_aux_register; ++ } + + /* Attach the panel-bridge to the dsi bridge */ + return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, + &ps_bridge->bridge, flags); + ++err_aux_register: ++ mipi_dsi_detach(dsi); + err_dsi_attach: + mipi_dsi_device_unregister(dsi); + return ret; + } + ++static void ps8640_bridge_detach(struct drm_bridge *bridge) ++{ ++ drm_dp_aux_unregister(&bridge_to_ps8640(bridge)->aux); ++} ++ + static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, + struct drm_connector *connector) + { +@@ -332,6 +504,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, + + static const struct drm_bridge_funcs ps8640_bridge_funcs = { + .attach = ps8640_bridge_attach, ++ .detach = ps8640_bridge_detach, + .get_edid = ps8640_bridge_get_edid, + .post_disable = ps8640_post_disable, + .pre_enable = ps8640_pre_enable, +@@ -407,6 +580,11 @@ static int ps8640_probe(struct i2c_client *client) + + i2c_set_clientdata(client, ps_bridge); + ++ ps_bridge->aux.name = "parade-ps8640-aux"; ++ ps_bridge->aux.dev = dev; ++ ps_bridge->aux.transfer = ps8640_aux_transfer; ++ drm_dp_aux_init(&ps_bridge->aux); ++ + drm_bridge_add(&ps_bridge->bridge); + + return 0; +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-parade-ps8640-enable-runtime-power-manage.patch b/queue-5.10/drm-bridge-parade-ps8640-enable-runtime-power-manage.patch new file mode 100644 index 00000000000..2985065bbf2 --- /dev/null +++ b/queue-5.10/drm-bridge-parade-ps8640-enable-runtime-power-manage.patch @@ -0,0 +1,350 @@ +From 6748190b8ca2e4190e17651940875380113e8cad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Oct 2021 10:58:10 -0700 +Subject: drm/bridge: parade-ps8640: Enable runtime power management + +From: Philip Chen + +[ Upstream commit 826cff3f7ebba460d3db61f135798ce76b0d26ed ] + +Fit ps8640 driver into runtime power management framework: + +First, break _poweron() to 3 parts: (1) turn on power and wait for +ps8640's internal MCU to finish init (2) check panel HPD (which is +proxied by GPIO9) (3) the other configs. As runtime_resume() can be +called before panel is powered, we only add (1) to _resume() and leave +(2)(3) to _pre_enable(). We also add (2) to _aux_transfer() as we want +to ensure panel HPD is asserted before we start AUX CH transactions. + +Second, the original driver has a mysterious delay of 50 ms between (2) +and (3). Since Parade's support can't explain what the delay is for, +and we don't see removing the delay break any boards at hand, remove +the delay to fit into this driver change. + +In addition, rename "powered" to "pre_enabled" and don't check for it +in the pm_runtime calls. The pm_runtime calls are already refcounted +so there's no reason to check there. The other user of "powered", +_get_edid(), only cares if pre_enable() has already been called. + +Lastly, change some existing DRM_...() logging to dev_...() along the +way, since DRM_...() seem to be deprecated in [1]. + +[1] https://patchwork.freedesktop.org/patch/454760/ + +Signed-off-by: Philip Chen +Reviewed-by: Douglas Anderson +Reviewed-by: Stephen Boyd +[dianders: fixed whitespace warning reported by dim tool] +Signed-off-by: Douglas Anderson +Link: https://patchwork.freedesktop.org/patch/msgid/20211028105754.v5.1.I828f5db745535fb7e36e8ffdd62d546f6d08b6d1@changeid +Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/parade-ps8640.c | 190 ++++++++++++++++--------- + 1 file changed, 119 insertions(+), 71 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c +index 43afa848a36a..52f2ea6fcb26 100644 +--- a/drivers/gpu/drm/bridge/parade-ps8640.c ++++ b/drivers/gpu/drm/bridge/parade-ps8640.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -98,7 +99,7 @@ struct ps8640 { + struct regulator_bulk_data supplies[2]; + struct gpio_desc *gpio_reset; + struct gpio_desc *gpio_powerdown; +- bool powered; ++ bool pre_enabled; + }; + + static const struct regmap_config ps8640_regmap_config[] = { +@@ -146,8 +147,29 @@ static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) + return container_of(aux, struct ps8640, aux); + } + +-static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, +- struct drm_dp_aux_msg *msg) ++static int ps8640_ensure_hpd(struct ps8640 *ps_bridge) ++{ ++ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; ++ struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; ++ int status; ++ int ret; ++ ++ /* ++ * Apparently something about the firmware in the chip signals that ++ * HPD goes high by reporting GPIO9 as high (even though HPD isn't ++ * actually connected to GPIO9). ++ */ ++ ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, ++ status & PS_GPIO9, 20 * 1000, 200 * 1000); ++ ++ if (ret < 0) ++ dev_warn(dev, "HPD didn't go high: %d\n", ret); ++ ++ return ret; ++} ++ ++static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, ++ struct drm_dp_aux_msg *msg) + { + struct ps8640 *ps_bridge = aux_to_ps8640(aux); + struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; +@@ -272,38 +294,49 @@ static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, + return len; + } + +-static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, +- const enum ps8640_vdo_control ctrl) ++static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, ++ struct drm_dp_aux_msg *msg) ++{ ++ struct ps8640 *ps_bridge = aux_to_ps8640(aux); ++ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; ++ int ret; ++ ++ pm_runtime_get_sync(dev); ++ ret = ps8640_ensure_hpd(ps_bridge); ++ if (!ret) ++ ret = ps8640_aux_transfer_msg(aux, msg); ++ pm_runtime_mark_last_busy(dev); ++ pm_runtime_put_autosuspend(dev); ++ ++ return ret; ++} ++ ++static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, ++ const enum ps8640_vdo_control ctrl) + { + struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; ++ struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; + u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; + int ret; + + ret = regmap_bulk_write(map, PAGE3_SET_ADD, + vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); + +- if (ret < 0) { +- DRM_ERROR("failed to %sable VDO: %d\n", +- ctrl == ENABLE ? "en" : "dis", ret); +- return ret; +- } +- +- return 0; ++ if (ret < 0) ++ dev_err(dev, "failed to %sable VDO: %d\n", ++ ctrl == ENABLE ? "en" : "dis", ret); + } + +-static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) ++static int __maybe_unused ps8640_resume(struct device *dev) + { +- struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; +- int ret, status; +- +- if (ps_bridge->powered) +- return; ++ struct ps8640 *ps_bridge = dev_get_drvdata(dev); ++ int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); + if (ret < 0) { +- DRM_ERROR("cannot enable regulators %d\n", ret); +- return; ++ dev_err(dev, "cannot enable regulators %d\n", ret); ++ return ret; + } + + gpiod_set_value(ps_bridge->gpio_powerdown, 0); +@@ -312,86 +345,78 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) + gpiod_set_value(ps_bridge->gpio_reset, 0); + + /* +- * Wait for the ps8640 embedded MCU to be ready +- * First wait 200ms and then check the MCU ready flag every 20ms ++ * Mystery 200 ms delay for the "MCU to be ready". It's unclear if ++ * this is truly necessary since the MCU will already signal that ++ * things are "good to go" by signaling HPD on "gpio 9". See ++ * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in ++ * case. + */ + msleep(200); + +- ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, +- status & PS_GPIO9, 20 * 1000, 200 * 1000); +- +- if (ret < 0) { +- DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret); +- goto err_regulators_disable; +- } +- +- msleep(50); +- +- /* +- * The Manufacturer Command Set (MCS) is a device dependent interface +- * intended for factory programming of the display module default +- * parameters. Once the display module is configured, the MCS shall be +- * disabled by the manufacturer. Once disabled, all MCS commands are +- * ignored by the display interface. +- */ +- +- ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); +- if (ret < 0) { +- DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); +- goto err_regulators_disable; +- } +- +- /* Switch access edp panel's edid through i2c */ +- ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); +- if (ret < 0) { +- DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); +- goto err_regulators_disable; +- } +- +- ps_bridge->powered = true; +- +- return; +- +-err_regulators_disable: +- regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), +- ps_bridge->supplies); ++ return 0; + } + +-static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge) ++static int __maybe_unused ps8640_suspend(struct device *dev) + { ++ struct ps8640 *ps_bridge = dev_get_drvdata(dev); + int ret; + +- if (!ps_bridge->powered) +- return; +- + gpiod_set_value(ps_bridge->gpio_reset, 1); + gpiod_set_value(ps_bridge->gpio_powerdown, 1); + ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); + if (ret < 0) +- DRM_ERROR("cannot disable regulators %d\n", ret); ++ dev_err(dev, "cannot disable regulators %d\n", ret); + +- ps_bridge->powered = false; ++ return ret; + } + ++static const struct dev_pm_ops ps8640_pm_ops = { ++ SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++}; ++ + static void ps8640_pre_enable(struct drm_bridge *bridge) + { + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); ++ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; ++ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; + int ret; + +- ps8640_bridge_poweron(ps_bridge); ++ pm_runtime_get_sync(dev); ++ ps8640_ensure_hpd(ps_bridge); + +- ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); ++ /* ++ * The Manufacturer Command Set (MCS) is a device dependent interface ++ * intended for factory programming of the display module default ++ * parameters. Once the display module is configured, the MCS shall be ++ * disabled by the manufacturer. Once disabled, all MCS commands are ++ * ignored by the display interface. ++ */ ++ ++ ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); ++ if (ret < 0) ++ dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); ++ ++ /* Switch access edp panel's edid through i2c */ ++ ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); + if (ret < 0) +- ps8640_bridge_poweroff(ps_bridge); ++ dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); ++ ++ ps8640_bridge_vdo_control(ps_bridge, ENABLE); ++ ++ ps_bridge->pre_enabled = true; + } + + static void ps8640_post_disable(struct drm_bridge *bridge) + { + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + ++ ps_bridge->pre_enabled = false; ++ + ps8640_bridge_vdo_control(ps_bridge, DISABLE); +- ps8640_bridge_poweroff(ps_bridge); ++ pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); + } + + static int ps8640_bridge_attach(struct drm_bridge *bridge, +@@ -472,7 +497,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, + struct drm_connector *connector) + { + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); +- bool poweroff = !ps_bridge->powered; ++ bool poweroff = !ps_bridge->pre_enabled; + struct edid *edid; + + /* +@@ -502,6 +527,12 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, + return edid; + } + ++static void ps8640_runtime_disable(void *data) ++{ ++ pm_runtime_dont_use_autosuspend(data); ++ pm_runtime_disable(data); ++} ++ + static const struct drm_bridge_funcs ps8640_bridge_funcs = { + .attach = ps8640_bridge_attach, + .detach = ps8640_bridge_detach, +@@ -585,6 +616,22 @@ static int ps8640_probe(struct i2c_client *client) + ps_bridge->aux.transfer = ps8640_aux_transfer; + drm_dp_aux_init(&ps_bridge->aux); + ++ pm_runtime_enable(dev); ++ /* ++ * Powering on ps8640 takes ~300ms. To avoid wasting time on power ++ * cycling ps8640 too often, set autosuspend_delay to 500ms to ensure ++ * the bridge wouldn't suspend in between each _aux_transfer_msg() call ++ * during EDID read (~20ms in my experiment) and in between the last ++ * _aux_transfer_msg() call during EDID read and the _pre_enable() call ++ * (~100ms in my experiment). ++ */ ++ pm_runtime_set_autosuspend_delay(dev, 500); ++ pm_runtime_use_autosuspend(dev); ++ pm_suspend_ignore_children(dev, true); ++ ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); ++ if (ret) ++ return ret; ++ + drm_bridge_add(&ps_bridge->bridge); + + return 0; +@@ -611,6 +658,7 @@ static struct i2c_driver ps8640_driver = { + .driver = { + .name = "ps8640", + .of_match_table = ps8640_match, ++ .pm = &ps8640_pm_ops, + }, + }; + module_i2c_driver(ps8640_driver); +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-parade-ps8640-fix-regulator-supply-order.patch b/queue-5.10/drm-bridge-parade-ps8640-fix-regulator-supply-order.patch new file mode 100644 index 00000000000..b46b0a3407c --- /dev/null +++ b/queue-5.10/drm-bridge-parade-ps8640-fix-regulator-supply-order.patch @@ -0,0 +1,44 @@ +From 142437988f919190ff7dc8a5bcf2bda9ccbbc024 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Jul 2022 17:22:58 +0800 +Subject: drm/bridge: parade-ps8640: Fix regulator supply order + +From: Chen-Yu Tsai + +[ Upstream commit fc94224c2e0ae8d83ac511a3ef4962178505469d ] + +The datasheet says that VDD12 must be enabled and at full voltage before +VDD33 is enabled. + +Reorder the bulk regulator supply names so that VDD12 is enabled before +VDD33. Any enable ramp delays should be handled by setting proper +constraints on the regulators. + +Fixes: bc1aee7fc8f0 ("drm/bridge: Add I2C based driver for ps8640 bridge") +Signed-off-by: Chen-Yu Tsai +Reviewed-by: Neil Armstrong +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20220721092258.3397461-1-wenst@chromium.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/parade-ps8640.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c +index 52f2ea6fcb26..1367cc2d6fd7 100644 +--- a/drivers/gpu/drm/bridge/parade-ps8640.c ++++ b/drivers/gpu/drm/bridge/parade-ps8640.c +@@ -565,8 +565,8 @@ static int ps8640_probe(struct i2c_client *client) + if (IS_ERR(ps_bridge->panel_bridge)) + return PTR_ERR(ps_bridge->panel_bridge); + +- ps_bridge->supplies[0].supply = "vdd33"; +- ps_bridge->supplies[1].supply = "vdd12"; ++ ps_bridge->supplies[0].supply = "vdd12"; ++ ps_bridge->supplies[1].supply = "vdd33"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); + if (ret) +-- +2.35.1 + diff --git a/queue-5.10/drm-bridge-parade-ps8640-use-regmap-apis.patch b/queue-5.10/drm-bridge-parade-ps8640-use-regmap-apis.patch new file mode 100644 index 00000000000..b82105e1dee --- /dev/null +++ b/queue-5.10/drm-bridge-parade-ps8640-use-regmap-apis.patch @@ -0,0 +1,204 @@ +From af54466e5b4eef355f8fee40de437401e6f8381a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Sep 2021 11:06:16 -0700 +Subject: drm/bridge: parade-ps8640: Use regmap APIs + +From: Philip Chen + +[ Upstream commit 692d8db0a5ca123017d7d4847856343512f87af9 ] + +Replace the direct i2c access (i2c_smbus_* functions) with regmap APIs, +which will simplify the future update on ps8640 driver. + +Signed-off-by: Philip Chen +Reviewed-by: Douglas Anderson +Acked-by: Sam Ravnborg +Reviewed-by: Stephen Boyd +[dianders: whitespace fixes reported by dim apply-branch] +Signed-off-by: Douglas Anderson +Link: https://patchwork.freedesktop.org/patch/msgid/20210921110556.v6.1.I2351df94f18d5d8debc22d4d100f36fac560409a@changeid +Stable-dep-of: fc94224c2e0a ("drm/bridge: parade-ps8640: Fix regulator supply order") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/parade-ps8640.c | 94 ++++++++++++++++++-------- + 1 file changed, 64 insertions(+), 30 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c +index 7bd0affa057a..88c9f3404ac1 100644 +--- a/drivers/gpu/drm/bridge/parade-ps8640.c ++++ b/drivers/gpu/drm/bridge/parade-ps8640.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -29,6 +30,11 @@ + #define VDO_EN 0x1c + #define DP_NUM_LANES 4 + ++#define COMMON_PS8640_REGMAP_CONFIG \ ++ .reg_bits = 8, \ ++ .val_bits = 8, \ ++ .cache_type = REGCACHE_NONE ++ + /* + * PS8640 uses multiple addresses: + * page[0]: for DP control +@@ -62,12 +68,48 @@ struct ps8640 { + struct drm_bridge *panel_bridge; + struct mipi_dsi_device *dsi; + struct i2c_client *page[MAX_DEVS]; ++ struct regmap *regmap[MAX_DEVS]; + struct regulator_bulk_data supplies[2]; + struct gpio_desc *gpio_reset; + struct gpio_desc *gpio_powerdown; + bool powered; + }; + ++static const struct regmap_config ps8640_regmap_config[] = { ++ [PAGE0_DP_CNTL] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xbf, ++ }, ++ [PAGE1_VDO_BDG] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xff, ++ }, ++ [PAGE2_TOP_CNTL] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xff, ++ }, ++ [PAGE3_DSI_CNTL1] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xff, ++ }, ++ [PAGE4_MIPI_PHY] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xff, ++ }, ++ [PAGE5_VPLL] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0x7f, ++ }, ++ [PAGE6_DSI_CNTL2] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xff, ++ }, ++ [PAGE7_SPI_CNTL] = { ++ COMMON_PS8640_REGMAP_CONFIG, ++ .max_register = 0xff, ++ }, ++}; ++ + static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) + { + return container_of(e, struct ps8640, bridge); +@@ -76,13 +118,13 @@ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) + static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + const enum ps8640_vdo_control ctrl) + { +- struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; ++ struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; + u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; + int ret; + +- ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD, +- sizeof(vdo_ctrl_buf), +- vdo_ctrl_buf); ++ ret = regmap_bulk_write(map, PAGE3_SET_ADD, ++ vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); ++ + if (ret < 0) { + DRM_ERROR("failed to %sable VDO: %d\n", + ctrl == ENABLE ? "en" : "dis", ret); +@@ -94,8 +136,7 @@ static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + + static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) + { +- struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; +- unsigned long timeout; ++ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; + int ret, status; + + if (ps_bridge->powered) +@@ -119,18 +160,12 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) + */ + msleep(200); + +- timeout = jiffies + msecs_to_jiffies(200) + 1; +- +- while (time_is_after_jiffies(timeout)) { +- status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H); +- if (status < 0) { +- DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status); +- goto err_regulators_disable; +- } +- if ((status & PS_GPIO9) == PS_GPIO9) +- break; ++ ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, ++ status & PS_GPIO9, 20 * 1000, 200 * 1000); + +- msleep(20); ++ if (ret < 0) { ++ DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", ret); ++ goto err_regulators_disable; + } + + msleep(50); +@@ -142,22 +177,15 @@ static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ +- status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN); +- if (status < 0) { +- DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status); +- goto err_regulators_disable; +- } + +- ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN, +- status & ~MCS_EN); ++ ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); + if (ret < 0) { + DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); + goto err_regulators_disable; + } + + /* Switch access edp panel's edid through i2c */ +- ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS, +- I2C_BYPASS_EN); ++ ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); + if (ret < 0) { + DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); + goto err_regulators_disable; +@@ -360,15 +388,21 @@ static int ps8640_probe(struct i2c_client *client) + + ps_bridge->page[PAGE0_DP_CNTL] = client; + ++ ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); ++ if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) ++ return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); ++ + for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { + ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, + client->adapter, + client->addr + i); +- if (IS_ERR(ps_bridge->page[i])) { +- dev_err(dev, "failed i2c dummy device, address %02x\n", +- client->addr + i); ++ if (IS_ERR(ps_bridge->page[i])) + return PTR_ERR(ps_bridge->page[i]); +- } ++ ++ ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], ++ ps8640_regmap_config + i); ++ if (IS_ERR(ps_bridge->regmap[i])) ++ return PTR_ERR(ps_bridge->regmap[i]); + } + + i2c_set_clientdata(client, ps_bridge); +-- +2.35.1 + diff --git a/queue-5.10/drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch b/queue-5.10/drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch new file mode 100644 index 00000000000..c9117f07207 --- /dev/null +++ b/queue-5.10/drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch @@ -0,0 +1,100 @@ +From 3a2da927712dbcd2c37f576acd416ac20c9d7861 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 Sep 2022 22:49:00 -0700 +Subject: drm/dp: Don't rewrite link config when setting phy test pattern + +From: Khaled Almahallawy + +[ Upstream commit 7b4d8db657192066bc6f1f6635d348413dac1e18 ] + +The sequence for Source DP PHY CTS automation is [2][1]: +1- Emulate successful Link Training(LT) +2- Short HPD and change link rates and number of lanes by LT. +(This is same flow for Link Layer CTS) +3- Short HPD and change PHY test pattern and swing/pre-emphasis +levels (This step should not trigger LT) + +The problem is with DP PHY compliance setup as follow: + + [DPTX + on board LTTPR]------Main Link--->[Scope] + ^ | + | | + | | + ----------Aux Ch------>[Aux Emulator] + +At step 3, before writing TRAINING_LANEx_SET/LINK_QUAL_PATTERN_SET +to declare the pattern/swing requested by scope, we write link +config in LINK_BW_SET/LANE_COUNT_SET on a port that has LTTPR. +As LTTPR snoops aux transaction, LINK_BW_SET/LANE_COUNT_SET writes +indicate a LT will start [Check DP 2.0 E11 -Sec 3.6.8.2 & 3.6.8.6.3], +and LTTPR will reset the link and stop sending DP signals to +DPTX/Scope causing the measurements to fail. Note that step 3 will +not trigger LT and DP link will never recovered by the +Aux Emulator/Scope. + +The reset of link can be tested with a monitor connected to LTTPR +port simply by writing to LINK_BW_SET or LANE_COUNT_SET as follow + + igt/tools/dpcd_reg write --offset=0x100 --value 0x14 --device=2 + +OR + + printf '\x14' | sudo dd of=/dev/drm_dp_aux2 bs=1 count=1 conv=notrunc + seek=$((0x100)) + +This single aux write causes the screen to blank, sending short HPD to +DPTX, setting LINK_STATUS_UPDATE = 1 in DPCD 0x204, and triggering LT. + +As stated in [1]: +"Before any TX electrical testing can be performed, the link between a +DPTX and DPRX (in this case, a piece of test equipment), including all +LTTPRs within the path, shall be trained as defined in this Standard." + +In addition, changing Phy pattern/Swing/Pre-emphasis (Step 3) uses the +same link rate and lane count applied on step 2, so no need to redo LT. + +The fix is to not rewrite link config in step 3, and just writes +TRAINING_LANEx_SET and LINK_QUAL_PATTERN_SET + +[1]: DP 2.0 E11 - 3.6.11.1 LTTPR DPTX_PHY Electrical Compliance + +[2]: Configuring UnigrafDPTC Controller - Automation Test Sequence +https://www.keysight.com/us/en/assets/9922-01244/help-files/ +D9040DPPC-DisplayPort-Test-Software-Online-Help-latest.chm + +Cc: Imre Deak +Cc: Jani Nikula +Cc: Or Cochvi +Signed-off-by: Khaled Almahallawy +Signed-off-by: Jani Nikula +Link: https://patchwork.freedesktop.org/patch/msgid/20220916054900.415804-1-khaled.almahallawy@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_dp_helper.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c +index 3c55753bab16..6ba16db77500 100644 +--- a/drivers/gpu/drm/drm_dp_helper.c ++++ b/drivers/gpu/drm/drm_dp_helper.c +@@ -2172,17 +2172,8 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data, u8 dp_rev) + { + int err, i; +- u8 link_config[2]; + u8 test_pattern; + +- link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate); +- link_config[1] = data->num_lanes; +- if (data->enhanced_frame_cap) +- link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; +- err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2); +- if (err < 0) +- return err; +- + test_pattern = data->phy_pattern; + if (dp_rev < 0x12) { + test_pattern = (test_pattern << 2) & +-- +2.35.1 + diff --git a/queue-5.10/drm-dp_mst-fix-drm_dp_dpcd_read-return-value-checks.patch b/queue-5.10/drm-dp_mst-fix-drm_dp_dpcd_read-return-value-checks.patch new file mode 100644 index 00000000000..9bb6f4ac552 --- /dev/null +++ b/queue-5.10/drm-dp_mst-fix-drm_dp_dpcd_read-return-value-checks.patch @@ -0,0 +1,57 @@ +From 30f438adec6f510411339c0af4aa8aa92f3f1545 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 10 Feb 2022 15:40:25 +0000 +Subject: drm/dp_mst: fix drm_dp_dpcd_read return value checks + +From: Simon Ser + +[ Upstream commit 2ac6cdd581f48c8f68747156fde5868486a44985 ] + +drm_dp_dpcd_read returns the number of bytes read. The previous code +would print garbage on DPCD error, and would exit with on error on +success. + +Signed-off-by: Simon Ser +Fixes: cb897542c6d2 ("drm/dp_mst: Fix W=1 warnings") +Cc: Lyude Paul +Cc: Benjamin Gaignard +Reviewed-by: Jani Nikula +Link: https://patchwork.freedesktop.org/patch/473500/ +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c +index ab423b0413ee..4272cd3622f8 100644 +--- a/drivers/gpu/drm/drm_dp_mst_topology.c ++++ b/drivers/gpu/drm/drm_dp_mst_topology.c +@@ -4856,14 +4856,14 @@ void drm_dp_mst_dump_topology(struct seq_file *m, + seq_printf(m, "dpcd: %*ph\n", DP_RECEIVER_CAP_SIZE, buf); + + ret = drm_dp_dpcd_read(mgr->aux, DP_FAUX_CAP, buf, 2); +- if (ret) { ++ if (ret != 2) { + seq_printf(m, "faux/mst read failed\n"); + goto out; + } + seq_printf(m, "faux/mst: %*ph\n", 2, buf); + + ret = drm_dp_dpcd_read(mgr->aux, DP_MSTM_CTRL, buf, 1); +- if (ret) { ++ if (ret != 1) { + seq_printf(m, "mst ctrl read failed\n"); + goto out; + } +@@ -4871,7 +4871,7 @@ void drm_dp_mst_dump_topology(struct seq_file *m, + + /* dump the standard OUI branch header */ + ret = drm_dp_dpcd_read(mgr->aux, DP_BRANCH_OUI, buf, DP_BRANCH_OUI_HEADER_SIZE); +- if (ret) { ++ if (ret != DP_BRANCH_OUI_HEADER_SIZE) { + seq_printf(m, "branch oui read failed\n"); + goto out; + } +-- +2.35.1 + diff --git a/queue-5.10/drm-exynos-fix-return-type-for-mixer_mode_valid-and-.patch b/queue-5.10/drm-exynos-fix-return-type-for-mixer_mode_valid-and-.patch new file mode 100644 index 00000000000..0f1986d1f04 --- /dev/null +++ b/queue-5.10/drm-exynos-fix-return-type-for-mixer_mode_valid-and-.patch @@ -0,0 +1,66 @@ +From bf2b251395831c692a1e11929038779027e8bbd3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 09:31:00 +0900 +Subject: drm/exynos: Fix return type for mixer_mode_valid and hdmi_mode_valid + +From: Nathan Huckleberry + +[ Upstream commit 1261255531088208daeca818e2b486030b5339e5 ] + +The field mode_valid in exynos_drm_crtc_ops is expected to be of type enum +drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode); + +Likewise for mode_valid in drm_connector_helper_funcs. + +The mismatched return type breaks forward edge kCFI since the underlying +function definition does not match the function hook definition. + +The return type of mixer_mode_valid and hdmi_mode_valid should be changed +from int to enum drm_mode_status. + +Reported-by: Dan Carpenter +Link: https://protect2.fireeye.com/v1/url?k=3e644738-5fef521d-3e65cc77- +74fe485cbff6-36ad29bf912d3c9f&q=1&e=5cc06174-77dd-4abd-ab50- +155da5711aa3&u=https%3A%2F%2Fgithub.com%2FClangBuiltLinux%2Flinux%2Fissues%2F +1703 +Cc: llvm@lists.linux.dev +Signed-off-by: Nathan Huckleberry +Signed-off-by: Inki Dae +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/exynos/exynos_hdmi.c | 4 ++-- + drivers/gpu/drm/exynos/exynos_mixer.c | 2 +- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c +index dc01c188c0e0..d864082b2592 100644 +--- a/drivers/gpu/drm/exynos/exynos_hdmi.c ++++ b/drivers/gpu/drm/exynos/exynos_hdmi.c +@@ -913,8 +913,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) + return -EINVAL; + } + +-static int hdmi_mode_valid(struct drm_connector *connector, +- struct drm_display_mode *mode) ++static enum drm_mode_status hdmi_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) + { + struct hdmi_context *hdata = connector_to_hdmi(connector); + int ret; +diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c +index af192e5a16ef..dd038b30e7e9 100644 +--- a/drivers/gpu/drm/exynos/exynos_mixer.c ++++ b/drivers/gpu/drm/exynos/exynos_mixer.c +@@ -1039,7 +1039,7 @@ static void mixer_atomic_disable(struct exynos_drm_crtc *crtc) + clear_bit(MXR_BIT_POWERED, &ctx->flags); + } + +-static int mixer_mode_valid(struct exynos_drm_crtc *crtc, ++static enum drm_mode_status mixer_mode_valid(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode) + { + struct mixer_context *ctx = crtc->ctx; +-- +2.35.1 + diff --git a/queue-5.10/drm-fix-drm_mipi_dbi-build-errors.patch b/queue-5.10/drm-fix-drm_mipi_dbi-build-errors.patch new file mode 100644 index 00000000000..5f4a5d84885 --- /dev/null +++ b/queue-5.10/drm-fix-drm_mipi_dbi-build-errors.patch @@ -0,0 +1,65 @@ +From 6c6cddc1e2f1a9f9f35aeff7913706bb58fb8454 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 22 Aug 2022 17:42:43 -0700 +Subject: drm: fix drm_mipi_dbi build errors +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Randy Dunlap + +[ Upstream commit eb7de496451bd969e203f02f66585131228ba4ae ] + +drm_mipi_dbi needs lots of DRM_KMS_HELPER support, so select +that Kconfig symbol like it is done is most other uses, and +the way that it was before MIPS_DBI was moved from tinydrm +to its core location. + +Fixes these build errors: + +ld: drivers/gpu/drm/drm_mipi_dbi.o: in function `mipi_dbi_buf_copy': +drivers/gpu/drm/drm_mipi_dbi.c:205: undefined reference to `drm_gem_fb_get_obj' +ld: drivers/gpu/drm/drm_mipi_dbi.c:211: undefined reference to `drm_gem_fb_begin_cpu_access' +ld: drivers/gpu/drm/drm_mipi_dbi.c:215: undefined reference to `drm_gem_fb_vmap' +ld: drivers/gpu/drm/drm_mipi_dbi.c:222: undefined reference to `drm_fb_swab' +ld: drivers/gpu/drm/drm_mipi_dbi.c:224: undefined reference to `drm_fb_memcpy' +ld: drivers/gpu/drm/drm_mipi_dbi.c:227: undefined reference to `drm_fb_xrgb8888_to_rgb565' +ld: drivers/gpu/drm/drm_mipi_dbi.c:235: undefined reference to `drm_gem_fb_vunmap' +ld: drivers/gpu/drm/drm_mipi_dbi.c:237: undefined reference to `drm_gem_fb_end_cpu_access' +ld: drivers/gpu/drm/drm_mipi_dbi.o: in function `mipi_dbi_dev_init_with_formats': +ld: drivers/gpu/drm/drm_mipi_dbi.o:/X64/../drivers/gpu/drm/drm_mipi_dbi.c:469: undefined reference to `drm_gem_fb_create_with_dirty' + +Fixes: 174102f4de23 ("drm/tinydrm: Move mipi-dbi") +Signed-off-by: Randy Dunlap +Reported-by: kernel test robot +Cc: Dillon Min +Cc: Linus Walleij +Cc: Sam Ravnborg +Cc: Noralf Trønnes +Cc: Thomas Zimmermann +Cc: Thierry Reding +Cc: dri-devel@lists.freedesktop.org +Cc: David Airlie +Cc: Daniel Vetter +Signed-off-by: Linus Walleij +Link: https://patchwork.freedesktop.org/patch/msgid/20220823004243.11596-1-rdunlap@infradead.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index ca868271f4c4..4e9b3a95fa7c 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -30,6 +30,7 @@ menuconfig DRM + config DRM_MIPI_DBI + tristate + depends on DRM ++ select DRM_KMS_HELPER + + config DRM_MIPI_DSI + bool +-- +2.35.1 + diff --git a/queue-5.10/drm-meson-explicitly-remove-aggregate-driver-at-modu.patch b/queue-5.10/drm-meson-explicitly-remove-aggregate-driver-at-modu.patch new file mode 100644 index 00000000000..b65d49dbd6d --- /dev/null +++ b/queue-5.10/drm-meson-explicitly-remove-aggregate-driver-at-modu.patch @@ -0,0 +1,197 @@ +From 0f67a4be25cbd6e9b928b325bcc315ef387335e3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 02:09:39 +0100 +Subject: drm/meson: explicitly remove aggregate driver at module unload time +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Adrián Larumbe + +[ Upstream commit 8616f2a0589a80e08434212324250eb22f6a66ce ] + +Because component_master_del wasn't being called when unloading the +meson_drm module, the aggregate device would linger forever in the global +aggregate_devices list. That means when unloading and reloading the +meson_dw_hdmi module, component_add would call into +try_to_bring_up_aggregate_device and find the unbound meson_drm aggregate +device. + +This would in turn dereference some of the aggregate_device's struct +entries which point to memory automatically freed by the devres API when +unbinding the aggregate device from meson_drv_unbind, and trigger an +use-after-free bug: + +[ +0.000014] ============================================================= +[ +0.000007] BUG: KASAN: use-after-free in find_components+0x468/0x500 +[ +0.000017] Read of size 8 at addr ffff000006731688 by task modprobe/2536 +[ +0.000018] CPU: 4 PID: 2536 Comm: modprobe Tainted: G C O 5.19.0-rc6-lrmbkasan+ #1 +[ +0.000010] Hardware name: Hardkernel ODROID-N2Plus (DT) +[ +0.000008] Call trace: +[ +0.000005] dump_backtrace+0x1ec/0x280 +[ +0.000011] show_stack+0x24/0x80 +[ +0.000007] dump_stack_lvl+0x98/0xd4 +[ +0.000010] print_address_description.constprop.0+0x80/0x520 +[ +0.000011] print_report+0x128/0x260 +[ +0.000007] kasan_report+0xb8/0xfc +[ +0.000007] __asan_report_load8_noabort+0x3c/0x50 +[ +0.000009] find_components+0x468/0x500 +[ +0.000008] try_to_bring_up_aggregate_device+0x64/0x390 +[ +0.000009] __component_add+0x1dc/0x49c +[ +0.000009] component_add+0x20/0x30 +[ +0.000008] meson_dw_hdmi_probe+0x28/0x34 [meson_dw_hdmi] +[ +0.000013] platform_probe+0xd0/0x220 +[ +0.000008] really_probe+0x3ac/0xa80 +[ +0.000008] __driver_probe_device+0x1f8/0x400 +[ +0.000008] driver_probe_device+0x68/0x1b0 +[ +0.000008] __driver_attach+0x20c/0x480 +[ +0.000009] bus_for_each_dev+0x114/0x1b0 +[ +0.000007] driver_attach+0x48/0x64 +[ +0.000009] bus_add_driver+0x390/0x564 +[ +0.000007] driver_register+0x1a8/0x3e4 +[ +0.000009] __platform_driver_register+0x6c/0x94 +[ +0.000007] meson_dw_hdmi_platform_driver_init+0x30/0x1000 [meson_dw_hdmi] +[ +0.000014] do_one_initcall+0xc4/0x2b0 +[ +0.000008] do_init_module+0x154/0x570 +[ +0.000010] load_module+0x1a78/0x1ea4 +[ +0.000008] __do_sys_init_module+0x184/0x1cc +[ +0.000008] __arm64_sys_init_module+0x78/0xb0 +[ +0.000008] invoke_syscall+0x74/0x260 +[ +0.000008] el0_svc_common.constprop.0+0xcc/0x260 +[ +0.000009] do_el0_svc+0x50/0x70 +[ +0.000008] el0_svc+0x68/0x1a0 +[ +0.000009] el0t_64_sync_handler+0x11c/0x150 +[ +0.000009] el0t_64_sync+0x18c/0x190 + +[ +0.000014] Allocated by task 902: +[ +0.000007] kasan_save_stack+0x2c/0x5c +[ +0.000009] __kasan_kmalloc+0x90/0xd0 +[ +0.000007] __kmalloc_node+0x240/0x580 +[ +0.000010] memcg_alloc_slab_cgroups+0xa4/0x1ac +[ +0.000010] memcg_slab_post_alloc_hook+0xbc/0x4c0 +[ +0.000008] kmem_cache_alloc_node+0x1d0/0x490 +[ +0.000009] __alloc_skb+0x1d4/0x310 +[ +0.000010] alloc_skb_with_frags+0x8c/0x620 +[ +0.000008] sock_alloc_send_pskb+0x5ac/0x6d0 +[ +0.000010] unix_dgram_sendmsg+0x2e0/0x12f0 +[ +0.000010] sock_sendmsg+0xcc/0x110 +[ +0.000007] sock_write_iter+0x1d0/0x304 +[ +0.000008] new_sync_write+0x364/0x460 +[ +0.000007] vfs_write+0x420/0x5ac +[ +0.000008] ksys_write+0x19c/0x1f0 +[ +0.000008] __arm64_sys_write+0x78/0xb0 +[ +0.000007] invoke_syscall+0x74/0x260 +[ +0.000008] el0_svc_common.constprop.0+0x1a8/0x260 +[ +0.000009] do_el0_svc+0x50/0x70 +[ +0.000007] el0_svc+0x68/0x1a0 +[ +0.000008] el0t_64_sync_handler+0x11c/0x150 +[ +0.000008] el0t_64_sync+0x18c/0x190 + +[ +0.000013] Freed by task 2509: +[ +0.000008] kasan_save_stack+0x2c/0x5c +[ +0.000007] kasan_set_track+0x2c/0x40 +[ +0.000008] kasan_set_free_info+0x28/0x50 +[ +0.000008] ____kasan_slab_free+0x128/0x1d4 +[ +0.000008] __kasan_slab_free+0x18/0x24 +[ +0.000007] slab_free_freelist_hook+0x108/0x230 +[ +0.000010] kfree+0x110/0x35c +[ +0.000008] release_nodes+0xf0/0x16c +[ +0.000008] devres_release_all+0xfc/0x180 +[ +0.000008] device_unbind_cleanup+0x24/0x164 +[ +0.000008] device_release_driver_internal+0x3e8/0x5b0 +[ +0.000010] driver_detach+0xac/0x1b0 +[ +0.000008] bus_remove_driver+0x158/0x29c +[ +0.000008] driver_unregister+0x70/0xb0 +[ +0.000009] platform_driver_unregister+0x20/0x2c +[ +0.000007] 0xffff800003722d98 +[ +0.000012] __do_sys_delete_module+0x288/0x400 +[ +0.000009] __arm64_sys_delete_module+0x5c/0x80 +[ +0.000008] invoke_syscall+0x74/0x260 +[ +0.000008] el0_svc_common.constprop.0+0xcc/0x260 +[ +0.000008] do_el0_svc+0x50/0x70 +[ +0.000007] el0_svc+0x68/0x1a0 +[ +0.000008] el0t_64_sync_handler+0x11c/0x150 +[ +0.000009] el0t_64_sync+0x18c/0x190 + +[ +0.000013] Last potentially related work creation: +[ +0.000007] kasan_save_stack+0x2c/0x5c +[ +0.000007] __kasan_record_aux_stack+0xb8/0xf0 +[ +0.000009] kasan_record_aux_stack_noalloc+0x14/0x20 +[ +0.000008] insert_work+0x54/0x290 +[ +0.000009] __queue_work+0x48c/0xd24 +[ +0.000008] queue_work_on+0x90/0x11c +[ +0.000008] call_usermodehelper_exec+0x188/0x404 +[ +0.000010] kobject_uevent_env+0x5a8/0x794 +[ +0.000010] kobject_uevent+0x14/0x20 +[ +0.000008] driver_register+0x230/0x3e4 +[ +0.000009] __platform_driver_register+0x6c/0x94 +[ +0.000007] gxbb_driver_init+0x28/0x34 +[ +0.000010] do_one_initcall+0xc4/0x2b0 +[ +0.000008] do_initcalls+0x20c/0x24c +[ +0.000010] kernel_init_freeable+0x22c/0x278 +[ +0.000009] kernel_init+0x3c/0x170 +[ +0.000008] ret_from_fork+0x10/0x20 + +[ +0.000013] The buggy address belongs to the object at ffff000006731600 + which belongs to the cache kmalloc-256 of size 256 +[ +0.000009] The buggy address is located 136 bytes inside of + 256-byte region [ffff000006731600, ffff000006731700) + +[ +0.000015] The buggy address belongs to the physical page: +[ +0.000008] page:fffffc000019cc00 refcount:1 mapcount:0 mapping:0000000000000000 index:0xffff000006730a00 pfn:0x6730 +[ +0.000011] head:fffffc000019cc00 order:2 compound_mapcount:0 compound_pincount:0 +[ +0.000008] flags: 0xffff00000010200(slab|head|node=0|zone=0|lastcpupid=0xffff) +[ +0.000016] raw: 0ffff00000010200 fffffc00000c3d08 fffffc0000ef2b08 ffff000000002680 +[ +0.000009] raw: ffff000006730a00 0000000000150014 00000001ffffffff 0000000000000000 +[ +0.000006] page dumped because: kasan: bad access detected + +[ +0.000011] Memory state around the buggy address: +[ +0.000007] ffff000006731580: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc +[ +0.000007] ffff000006731600: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb +[ +0.000007] >ffff000006731680: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb +[ +0.000007] ^ +[ +0.000006] ffff000006731700: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc +[ +0.000007] ffff000006731780: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc +[ +0.000006] ================================================================== + +Fix by adding 'remove' driver callback for meson-drm, and explicitly deleting the +aggregate device. + +Signed-off-by: Adrián Larumbe +Reviewed-by: Neil Armstrong +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20220919010940.419893-3-adrian.larumbe@collabora.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/meson/meson_drv.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index 2d022f3fb437..b0bfe85f5f6a 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -528,6 +528,13 @@ static int meson_drv_probe(struct platform_device *pdev) + return 0; + }; + ++static int meson_drv_remove(struct platform_device *pdev) ++{ ++ component_master_del(&pdev->dev, &meson_drv_master_ops); ++ ++ return 0; ++} ++ + static struct meson_drm_match_data meson_drm_gxbb_data = { + .compat = VPU_COMPATIBLE_GXBB, + }; +@@ -565,6 +572,7 @@ static const struct dev_pm_ops meson_drv_pm_ops = { + + static struct platform_driver meson_drm_platform_driver = { + .probe = meson_drv_probe, ++ .remove = meson_drv_remove, + .shutdown = meson_drv_shutdown, + .driver = { + .name = "meson-drm", +-- +2.35.1 + diff --git a/queue-5.10/drm-mipi-dsi-detach-devices-when-removing-the-host.patch b/queue-5.10/drm-mipi-dsi-detach-devices-when-removing-the-host.patch new file mode 100644 index 00000000000..e5c6aa1780b --- /dev/null +++ b/queue-5.10/drm-mipi-dsi-detach-devices-when-removing-the-host.patch @@ -0,0 +1,41 @@ +From 7c971d1fa33467a0329ee31be65fab71ab526e16 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Jul 2022 19:38:31 +0200 +Subject: drm/mipi-dsi: Detach devices when removing the host + +From: Maxime Ripard + +[ Upstream commit 668a8f17b5290d04ef7343636a5588a0692731a1 ] + +Whenever the MIPI-DSI host is unregistered, the code of +mipi_dsi_host_unregister() loops over every device currently found on that +bus and will unregister it. + +However, it doesn't detach it from the bus first, which leads to all kind +of resource leaks if the host wants to perform some clean up whenever a +device is detached. + +Fixes: 068a00233969 ("drm: Add MIPI DSI bus support") +Acked-by: Thomas Zimmermann +Signed-off-by: Maxime Ripard +Link: https://lore.kernel.org/r/20220711173939.1132294-2-maxime@cerno.tech +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_mipi_dsi.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c +index 5dd475e82995..2c43d54766f3 100644 +--- a/drivers/gpu/drm/drm_mipi_dsi.c ++++ b/drivers/gpu/drm/drm_mipi_dsi.c +@@ -300,6 +300,7 @@ static int mipi_dsi_remove_device_fn(struct device *dev, void *priv) + { + struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); + ++ mipi_dsi_detach(dsi); + mipi_dsi_device_unregister(dsi); + + return 0; +-- +2.35.1 + diff --git a/queue-5.10/drm-msm-dp-correct-1.62g-link-rate-at-dp_catalog_ctr.patch b/queue-5.10/drm-msm-dp-correct-1.62g-link-rate-at-dp_catalog_ctr.patch new file mode 100644 index 00000000000..5775bac1929 --- /dev/null +++ b/queue-5.10/drm-msm-dp-correct-1.62g-link-rate-at-dp_catalog_ctr.patch @@ -0,0 +1,50 @@ +From de8fd977b1ceb5b01fec0cab632134d351b8cb7b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 13:15:50 -0700 +Subject: drm/msm/dp: correct 1.62G link rate at dp_catalog_ctrl_config_msa() + +From: Kuogee Hsieh + +[ Upstream commit aa0bff10af1c4b92e6b56e3e1b7f81c660d3ba78 ] + +At current implementation there is an extra 0 at 1.62G link rate which +cause no correct pixel_div selected for 1.62G link rate to calculate +mvid and nvid. This patch delete the extra 0 to have mvid and nvid be +calculated correctly. + +Changes in v2: +-- fix Fixes tag's text + +Changes in v3: +-- fix misspelling of "Reviewed-by" + +Fixes: 937f941ca06f ("drm/msm/dp: Use qmp phy for DP PLL and PHY") +Signed-off-by: Kuogee Hsieh +Reviewed-by: Stephen Boyd +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/499328/ +Link: https://lore.kernel.org/r/1661372150-3764-1-git-send-email-quic_khsieh@quicinc.com +[DB: rewrapped commit message] +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Rob Clark +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c +index 2da6982efdbf..613348b022fe 100644 +--- a/drivers/gpu/drm/msm/dp/dp_catalog.c ++++ b/drivers/gpu/drm/msm/dp/dp_catalog.c +@@ -416,7 +416,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, + + if (rate == link_rate_hbr3) + pixel_div = 6; +- else if (rate == 1620000 || rate == 270000) ++ else if (rate == 162000 || rate == 270000) + pixel_div = 2; + else if (rate == link_rate_hbr2) + pixel_div = 4; +-- +2.35.1 + diff --git a/queue-5.10/drm-msm-dpu-index-dpu_kms-hw_vbif-using-vbif_idx.patch b/queue-5.10/drm-msm-dpu-index-dpu_kms-hw_vbif-using-vbif_idx.patch new file mode 100644 index 00000000000..fd2223686ec --- /dev/null +++ b/queue-5.10/drm-msm-dpu-index-dpu_kms-hw_vbif-using-vbif_idx.patch @@ -0,0 +1,127 @@ +From f404f653edcd47f22bf7ac51c375fb30856ee747 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 15 Jun 2022 15:57:01 +0300 +Subject: drm/msm/dpu: index dpu_kms->hw_vbif using vbif_idx + +From: Dmitry Baryshkov + +[ Upstream commit 7538f80ae0d98bf51eb89eee5344aec219902d42 ] + +Remove loops over hw_vbif. Instead always VBIF's idx as an index in the +array. This fixes an error in dpu_kms_hw_init(), where we fill +dpu_kms->hw_vbif[i], but check for an error pointer at +dpu_kms->hw_vbif[vbif_idx]. + +Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") +Signed-off-by: Dmitry Baryshkov +Reviewed-by: Abhinav Kumar +Patchwork: https://patchwork.freedesktop.org/patch/489569/ +Link: https://lore.kernel.org/r/20220615125703.24647-1-dmitry.baryshkov@linaro.org +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Rob Clark +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++------ + drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 29 +++++++++++------------- + 2 files changed, 18 insertions(+), 23 deletions(-) + +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +index 7503f093f3b6..b7841f7fc10a 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +@@ -675,12 +675,10 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) + _dpu_kms_mmu_destroy(dpu_kms); + + if (dpu_kms->catalog) { +- for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { +- u32 vbif_idx = dpu_kms->catalog->vbif[i].id; +- +- if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx]) { +- dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]); +- dpu_kms->hw_vbif[vbif_idx] = NULL; ++ for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { ++ if (dpu_kms->hw_vbif[i]) { ++ dpu_hw_vbif_destroy(dpu_kms->hw_vbif[i]); ++ dpu_kms->hw_vbif[i] = NULL; + } + } + } +@@ -987,7 +985,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) + for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { + u32 vbif_idx = dpu_kms->catalog->vbif[i].id; + +- dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx, ++ dpu_kms->hw_vbif[vbif_idx] = dpu_hw_vbif_init(vbif_idx, + dpu_kms->vbif[vbif_idx], dpu_kms->catalog); + if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) { + rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]); +diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +index 5e8c3f3e6625..fc86d34aec80 100644 +--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c ++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +@@ -11,6 +11,14 @@ + #include "dpu_hw_vbif.h" + #include "dpu_trace.h" + ++static struct dpu_hw_vbif *dpu_get_vbif(struct dpu_kms *dpu_kms, enum dpu_vbif vbif_idx) ++{ ++ if (vbif_idx < ARRAY_SIZE(dpu_kms->hw_vbif)) ++ return dpu_kms->hw_vbif[vbif_idx]; ++ ++ return NULL; ++} ++ + /** + * _dpu_vbif_wait_for_xin_halt - wait for the xin to halt + * @vbif: Pointer to hardware vbif driver +@@ -148,20 +156,15 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif, + void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, + struct dpu_vbif_set_ot_params *params) + { +- struct dpu_hw_vbif *vbif = NULL; ++ struct dpu_hw_vbif *vbif; + struct dpu_hw_mdp *mdp; + bool forced_on = false; + u32 ot_lim; +- int ret, i; ++ int ret; + + mdp = dpu_kms->hw_mdp; + +- for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { +- if (dpu_kms->hw_vbif[i] && +- dpu_kms->hw_vbif[i]->idx == params->vbif_idx) +- vbif = dpu_kms->hw_vbif[i]; +- } +- ++ vbif = dpu_get_vbif(dpu_kms, params->vbif_idx); + if (!vbif || !mdp) { + DPU_DEBUG("invalid arguments vbif %d mdp %d\n", + vbif != NULL, mdp != NULL); +@@ -204,7 +207,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, + void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, + struct dpu_vbif_set_qos_params *params) + { +- struct dpu_hw_vbif *vbif = NULL; ++ struct dpu_hw_vbif *vbif; + struct dpu_hw_mdp *mdp; + bool forced_on = false; + const struct dpu_vbif_qos_tbl *qos_tbl; +@@ -216,13 +219,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, + } + mdp = dpu_kms->hw_mdp; + +- for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { +- if (dpu_kms->hw_vbif[i] && +- dpu_kms->hw_vbif[i]->idx == params->vbif_idx) { +- vbif = dpu_kms->hw_vbif[i]; +- break; +- } +- } ++ vbif = dpu_get_vbif(dpu_kms, params->vbif_idx); + + if (!vbif || !vbif->cap) { + DPU_ERROR("invalid vbif %d\n", params->vbif_idx); +-- +2.35.1 + diff --git a/queue-5.10/drm-msm-make-.remove-and-.shutdown-hw-shutdown-consi.patch b/queue-5.10/drm-msm-make-.remove-and-.shutdown-hw-shutdown-consi.patch new file mode 100644 index 00000000000..c80e7b8c28a --- /dev/null +++ b/queue-5.10/drm-msm-make-.remove-and-.shutdown-hw-shutdown-consi.patch @@ -0,0 +1,163 @@ +From 1cb7935a0000a3b3b264dd747aac9d8c3c0ae8f6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Aug 2022 15:46:12 +0200 +Subject: drm/msm: Make .remove and .shutdown HW shutdown consistent + +From: Javier Martinez Canillas + +[ Upstream commit 0a58d2ae572adaec8d046f8d35b40c2c32ac7468 ] + +Drivers' .remove and .shutdown callbacks are executed on different code +paths. The former is called when a device is removed from the bus, while +the latter is called at system shutdown time to quiesce the device. + +This means that some overlap exists between the two, because both have to +take care of properly shutting down the hardware. But currently the logic +used in these two callbacks isn't consistent in msm drivers, which could +lead to kernel panic. + +For example, on .remove the component is deleted and its .unbind callback +leads to the hardware being shutdown but only if the DRM device has been +marked as registered. + +That check doesn't exist in the .shutdown logic and this can lead to the +driver calling drm_atomic_helper_shutdown() for a DRM device that hasn't +been properly initialized. + +A situation like this can happen if drivers for expected sub-devices fail +to probe, since the .bind callback will never be executed. If that is the +case, drm_atomic_helper_shutdown() will attempt to take mutexes that are +only initialized if drm_mode_config_init() is called during a device bind. + +This bug was attempted to be fixed in commit 623f279c7781 ("drm/msm: fix +shutdown hook in case GPU components failed to bind"), but unfortunately +it still happens in some cases as the one mentioned above, i.e: + + systemd-shutdown[1]: Powering off. + kvm: exiting hardware virtualization + platform wifi-firmware.0: Removing from iommu group 12 + platform video-firmware.0: Removing from iommu group 10 + ------------[ cut here ]------------ + WARNING: CPU: 6 PID: 1 at drivers/gpu/drm/drm_modeset_lock.c:317 drm_modeset_lock_all_ctx+0x3c4/0x3d0 + ... + Hardware name: Google CoachZ (rev3+) (DT) + pstate: a0400009 (NzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) + pc : drm_modeset_lock_all_ctx+0x3c4/0x3d0 + lr : drm_modeset_lock_all_ctx+0x48/0x3d0 + sp : ffff80000805bb80 + x29: ffff80000805bb80 x28: ffff327c00128000 x27: 0000000000000000 + x26: 0000000000000000 x25: 0000000000000001 x24: ffffc95d820ec030 + x23: ffff327c00bbd090 x22: ffffc95d8215eca0 x21: ffff327c039c5800 + x20: ffff327c039c5988 x19: ffff80000805bbe8 x18: 0000000000000034 + x17: 000000040044ffff x16: ffffc95d80cac920 x15: 0000000000000000 + x14: 0000000000000315 x13: 0000000000000315 x12: 0000000000000000 + x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000 + x8 : ffff80000805bc28 x7 : 0000000000000000 x6 : 0000000000000000 + x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 + x2 : ffff327c00128000 x1 : 0000000000000000 x0 : ffff327c039c59b0 + Call trace: + drm_modeset_lock_all_ctx+0x3c4/0x3d0 + drm_atomic_helper_shutdown+0x70/0x134 + msm_drv_shutdown+0x30/0x40 + platform_shutdown+0x28/0x40 + device_shutdown+0x148/0x350 + kernel_power_off+0x38/0x80 + __do_sys_reboot+0x288/0x2c0 + __arm64_sys_reboot+0x28/0x34 + invoke_syscall+0x48/0x114 + el0_svc_common.constprop.0+0x44/0xec + do_el0_svc+0x2c/0xc0 + el0_svc+0x2c/0x84 + el0t_64_sync_handler+0x11c/0x150 + el0t_64_sync+0x18c/0x190 + ---[ end trace 0000000000000000 ]--- + Unable to handle kernel NULL pointer dereference at virtual address 0000000000000018 + Mem abort info: + ESR = 0x0000000096000004 + EC = 0x25: DABT (current EL), IL = 32 bits + SET = 0, FnV = 0 + EA = 0, S1PTW = 0 + FSC = 0x04: level 0 translation fault + Data abort info: + ISV = 0, ISS = 0x00000004 + CM = 0, WnR = 0 + user pgtable: 4k pages, 48-bit VAs, pgdp=000000010eab1000 + [0000000000000018] pgd=0000000000000000, p4d=0000000000000000 + Internal error: Oops: 96000004 [#1] PREEMPT SMP + ... + Hardware name: Google CoachZ (rev3+) (DT) + pstate: a0400009 (NzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) + pc : ww_mutex_lock+0x28/0x32c + lr : drm_modeset_lock_all_ctx+0x1b0/0x3d0 + sp : ffff80000805bb50 + x29: ffff80000805bb50 x28: ffff327c00128000 x27: 0000000000000000 + x26: 0000000000000000 x25: 0000000000000001 x24: 0000000000000018 + x23: ffff80000805bc10 x22: ffff327c039c5ad8 x21: ffff327c039c5800 + x20: ffff80000805bbe8 x19: 0000000000000018 x18: 0000000000000034 + x17: 000000040044ffff x16: ffffc95d80cac920 x15: 0000000000000000 + x14: 0000000000000315 x13: 0000000000000315 x12: 0000000000000000 + x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000 + x8 : ffff80000805bc28 x7 : 0000000000000000 x6 : 0000000000000000 + x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 + x2 : ffff327c00128000 x1 : 0000000000000000 x0 : 0000000000000018 + Call trace: + ww_mutex_lock+0x28/0x32c + drm_modeset_lock_all_ctx+0x1b0/0x3d0 + drm_atomic_helper_shutdown+0x70/0x134 + msm_drv_shutdown+0x30/0x40 + platform_shutdown+0x28/0x40 + device_shutdown+0x148/0x350 + kernel_power_off+0x38/0x80 + __do_sys_reboot+0x288/0x2c0 + __arm64_sys_reboot+0x28/0x34 + invoke_syscall+0x48/0x114 + el0_svc_common.constprop.0+0x44/0xec + do_el0_svc+0x2c/0xc0 + el0_svc+0x2c/0x84 + el0t_64_sync_handler+0x11c/0x150 + el0t_64_sync+0x18c/0x190 + Code: aa0103f4 d503201f d2800001 aa0103e3 (c8e37c02) + ---[ end trace 0000000000000000 ]--- + Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b + Kernel Offset: 0x495d77c00000 from 0xffff800008000000 + PHYS_OFFSET: 0xffffcd8500000000 + CPU features: 0x800,00c2a015,19801c82 + Memory Limit: none + ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]--- + +Fixes: 9d5cbf5fe46e ("drm/msm: add shutdown support for display platform_driver") +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Abhinav Kumar +Link: https://patchwork.freedesktop.org/patch/msgid/20220816134612.916527-1-javierm@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/msm/msm_drv.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c +index 087efcb1f34c..13d597ed929c 100644 +--- a/drivers/gpu/drm/msm/msm_drv.c ++++ b/drivers/gpu/drm/msm/msm_drv.c +@@ -1334,10 +1334,15 @@ static void msm_pdev_shutdown(struct platform_device *pdev) + struct drm_device *drm = platform_get_drvdata(pdev); + struct msm_drm_private *priv = drm ? drm->dev_private : NULL; + +- if (!priv || !priv->kms) +- return; +- +- drm_atomic_helper_shutdown(drm); ++ /* ++ * Shutdown the hw if we're far enough along where things might be on. ++ * If we run this too early, we'll end up panicking in any variety of ++ * places. Since we don't register the drm device until late in ++ * msm_drm_init, drm_dev->registered is used as an indicator that the ++ * shutdown will be successful. ++ */ ++ if (drm && drm->registered) ++ drm_atomic_helper_shutdown(drm); + } + + static const struct of_device_id dt_match[] = { +-- +2.35.1 + diff --git a/queue-5.10/drm-nouveau-nouveau_bo-fix-potential-memory-leak-in-.patch b/queue-5.10/drm-nouveau-nouveau_bo-fix-potential-memory-leak-in-.patch new file mode 100644 index 00000000000..ff5d31a8d64 --- /dev/null +++ b/queue-5.10/drm-nouveau-nouveau_bo-fix-potential-memory-leak-in-.patch @@ -0,0 +1,45 @@ +From ec0ec9f051fbd64e66f168653f2dc2b5c143911b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Jul 2022 17:43:06 +0800 +Subject: drm/nouveau/nouveau_bo: fix potential memory leak in + nouveau_bo_alloc() + +From: Jianglei Nie + +[ Upstream commit 6dc548745d5b5102e3c53dc5097296ac270b6c69 ] + +nouveau_bo_alloc() allocates a memory chunk for "nvbo" with kzalloc(). +When some error occurs, "nvbo" should be released. But when +WARN_ON(pi < 0)) equals true, the function return ERR_PTR without +releasing the "nvbo", which will lead to a memory leak. + +We should release the "nvbo" with kfree() if WARN_ON(pi < 0)) equals true. + +Signed-off-by: Jianglei Nie +Signed-off-by: Lyude Paul +Reviewed-by: Lyude Paul +Link: https://patchwork.freedesktop.org/patch/msgid/20220705094306.2244103-1-niejianglei2021@163.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/nouveau/nouveau_bo.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c +index b4946b595d86..b57dcad8865f 100644 +--- a/drivers/gpu/drm/nouveau/nouveau_bo.c ++++ b/drivers/gpu/drm/nouveau/nouveau_bo.c +@@ -279,8 +279,10 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, + break; + } + +- if (WARN_ON(pi < 0)) ++ if (WARN_ON(pi < 0)) { ++ kfree(nvbo); + return ERR_PTR(-EINVAL); ++ } + + /* Disable compression if suitable settings couldn't be found. */ + if (nvbo->comp && !vmm->page[pi].comp) { +-- +2.35.1 + diff --git a/queue-5.10/drm-omap-dss-fix-refcount-leak-bugs.patch b/queue-5.10/drm-omap-dss-fix-refcount-leak-bugs.patch new file mode 100644 index 00000000000..09630793b13 --- /dev/null +++ b/queue-5.10/drm-omap-dss-fix-refcount-leak-bugs.patch @@ -0,0 +1,51 @@ +From 619f426c71970de248bbd070a19457278aedccbd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Jul 2022 22:43:48 +0800 +Subject: drm/omap: dss: Fix refcount leak bugs + +From: Liang He + +[ Upstream commit 8b42057e62120813ebe9274f508fa785b7cab33a ] + +In dss_init_ports() and __dss_uninit_ports(), we should call +of_node_put() for the reference returned by of_graph_get_port_by_id() +in fail path or when it is not used anymore. + +Fixes: 09bffa6e5192 ("drm: omap: use common OF graph helpers") +Signed-off-by: Liang He +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20220722144348.1306569-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/omapdrm/dss/dss.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c +index 6ccbc29c4ce4..d5b3123ed081 100644 +--- a/drivers/gpu/drm/omapdrm/dss/dss.c ++++ b/drivers/gpu/drm/omapdrm/dss/dss.c +@@ -1173,6 +1173,7 @@ static void __dss_uninit_ports(struct dss_device *dss, unsigned int num_ports) + default: + break; + } ++ of_node_put(port); + } + } + +@@ -1205,11 +1206,13 @@ static int dss_init_ports(struct dss_device *dss) + default: + break; + } ++ of_node_put(port); + } + + return 0; + + error: ++ of_node_put(port); + __dss_uninit_ports(dss, i); + return r; + } +-- +2.35.1 + diff --git a/queue-5.10/drm-panel-orientation-quirks-add-quirk-for-anbernic-.patch b/queue-5.10/drm-panel-orientation-quirks-add-quirk-for-anbernic-.patch new file mode 100644 index 00000000000..5b8ff5a472b --- /dev/null +++ b/queue-5.10/drm-panel-orientation-quirks-add-quirk-for-anbernic-.patch @@ -0,0 +1,41 @@ +From 2f7c464bd12a71ee39b6ca77deeeddf38b284618 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Aug 2022 20:24:03 +0200 +Subject: drm: panel-orientation-quirks: Add quirk for Anbernic Win600 + +From: Maya Matuszczyk + +[ Upstream commit 770e19076065e079a32f33eb11be2057c87f1cde ] + +This device is another x86 gaming handheld, and as (hopefully) there is +only one set of DMI IDs it's using DMI_EXACT_MATCH + +Signed-off-by: Maya Matuszczyk +Reviewed-by: Hans de Goede +Signed-off-by: Hans de Goede +Link: https://patchwork.freedesktop.org/patch/msgid/20220803182402.1217293-1-maccraft123mc@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c +index f5ab891731d0..083273736c83 100644 +--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c ++++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c +@@ -128,6 +128,12 @@ static const struct dmi_system_id orientation_data[] = { + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "One S1003"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, ++ }, { /* Anbernic Win600 */ ++ .matches = { ++ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Anbernic"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Win600"), ++ }, ++ .driver_data = (void *)&lcd720x1280_rightside_up, + }, { /* Asus T100HA */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), +-- +2.35.1 + diff --git a/queue-5.10/drm-pl111-add-of_node_put-when-breaking-out-of-for_e.patch b/queue-5.10/drm-pl111-add-of_node_put-when-breaking-out-of-for_e.patch new file mode 100644 index 00000000000..f8834196a49 --- /dev/null +++ b/queue-5.10/drm-pl111-add-of_node_put-when-breaking-out-of-for_e.patch @@ -0,0 +1,41 @@ +From f34397416c55e9fe8dfd9bc13a8b68b9c29801f7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 11 Jul 2022 21:15:50 +0800 +Subject: drm:pl111: Add of_node_put() when breaking out of + for_each_available_child_of_node() + +From: Liang He + +[ Upstream commit e0686dc6f2252e009c455fe99e2ce9d62a60eb47 ] + +The reference 'child' in the iteration of for_each_available_child_of_node() +is only escaped out into a local variable which is only used to check +its value. So we still need to the of_node_put() when breaking of the +for_each_available_child_of_node() which will automatically increase +and decrease the refcount. + +Fixes: ca454bd42dc2 ("drm/pl111: Support the Versatile Express") +Signed-off-by: Liang He +Reviewed-by: Rob Herring +Signed-off-by: Daniel Vetter +Link: https://patchwork.freedesktop.org/patch/msgid/20220711131550.361350-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/pl111/pl111_versatile.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c +index bdd883f4f0da..963a5d5e6987 100644 +--- a/drivers/gpu/drm/pl111/pl111_versatile.c ++++ b/drivers/gpu/drm/pl111/pl111_versatile.c +@@ -402,6 +402,7 @@ static int pl111_vexpress_clcd_init(struct device *dev, struct device_node *np, + if (of_device_is_compatible(child, "arm,pl111")) { + has_coretile_clcd = true; + ct_clcd = child; ++ of_node_put(child); + break; + } + if (of_device_is_compatible(child, "arm,hdlcd")) { +-- +2.35.1 + diff --git a/queue-5.10/drm-prevent-drm_copy_field-to-attempt-copying-a-null.patch b/queue-5.10/drm-prevent-drm_copy_field-to-attempt-copying-a-null.patch new file mode 100644 index 00000000000..1fead843797 --- /dev/null +++ b/queue-5.10/drm-prevent-drm_copy_field-to-attempt-copying-a-null.patch @@ -0,0 +1,87 @@ +From a3c625401ede7edf14b9e363c0a6a451ea0692c2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Jul 2022 12:02:14 +0200 +Subject: drm: Prevent drm_copy_field() to attempt copying a NULL pointer + +From: Javier Martinez Canillas + +[ Upstream commit f6ee30407e883042482ad4ad30da5eaba47872ee ] + +There are some struct drm_driver fields that are required by drivers since +drm_copy_field() attempts to copy them to user-space via DRM_IOCTL_VERSION. + +But it can be possible that a driver has a bug and did not set some of the +fields, which leads to drm_copy_field() attempting to copy a NULL pointer: + +[ +10.395966] Unable to handle kernel access to user memory outside uaccess routines at virtual address 0000000000000000 +[ +0.010955] Mem abort info: +[ +0.002835] ESR = 0x0000000096000004 +[ +0.003872] EC = 0x25: DABT (current EL), IL = 32 bits +[ +0.005395] SET = 0, FnV = 0 +[ +0.003113] EA = 0, S1PTW = 0 +[ +0.003182] FSC = 0x04: level 0 translation fault +[ +0.004964] Data abort info: +[ +0.002919] ISV = 0, ISS = 0x00000004 +[ +0.003886] CM = 0, WnR = 0 +[ +0.003040] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000115dad000 +[ +0.006536] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000 +[ +0.006925] Internal error: Oops: 96000004 [#1] SMP +... +[ +0.011113] pstate: 80400005 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) +[ +0.007061] pc : __pi_strlen+0x14/0x150 +[ +0.003895] lr : drm_copy_field+0x30/0x1a4 +[ +0.004156] sp : ffff8000094b3a50 +[ +0.003355] x29: ffff8000094b3a50 x28: ffff8000094b3b70 x27: 0000000000000040 +[ +0.007242] x26: ffff443743c2ba00 x25: 0000000000000000 x24: 0000000000000040 +[ +0.007243] x23: ffff443743c2ba00 x22: ffff8000094b3b70 x21: 0000000000000000 +[ +0.007241] x20: 0000000000000000 x19: ffff8000094b3b90 x18: 0000000000000000 +[ +0.007241] x17: 0000000000000000 x16: 0000000000000000 x15: 0000aaab14b9af40 +[ +0.007241] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 +[ +0.007239] x11: 0000000000000000 x10: 0000000000000000 x9 : ffffa524ad67d4d8 +[ +0.007242] x8 : 0101010101010101 x7 : 7f7f7f7f7f7f7f7f x6 : 6c6e6263606e7141 +[ +0.007239] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 +[ +0.007241] x2 : 0000000000000000 x1 : ffff8000094b3b90 x0 : 0000000000000000 +[ +0.007240] Call trace: +[ +0.002475] __pi_strlen+0x14/0x150 +[ +0.003537] drm_version+0x84/0xac +[ +0.003448] drm_ioctl_kernel+0xa8/0x16c +[ +0.003975] drm_ioctl+0x270/0x580 +[ +0.003448] __arm64_sys_ioctl+0xb8/0xfc +[ +0.003978] invoke_syscall+0x78/0x100 +[ +0.003799] el0_svc_common.constprop.0+0x4c/0xf4 +[ +0.004767] do_el0_svc+0x38/0x4c +[ +0.003357] el0_svc+0x34/0x100 +[ +0.003185] el0t_64_sync_handler+0x11c/0x150 +[ +0.004418] el0t_64_sync+0x190/0x194 +[ +0.003716] Code: 92402c04 b200c3e8 f13fc09f 5400088c (a9400c02) +[ +0.006180] ---[ end trace 0000000000000000 ]--- + +Reported-by: Peter Robinson +Signed-off-by: Javier Martinez Canillas +Acked-by: Thomas Zimmermann +Link: https://patchwork.freedesktop.org/patch/msgid/20220705100215.572498-3-javierm@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_ioctl.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c +index a15d55d06510..c160a45a4274 100644 +--- a/drivers/gpu/drm/drm_ioctl.c ++++ b/drivers/gpu/drm/drm_ioctl.c +@@ -475,6 +475,12 @@ static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value) + { + size_t len; + ++ /* don't attempt to copy a NULL pointer */ ++ if (WARN_ONCE(!value, "BUG: the value to copy was not set!")) { ++ *buf_len = 0; ++ return 0; ++ } ++ + /* don't overflow userbuf */ + len = strlen(value); + if (len > *buf_len) +-- +2.35.1 + diff --git a/queue-5.10/drm-use-size_t-type-for-len-variable-in-drm_copy_fie.patch b/queue-5.10/drm-use-size_t-type-for-len-variable-in-drm_copy_fie.patch new file mode 100644 index 00000000000..d93c2442f36 --- /dev/null +++ b/queue-5.10/drm-use-size_t-type-for-len-variable-in-drm_copy_fie.patch @@ -0,0 +1,48 @@ +From ee0cf1a21a2712e0c72e0ed811682492764202ee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Jul 2022 12:02:13 +0200 +Subject: drm: Use size_t type for len variable in drm_copy_field() + +From: Javier Martinez Canillas + +[ Upstream commit 94dc3471d1b2b58b3728558d0e3f264e9ce6ff59 ] + +The strlen() function returns a size_t which is an unsigned int on 32-bit +arches and an unsigned long on 64-bit arches. But in the drm_copy_field() +function, the strlen() return value is assigned to an 'int len' variable. + +Later, the len variable is passed as copy_from_user() third argument that +is an unsigned long parameter as well. + +In theory, this can lead to an integer overflow via type conversion. Since +the assignment happens to a signed int lvalue instead of a size_t lvalue. + +In practice though, that's unlikely since the values copied are set by DRM +drivers and not controlled by userspace. But using a size_t for len is the +correct thing to do anyways. + +Signed-off-by: Javier Martinez Canillas +Tested-by: Peter Robinson +Reviewed-by: Thomas Zimmermann +Link: https://patchwork.freedesktop.org/patch/msgid/20220705100215.572498-2-javierm@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/drm_ioctl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c +index 4606cc938b36..a15d55d06510 100644 +--- a/drivers/gpu/drm/drm_ioctl.c ++++ b/drivers/gpu/drm/drm_ioctl.c +@@ -473,7 +473,7 @@ EXPORT_SYMBOL(drm_invalid_op); + */ + static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value) + { +- int len; ++ size_t len; + + /* don't overflow userbuf */ + len = strlen(value); +-- +2.35.1 + diff --git a/queue-5.10/drm-vc4-vec-fix-timings-for-vec-modes.patch b/queue-5.10/drm-vc4-vec-fix-timings-for-vec-modes.patch new file mode 100644 index 00000000000..58e709269de --- /dev/null +++ b/queue-5.10/drm-vc4-vec-fix-timings-for-vec-modes.patch @@ -0,0 +1,54 @@ +From 989ab6400fa8decdabd881c2f8a3fbdf5de914e3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 29 Aug 2022 15:11:42 +0200 +Subject: drm/vc4: vec: Fix timings for VEC modes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Mateusz Kwiatkowski + +[ Upstream commit 30d7565be96b3946c18a1ce3fd538f7946839092 ] + +This commit fixes vertical timings of the VEC (composite output) modes +to accurately represent the 525-line ("NTSC") and 625-line ("PAL") ITU-R +standards. + +Previous timings were actually defined as 502 and 601 lines, resulting +in non-standard 62.69 Hz and 52 Hz signals being generated, +respectively. + +Signed-off-by: Mateusz Kwiatkowski +Acked-by: Noralf Trønnes +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20220728-rpi-analog-tv-properties-v2-28-459522d653a7@cerno.tech +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/vc4/vc4_vec.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c +index bd5b8eb58b18..c6bd168a5898 100644 +--- a/drivers/gpu/drm/vc4/vc4_vec.c ++++ b/drivers/gpu/drm/vc4/vc4_vec.c +@@ -257,7 +257,7 @@ static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec) + static const struct drm_display_mode ntsc_mode = { + DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0, +- 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0, ++ 480, 480 + 7, 480 + 7 + 6, 525, 0, + DRM_MODE_FLAG_INTERLACE) + }; + +@@ -279,7 +279,7 @@ static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec) + static const struct drm_display_mode pal_mode = { + DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0, +- 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0, ++ 576, 576 + 4, 576 + 4 + 6, 625, 0, + DRM_MODE_FLAG_INTERLACE) + }; + +-- +2.35.1 + diff --git a/queue-5.10/dyndbg-drop-exported-dynamic_debug_exec_queries.patch b/queue-5.10/dyndbg-drop-exported-dynamic_debug_exec_queries.patch new file mode 100644 index 00000000000..92671189a81 --- /dev/null +++ b/queue-5.10/dyndbg-drop-exported-dynamic_debug_exec_queries.patch @@ -0,0 +1,99 @@ +From 77a3c8a826b75bb9f6b8b09ba67341a233fafebf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 15:40:46 -0600 +Subject: dyndbg: drop EXPORTed dynamic_debug_exec_queries + +From: Jim Cromie + +[ Upstream commit e26ef3af964acfea311403126acee8c56c89e26b ] + +This exported fn is unused, and will not be needed. Lets dump it. + +The export was added to let drm control pr_debugs, as part of using +them to avoid drm_debug_enabled overheads. But its better to just +implement the drm.debug bitmap interface, then its available for +everyone. + +Fixes: a2d375eda771 ("dyndbg: refine export, rename to dynamic_debug_exec_queries()") +Fixes: 4c0d77828d4f ("dyndbg: export ddebug_exec_queries") +Acked-by: Jason Baron +Acked-by: Daniel Vetter +Signed-off-by: Jim Cromie +Link: https://lore.kernel.org/r/20220904214134.408619-10-jim.cromie@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + include/linux/dynamic_debug.h | 9 --------- + lib/dynamic_debug.c | 29 ----------------------------- + 2 files changed, 38 deletions(-) + +diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h +index b0b23679b2c2..c0c6ea9ea7e3 100644 +--- a/include/linux/dynamic_debug.h ++++ b/include/linux/dynamic_debug.h +@@ -50,9 +50,6 @@ struct _ddebug { + + #if defined(CONFIG_DYNAMIC_DEBUG_CORE) + +-/* exported for module authors to exercise >control */ +-int dynamic_debug_exec_queries(const char *query, const char *modname); +- + int ddebug_add_module(struct _ddebug *tab, unsigned int n, + const char *modname); + extern int ddebug_remove_module(const char *mod_name); +@@ -216,12 +213,6 @@ static inline int ddebug_dyndbg_module_param_cb(char *param, char *val, + rowsize, groupsize, buf, len, ascii); \ + } while (0) + +-static inline int dynamic_debug_exec_queries(const char *query, const char *modname) +-{ +- pr_warn("kernel not built with CONFIG_DYNAMIC_DEBUG_CORE\n"); +- return 0; +-} +- + #endif /* !CONFIG_DYNAMIC_DEBUG_CORE */ + + #endif +diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c +index 02a1a6496375..10a50c03074e 100644 +--- a/lib/dynamic_debug.c ++++ b/lib/dynamic_debug.c +@@ -552,35 +552,6 @@ static int ddebug_exec_queries(char *query, const char *modname) + return nfound; + } + +-/** +- * dynamic_debug_exec_queries - select and change dynamic-debug prints +- * @query: query-string described in admin-guide/dynamic-debug-howto +- * @modname: string containing module name, usually &module.mod_name +- * +- * This uses the >/proc/dynamic_debug/control reader, allowing module +- * authors to modify their dynamic-debug callsites. The modname is +- * canonically struct module.mod_name, but can also be null or a +- * module-wildcard, for example: "drm*". +- */ +-int dynamic_debug_exec_queries(const char *query, const char *modname) +-{ +- int rc; +- char *qry; /* writable copy of query */ +- +- if (!query) { +- pr_err("non-null query/command string expected\n"); +- return -EINVAL; +- } +- qry = kstrndup(query, PAGE_SIZE, GFP_KERNEL); +- if (!qry) +- return -ENOMEM; +- +- rc = ddebug_exec_queries(qry, modname); +- kfree(qry); +- return rc; +-} +-EXPORT_SYMBOL_GPL(dynamic_debug_exec_queries); +- + #define PREFIX_SIZE 64 + + static int remaining(int wrote) +-- +2.35.1 + diff --git a/queue-5.10/dyndbg-fix-module.dyndbg-handling.patch b/queue-5.10/dyndbg-fix-module.dyndbg-handling.patch new file mode 100644 index 00000000000..547095ea2c2 --- /dev/null +++ b/queue-5.10/dyndbg-fix-module.dyndbg-handling.patch @@ -0,0 +1,52 @@ +From b49d5b6eee7901b351753782bbb21837ef332223 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 15:40:39 -0600 +Subject: dyndbg: fix module.dyndbg handling + +From: Jim Cromie + +[ Upstream commit 85d6b66d31c35158364058ee98fb69ab5bb6a6b1 ] + +For CONFIG_DYNAMIC_DEBUG=N, the ddebug_dyndbg_module_param_cb() +stub-fn is too permissive: + +bash-5.1# modprobe drm JUNKdyndbg +bash-5.1# modprobe drm dyndbgJUNK +[ 42.933220] dyndbg param is supported only in CONFIG_DYNAMIC_DEBUG builds +[ 42.937484] ACPI: bus type drm_connector registered + +This caused no ill effects, because unknown parameters are either +ignored by default with an "unknown parameter" warning, or ignored +because dyndbg allows its no-effect use on non-dyndbg builds. + +But since the code has an explicit feedback message, it should be +issued accurately. Fix with strcmp for exact param-name match. + +Fixes: b48420c1d301 dynamic_debug: make dynamic-debug work for module initialization +Reported-by: Rasmus Villemoes +Acked-by: Jason Baron +Acked-by: Daniel Vetter +Signed-off-by: Jim Cromie +Link: https://lore.kernel.org/r/20220904214134.408619-3-jim.cromie@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + include/linux/dynamic_debug.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h +index a57ee75342cf..b0b23679b2c2 100644 +--- a/include/linux/dynamic_debug.h ++++ b/include/linux/dynamic_debug.h +@@ -196,7 +196,7 @@ static inline int ddebug_remove_module(const char *mod) + static inline int ddebug_dyndbg_module_param_cb(char *param, char *val, + const char *modname) + { +- if (strstr(param, "dyndbg")) { ++ if (!strcmp(param, "dyndbg")) { + /* avoid pr_warn(), which wants pr_fmt() fully defined */ + printk(KERN_WARNING "dyndbg param is supported only in " + "CONFIG_DYNAMIC_DEBUG builds\n"); +-- +2.35.1 + diff --git a/queue-5.10/dyndbg-fix-static_branch-manipulation.patch b/queue-5.10/dyndbg-fix-static_branch-manipulation.patch new file mode 100644 index 00000000000..1ce47fb32f6 --- /dev/null +++ b/queue-5.10/dyndbg-fix-static_branch-manipulation.patch @@ -0,0 +1,74 @@ +From 394021814555f57298a5c5dce56f309dce5a09cc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 15:40:38 -0600 +Subject: dyndbg: fix static_branch manipulation + +From: Jim Cromie + +[ Upstream commit ee879be38bc87f8cedc79ae2742958db6533ca59 ] + +In https://lore.kernel.org/lkml/20211209150910.GA23668@axis.com/ + +Vincent's patch commented on, and worked around, a bug toggling +static_branch's, when a 2nd PRINTK-ish flag was added. The bug +results in a premature static_branch_disable when the 1st of 2 flags +was disabled. + +The cited commit computed newflags, but then in the JUMP_LABEL block, +failed to use that result, instead using just one of the terms in it. +Using newflags instead made the code work properly. + +This is Vincents test-case, reduced. It needs the 2nd flag to +demonstrate the bug, but it's explanatory here. + +pt_test() { + echo 5 > /sys/module/dynamic_debug/verbose + + site="module tcp" # just one callsite + echo " $site =_ " > /proc/dynamic_debug/control # clear it + + # A B ~A ~B + for flg in +T +p "-T #broke here" -p; do + echo " $site $flg " > /proc/dynamic_debug/control + done; + + # A B ~B ~A + for flg in +T +p "-p #broke here" -T; do + echo " $site $flg " > /proc/dynamic_debug/control + done +} +pt_test + +Fixes: 84da83a6ffc0 dyndbg: combine flags & mask into a struct, simplify with it +CC: vincent.whitchurch@axis.com +Acked-by: Jason Baron +Acked-by: Daniel Vetter +Signed-off-by: Jim Cromie +Link: https://lore.kernel.org/r/20220904214134.408619-2-jim.cromie@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + lib/dynamic_debug.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c +index 921d0a654243..e67655d7b7cb 100644 +--- a/lib/dynamic_debug.c ++++ b/lib/dynamic_debug.c +@@ -207,10 +207,11 @@ static int ddebug_change(const struct ddebug_query *query, + continue; + #ifdef CONFIG_JUMP_LABEL + if (dp->flags & _DPRINTK_FLAGS_PRINT) { +- if (!(modifiers->flags & _DPRINTK_FLAGS_PRINT)) ++ if (!(newflags & _DPRINTK_FLAGS_PRINT)) + static_branch_disable(&dp->key.dd_key_true); +- } else if (modifiers->flags & _DPRINTK_FLAGS_PRINT) ++ } else if (newflags & _DPRINTK_FLAGS_PRINT) { + static_branch_enable(&dp->key.dd_key_true); ++ } + #endif + dp->flags = newflags; + v2pr_info("changed %s:%d [%s]%s =%s\n", +-- +2.35.1 + diff --git a/queue-5.10/dyndbg-let-query-modname-override-actual-module-name.patch b/queue-5.10/dyndbg-let-query-modname-override-actual-module-name.patch new file mode 100644 index 00000000000..e1665f6ecb3 --- /dev/null +++ b/queue-5.10/dyndbg-let-query-modname-override-actual-module-name.patch @@ -0,0 +1,80 @@ +From bcec85c0fb10d518587c316cab1b4e9951f8e760 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 15:40:44 -0600 +Subject: dyndbg: let query-modname override actual module name + +From: Jim Cromie + +[ Upstream commit e75ef56f74965f426dd819a41336b640ffdd8fbc ] + +dyndbg's control-parser: ddebug_parse_query(), requires that search +terms: module, func, file, lineno, are used only once in a query; a +thing cannot be named both foo and bar. + +The cited commit added an overriding module modname, taken from the +module loader, which is authoritative. So it set query.module 1st, +which disallowed its use in the query-string. + +But now, its useful to allow a module-load to enable classes across a +whole (or part of) a subsystem at once. + + # enable (dynamic-debug in) drm only + modprobe drm dyndbg="class DRM_UT_CORE +p" + + # get drm_helper too + modprobe drm dyndbg="class DRM_UT_CORE module drm* +p" + + # get everything that knows DRM_UT_CORE + modprobe drm dyndbg="class DRM_UT_CORE module * +p" + + # also for boot-args: + drm.dyndbg="class DRM_UT_CORE module * +p" + +So convert the override into a default, by filling it only when/after +the query-string omitted the module. + +NB: the query class FOO handling is forthcoming. + +Fixes: 8e59b5cfb9a6 dynamic_debug: add modname arg to exec_query callchain +Acked-by: Jason Baron +Acked-by: Daniel Vetter +Signed-off-by: Jim Cromie +Link: https://lore.kernel.org/r/20220904214134.408619-8-jim.cromie@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + lib/dynamic_debug.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c +index e67655d7b7cb..02a1a6496375 100644 +--- a/lib/dynamic_debug.c ++++ b/lib/dynamic_debug.c +@@ -380,10 +380,6 @@ static int ddebug_parse_query(char *words[], int nwords, + return -EINVAL; + } + +- if (modname) +- /* support $modname.dyndbg= */ +- query->module = modname; +- + for (i = 0; i < nwords; i += 2) { + char *keyword = words[i]; + char *arg = words[i+1]; +@@ -424,6 +420,13 @@ static int ddebug_parse_query(char *words[], int nwords, + if (rc) + return rc; + } ++ if (!query->module && modname) ++ /* ++ * support $modname.dyndbg=, when ++ * not given in the query itself ++ */ ++ query->module = modname; ++ + vpr_info_dq(query, "parsed"); + return 0; + } +-- +2.35.1 + diff --git a/queue-5.10/f2fs-fix-race-condition-on-setting-fi_no_extent-flag.patch b/queue-5.10/f2fs-fix-race-condition-on-setting-fi_no_extent-flag.patch new file mode 100644 index 00000000000..f0d25534a52 --- /dev/null +++ b/queue-5.10/f2fs-fix-race-condition-on-setting-fi_no_extent-flag.patch @@ -0,0 +1,55 @@ +From 7f6799823f17990f088b74c7c5c4c89f5c5ce373 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Sep 2022 12:59:17 +0800 +Subject: f2fs: fix race condition on setting FI_NO_EXTENT flag + +From: Zhang Qilong + +[ Upstream commit 07725adc55c0a414c10acb5c8c86cea34b95ddef ] + +The following scenarios exist. +process A: process B: +->f2fs_drop_extent_tree ->f2fs_update_extent_cache_range + ->f2fs_update_extent_tree_range + ->write_lock + ->set_inode_flag + ->is_inode_flag_set + ->__free_extent_tree // Shouldn't + // have been + // cleaned up + // here + ->write_lock + +In this case, the "FI_NO_EXTENT" flag is set between +f2fs_update_extent_tree_range and is_inode_flag_set +by other process. it leads to clearing the whole exten +tree which should not have happened. And we fix it by +move the setting it to the range of write_lock. + +Fixes:5f281fab9b9a3 ("f2fs: disable extent_cache for fcollapse/finsert inodes") +Signed-off-by: Zhang Qilong +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/extent_cache.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c +index 3ebf976a682d..bd16c78b5bf2 100644 +--- a/fs/f2fs/extent_cache.c ++++ b/fs/f2fs/extent_cache.c +@@ -762,9 +762,8 @@ void f2fs_drop_extent_tree(struct inode *inode) + if (!f2fs_may_extent_tree(inode)) + return; + +- set_inode_flag(inode, FI_NO_EXTENT); +- + write_lock(&et->lock); ++ set_inode_flag(inode, FI_NO_EXTENT); + __free_extent_tree(sbi, et); + if (et->largest.len) { + et->largest.len = 0; +-- +2.35.1 + diff --git a/queue-5.10/f2fs-fix-to-account-fs_cp_data_io-correctly.patch b/queue-5.10/f2fs-fix-to-account-fs_cp_data_io-correctly.patch new file mode 100644 index 00000000000..4714df35633 --- /dev/null +++ b/queue-5.10/f2fs-fix-to-account-fs_cp_data_io-correctly.patch @@ -0,0 +1,138 @@ +From 646bfdfccae71e6059b361df3e7326ebe0222845 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 14 Sep 2022 21:28:46 +0800 +Subject: f2fs: fix to account FS_CP_DATA_IO correctly + +From: Chao Yu + +[ Upstream commit d80afefb17e01aa0c46a8eebc01882e0ebd8b0f6 ] + +f2fs_inode_info.cp_task was introduced for FS_CP_DATA_IO accounting +since commit b0af6d491a6b ("f2fs: add app/fs io stat"). + +However, cp_task usage coverage has been increased due to below +commits: +commit 040d2bb318d1 ("f2fs: fix to avoid deadloop if data_flush is on") +commit 186857c5a14a ("f2fs: fix potential recursive call when enabling data_flush") + +So that, if data_flush mountoption is on, when data flush was +triggered from background, the IO from data flush will be accounted +as checkpoint IO type incorrectly. + +In order to fix this issue, this patch splits cp_task into two: +a) cp_task: used for IO accounting +b) wb_task: used to avoid deadlock + +Fixes: 040d2bb318d1 ("f2fs: fix to avoid deadloop if data_flush is on") +Fixes: 186857c5a14a ("f2fs: fix potential recursive call when enabling data_flush") +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Sasha Levin +--- + fs/f2fs/checkpoint.c | 13 +++++++++---- + fs/f2fs/data.c | 4 ++-- + fs/f2fs/f2fs.h | 4 +++- + fs/f2fs/segment.c | 2 +- + 4 files changed, 15 insertions(+), 8 deletions(-) + +diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c +index 0653c54873b5..cd46a64ace1b 100644 +--- a/fs/f2fs/checkpoint.c ++++ b/fs/f2fs/checkpoint.c +@@ -1047,7 +1047,8 @@ void f2fs_remove_dirty_inode(struct inode *inode) + spin_unlock(&sbi->inode_lock[type]); + } + +-int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type) ++int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type, ++ bool from_cp) + { + struct list_head *head; + struct inode *inode; +@@ -1082,11 +1083,15 @@ int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type) + if (inode) { + unsigned long cur_ino = inode->i_ino; + +- F2FS_I(inode)->cp_task = current; ++ if (from_cp) ++ F2FS_I(inode)->cp_task = current; ++ F2FS_I(inode)->wb_task = current; + + filemap_fdatawrite(inode->i_mapping); + +- F2FS_I(inode)->cp_task = NULL; ++ F2FS_I(inode)->wb_task = NULL; ++ if (from_cp) ++ F2FS_I(inode)->cp_task = NULL; + + iput(inode); + /* We need to give cpu to another writers. */ +@@ -1215,7 +1220,7 @@ static int block_operations(struct f2fs_sb_info *sbi) + /* write all the dirty dentry pages */ + if (get_pages(sbi, F2FS_DIRTY_DENTS)) { + f2fs_unlock_all(sbi); +- err = f2fs_sync_dirty_inodes(sbi, DIR_INODE); ++ err = f2fs_sync_dirty_inodes(sbi, DIR_INODE, true); + if (err) + return err; + cond_resched(); +diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c +index b2016fd3a7ca..9270330ec5ce 100644 +--- a/fs/f2fs/data.c ++++ b/fs/f2fs/data.c +@@ -2912,7 +2912,7 @@ int f2fs_write_single_data_page(struct page *page, int *submitted, + } + unlock_page(page); + if (!S_ISDIR(inode->i_mode) && !IS_NOQUOTA(inode) && +- !F2FS_I(inode)->cp_task && allow_balance) ++ !F2FS_I(inode)->wb_task && allow_balance) + f2fs_balance_fs(sbi, need_balance_fs); + + if (unlikely(f2fs_cp_error(sbi))) { +@@ -3210,7 +3210,7 @@ static inline bool __should_serialize_io(struct inode *inode, + struct writeback_control *wbc) + { + /* to avoid deadlock in path of data flush */ +- if (F2FS_I(inode)->cp_task) ++ if (F2FS_I(inode)->wb_task) + return false; + + if (!S_ISREG(inode->i_mode)) +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index 70fec13d35b7..c03fdda1bddf 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -701,6 +701,7 @@ struct f2fs_inode_info { + unsigned int clevel; /* maximum level of given file name */ + struct task_struct *task; /* lookup and create consistency */ + struct task_struct *cp_task; /* separate cp/wb IO stats*/ ++ struct task_struct *wb_task; /* indicate inode is in context of writeback */ + nid_t i_xattr_nid; /* node id that contains xattrs */ + loff_t last_disk_size; /* lastly written file size */ + spinlock_t i_size_lock; /* protect last_disk_size */ +@@ -3400,7 +3401,8 @@ int f2fs_recover_orphan_inodes(struct f2fs_sb_info *sbi); + int f2fs_get_valid_checkpoint(struct f2fs_sb_info *sbi); + void f2fs_update_dirty_page(struct inode *inode, struct page *page); + void f2fs_remove_dirty_inode(struct inode *inode); +-int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type); ++int f2fs_sync_dirty_inodes(struct f2fs_sb_info *sbi, enum inode_type type, ++ bool from_cp); + void f2fs_wait_on_all_pages(struct f2fs_sb_info *sbi, int type); + int f2fs_write_checkpoint(struct f2fs_sb_info *sbi, struct cp_control *cpc); + void f2fs_init_ino_entry_info(struct f2fs_sb_info *sbi); +diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c +index 173161f1ced0..3123fd49c8ce 100644 +--- a/fs/f2fs/segment.c ++++ b/fs/f2fs/segment.c +@@ -561,7 +561,7 @@ void f2fs_balance_fs_bg(struct f2fs_sb_info *sbi, bool from_bg) + mutex_lock(&sbi->flush_lock); + + blk_start_plug(&plug); +- f2fs_sync_dirty_inodes(sbi, FILE_INODE); ++ f2fs_sync_dirty_inodes(sbi, FILE_INODE, false); + blk_finish_plug(&plug); + + mutex_unlock(&sbi->flush_lock); +-- +2.35.1 + diff --git a/queue-5.10/f2fs-fix-to-avoid-req_time-and-cp_time-collision.patch b/queue-5.10/f2fs-fix-to-avoid-req_time-and-cp_time-collision.patch new file mode 100644 index 00000000000..83dcc3806f1 --- /dev/null +++ b/queue-5.10/f2fs-fix-to-avoid-req_time-and-cp_time-collision.patch @@ -0,0 +1,150 @@ +From f85504dc985c81e0ae8a652a49098fdd4db85a26 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 Nov 2020 10:57:36 +0800 +Subject: f2fs: fix to avoid REQ_TIME and CP_TIME collision + +From: Chao Yu + +[ Upstream commit 493720a4854343b7c3fe100cda6a3a2c3f8d4b5d ] + +Lei Li reported a issue: if foreground operations are frequent, background +checkpoint may be always skipped due to below check, result in losing more +data after sudden power-cut. + +f2fs_balance_fs_bg() +... + if (!is_idle(sbi, REQ_TIME) && + (!excess_dirty_nats(sbi) && !excess_dirty_nodes(sbi))) + return; + +E.g: +cp_interval = 5 second +idle_interval = 2 second +foreground operation interval = 1 second (append 1 byte per second into file) + +In such case, no matter when it calls f2fs_balance_fs_bg(), is_idle(, REQ_TIME) +returns false, result in skipping background checkpoint. + +This patch changes as below to make trigger condition being more reasonable: +- trigger sync_fs() if dirty_{nats,nodes} and prefree segs exceeds threshold; +- skip triggering sync_fs() if there is any background inflight IO or there is +foreground operation recently and meanwhile cp_rwsem is being held by someone; + +Reported-by: Lei Li +Signed-off-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Stable-dep-of: d80afefb17e0 ("f2fs: fix to account FS_CP_DATA_IO correctly") +Signed-off-by: Sasha Levin +--- + fs/f2fs/f2fs.h | 19 +++++++++++++------ + fs/f2fs/segment.c | 47 +++++++++++++++++++++++++++-------------------- + 2 files changed, 40 insertions(+), 26 deletions(-) + +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index dbe9fcef07e3..70fec13d35b7 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -2426,24 +2426,31 @@ static inline void *f2fs_kmem_cache_alloc(struct kmem_cache *cachep, + return entry; + } + +-static inline bool is_idle(struct f2fs_sb_info *sbi, int type) ++static inline bool is_inflight_io(struct f2fs_sb_info *sbi, int type) + { +- if (sbi->gc_mode == GC_URGENT_HIGH) +- return true; +- + if (get_pages(sbi, F2FS_RD_DATA) || get_pages(sbi, F2FS_RD_NODE) || + get_pages(sbi, F2FS_RD_META) || get_pages(sbi, F2FS_WB_DATA) || + get_pages(sbi, F2FS_WB_CP_DATA) || + get_pages(sbi, F2FS_DIO_READ) || + get_pages(sbi, F2FS_DIO_WRITE)) +- return false; ++ return true; + + if (type != DISCARD_TIME && SM_I(sbi) && SM_I(sbi)->dcc_info && + atomic_read(&SM_I(sbi)->dcc_info->queued_discard)) +- return false; ++ return true; + + if (SM_I(sbi) && SM_I(sbi)->fcc_info && + atomic_read(&SM_I(sbi)->fcc_info->queued_flush)) ++ return true; ++ return false; ++} ++ ++static inline bool is_idle(struct f2fs_sb_info *sbi, int type) ++{ ++ if (sbi->gc_mode == GC_URGENT_HIGH) ++ return true; ++ ++ if (is_inflight_io(sbi, type)) + return false; + + if (sbi->gc_mode == GC_URGENT_LOW && +diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c +index 19224e7d2ad0..173161f1ced0 100644 +--- a/fs/f2fs/segment.c ++++ b/fs/f2fs/segment.c +@@ -536,31 +536,38 @@ void f2fs_balance_fs_bg(struct f2fs_sb_info *sbi, bool from_bg) + else + f2fs_build_free_nids(sbi, false, false); + +- if (!is_idle(sbi, REQ_TIME) && +- (!excess_dirty_nats(sbi) && !excess_dirty_nodes(sbi))) ++ if (excess_dirty_nats(sbi) || excess_dirty_nodes(sbi) || ++ excess_prefree_segs(sbi)) ++ goto do_sync; ++ ++ /* there is background inflight IO or foreground operation recently */ ++ if (is_inflight_io(sbi, REQ_TIME) || ++ (!f2fs_time_over(sbi, REQ_TIME) && rwsem_is_locked(&sbi->cp_rwsem))) + return; + ++ /* exceed periodical checkpoint timeout threshold */ ++ if (f2fs_time_over(sbi, CP_TIME)) ++ goto do_sync; ++ + /* checkpoint is the only way to shrink partial cached entries */ +- if (!f2fs_available_free_memory(sbi, NAT_ENTRIES) || +- !f2fs_available_free_memory(sbi, INO_ENTRIES) || +- excess_prefree_segs(sbi) || +- excess_dirty_nats(sbi) || +- excess_dirty_nodes(sbi) || +- f2fs_time_over(sbi, CP_TIME)) { +- if (test_opt(sbi, DATA_FLUSH) && from_bg) { +- struct blk_plug plug; +- +- mutex_lock(&sbi->flush_lock); +- +- blk_start_plug(&plug); +- f2fs_sync_dirty_inodes(sbi, FILE_INODE); +- blk_finish_plug(&plug); ++ if (f2fs_available_free_memory(sbi, NAT_ENTRIES) || ++ f2fs_available_free_memory(sbi, INO_ENTRIES)) ++ return; + +- mutex_unlock(&sbi->flush_lock); +- } +- f2fs_sync_fs(sbi->sb, true); +- stat_inc_bg_cp_count(sbi->stat_info); ++do_sync: ++ if (test_opt(sbi, DATA_FLUSH) && from_bg) { ++ struct blk_plug plug; ++ ++ mutex_lock(&sbi->flush_lock); ++ ++ blk_start_plug(&plug); ++ f2fs_sync_dirty_inodes(sbi, FILE_INODE); ++ blk_finish_plug(&plug); ++ ++ mutex_unlock(&sbi->flush_lock); + } ++ f2fs_sync_fs(sbi->sb, true); ++ stat_inc_bg_cp_count(sbi->stat_info); + } + + static int __submit_flush_wait(struct f2fs_sb_info *sbi, +-- +2.35.1 + diff --git a/queue-5.10/firmware-google-test-spinlock-on-panic-path-to-avoid.patch b/queue-5.10/firmware-google-test-spinlock-on-panic-path-to-avoid.patch new file mode 100644 index 00000000000..1c48793f92e --- /dev/null +++ b/queue-5.10/firmware-google-test-spinlock-on-panic-path-to-avoid.patch @@ -0,0 +1,59 @@ +From 8e720c54bf9011565159555645d21c37f0b768ff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 17:07:55 -0300 +Subject: firmware: google: Test spinlock on panic path to avoid lockups + +From: Guilherme G. Piccoli + +[ Upstream commit 3e081438b8e639cc76ef1a5ce0c1bd8a154082c7 ] + +Currently the gsmi driver registers a panic notifier as well as +reboot and die notifiers. The callbacks registered are called in +atomic and very limited context - for instance, panic disables +preemption and local IRQs, also all secondary CPUs (not executing +the panic path) are shutdown. + +With that said, taking a spinlock in this scenario is a dangerous +invitation for lockup scenarios. So, fix that by checking if the +spinlock is free to acquire in the panic notifier callback - if not, +bail-out and avoid a potential hang. + +Fixes: 74c5b31c6618 ("driver: Google EFI SMI") +Cc: Andrew Morton +Cc: Ard Biesheuvel +Cc: David Gow +Cc: Greg Kroah-Hartman +Cc: Julius Werner +Cc: Petr Mladek +Reviewed-by: Evan Green +Signed-off-by: Guilherme G. Piccoli +Link: https://lore.kernel.org/r/20220909200755.189679-1-gpiccoli@igalia.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/firmware/google/gsmi.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/firmware/google/gsmi.c b/drivers/firmware/google/gsmi.c +index 7d9367b22010..c1cd5ca875ca 100644 +--- a/drivers/firmware/google/gsmi.c ++++ b/drivers/firmware/google/gsmi.c +@@ -680,6 +680,15 @@ static struct notifier_block gsmi_die_notifier = { + static int gsmi_panic_callback(struct notifier_block *nb, + unsigned long reason, void *arg) + { ++ ++ /* ++ * Panic callbacks are executed with all other CPUs stopped, ++ * so we must not attempt to spin waiting for gsmi_dev.lock ++ * to be released. ++ */ ++ if (spin_is_locked(&gsmi_dev.lock)) ++ return NOTIFY_DONE; ++ + gsmi_shutdown_reason(GSMI_SHUTDOWN_PANIC); + return NOTIFY_DONE; + } +-- +2.35.1 + diff --git a/queue-5.10/fpga-prevent-integer-overflow-in-dfl_feature_ioctl_s.patch b/queue-5.10/fpga-prevent-integer-overflow-in-dfl_feature_ioctl_s.patch new file mode 100644 index 00000000000..3f090da8d8b --- /dev/null +++ b/queue-5.10/fpga-prevent-integer-overflow-in-dfl_feature_ioctl_s.patch @@ -0,0 +1,38 @@ +From 94d5522ebb6b553ca019f5c1b76a2cace1b3523a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 08:18:45 +0300 +Subject: fpga: prevent integer overflow in dfl_feature_ioctl_set_irq() + +From: Dan Carpenter + +[ Upstream commit 939bc5453b8cbdde9f1e5110ce8309aedb1b501a ] + +The "hdr.count * sizeof(s32)" multiplication can overflow on 32 bit +systems leading to memory corruption. Use array_size() to fix that. + +Fixes: 322b598be4d9 ("fpga: dfl: introduce interrupt trigger setting API") +Signed-off-by: Dan Carpenter +Acked-by: Xu Yilun +Link: https://lore.kernel.org/r/YxBAtYCM38dM7yzI@kili +Signed-off-by: Xu Yilun +Signed-off-by: Sasha Levin +--- + drivers/fpga/dfl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c +index b450870b75ed..eb8a6e329af9 100644 +--- a/drivers/fpga/dfl.c ++++ b/drivers/fpga/dfl.c +@@ -1857,7 +1857,7 @@ long dfl_feature_ioctl_set_irq(struct platform_device *pdev, + return -EINVAL; + + fds = memdup_user((void __user *)(arg + sizeof(hdr)), +- hdr.count * sizeof(s32)); ++ array_size(hdr.count, sizeof(s32))); + if (IS_ERR(fds)) + return PTR_ERR(fds); + +-- +2.35.1 + diff --git a/queue-5.10/fs-security-add-sb_delete-hook.patch b/queue-5.10/fs-security-add-sb_delete-hook.patch new file mode 100644 index 00000000000..a190c62ff6c --- /dev/null +++ b/queue-5.10/fs-security-add-sb_delete-hook.patch @@ -0,0 +1,117 @@ +From d46fe169d6c766a600e6037e8fa87ac94d0f8bd8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Apr 2021 17:41:16 +0200 +Subject: fs,security: Add sb_delete hook +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Mickaël Salaün + +[ Upstream commit 83e804f0bfee2247b1c0aa64845c81a38562da7a ] + +The sb_delete security hook is called when shutting down a superblock, +which may be useful to release kernel objects tied to the superblock's +lifetime (e.g. inodes). + +This new hook is needed by Landlock to release (ephemerally) tagged +struct inodes. This comes from the unprivileged nature of Landlock +described in the next commit. + +Cc: Al Viro +Cc: James Morris +Signed-off-by: Mickaël Salaün +Reviewed-by: Jann Horn +Acked-by: Serge Hallyn +Reviewed-by: Kees Cook +Link: https://lore.kernel.org/r/20210422154123.13086-7-mic@digikod.net +Signed-off-by: James Morris +Stable-dep-of: d7e7b9af104c ("fscrypt: stop using keyrings subsystem for fscrypt_master_key") +Signed-off-by: Sasha Levin +--- + fs/super.c | 1 + + include/linux/lsm_hook_defs.h | 1 + + include/linux/lsm_hooks.h | 3 +++ + include/linux/security.h | 4 ++++ + security/security.c | 5 +++++ + 5 files changed, 14 insertions(+) + +diff --git a/fs/super.c b/fs/super.c +index bae3fe80f852..705be5d0600e 100644 +--- a/fs/super.c ++++ b/fs/super.c +@@ -454,6 +454,7 @@ void generic_shutdown_super(struct super_block *sb) + evict_inodes(sb); + /* only nonzero refcount inodes can have marks */ + fsnotify_sb_delete(sb); ++ security_sb_delete(sb); + + if (sb->s_dio_done_wq) { + destroy_workqueue(sb->s_dio_done_wq); +diff --git a/include/linux/lsm_hook_defs.h b/include/linux/lsm_hook_defs.h +index d13631a5e908..d74ffcdc7be6 100644 +--- a/include/linux/lsm_hook_defs.h ++++ b/include/linux/lsm_hook_defs.h +@@ -59,6 +59,7 @@ LSM_HOOK(int, 0, fs_context_dup, struct fs_context *fc, + LSM_HOOK(int, -ENOPARAM, fs_context_parse_param, struct fs_context *fc, + struct fs_parameter *param) + LSM_HOOK(int, 0, sb_alloc_security, struct super_block *sb) ++LSM_HOOK(void, LSM_RET_VOID, sb_delete, struct super_block *sb) + LSM_HOOK(void, LSM_RET_VOID, sb_free_security, struct super_block *sb) + LSM_HOOK(void, LSM_RET_VOID, sb_free_mnt_opts, void *mnt_opts) + LSM_HOOK(int, 0, sb_eat_lsm_opts, char *orig, void **mnt_opts) +diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h +index 64cdf4d7bfb3..73abbdd94c13 100644 +--- a/include/linux/lsm_hooks.h ++++ b/include/linux/lsm_hooks.h +@@ -108,6 +108,9 @@ + * allocated. + * @sb contains the super_block structure to be modified. + * Return 0 if operation was successful. ++ * @sb_delete: ++ * Release objects tied to a superblock (e.g. inodes). ++ * @sb contains the super_block structure being released. + * @sb_free_security: + * Deallocate and clear the sb->s_security field. + * @sb contains the super_block structure to be modified. +diff --git a/include/linux/security.h b/include/linux/security.h +index e9b4b5410614..f37087d76913 100644 +--- a/include/linux/security.h ++++ b/include/linux/security.h +@@ -290,6 +290,7 @@ void security_bprm_committed_creds(struct linux_binprm *bprm); + int security_fs_context_dup(struct fs_context *fc, struct fs_context *src_fc); + int security_fs_context_parse_param(struct fs_context *fc, struct fs_parameter *param); + int security_sb_alloc(struct super_block *sb); ++void security_sb_delete(struct super_block *sb); + void security_sb_free(struct super_block *sb); + void security_free_mnt_opts(void **mnt_opts); + int security_sb_eat_lsm_opts(char *options, void **mnt_opts); +@@ -622,6 +623,9 @@ static inline int security_sb_alloc(struct super_block *sb) + return 0; + } + ++static inline void security_sb_delete(struct super_block *sb) ++{ } ++ + static inline void security_sb_free(struct super_block *sb) + { } + +diff --git a/security/security.c b/security/security.c +index 8ea826ea6167..771ec21a6e0b 100644 +--- a/security/security.c ++++ b/security/security.c +@@ -885,6 +885,11 @@ int security_sb_alloc(struct super_block *sb) + return call_int_hook(sb_alloc_security, 0, sb); + } + ++void security_sb_delete(struct super_block *sb) ++{ ++ call_void_hook(sb_delete, sb); ++} ++ + void security_sb_free(struct super_block *sb) + { + call_void_hook(sb_free_security, sb); +-- +2.35.1 + diff --git a/queue-5.10/fscrypt-simplify-master-key-locking.patch b/queue-5.10/fscrypt-simplify-master-key-locking.patch new file mode 100644 index 00000000000..7a953d5d248 --- /dev/null +++ b/queue-5.10/fscrypt-simplify-master-key-locking.patch @@ -0,0 +1,215 @@ +From 49f9da1c3120bc16688a203dac6f292f4487d997 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Nov 2020 19:26:26 -0800 +Subject: fscrypt: simplify master key locking + +From: Eric Biggers + +[ Upstream commit 4a4b8721f1a5e4b01e45b3153c68d5a1014b25de ] + +The stated reasons for separating fscrypt_master_key::mk_secret_sem from +the standard semaphore contained in every 'struct key' no longer apply. + +First, due to commit a992b20cd4ee ("fscrypt: add +fscrypt_prepare_new_inode() and fscrypt_set_context()"), +fscrypt_get_encryption_info() is no longer called from within a +filesystem transaction. + +Second, due to commit d3ec10aa9581 ("KEYS: Don't write out to userspace +while holding key semaphore"), the semaphore for the "keyring" key type +no longer ranks above page faults. + +That leaves performance as the only possible reason to keep the separate +mk_secret_sem. Specifically, having mk_secret_sem reduces the +contention between setup_file_encryption_key() and +FS_IOC_{ADD,REMOVE}_ENCRYPTION_KEY. However, these ioctls aren't +executed often, so this doesn't seem to be worth the extra complexity. + +Therefore, simplify the locking design by just using key->sem instead of +mk_secret_sem. + +Link: https://lore.kernel.org/r/20201117032626.320275-1-ebiggers@kernel.org +Signed-off-by: Eric Biggers +Stable-dep-of: d7e7b9af104c ("fscrypt: stop using keyrings subsystem for fscrypt_master_key") +Signed-off-by: Sasha Levin +--- + fs/crypto/fscrypt_private.h | 19 ++++++------------- + fs/crypto/hooks.c | 8 +++++--- + fs/crypto/keyring.c | 8 +------- + fs/crypto/keysetup.c | 20 +++++++++----------- + 4 files changed, 21 insertions(+), 34 deletions(-) + +diff --git a/fs/crypto/fscrypt_private.h b/fs/crypto/fscrypt_private.h +index 052ad40ecdb2..8a0141f7195b 100644 +--- a/fs/crypto/fscrypt_private.h ++++ b/fs/crypto/fscrypt_private.h +@@ -439,16 +439,9 @@ struct fscrypt_master_key { + * FS_IOC_REMOVE_ENCRYPTION_KEY can be retried, or + * FS_IOC_ADD_ENCRYPTION_KEY can add the secret again. + * +- * Locking: protected by key->sem (outer) and mk_secret_sem (inner). +- * The reason for two locks is that key->sem also protects modifying +- * mk_users, which ranks it above the semaphore for the keyring key +- * type, which is in turn above page faults (via keyring_read). But +- * sometimes filesystems call fscrypt_get_encryption_info() from within +- * a transaction, which ranks it below page faults. So we need a +- * separate lock which protects mk_secret but not also mk_users. ++ * Locking: protected by this master key's key->sem. + */ + struct fscrypt_master_key_secret mk_secret; +- struct rw_semaphore mk_secret_sem; + + /* + * For v1 policy keys: an arbitrary key descriptor which was assigned by +@@ -467,8 +460,8 @@ struct fscrypt_master_key { + * + * This is NULL for v1 policy keys; those can only be added by root. + * +- * Locking: in addition to this keyrings own semaphore, this is +- * protected by the master key's key->sem, so we can do atomic ++ * Locking: in addition to this keyring's own semaphore, this is ++ * protected by this master key's key->sem, so we can do atomic + * search+insert. It can also be searched without taking any locks, but + * in that case the returned key may have already been removed. + */ +@@ -510,9 +503,9 @@ is_master_key_secret_present(const struct fscrypt_master_key_secret *secret) + /* + * The READ_ONCE() is only necessary for fscrypt_drop_inode() and + * fscrypt_key_describe(). These run in atomic context, so they can't +- * take ->mk_secret_sem and thus 'secret' can change concurrently which +- * would be a data race. But they only need to know whether the secret +- * *was* present at the time of check, so READ_ONCE() suffices. ++ * take the key semaphore and thus 'secret' can change concurrently ++ * which would be a data race. But they only need to know whether the ++ * secret *was* present at the time of check, so READ_ONCE() suffices. + */ + return READ_ONCE(secret->size) != 0; + } +diff --git a/fs/crypto/hooks.c b/fs/crypto/hooks.c +index 4180371bf864..0c6fa5c2d6f3 100644 +--- a/fs/crypto/hooks.c ++++ b/fs/crypto/hooks.c +@@ -139,6 +139,7 @@ int fscrypt_prepare_setflags(struct inode *inode, + unsigned int oldflags, unsigned int flags) + { + struct fscrypt_info *ci; ++ struct key *key; + struct fscrypt_master_key *mk; + int err; + +@@ -154,13 +155,14 @@ int fscrypt_prepare_setflags(struct inode *inode, + ci = inode->i_crypt_info; + if (ci->ci_policy.version != FSCRYPT_POLICY_V2) + return -EINVAL; +- mk = ci->ci_master_key->payload.data[0]; +- down_read(&mk->mk_secret_sem); ++ key = ci->ci_master_key; ++ mk = key->payload.data[0]; ++ down_read(&key->sem); + if (is_master_key_secret_present(&mk->mk_secret)) + err = fscrypt_derive_dirhash_key(ci, mk); + else + err = -ENOKEY; +- up_read(&mk->mk_secret_sem); ++ up_read(&key->sem); + return err; + } + return 0; +diff --git a/fs/crypto/keyring.c b/fs/crypto/keyring.c +index d7ec52cb3d9a..0b3ffbb4faf4 100644 +--- a/fs/crypto/keyring.c ++++ b/fs/crypto/keyring.c +@@ -347,7 +347,6 @@ static int add_new_master_key(struct fscrypt_master_key_secret *secret, + mk->mk_spec = *mk_spec; + + move_master_key_secret(&mk->mk_secret, secret); +- init_rwsem(&mk->mk_secret_sem); + + refcount_set(&mk->mk_refcount, 1); /* secret is present */ + INIT_LIST_HEAD(&mk->mk_decrypted_inodes); +@@ -427,11 +426,8 @@ static int add_existing_master_key(struct fscrypt_master_key *mk, + } + + /* Re-add the secret if needed. */ +- if (rekey) { +- down_write(&mk->mk_secret_sem); ++ if (rekey) + move_master_key_secret(&mk->mk_secret, secret); +- up_write(&mk->mk_secret_sem); +- } + return 0; + } + +@@ -975,10 +971,8 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users) + /* No user claims remaining. Go ahead and wipe the secret. */ + dead = false; + if (is_master_key_secret_present(&mk->mk_secret)) { +- down_write(&mk->mk_secret_sem); + wipe_master_key_secret(&mk->mk_secret); + dead = refcount_dec_and_test(&mk->mk_refcount); +- up_write(&mk->mk_secret_sem); + } + up_write(&key->sem); + if (dead) { +diff --git a/fs/crypto/keysetup.c b/fs/crypto/keysetup.c +index 73d96e35d9ae..72aec33e0ea5 100644 +--- a/fs/crypto/keysetup.c ++++ b/fs/crypto/keysetup.c +@@ -405,11 +405,11 @@ static bool fscrypt_valid_master_key_size(const struct fscrypt_master_key *mk, + * Find the master key, then set up the inode's actual encryption key. + * + * If the master key is found in the filesystem-level keyring, then the +- * corresponding 'struct key' is returned in *master_key_ret with +- * ->mk_secret_sem read-locked. This is needed to ensure that only one task +- * links the fscrypt_info into ->mk_decrypted_inodes (as multiple tasks may race +- * to create an fscrypt_info for the same inode), and to synchronize the master +- * key being removed with a new inode starting to use it. ++ * corresponding 'struct key' is returned in *master_key_ret with its semaphore ++ * read-locked. This is needed to ensure that only one task links the ++ * fscrypt_info into ->mk_decrypted_inodes (as multiple tasks may race to create ++ * an fscrypt_info for the same inode), and to synchronize the master key being ++ * removed with a new inode starting to use it. + */ + static int setup_file_encryption_key(struct fscrypt_info *ci, + bool need_dirhash_key, +@@ -458,7 +458,7 @@ static int setup_file_encryption_key(struct fscrypt_info *ci, + } + + mk = key->payload.data[0]; +- down_read(&mk->mk_secret_sem); ++ down_read(&key->sem); + + /* Has the secret been removed (via FS_IOC_REMOVE_ENCRYPTION_KEY)? */ + if (!is_master_key_secret_present(&mk->mk_secret)) { +@@ -490,7 +490,7 @@ static int setup_file_encryption_key(struct fscrypt_info *ci, + return 0; + + out_release_key: +- up_read(&mk->mk_secret_sem); ++ up_read(&key->sem); + key_put(key); + return err; + } +@@ -593,9 +593,7 @@ fscrypt_setup_encryption_info(struct inode *inode, + res = 0; + out: + if (master_key) { +- struct fscrypt_master_key *mk = master_key->payload.data[0]; +- +- up_read(&mk->mk_secret_sem); ++ up_read(&master_key->sem); + key_put(master_key); + } + put_crypt_info(crypt_info); +@@ -769,7 +767,7 @@ int fscrypt_drop_inode(struct inode *inode) + return 0; + + /* +- * Note: since we aren't holding ->mk_secret_sem, the result here can ++ * Note: since we aren't holding the key semaphore, the result here can + * immediately become outdated. But there's no correctness problem with + * unnecessarily evicting. Nor is there a correctness problem with not + * evicting while iput() is racing with the key being removed, since +-- +2.35.1 + diff --git a/queue-5.10/fscrypt-stop-using-keyrings-subsystem-for-fscrypt_ma.patch b/queue-5.10/fscrypt-stop-using-keyrings-subsystem-for-fscrypt_ma.patch new file mode 100644 index 00000000000..570c7cc242b --- /dev/null +++ b/queue-5.10/fscrypt-stop-using-keyrings-subsystem-for-fscrypt_ma.patch @@ -0,0 +1,1304 @@ +From 19907e51e7fec7ef211076b11f8a4429993df750 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 12:32:06 -0700 +Subject: fscrypt: stop using keyrings subsystem for fscrypt_master_key + +From: Eric Biggers + +[ Upstream commit d7e7b9af104c7b389a0c21eb26532511bce4b510 ] + +The approach of fs/crypto/ internally managing the fscrypt_master_key +structs as the payloads of "struct key" objects contained in a +"struct key" keyring has outlived its usefulness. The original idea was +to simplify the code by reusing code from the keyrings subsystem. +However, several issues have arisen that can't easily be resolved: + +- When a master key struct is destroyed, blk_crypto_evict_key() must be + called on any per-mode keys embedded in it. (This started being the + case when inline encryption support was added.) Yet, the keyrings + subsystem can arbitrarily delay the destruction of keys, even past the + time the filesystem was unmounted. Therefore, currently there is no + easy way to call blk_crypto_evict_key() when a master key is + destroyed. Currently, this is worked around by holding an extra + reference to the filesystem's request_queue(s). But it was overlooked + that the request_queue reference is *not* guaranteed to pin the + corresponding blk_crypto_profile too; for device-mapper devices that + support inline crypto, it doesn't. This can cause a use-after-free. + +- When the last inode that was using an incompletely-removed master key + is evicted, the master key removal is completed by removing the key + struct from the keyring. Currently this is done via key_invalidate(). + Yet, key_invalidate() takes the key semaphore. This can deadlock when + called from the shrinker, since in fscrypt_ioctl_add_key(), memory is + allocated with GFP_KERNEL under the same semaphore. + +- More generally, the fact that the keyrings subsystem can arbitrarily + delay the destruction of keys (via garbage collection delay, or via + random processes getting temporary key references) is undesirable, as + it means we can't strictly guarantee that all secrets are ever wiped. + +- Doing the master key lookups via the keyrings subsystem results in the + key_permission LSM hook being called. fscrypt doesn't want this, as + all access control for encrypted files is designed to happen via the + files themselves, like any other files. The workaround which SELinux + users are using is to change their SELinux policy to grant key search + access to all domains. This works, but it is an odd extra step that + shouldn't really have to be done. + +The fix for all these issues is to change the implementation to what I +should have done originally: don't use the keyrings subsystem to keep +track of the filesystem's fscrypt_master_key structs. Instead, just +store them in a regular kernel data structure, and rework the reference +counting, locking, and lifetime accordingly. Retain support for +RCU-mode key lookups by using a hash table. Replace fscrypt_sb_free() +with fscrypt_sb_delete(), which releases the keys synchronously and runs +a bit earlier during unmount, so that block devices are still available. + +A side effect of this patch is that neither the master keys themselves +nor the filesystem keyrings will be listed in /proc/keys anymore. +("Master key users" and the master key users keyrings will still be +listed.) However, this was mostly an implementation detail, and it was +intended just for debugging purposes. I don't know of anyone using it. + +This patch does *not* change how "master key users" (->mk_users) works; +that still uses the keyrings subsystem. That is still needed for key +quotas, and changing that isn't necessary to solve the issues listed +above. If we decide to change that too, it would be a separate patch. + +I've marked this as fixing the original commit that added the fscrypt +keyring, but as noted above the most important issue that this patch +fixes wasn't introduced until the addition of inline encryption support. + +Fixes: 22d94f493bfb ("fscrypt: add FS_IOC_ADD_ENCRYPTION_KEY ioctl") +Signed-off-by: Eric Biggers +Link: https://lore.kernel.org/r/20220901193208.138056-2-ebiggers@kernel.org +Signed-off-by: Sasha Levin +--- + fs/crypto/fscrypt_private.h | 71 ++++-- + fs/crypto/hooks.c | 10 +- + fs/crypto/keyring.c | 486 +++++++++++++++++++----------------- + fs/crypto/keysetup.c | 81 +++--- + fs/crypto/policy.c | 8 +- + fs/super.c | 2 +- + include/linux/fs.h | 2 +- + include/linux/fscrypt.h | 4 +- + 8 files changed, 353 insertions(+), 311 deletions(-) + +diff --git a/fs/crypto/fscrypt_private.h b/fs/crypto/fscrypt_private.h +index 8a0141f7195b..b746d7df3758 100644 +--- a/fs/crypto/fscrypt_private.h ++++ b/fs/crypto/fscrypt_private.h +@@ -220,7 +220,7 @@ struct fscrypt_info { + * will be NULL if the master key was found in a process-subscribed + * keyring rather than in the filesystem-level keyring. + */ +- struct key *ci_master_key; ++ struct fscrypt_master_key *ci_master_key; + + /* + * Link in list of inodes that were unlocked with the master key. +@@ -431,6 +431,40 @@ struct fscrypt_master_key_secret { + */ + struct fscrypt_master_key { + ++ /* ++ * Back-pointer to the super_block of the filesystem to which this ++ * master key has been added. Only valid if ->mk_active_refs > 0. ++ */ ++ struct super_block *mk_sb; ++ ++ /* ++ * Link in ->mk_sb->s_master_keys->key_hashtable. ++ * Only valid if ->mk_active_refs > 0. ++ */ ++ struct hlist_node mk_node; ++ ++ /* Semaphore that protects ->mk_secret and ->mk_users */ ++ struct rw_semaphore mk_sem; ++ ++ /* ++ * Active and structural reference counts. An active ref guarantees ++ * that the struct continues to exist, continues to be in the keyring ++ * ->mk_sb->s_master_keys, and that any embedded subkeys (e.g. ++ * ->mk_direct_keys) that have been prepared continue to exist. ++ * A structural ref only guarantees that the struct continues to exist. ++ * ++ * There is one active ref associated with ->mk_secret being present, ++ * and one active ref for each inode in ->mk_decrypted_inodes. ++ * ++ * There is one structural ref associated with the active refcount being ++ * nonzero. Finding a key in the keyring also takes a structural ref, ++ * which is then held temporarily while the key is operated on. ++ */ ++ refcount_t mk_active_refs; ++ refcount_t mk_struct_refs; ++ ++ struct rcu_head mk_rcu_head; ++ + /* + * The secret key material. After FS_IOC_REMOVE_ENCRYPTION_KEY is + * executed, this is wiped and no new inodes can be unlocked with this +@@ -439,7 +473,10 @@ struct fscrypt_master_key { + * FS_IOC_REMOVE_ENCRYPTION_KEY can be retried, or + * FS_IOC_ADD_ENCRYPTION_KEY can add the secret again. + * +- * Locking: protected by this master key's key->sem. ++ * While ->mk_secret is present, one ref in ->mk_active_refs is held. ++ * ++ * Locking: protected by ->mk_sem. The manipulation of ->mk_active_refs ++ * associated with this field is protected by ->mk_sem as well. + */ + struct fscrypt_master_key_secret mk_secret; + +@@ -460,22 +497,12 @@ struct fscrypt_master_key { + * + * This is NULL for v1 policy keys; those can only be added by root. + * +- * Locking: in addition to this keyring's own semaphore, this is +- * protected by this master key's key->sem, so we can do atomic +- * search+insert. It can also be searched without taking any locks, but +- * in that case the returned key may have already been removed. ++ * Locking: protected by ->mk_sem. (We don't just rely on the keyrings ++ * subsystem semaphore ->mk_users->sem, as we need support for atomic ++ * search+insert along with proper synchronization with ->mk_secret.) + */ + struct key *mk_users; + +- /* +- * Length of ->mk_decrypted_inodes, plus one if mk_secret is present. +- * Once this goes to 0, the master key is removed from ->s_master_keys. +- * The 'struct fscrypt_master_key' will continue to live as long as the +- * 'struct key' whose payload it is, but we won't let this reference +- * count rise again. +- */ +- refcount_t mk_refcount; +- + /* + * List of inodes that were unlocked using this key. This allows the + * inodes to be evicted efficiently if the key is removed. +@@ -501,10 +528,10 @@ static inline bool + is_master_key_secret_present(const struct fscrypt_master_key_secret *secret) + { + /* +- * The READ_ONCE() is only necessary for fscrypt_drop_inode() and +- * fscrypt_key_describe(). These run in atomic context, so they can't +- * take the key semaphore and thus 'secret' can change concurrently +- * which would be a data race. But they only need to know whether the ++ * The READ_ONCE() is only necessary for fscrypt_drop_inode(). ++ * fscrypt_drop_inode() runs in atomic context, so it can't take the key ++ * semaphore and thus 'secret' can change concurrently which would be a ++ * data race. But fscrypt_drop_inode() only need to know whether the + * secret *was* present at the time of check, so READ_ONCE() suffices. + */ + return READ_ONCE(secret->size) != 0; +@@ -533,7 +560,11 @@ static inline int master_key_spec_len(const struct fscrypt_key_specifier *spec) + return 0; + } + +-struct key * ++void fscrypt_put_master_key(struct fscrypt_master_key *mk); ++ ++void fscrypt_put_master_key_activeref(struct fscrypt_master_key *mk); ++ ++struct fscrypt_master_key * + fscrypt_find_master_key(struct super_block *sb, + const struct fscrypt_key_specifier *mk_spec); + +diff --git a/fs/crypto/hooks.c b/fs/crypto/hooks.c +index 0c6fa5c2d6f3..8268206ef21e 100644 +--- a/fs/crypto/hooks.c ++++ b/fs/crypto/hooks.c +@@ -5,8 +5,6 @@ + * Encryption hooks for higher-level filesystem operations. + */ + +-#include +- + #include "fscrypt_private.h" + + /** +@@ -139,7 +137,6 @@ int fscrypt_prepare_setflags(struct inode *inode, + unsigned int oldflags, unsigned int flags) + { + struct fscrypt_info *ci; +- struct key *key; + struct fscrypt_master_key *mk; + int err; + +@@ -155,14 +152,13 @@ int fscrypt_prepare_setflags(struct inode *inode, + ci = inode->i_crypt_info; + if (ci->ci_policy.version != FSCRYPT_POLICY_V2) + return -EINVAL; +- key = ci->ci_master_key; +- mk = key->payload.data[0]; +- down_read(&key->sem); ++ mk = ci->ci_master_key; ++ down_read(&mk->mk_sem); + if (is_master_key_secret_present(&mk->mk_secret)) + err = fscrypt_derive_dirhash_key(ci, mk); + else + err = -ENOKEY; +- up_read(&key->sem); ++ up_read(&mk->mk_sem); + return err; + } + return 0; +diff --git a/fs/crypto/keyring.c b/fs/crypto/keyring.c +index 0b3ffbb4faf4..175b071beaf8 100644 +--- a/fs/crypto/keyring.c ++++ b/fs/crypto/keyring.c +@@ -18,6 +18,7 @@ + * information about these ioctls. + */ + ++#include + #include + #include + #include +@@ -25,6 +26,18 @@ + + #include "fscrypt_private.h" + ++/* The master encryption keys for a filesystem (->s_master_keys) */ ++struct fscrypt_keyring { ++ /* ++ * Lock that protects ->key_hashtable. It does *not* protect the ++ * fscrypt_master_key structs themselves. ++ */ ++ spinlock_t lock; ++ ++ /* Hash table that maps fscrypt_key_specifier to fscrypt_master_key */ ++ struct hlist_head key_hashtable[128]; ++}; ++ + static void wipe_master_key_secret(struct fscrypt_master_key_secret *secret) + { + fscrypt_destroy_hkdf(&secret->hkdf); +@@ -38,20 +51,70 @@ static void move_master_key_secret(struct fscrypt_master_key_secret *dst, + memzero_explicit(src, sizeof(*src)); + } + +-static void free_master_key(struct fscrypt_master_key *mk) ++static void fscrypt_free_master_key(struct rcu_head *head) ++{ ++ struct fscrypt_master_key *mk = ++ container_of(head, struct fscrypt_master_key, mk_rcu_head); ++ /* ++ * The master key secret and any embedded subkeys should have already ++ * been wiped when the last active reference to the fscrypt_master_key ++ * struct was dropped; doing it here would be unnecessarily late. ++ * Nevertheless, use kfree_sensitive() in case anything was missed. ++ */ ++ kfree_sensitive(mk); ++} ++ ++void fscrypt_put_master_key(struct fscrypt_master_key *mk) ++{ ++ if (!refcount_dec_and_test(&mk->mk_struct_refs)) ++ return; ++ /* ++ * No structural references left, so free ->mk_users, and also free the ++ * fscrypt_master_key struct itself after an RCU grace period ensures ++ * that concurrent keyring lookups can no longer find it. ++ */ ++ WARN_ON(refcount_read(&mk->mk_active_refs) != 0); ++ key_put(mk->mk_users); ++ mk->mk_users = NULL; ++ call_rcu(&mk->mk_rcu_head, fscrypt_free_master_key); ++} ++ ++void fscrypt_put_master_key_activeref(struct fscrypt_master_key *mk) + { ++ struct super_block *sb = mk->mk_sb; ++ struct fscrypt_keyring *keyring = sb->s_master_keys; + size_t i; + +- wipe_master_key_secret(&mk->mk_secret); ++ if (!refcount_dec_and_test(&mk->mk_active_refs)) ++ return; ++ /* ++ * No active references left, so complete the full removal of this ++ * fscrypt_master_key struct by removing it from the keyring and ++ * destroying any subkeys embedded in it. ++ */ ++ ++ spin_lock(&keyring->lock); ++ hlist_del_rcu(&mk->mk_node); ++ spin_unlock(&keyring->lock); ++ ++ /* ++ * ->mk_active_refs == 0 implies that ->mk_secret is not present and ++ * that ->mk_decrypted_inodes is empty. ++ */ ++ WARN_ON(is_master_key_secret_present(&mk->mk_secret)); ++ WARN_ON(!list_empty(&mk->mk_decrypted_inodes)); + + for (i = 0; i <= FSCRYPT_MODE_MAX; i++) { + fscrypt_destroy_prepared_key(&mk->mk_direct_keys[i]); + fscrypt_destroy_prepared_key(&mk->mk_iv_ino_lblk_64_keys[i]); + fscrypt_destroy_prepared_key(&mk->mk_iv_ino_lblk_32_keys[i]); + } ++ memzero_explicit(&mk->mk_ino_hash_key, ++ sizeof(mk->mk_ino_hash_key)); ++ mk->mk_ino_hash_key_initialized = false; + +- key_put(mk->mk_users); +- kfree_sensitive(mk); ++ /* Drop the structural ref associated with the active refs. */ ++ fscrypt_put_master_key(mk); + } + + static inline bool valid_key_spec(const struct fscrypt_key_specifier *spec) +@@ -61,44 +124,6 @@ static inline bool valid_key_spec(const struct fscrypt_key_specifier *spec) + return master_key_spec_len(spec) != 0; + } + +-static int fscrypt_key_instantiate(struct key *key, +- struct key_preparsed_payload *prep) +-{ +- key->payload.data[0] = (struct fscrypt_master_key *)prep->data; +- return 0; +-} +- +-static void fscrypt_key_destroy(struct key *key) +-{ +- free_master_key(key->payload.data[0]); +-} +- +-static void fscrypt_key_describe(const struct key *key, struct seq_file *m) +-{ +- seq_puts(m, key->description); +- +- if (key_is_positive(key)) { +- const struct fscrypt_master_key *mk = key->payload.data[0]; +- +- if (!is_master_key_secret_present(&mk->mk_secret)) +- seq_puts(m, ": secret removed"); +- } +-} +- +-/* +- * Type of key in ->s_master_keys. Each key of this type represents a master +- * key which has been added to the filesystem. Its payload is a +- * 'struct fscrypt_master_key'. The "." prefix in the key type name prevents +- * users from adding keys of this type via the keyrings syscalls rather than via +- * the intended method of FS_IOC_ADD_ENCRYPTION_KEY. +- */ +-static struct key_type key_type_fscrypt = { +- .name = "._fscrypt", +- .instantiate = fscrypt_key_instantiate, +- .destroy = fscrypt_key_destroy, +- .describe = fscrypt_key_describe, +-}; +- + static int fscrypt_user_key_instantiate(struct key *key, + struct key_preparsed_payload *prep) + { +@@ -131,32 +156,6 @@ static struct key_type key_type_fscrypt_user = { + .describe = fscrypt_user_key_describe, + }; + +-/* Search ->s_master_keys or ->mk_users */ +-static struct key *search_fscrypt_keyring(struct key *keyring, +- struct key_type *type, +- const char *description) +-{ +- /* +- * We need to mark the keyring reference as "possessed" so that we +- * acquire permission to search it, via the KEY_POS_SEARCH permission. +- */ +- key_ref_t keyref = make_key_ref(keyring, true /* possessed */); +- +- keyref = keyring_search(keyref, type, description, false); +- if (IS_ERR(keyref)) { +- if (PTR_ERR(keyref) == -EAGAIN || /* not found */ +- PTR_ERR(keyref) == -EKEYREVOKED) /* recently invalidated */ +- keyref = ERR_PTR(-ENOKEY); +- return ERR_CAST(keyref); +- } +- return key_ref_to_ptr(keyref); +-} +- +-#define FSCRYPT_FS_KEYRING_DESCRIPTION_SIZE \ +- (CONST_STRLEN("fscrypt-") + sizeof_field(struct super_block, s_id)) +- +-#define FSCRYPT_MK_DESCRIPTION_SIZE (2 * FSCRYPT_KEY_IDENTIFIER_SIZE + 1) +- + #define FSCRYPT_MK_USERS_DESCRIPTION_SIZE \ + (CONST_STRLEN("fscrypt-") + 2 * FSCRYPT_KEY_IDENTIFIER_SIZE + \ + CONST_STRLEN("-users") + 1) +@@ -164,21 +163,6 @@ static struct key *search_fscrypt_keyring(struct key *keyring, + #define FSCRYPT_MK_USER_DESCRIPTION_SIZE \ + (2 * FSCRYPT_KEY_IDENTIFIER_SIZE + CONST_STRLEN(".uid.") + 10 + 1) + +-static void format_fs_keyring_description( +- char description[FSCRYPT_FS_KEYRING_DESCRIPTION_SIZE], +- const struct super_block *sb) +-{ +- sprintf(description, "fscrypt-%s", sb->s_id); +-} +- +-static void format_mk_description( +- char description[FSCRYPT_MK_DESCRIPTION_SIZE], +- const struct fscrypt_key_specifier *mk_spec) +-{ +- sprintf(description, "%*phN", +- master_key_spec_len(mk_spec), (u8 *)&mk_spec->u); +-} +- + static void format_mk_users_keyring_description( + char description[FSCRYPT_MK_USERS_DESCRIPTION_SIZE], + const u8 mk_identifier[FSCRYPT_KEY_IDENTIFIER_SIZE]) +@@ -199,20 +183,15 @@ static void format_mk_user_description( + /* Create ->s_master_keys if needed. Synchronized by fscrypt_add_key_mutex. */ + static int allocate_filesystem_keyring(struct super_block *sb) + { +- char description[FSCRYPT_FS_KEYRING_DESCRIPTION_SIZE]; +- struct key *keyring; ++ struct fscrypt_keyring *keyring; + + if (sb->s_master_keys) + return 0; + +- format_fs_keyring_description(description, sb); +- keyring = keyring_alloc(description, GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, +- current_cred(), KEY_POS_SEARCH | +- KEY_USR_SEARCH | KEY_USR_READ | KEY_USR_VIEW, +- KEY_ALLOC_NOT_IN_QUOTA, NULL, NULL); +- if (IS_ERR(keyring)) +- return PTR_ERR(keyring); +- ++ keyring = kzalloc(sizeof(*keyring), GFP_KERNEL); ++ if (!keyring) ++ return -ENOMEM; ++ spin_lock_init(&keyring->lock); + /* + * Pairs with the smp_load_acquire() in fscrypt_find_master_key(). + * I.e., here we publish ->s_master_keys with a RELEASE barrier so that +@@ -222,21 +201,75 @@ static int allocate_filesystem_keyring(struct super_block *sb) + return 0; + } + +-void fscrypt_sb_free(struct super_block *sb) ++/* ++ * This is called at unmount time to release all encryption keys that have been ++ * added to the filesystem, along with the keyring that contains them. ++ * ++ * Note that besides clearing and freeing memory, this might need to evict keys ++ * from the keyslots of an inline crypto engine. Therefore, this must be called ++ * while the filesystem's underlying block device(s) are still available. ++ */ ++void fscrypt_sb_delete(struct super_block *sb) + { +- key_put(sb->s_master_keys); ++ struct fscrypt_keyring *keyring = sb->s_master_keys; ++ size_t i; ++ ++ if (!keyring) ++ return; ++ ++ for (i = 0; i < ARRAY_SIZE(keyring->key_hashtable); i++) { ++ struct hlist_head *bucket = &keyring->key_hashtable[i]; ++ struct fscrypt_master_key *mk; ++ struct hlist_node *tmp; ++ ++ hlist_for_each_entry_safe(mk, tmp, bucket, mk_node) { ++ /* ++ * Since all inodes were already evicted, every key ++ * remaining in the keyring should have an empty inode ++ * list, and should only still be in the keyring due to ++ * the single active ref associated with ->mk_secret. ++ * There should be no structural refs beyond the one ++ * associated with the active ref. ++ */ ++ WARN_ON(refcount_read(&mk->mk_active_refs) != 1); ++ WARN_ON(refcount_read(&mk->mk_struct_refs) != 1); ++ WARN_ON(!is_master_key_secret_present(&mk->mk_secret)); ++ wipe_master_key_secret(&mk->mk_secret); ++ fscrypt_put_master_key_activeref(mk); ++ } ++ } ++ kfree_sensitive(keyring); + sb->s_master_keys = NULL; + } + ++static struct hlist_head * ++fscrypt_mk_hash_bucket(struct fscrypt_keyring *keyring, ++ const struct fscrypt_key_specifier *mk_spec) ++{ ++ /* ++ * Since key specifiers should be "random" values, it is sufficient to ++ * use a trivial hash function that just takes the first several bits of ++ * the key specifier. ++ */ ++ unsigned long i = get_unaligned((unsigned long *)&mk_spec->u); ++ ++ return &keyring->key_hashtable[i % ARRAY_SIZE(keyring->key_hashtable)]; ++} ++ + /* +- * Find the specified master key in ->s_master_keys. +- * Returns ERR_PTR(-ENOKEY) if not found. ++ * Find the specified master key struct in ->s_master_keys and take a structural ++ * ref to it. The structural ref guarantees that the key struct continues to ++ * exist, but it does *not* guarantee that ->s_master_keys continues to contain ++ * the key struct. The structural ref needs to be dropped by ++ * fscrypt_put_master_key(). Returns NULL if the key struct is not found. + */ +-struct key *fscrypt_find_master_key(struct super_block *sb, +- const struct fscrypt_key_specifier *mk_spec) ++struct fscrypt_master_key * ++fscrypt_find_master_key(struct super_block *sb, ++ const struct fscrypt_key_specifier *mk_spec) + { +- struct key *keyring; +- char description[FSCRYPT_MK_DESCRIPTION_SIZE]; ++ struct fscrypt_keyring *keyring; ++ struct hlist_head *bucket; ++ struct fscrypt_master_key *mk; + + /* + * Pairs with the smp_store_release() in allocate_filesystem_keyring(). +@@ -246,10 +279,38 @@ struct key *fscrypt_find_master_key(struct super_block *sb, + */ + keyring = smp_load_acquire(&sb->s_master_keys); + if (keyring == NULL) +- return ERR_PTR(-ENOKEY); /* No keyring yet, so no keys yet. */ +- +- format_mk_description(description, mk_spec); +- return search_fscrypt_keyring(keyring, &key_type_fscrypt, description); ++ return NULL; /* No keyring yet, so no keys yet. */ ++ ++ bucket = fscrypt_mk_hash_bucket(keyring, mk_spec); ++ rcu_read_lock(); ++ switch (mk_spec->type) { ++ case FSCRYPT_KEY_SPEC_TYPE_DESCRIPTOR: ++ hlist_for_each_entry_rcu(mk, bucket, mk_node) { ++ if (mk->mk_spec.type == ++ FSCRYPT_KEY_SPEC_TYPE_DESCRIPTOR && ++ memcmp(mk->mk_spec.u.descriptor, ++ mk_spec->u.descriptor, ++ FSCRYPT_KEY_DESCRIPTOR_SIZE) == 0 && ++ refcount_inc_not_zero(&mk->mk_struct_refs)) ++ goto out; ++ } ++ break; ++ case FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER: ++ hlist_for_each_entry_rcu(mk, bucket, mk_node) { ++ if (mk->mk_spec.type == ++ FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER && ++ memcmp(mk->mk_spec.u.identifier, ++ mk_spec->u.identifier, ++ FSCRYPT_KEY_IDENTIFIER_SIZE) == 0 && ++ refcount_inc_not_zero(&mk->mk_struct_refs)) ++ goto out; ++ } ++ break; ++ } ++ mk = NULL; ++out: ++ rcu_read_unlock(); ++ return mk; + } + + static int allocate_master_key_users_keyring(struct fscrypt_master_key *mk) +@@ -277,17 +338,30 @@ static int allocate_master_key_users_keyring(struct fscrypt_master_key *mk) + static struct key *find_master_key_user(struct fscrypt_master_key *mk) + { + char description[FSCRYPT_MK_USER_DESCRIPTION_SIZE]; ++ key_ref_t keyref; + + format_mk_user_description(description, mk->mk_spec.u.identifier); +- return search_fscrypt_keyring(mk->mk_users, &key_type_fscrypt_user, +- description); ++ ++ /* ++ * We need to mark the keyring reference as "possessed" so that we ++ * acquire permission to search it, via the KEY_POS_SEARCH permission. ++ */ ++ keyref = keyring_search(make_key_ref(mk->mk_users, true /*possessed*/), ++ &key_type_fscrypt_user, description, false); ++ if (IS_ERR(keyref)) { ++ if (PTR_ERR(keyref) == -EAGAIN || /* not found */ ++ PTR_ERR(keyref) == -EKEYREVOKED) /* recently invalidated */ ++ keyref = ERR_PTR(-ENOKEY); ++ return ERR_CAST(keyref); ++ } ++ return key_ref_to_ptr(keyref); + } + + /* + * Give the current user a "key" in ->mk_users. This charges the user's quota + * and marks the master key as added by the current user, so that it cannot be +- * removed by another user with the key. Either the master key's key->sem must +- * be held for write, or the master key must be still undergoing initialization. ++ * removed by another user with the key. Either ->mk_sem must be held for ++ * write, or the master key must be still undergoing initialization. + */ + static int add_master_key_user(struct fscrypt_master_key *mk) + { +@@ -309,7 +383,7 @@ static int add_master_key_user(struct fscrypt_master_key *mk) + + /* + * Remove the current user's "key" from ->mk_users. +- * The master key's key->sem must be held for write. ++ * ->mk_sem must be held for write. + * + * Returns 0 if removed, -ENOKEY if not found, or another -errno code. + */ +@@ -327,63 +401,49 @@ static int remove_master_key_user(struct fscrypt_master_key *mk) + } + + /* +- * Allocate a new fscrypt_master_key which contains the given secret, set it as +- * the payload of a new 'struct key' of type fscrypt, and link the 'struct key' +- * into the given keyring. Synchronized by fscrypt_add_key_mutex. ++ * Allocate a new fscrypt_master_key, transfer the given secret over to it, and ++ * insert it into sb->s_master_keys. + */ +-static int add_new_master_key(struct fscrypt_master_key_secret *secret, +- const struct fscrypt_key_specifier *mk_spec, +- struct key *keyring) ++static int add_new_master_key(struct super_block *sb, ++ struct fscrypt_master_key_secret *secret, ++ const struct fscrypt_key_specifier *mk_spec) + { ++ struct fscrypt_keyring *keyring = sb->s_master_keys; + struct fscrypt_master_key *mk; +- char description[FSCRYPT_MK_DESCRIPTION_SIZE]; +- struct key *key; + int err; + + mk = kzalloc(sizeof(*mk), GFP_KERNEL); + if (!mk) + return -ENOMEM; + ++ mk->mk_sb = sb; ++ init_rwsem(&mk->mk_sem); ++ refcount_set(&mk->mk_struct_refs, 1); + mk->mk_spec = *mk_spec; + +- move_master_key_secret(&mk->mk_secret, secret); +- +- refcount_set(&mk->mk_refcount, 1); /* secret is present */ + INIT_LIST_HEAD(&mk->mk_decrypted_inodes); + spin_lock_init(&mk->mk_decrypted_inodes_lock); + + if (mk_spec->type == FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER) { + err = allocate_master_key_users_keyring(mk); + if (err) +- goto out_free_mk; ++ goto out_put; + err = add_master_key_user(mk); + if (err) +- goto out_free_mk; ++ goto out_put; + } + +- /* +- * Note that we don't charge this key to anyone's quota, since when +- * ->mk_users is in use those keys are charged instead, and otherwise +- * (when ->mk_users isn't in use) only root can add these keys. +- */ +- format_mk_description(description, mk_spec); +- key = key_alloc(&key_type_fscrypt, description, +- GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, current_cred(), +- KEY_POS_SEARCH | KEY_USR_SEARCH | KEY_USR_VIEW, +- KEY_ALLOC_NOT_IN_QUOTA, NULL); +- if (IS_ERR(key)) { +- err = PTR_ERR(key); +- goto out_free_mk; +- } +- err = key_instantiate_and_link(key, mk, sizeof(*mk), keyring, NULL); +- key_put(key); +- if (err) +- goto out_free_mk; ++ move_master_key_secret(&mk->mk_secret, secret); ++ refcount_set(&mk->mk_active_refs, 1); /* ->mk_secret is present */ + ++ spin_lock(&keyring->lock); ++ hlist_add_head_rcu(&mk->mk_node, ++ fscrypt_mk_hash_bucket(keyring, mk_spec)); ++ spin_unlock(&keyring->lock); + return 0; + +-out_free_mk: +- free_master_key(mk); ++out_put: ++ fscrypt_put_master_key(mk); + return err; + } + +@@ -392,42 +452,34 @@ static int add_new_master_key(struct fscrypt_master_key_secret *secret, + static int add_existing_master_key(struct fscrypt_master_key *mk, + struct fscrypt_master_key_secret *secret) + { +- struct key *mk_user; +- bool rekey; + int err; + + /* + * If the current user is already in ->mk_users, then there's nothing to +- * do. (Not applicable for v1 policy keys, which have NULL ->mk_users.) ++ * do. Otherwise, we need to add the user to ->mk_users. (Neither is ++ * applicable for v1 policy keys, which have NULL ->mk_users.) + */ + if (mk->mk_users) { +- mk_user = find_master_key_user(mk); ++ struct key *mk_user = find_master_key_user(mk); ++ + if (mk_user != ERR_PTR(-ENOKEY)) { + if (IS_ERR(mk_user)) + return PTR_ERR(mk_user); + key_put(mk_user); + return 0; + } +- } +- +- /* If we'll be re-adding ->mk_secret, try to take the reference. */ +- rekey = !is_master_key_secret_present(&mk->mk_secret); +- if (rekey && !refcount_inc_not_zero(&mk->mk_refcount)) +- return KEY_DEAD; +- +- /* Add the current user to ->mk_users, if applicable. */ +- if (mk->mk_users) { + err = add_master_key_user(mk); +- if (err) { +- if (rekey && refcount_dec_and_test(&mk->mk_refcount)) +- return KEY_DEAD; ++ if (err) + return err; +- } + } + + /* Re-add the secret if needed. */ +- if (rekey) ++ if (!is_master_key_secret_present(&mk->mk_secret)) { ++ if (!refcount_inc_not_zero(&mk->mk_active_refs)) ++ return KEY_DEAD; + move_master_key_secret(&mk->mk_secret, secret); ++ } ++ + return 0; + } + +@@ -436,38 +488,36 @@ static int do_add_master_key(struct super_block *sb, + const struct fscrypt_key_specifier *mk_spec) + { + static DEFINE_MUTEX(fscrypt_add_key_mutex); +- struct key *key; ++ struct fscrypt_master_key *mk; + int err; + + mutex_lock(&fscrypt_add_key_mutex); /* serialize find + link */ +-retry: +- key = fscrypt_find_master_key(sb, mk_spec); +- if (IS_ERR(key)) { +- err = PTR_ERR(key); +- if (err != -ENOKEY) +- goto out_unlock; ++ ++ mk = fscrypt_find_master_key(sb, mk_spec); ++ if (!mk) { + /* Didn't find the key in ->s_master_keys. Add it. */ + err = allocate_filesystem_keyring(sb); +- if (err) +- goto out_unlock; +- err = add_new_master_key(secret, mk_spec, sb->s_master_keys); ++ if (!err) ++ err = add_new_master_key(sb, secret, mk_spec); + } else { + /* + * Found the key in ->s_master_keys. Re-add the secret if + * needed, and add the user to ->mk_users if needed. + */ +- down_write(&key->sem); +- err = add_existing_master_key(key->payload.data[0], secret); +- up_write(&key->sem); ++ down_write(&mk->mk_sem); ++ err = add_existing_master_key(mk, secret); ++ up_write(&mk->mk_sem); + if (err == KEY_DEAD) { +- /* Key being removed or needs to be removed */ +- key_invalidate(key); +- key_put(key); +- goto retry; ++ /* ++ * We found a key struct, but it's already been fully ++ * removed. Ignore the old struct and add a new one. ++ * fscrypt_add_key_mutex means we don't need to worry ++ * about concurrent adds. ++ */ ++ err = add_new_master_key(sb, secret, mk_spec); + } +- key_put(key); ++ fscrypt_put_master_key(mk); + } +-out_unlock: + mutex_unlock(&fscrypt_add_key_mutex); + return err; + } +@@ -731,19 +781,19 @@ int fscrypt_verify_key_added(struct super_block *sb, + const u8 identifier[FSCRYPT_KEY_IDENTIFIER_SIZE]) + { + struct fscrypt_key_specifier mk_spec; +- struct key *key, *mk_user; + struct fscrypt_master_key *mk; ++ struct key *mk_user; + int err; + + mk_spec.type = FSCRYPT_KEY_SPEC_TYPE_IDENTIFIER; + memcpy(mk_spec.u.identifier, identifier, FSCRYPT_KEY_IDENTIFIER_SIZE); + +- key = fscrypt_find_master_key(sb, &mk_spec); +- if (IS_ERR(key)) { +- err = PTR_ERR(key); ++ mk = fscrypt_find_master_key(sb, &mk_spec); ++ if (!mk) { ++ err = -ENOKEY; + goto out; + } +- mk = key->payload.data[0]; ++ down_read(&mk->mk_sem); + mk_user = find_master_key_user(mk); + if (IS_ERR(mk_user)) { + err = PTR_ERR(mk_user); +@@ -751,7 +801,8 @@ int fscrypt_verify_key_added(struct super_block *sb, + key_put(mk_user); + err = 0; + } +- key_put(key); ++ up_read(&mk->mk_sem); ++ fscrypt_put_master_key(mk); + out: + if (err == -ENOKEY && capable(CAP_FOWNER)) + err = 0; +@@ -913,11 +964,10 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users) + struct super_block *sb = file_inode(filp)->i_sb; + struct fscrypt_remove_key_arg __user *uarg = _uarg; + struct fscrypt_remove_key_arg arg; +- struct key *key; + struct fscrypt_master_key *mk; + u32 status_flags = 0; + int err; +- bool dead; ++ bool inodes_remain; + + if (copy_from_user(&arg, uarg, sizeof(arg))) + return -EFAULT; +@@ -937,12 +987,10 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users) + return -EACCES; + + /* Find the key being removed. */ +- key = fscrypt_find_master_key(sb, &arg.key_spec); +- if (IS_ERR(key)) +- return PTR_ERR(key); +- mk = key->payload.data[0]; +- +- down_write(&key->sem); ++ mk = fscrypt_find_master_key(sb, &arg.key_spec); ++ if (!mk) ++ return -ENOKEY; ++ down_write(&mk->mk_sem); + + /* If relevant, remove current user's (or all users) claim to the key */ + if (mk->mk_users && mk->mk_users->keys.nr_leaves_on_tree != 0) { +@@ -951,7 +999,7 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users) + else + err = remove_master_key_user(mk); + if (err) { +- up_write(&key->sem); ++ up_write(&mk->mk_sem); + goto out_put_key; + } + if (mk->mk_users->keys.nr_leaves_on_tree != 0) { +@@ -963,26 +1011,22 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users) + status_flags |= + FSCRYPT_KEY_REMOVAL_STATUS_FLAG_OTHER_USERS; + err = 0; +- up_write(&key->sem); ++ up_write(&mk->mk_sem); + goto out_put_key; + } + } + + /* No user claims remaining. Go ahead and wipe the secret. */ +- dead = false; ++ err = -ENOKEY; + if (is_master_key_secret_present(&mk->mk_secret)) { + wipe_master_key_secret(&mk->mk_secret); +- dead = refcount_dec_and_test(&mk->mk_refcount); +- } +- up_write(&key->sem); +- if (dead) { +- /* +- * No inodes reference the key, and we wiped the secret, so the +- * key object is free to be removed from the keyring. +- */ +- key_invalidate(key); ++ fscrypt_put_master_key_activeref(mk); + err = 0; +- } else { ++ } ++ inodes_remain = refcount_read(&mk->mk_active_refs) > 0; ++ up_write(&mk->mk_sem); ++ ++ if (inodes_remain) { + /* Some inodes still reference this key; try to evict them. */ + err = try_to_lock_encrypted_files(sb, mk); + if (err == -EBUSY) { +@@ -998,7 +1042,7 @@ static int do_remove_key(struct file *filp, void __user *_uarg, bool all_users) + * has been fully removed including all files locked. + */ + out_put_key: +- key_put(key); ++ fscrypt_put_master_key(mk); + if (err == 0) + err = put_user(status_flags, &uarg->removal_status_flags); + return err; +@@ -1045,7 +1089,6 @@ int fscrypt_ioctl_get_key_status(struct file *filp, void __user *uarg) + { + struct super_block *sb = file_inode(filp)->i_sb; + struct fscrypt_get_key_status_arg arg; +- struct key *key; + struct fscrypt_master_key *mk; + int err; + +@@ -1062,19 +1105,18 @@ int fscrypt_ioctl_get_key_status(struct file *filp, void __user *uarg) + arg.user_count = 0; + memset(arg.__out_reserved, 0, sizeof(arg.__out_reserved)); + +- key = fscrypt_find_master_key(sb, &arg.key_spec); +- if (IS_ERR(key)) { +- if (key != ERR_PTR(-ENOKEY)) +- return PTR_ERR(key); ++ mk = fscrypt_find_master_key(sb, &arg.key_spec); ++ if (!mk) { + arg.status = FSCRYPT_KEY_STATUS_ABSENT; + err = 0; + goto out; + } +- mk = key->payload.data[0]; +- down_read(&key->sem); ++ down_read(&mk->mk_sem); + + if (!is_master_key_secret_present(&mk->mk_secret)) { +- arg.status = FSCRYPT_KEY_STATUS_INCOMPLETELY_REMOVED; ++ arg.status = refcount_read(&mk->mk_active_refs) > 0 ? ++ FSCRYPT_KEY_STATUS_INCOMPLETELY_REMOVED : ++ FSCRYPT_KEY_STATUS_ABSENT /* raced with full removal */; + err = 0; + goto out_release_key; + } +@@ -1096,8 +1138,8 @@ int fscrypt_ioctl_get_key_status(struct file *filp, void __user *uarg) + } + err = 0; + out_release_key: +- up_read(&key->sem); +- key_put(key); ++ up_read(&mk->mk_sem); ++ fscrypt_put_master_key(mk); + out: + if (!err && copy_to_user(uarg, &arg, sizeof(arg))) + err = -EFAULT; +@@ -1109,13 +1151,9 @@ int __init fscrypt_init_keyring(void) + { + int err; + +- err = register_key_type(&key_type_fscrypt); +- if (err) +- return err; +- + err = register_key_type(&key_type_fscrypt_user); + if (err) +- goto err_unregister_fscrypt; ++ return err; + + err = register_key_type(&key_type_fscrypt_provisioning); + if (err) +@@ -1125,7 +1163,5 @@ int __init fscrypt_init_keyring(void) + + err_unregister_fscrypt_user: + unregister_key_type(&key_type_fscrypt_user); +-err_unregister_fscrypt: +- unregister_key_type(&key_type_fscrypt); + return err; + } +diff --git a/fs/crypto/keysetup.c b/fs/crypto/keysetup.c +index 72aec33e0ea5..7b14054fab49 100644 +--- a/fs/crypto/keysetup.c ++++ b/fs/crypto/keysetup.c +@@ -9,7 +9,6 @@ + */ + + #include +-#include + #include + + #include "fscrypt_private.h" +@@ -151,6 +150,7 @@ void fscrypt_destroy_prepared_key(struct fscrypt_prepared_key *prep_key) + { + crypto_free_skcipher(prep_key->tfm); + fscrypt_destroy_inline_crypt_key(prep_key); ++ memzero_explicit(prep_key, sizeof(*prep_key)); + } + + /* Given a per-file encryption key, set up the file's crypto transform object */ +@@ -404,20 +404,18 @@ static bool fscrypt_valid_master_key_size(const struct fscrypt_master_key *mk, + /* + * Find the master key, then set up the inode's actual encryption key. + * +- * If the master key is found in the filesystem-level keyring, then the +- * corresponding 'struct key' is returned in *master_key_ret with its semaphore +- * read-locked. This is needed to ensure that only one task links the +- * fscrypt_info into ->mk_decrypted_inodes (as multiple tasks may race to create +- * an fscrypt_info for the same inode), and to synchronize the master key being +- * removed with a new inode starting to use it. ++ * If the master key is found in the filesystem-level keyring, then it is ++ * returned in *mk_ret with its semaphore read-locked. This is needed to ensure ++ * that only one task links the fscrypt_info into ->mk_decrypted_inodes (as ++ * multiple tasks may race to create an fscrypt_info for the same inode), and to ++ * synchronize the master key being removed with a new inode starting to use it. + */ + static int setup_file_encryption_key(struct fscrypt_info *ci, + bool need_dirhash_key, +- struct key **master_key_ret) ++ struct fscrypt_master_key **mk_ret) + { +- struct key *key; +- struct fscrypt_master_key *mk = NULL; + struct fscrypt_key_specifier mk_spec; ++ struct fscrypt_master_key *mk; + int err; + + err = fscrypt_select_encryption_impl(ci); +@@ -442,11 +440,10 @@ static int setup_file_encryption_key(struct fscrypt_info *ci, + return -EINVAL; + } + +- key = fscrypt_find_master_key(ci->ci_inode->i_sb, &mk_spec); +- if (IS_ERR(key)) { +- if (key != ERR_PTR(-ENOKEY) || +- ci->ci_policy.version != FSCRYPT_POLICY_V1) +- return PTR_ERR(key); ++ mk = fscrypt_find_master_key(ci->ci_inode->i_sb, &mk_spec); ++ if (!mk) { ++ if (ci->ci_policy.version != FSCRYPT_POLICY_V1) ++ return -ENOKEY; + + /* + * As a legacy fallback for v1 policies, search for the key in +@@ -456,9 +453,7 @@ static int setup_file_encryption_key(struct fscrypt_info *ci, + */ + return fscrypt_setup_v1_file_key_via_subscribed_keyrings(ci); + } +- +- mk = key->payload.data[0]; +- down_read(&key->sem); ++ down_read(&mk->mk_sem); + + /* Has the secret been removed (via FS_IOC_REMOVE_ENCRYPTION_KEY)? */ + if (!is_master_key_secret_present(&mk->mk_secret)) { +@@ -486,18 +481,18 @@ static int setup_file_encryption_key(struct fscrypt_info *ci, + if (err) + goto out_release_key; + +- *master_key_ret = key; ++ *mk_ret = mk; + return 0; + + out_release_key: +- up_read(&key->sem); +- key_put(key); ++ up_read(&mk->mk_sem); ++ fscrypt_put_master_key(mk); + return err; + } + + static void put_crypt_info(struct fscrypt_info *ci) + { +- struct key *key; ++ struct fscrypt_master_key *mk; + + if (!ci) + return; +@@ -507,24 +502,18 @@ static void put_crypt_info(struct fscrypt_info *ci) + else if (ci->ci_owns_key) + fscrypt_destroy_prepared_key(&ci->ci_enc_key); + +- key = ci->ci_master_key; +- if (key) { +- struct fscrypt_master_key *mk = key->payload.data[0]; +- ++ mk = ci->ci_master_key; ++ if (mk) { + /* + * Remove this inode from the list of inodes that were unlocked +- * with the master key. +- * +- * In addition, if we're removing the last inode from a key that +- * already had its secret removed, invalidate the key so that it +- * gets removed from ->s_master_keys. ++ * with the master key. In addition, if we're removing the last ++ * inode from a master key struct that already had its secret ++ * removed, then complete the full removal of the struct. + */ + spin_lock(&mk->mk_decrypted_inodes_lock); + list_del(&ci->ci_master_key_link); + spin_unlock(&mk->mk_decrypted_inodes_lock); +- if (refcount_dec_and_test(&mk->mk_refcount)) +- key_invalidate(key); +- key_put(key); ++ fscrypt_put_master_key_activeref(mk); + } + memzero_explicit(ci, sizeof(*ci)); + kmem_cache_free(fscrypt_info_cachep, ci); +@@ -538,7 +527,7 @@ fscrypt_setup_encryption_info(struct inode *inode, + { + struct fscrypt_info *crypt_info; + struct fscrypt_mode *mode; +- struct key *master_key = NULL; ++ struct fscrypt_master_key *mk = NULL; + int res; + + res = fscrypt_initialize(inode->i_sb->s_cop->flags); +@@ -561,8 +550,7 @@ fscrypt_setup_encryption_info(struct inode *inode, + WARN_ON(mode->ivsize > FSCRYPT_MAX_IV_SIZE); + crypt_info->ci_mode = mode; + +- res = setup_file_encryption_key(crypt_info, need_dirhash_key, +- &master_key); ++ res = setup_file_encryption_key(crypt_info, need_dirhash_key, &mk); + if (res) + goto out; + +@@ -577,12 +565,9 @@ fscrypt_setup_encryption_info(struct inode *inode, + * We won the race and set ->i_crypt_info to our crypt_info. + * Now link it into the master key's inode list. + */ +- if (master_key) { +- struct fscrypt_master_key *mk = +- master_key->payload.data[0]; +- +- refcount_inc(&mk->mk_refcount); +- crypt_info->ci_master_key = key_get(master_key); ++ if (mk) { ++ crypt_info->ci_master_key = mk; ++ refcount_inc(&mk->mk_active_refs); + spin_lock(&mk->mk_decrypted_inodes_lock); + list_add(&crypt_info->ci_master_key_link, + &mk->mk_decrypted_inodes); +@@ -592,9 +577,9 @@ fscrypt_setup_encryption_info(struct inode *inode, + } + res = 0; + out: +- if (master_key) { +- up_read(&master_key->sem); +- key_put(master_key); ++ if (mk) { ++ up_read(&mk->mk_sem); ++ fscrypt_put_master_key(mk); + } + put_crypt_info(crypt_info); + return res; +@@ -745,7 +730,6 @@ EXPORT_SYMBOL(fscrypt_free_inode); + int fscrypt_drop_inode(struct inode *inode) + { + const struct fscrypt_info *ci = fscrypt_get_info(inode); +- const struct fscrypt_master_key *mk; + + /* + * If ci is NULL, then the inode doesn't have an encryption key set up +@@ -755,7 +739,6 @@ int fscrypt_drop_inode(struct inode *inode) + */ + if (!ci || !ci->ci_master_key) + return 0; +- mk = ci->ci_master_key->payload.data[0]; + + /* + * With proper, non-racy use of FS_IOC_REMOVE_ENCRYPTION_KEY, all inodes +@@ -774,6 +757,6 @@ int fscrypt_drop_inode(struct inode *inode) + * then the thread removing the key will either evict the inode itself + * or will correctly detect that it wasn't evicted due to the race. + */ +- return !is_master_key_secret_present(&mk->mk_secret); ++ return !is_master_key_secret_present(&ci->ci_master_key->mk_secret); + } + EXPORT_SYMBOL_GPL(fscrypt_drop_inode); +diff --git a/fs/crypto/policy.c b/fs/crypto/policy.c +index faa0f21daa68..f68265c36377 100644 +--- a/fs/crypto/policy.c ++++ b/fs/crypto/policy.c +@@ -686,12 +686,8 @@ int fscrypt_set_context(struct inode *inode, void *fs_data) + * delayed key setup that requires the inode number. + */ + if (ci->ci_policy.version == FSCRYPT_POLICY_V2 && +- (ci->ci_policy.v2.flags & FSCRYPT_POLICY_FLAG_IV_INO_LBLK_32)) { +- const struct fscrypt_master_key *mk = +- ci->ci_master_key->payload.data[0]; +- +- fscrypt_hash_inode_number(ci, mk); +- } ++ (ci->ci_policy.v2.flags & FSCRYPT_POLICY_FLAG_IV_INO_LBLK_32)) ++ fscrypt_hash_inode_number(ci, ci->ci_master_key); + + return inode->i_sb->s_cop->set_context(inode, &ctx, ctxsize, fs_data); + } +diff --git a/fs/super.c b/fs/super.c +index 705be5d0600e..88ecc2c6dba5 100644 +--- a/fs/super.c ++++ b/fs/super.c +@@ -293,7 +293,6 @@ static void __put_super(struct super_block *s) + WARN_ON(s->s_inode_lru.node); + WARN_ON(!list_empty(&s->s_mounts)); + security_sb_free(s); +- fscrypt_sb_free(s); + put_user_ns(s->s_user_ns); + kfree(s->s_subtype); + call_rcu(&s->rcu, destroy_super_rcu); +@@ -454,6 +453,7 @@ void generic_shutdown_super(struct super_block *sb) + evict_inodes(sb); + /* only nonzero refcount inodes can have marks */ + fsnotify_sb_delete(sb); ++ fscrypt_sb_delete(sb); + security_sb_delete(sb); + + if (sb->s_dio_done_wq) { +diff --git a/include/linux/fs.h b/include/linux/fs.h +index c8f887641878..df54acdd3554 100644 +--- a/include/linux/fs.h ++++ b/include/linux/fs.h +@@ -1437,7 +1437,7 @@ struct super_block { + const struct xattr_handler **s_xattr; + #ifdef CONFIG_FS_ENCRYPTION + const struct fscrypt_operations *s_cop; +- struct key *s_master_keys; /* master crypto keys in use */ ++ struct fscrypt_keyring *s_master_keys; /* master crypto keys in use */ + #endif + #ifdef CONFIG_FS_VERITY + const struct fsverity_operations *s_vop; +diff --git a/include/linux/fscrypt.h b/include/linux/fscrypt.h +index d0a1b8edfd9d..23d3ea47f764 100644 +--- a/include/linux/fscrypt.h ++++ b/include/linux/fscrypt.h +@@ -193,7 +193,7 @@ fscrypt_free_dummy_policy(struct fscrypt_dummy_policy *dummy_policy) + } + + /* keyring.c */ +-void fscrypt_sb_free(struct super_block *sb); ++void fscrypt_sb_delete(struct super_block *sb); + int fscrypt_ioctl_add_key(struct file *filp, void __user *arg); + int fscrypt_ioctl_remove_key(struct file *filp, void __user *arg); + int fscrypt_ioctl_remove_key_all_users(struct file *filp, void __user *arg); +@@ -380,7 +380,7 @@ fscrypt_free_dummy_policy(struct fscrypt_dummy_policy *dummy_policy) + } + + /* keyring.c */ +-static inline void fscrypt_sb_free(struct super_block *sb) ++static inline void fscrypt_sb_delete(struct super_block *sb) + { + } + +-- +2.35.1 + diff --git a/queue-5.10/fsi-core-check-error-number-after-calling-ida_simple.patch b/queue-5.10/fsi-core-check-error-number-after-calling-ida_simple.patch new file mode 100644 index 00000000000..5cb6b8ddb18 --- /dev/null +++ b/queue-5.10/fsi-core-check-error-number-after-calling-ida_simple.patch @@ -0,0 +1,41 @@ +From 5fbd60955b10274bef1e124e25efbe539ebfef42 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 11 Jan 2022 15:34:11 +0800 +Subject: fsi: core: Check error number after calling ida_simple_get + +From: Jiasheng Jiang + +[ Upstream commit 35af9fb49bc5c6d61ef70b501c3a56fe161cce3e ] + +If allocation fails, the ida_simple_get() will return error number. +So master->idx could be error number and be used in dev_set_name(). +Therefore, it should be better to check it and return error if fails, +like the ida_simple_get() in __fsi_get_new_minor(). + +Fixes: 09aecfab93b8 ("drivers/fsi: Add fsi master definition") +Signed-off-by: Jiasheng Jiang +Reviewed-by: Eddie James +Link: https://lore.kernel.org/r/20220111073411.614138-1-jiasheng@iscas.ac.cn +Signed-off-by: Joel Stanley +Signed-off-by: Sasha Levin +--- + drivers/fsi/fsi-core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c +index 59ddc9fd5bca..92e6eebd1851 100644 +--- a/drivers/fsi/fsi-core.c ++++ b/drivers/fsi/fsi-core.c +@@ -1309,6 +1309,9 @@ int fsi_master_register(struct fsi_master *master) + + mutex_init(&master->scan_lock); + master->idx = ida_simple_get(&master_ida, 0, INT_MAX, GFP_KERNEL); ++ if (master->idx < 0) ++ return master->idx; ++ + dev_set_name(&master->dev, "fsi%d", master->idx); + master->dev.class = &fsi_master_class; + +-- +2.35.1 + diff --git a/queue-5.10/fsi-master-ast-cf-fix-missing-of_node_put-in-fsi_mas.patch b/queue-5.10/fsi-master-ast-cf-fix-missing-of_node_put-in-fsi_mas.patch new file mode 100644 index 00000000000..8a90df4dcff --- /dev/null +++ b/queue-5.10/fsi-master-ast-cf-fix-missing-of_node_put-in-fsi_mas.patch @@ -0,0 +1,43 @@ +From 1a02109d512900f94a2b925629c63b5d80af8c93 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Apr 2022 08:59:11 +0000 +Subject: fsi: master-ast-cf: Fix missing of_node_put in fsi_master_acf_probe + +From: Lv Ruyi + +[ Upstream commit 182d98e00e4745fe253cb0c24c63bbac253464a2 ] + +of_parse_phandle returns node pointer with refcount incremented, use +of_node_put() on it when done. + +Reported-by: Zeal Robot +Signed-off-by: Lv Ruyi +Link: https://lore.kernel.org/r/20220407085911.2491719-1-lv.ruyi@zte.com.cn +Signed-off-by: Joel Stanley +Signed-off-by: Sasha Levin +--- + drivers/fsi/fsi-master-ast-cf.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c +index 70c03e304d6c..ae27ea30fe2d 100644 +--- a/drivers/fsi/fsi-master-ast-cf.c ++++ b/drivers/fsi/fsi-master-ast-cf.c +@@ -1325,12 +1325,14 @@ static int fsi_master_acf_probe(struct platform_device *pdev) + } + master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL); + if (IS_ERR(master->cvic)) { ++ of_node_put(np); + rc = PTR_ERR(master->cvic); + dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc); + goto err_free; + } + rc = of_property_read_u32(np, "copro-sw-interrupts", + &master->cvic_sw_irq); ++ of_node_put(np); + if (rc) { + dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n"); + goto err_free; +-- +2.35.1 + diff --git a/queue-5.10/gpu-lontium-lt9611-fix-null-pointer-dereference-in-l.patch b/queue-5.10/gpu-lontium-lt9611-fix-null-pointer-dereference-in-l.patch new file mode 100644 index 00000000000..0077fa9e304 --- /dev/null +++ b/queue-5.10/gpu-lontium-lt9611-fix-null-pointer-dereference-in-l.patch @@ -0,0 +1,48 @@ +From 78376dfd82d268737981090b6f2fb38039032673 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Jul 2022 15:31:19 +0800 +Subject: gpu: lontium-lt9611: Fix NULL pointer dereference in + lt9611_connector_init() + +From: Zeng Jingxiang + +[ Upstream commit ef8886f321c5dab8124b9153d25afa2a71d05323 ] + +A NULL check for bridge->encoder shows that it may be NULL, but it +already been dereferenced on all paths leading to the check. +812 if (!bridge->encoder) { + +Dereference the pointer bridge->encoder. +810 drm_connector_attach_encoder(<9611->connector, bridge->encoder); + +Signed-off-by: Zeng Jingxiang +Signed-off-by: Robert Foss +Link: https://patchwork.freedesktop.org/patch/msgid/20220727073119.1578972-1-zengjx95@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/bridge/lontium-lt9611.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c +index 29b1ce2140ab..1dcc28a4d853 100644 +--- a/drivers/gpu/drm/bridge/lontium-lt9611.c ++++ b/drivers/gpu/drm/bridge/lontium-lt9611.c +@@ -816,13 +816,14 @@ static int lt9611_connector_init(struct drm_bridge *bridge, struct lt9611 *lt961 + + drm_connector_helper_add(<9611->connector, + <9611_bridge_connector_helper_funcs); +- drm_connector_attach_encoder(<9611->connector, bridge->encoder); + + if (!bridge->encoder) { + DRM_ERROR("Parent encoder object not found"); + return -ENODEV; + } + ++ drm_connector_attach_encoder(<9611->connector, bridge->encoder); ++ + return 0; + } + +-- +2.35.1 + diff --git a/queue-5.10/hid-roccat-fix-use-after-free-in-roccat_read.patch b/queue-5.10/hid-roccat-fix-use-after-free-in-roccat_read.patch new file mode 100644 index 00000000000..ce79667fcbc --- /dev/null +++ b/queue-5.10/hid-roccat-fix-use-after-free-in-roccat_read.patch @@ -0,0 +1,108 @@ +From 8edfec3d1726c1980d9ce6482d228b26292d4f3f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Sep 2022 12:31:15 -0700 +Subject: HID: roccat: Fix use-after-free in roccat_read() + +From: Hyunwoo Kim + +[ Upstream commit cacdb14b1c8d3804a3a7d31773bc7569837b71a4 ] + +roccat_report_event() is responsible for registering +roccat-related reports in struct roccat_device. + +int roccat_report_event(int minor, u8 const *data) +{ + struct roccat_device *device; + struct roccat_reader *reader; + struct roccat_report *report; + uint8_t *new_value; + + device = devices[minor]; + + new_value = kmemdup(data, device->report_size, GFP_ATOMIC); + if (!new_value) + return -ENOMEM; + + report = &device->cbuf[device->cbuf_end]; + + /* passing NULL is safe */ + kfree(report->value); + ... + +The registered report is stored in the struct roccat_device member +"struct roccat_report cbuf[ROCCAT_CBUF_SIZE];". +If more reports are received than the "ROCCAT_CBUF_SIZE" value, +kfree() the saved report from cbuf[0] and allocates a new reprot. +Since there is no lock when this kfree() is performed, +kfree() can be performed even while reading the saved report. + +static ssize_t roccat_read(struct file *file, char __user *buffer, + size_t count, loff_t *ppos) +{ + struct roccat_reader *reader = file->private_data; + struct roccat_device *device = reader->device; + struct roccat_report *report; + ssize_t retval = 0, len; + DECLARE_WAITQUEUE(wait, current); + + mutex_lock(&device->cbuf_lock); + + ... + + report = &device->cbuf[reader->cbuf_start]; + /* + * If report is larger than requested amount of data, rest of report + * is lost! + */ + len = device->report_size > count ? count : device->report_size; + + if (copy_to_user(buffer, report->value, len)) { + retval = -EFAULT; + goto exit_unlock; + } + ... + +The roccat_read() function receives the device->cbuf report and +delivers it to the user through copy_to_user(). +If the N+ROCCAT_CBUF_SIZE th report is received while copying of +the Nth report->value is in progress, the pointer that copy_to_user() +is working on is kfree()ed and UAF read may occur. (race condition) + +Since the device node of this driver does not set separate permissions, +this is not a security vulnerability, but because it is used for +requesting screen display of profile or dpi settings, +a user using the roccat device can apply udev to this device node or +There is a possibility to use it by giving. + +Signed-off-by: Hyunwoo Kim +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-roccat.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/hid/hid-roccat.c b/drivers/hid/hid-roccat.c +index 26373b82fe81..6da80e442fdd 100644 +--- a/drivers/hid/hid-roccat.c ++++ b/drivers/hid/hid-roccat.c +@@ -257,6 +257,8 @@ int roccat_report_event(int minor, u8 const *data) + if (!new_value) + return -ENOMEM; + ++ mutex_lock(&device->cbuf_lock); ++ + report = &device->cbuf[device->cbuf_end]; + + /* passing NULL is safe */ +@@ -276,6 +278,8 @@ int roccat_report_event(int minor, u8 const *data) + reader->cbuf_start = (reader->cbuf_start + 1) % ROCCAT_CBUF_SIZE; + } + ++ mutex_unlock(&device->cbuf_lock); ++ + wake_up_interruptible(&device->wait); + return 0; + } +-- +2.35.1 + diff --git a/queue-5.10/hid-topre-add-driver-fixing-report-descriptor.patch b/queue-5.10/hid-topre-add-driver-fixing-report-descriptor.patch new file mode 100644 index 00000000000..b11694dfa8c --- /dev/null +++ b/queue-5.10/hid-topre-add-driver-fixing-report-descriptor.patch @@ -0,0 +1,139 @@ +From c823974b49d5bc6f2b6743bb5a30c272bd178f4a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 10 Sep 2022 20:36:13 -0400 +Subject: hid: topre: Add driver fixing report descriptor + +From: Harry Stern + +[ Upstream commit a109d5c45b3d6728b9430716b915afbe16eef27c ] + +The Topre REALFORCE R2 firmware incorrectly reports that interface +descriptor number 1, input report descriptor 2's events are array events +rather than variable events. That particular report descriptor is used +to report keypresses when there are more than 6 keys held at a time. +This bug prevents events from this interface from being registered +properly, so only 6 keypresses (from a different interface) can be +registered at once, rather than full n-key rollover. + +This commit fixes the bug by setting the correct value in a report_fixup +function. + +The original bug report can be found here: +Link: https://gitlab.freedesktop.org/libinput/libinput/-/issues/804 + +Thanks to Benjamin Tissoires for diagnosing the issue with the report +descriptor. + +Signed-off-by: Harry Stern +Signed-off-by: Benjamin Tissoires +Link: https://lore.kernel.org/r/20220911003614.297613-1-harry@harrystern.net +Signed-off-by: Sasha Levin +--- + drivers/hid/Kconfig | 6 +++++ + drivers/hid/Makefile | 1 + + drivers/hid/hid-ids.h | 3 +++ + drivers/hid/hid-topre.c | 49 +++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 59 insertions(+) + create mode 100644 drivers/hid/hid-topre.c + +diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig +index f8ad3b2be0bf..2dd5c7944019 100644 +--- a/drivers/hid/Kconfig ++++ b/drivers/hid/Kconfig +@@ -1010,6 +1010,12 @@ config HID_TOPSEED + Say Y if you have a TopSeed Cyberlink or BTC Emprex or Conceptronic + CLLRCMCE remote control. + ++config HID_TOPRE ++ tristate "Topre REALFORCE keyboards" ++ depends on HID ++ help ++ Say Y for N-key rollover support on Topre REALFORCE R2 108 key keyboards. ++ + config HID_THINGM + tristate "ThingM blink(1) USB RGB LED" + depends on HID +diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile +index 4acb583c92a6..09830511909c 100644 +--- a/drivers/hid/Makefile ++++ b/drivers/hid/Makefile +@@ -114,6 +114,7 @@ obj-$(CONFIG_HID_GREENASIA) += hid-gaff.o + obj-$(CONFIG_HID_THRUSTMASTER) += hid-tmff.o + obj-$(CONFIG_HID_TIVO) += hid-tivo.o + obj-$(CONFIG_HID_TOPSEED) += hid-topseed.o ++obj-$(CONFIG_HID_TOPRE) += hid-topre.o + obj-$(CONFIG_HID_TWINHAN) += hid-twinhan.o + obj-$(CONFIG_HID_U2FZERO) += hid-u2fzero.o + hid-uclogic-objs := hid-uclogic-core.o \ +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index bb096dfb7b36..ab439aa4c4cb 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -1166,6 +1166,9 @@ + #define USB_DEVICE_ID_TIVO_SLIDE 0x1201 + #define USB_DEVICE_ID_TIVO_SLIDE_PRO 0x1203 + ++#define USB_VENDOR_ID_TOPRE 0x0853 ++#define USB_DEVICE_ID_TOPRE_REALFORCE_R2_108 0x0148 ++ + #define USB_VENDOR_ID_TOPSEED 0x0766 + #define USB_DEVICE_ID_TOPSEED_CYBERLINK 0x0204 + +diff --git a/drivers/hid/hid-topre.c b/drivers/hid/hid-topre.c +new file mode 100644 +index 000000000000..88a91cdad5f8 +--- /dev/null ++++ b/drivers/hid/hid-topre.c +@@ -0,0 +1,49 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * HID driver for Topre REALFORCE Keyboards ++ * ++ * Copyright (c) 2022 Harry Stern ++ * ++ * Based on the hid-macally driver ++ */ ++ ++#include ++#include ++ ++#include "hid-ids.h" ++ ++MODULE_AUTHOR("Harry Stern "); ++MODULE_DESCRIPTION("REALFORCE R2 Keyboard driver"); ++MODULE_LICENSE("GPL"); ++ ++/* ++ * Fix the REALFORCE R2's non-boot interface's report descriptor to match the ++ * events it's actually sending. It claims to send array events but is instead ++ * sending variable events. ++ */ ++static __u8 *topre_report_fixup(struct hid_device *hdev, __u8 *rdesc, ++ unsigned int *rsize) ++{ ++ if (*rsize >= 119 && rdesc[69] == 0x29 && rdesc[70] == 0xe7 && ++ rdesc[71] == 0x81 && rdesc[72] == 0x00) { ++ hid_info(hdev, ++ "fixing up Topre REALFORCE keyboard report descriptor\n"); ++ rdesc[72] = 0x02; ++ } ++ return rdesc; ++} ++ ++static const struct hid_device_id topre_id_table[] = { ++ { HID_USB_DEVICE(USB_VENDOR_ID_TOPRE, ++ USB_DEVICE_ID_TOPRE_REALFORCE_R2_108) }, ++ { } ++}; ++MODULE_DEVICE_TABLE(hid, topre_id_table); ++ ++static struct hid_driver topre_driver = { ++ .name = "topre", ++ .id_table = topre_id_table, ++ .report_fixup = topre_report_fixup, ++}; ++ ++module_hid_driver(topre_driver); +-- +2.35.1 + diff --git a/queue-5.10/hid-uclogic-fix-warning-in-uclogic_rdesc_template_ap.patch b/queue-5.10/hid-uclogic-fix-warning-in-uclogic_rdesc_template_ap.patch new file mode 100644 index 00000000000..e69cc0712c0 --- /dev/null +++ b/queue-5.10/hid-uclogic-fix-warning-in-uclogic_rdesc_template_ap.patch @@ -0,0 +1,44 @@ +From a76ad9e149101215d0334de93695474cbbfb1110 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Aug 2022 16:27:06 +0200 +Subject: HID: uclogic: Fix warning in uclogic_rdesc_template_apply +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: José Expósito + +[ Upstream commit 609174edeb758d1e2d713e7ab4e09ea8d45aa4f7 ] + +Building with Sparse enabled prints this warning: + + warning: incorrect type in assignment (different base types) + expected signed int x + got restricted __le32 [usertype] + +Cast the return value of cpu_to_le32() to fix the warning. + +Fixes: 08177f4 ("HID: uclogic: merge hid-huion driver in hid-uclogic") +Signed-off-by: José Expósito +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-uclogic-rdesc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/hid/hid-uclogic-rdesc.c b/drivers/hid/hid-uclogic-rdesc.c +index 9d4b8ca77f91..bdf632cc7355 100644 +--- a/drivers/hid/hid-uclogic-rdesc.c ++++ b/drivers/hid/hid-uclogic-rdesc.c +@@ -851,7 +851,7 @@ __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr, + if (memcmp(p, pen_head, sizeof(pen_head)) == 0 && + p[sizeof(pen_head)] < param_num) { + v = param_list[p[sizeof(pen_head)]]; +- put_unaligned(cpu_to_le32(v), (s32 *)p); ++ put_unaligned((__force u32)cpu_to_le32(v), (s32 *)p); + p += sizeof(pen_head) + 1; + } else { + p++; +-- +2.35.1 + diff --git a/queue-5.10/hid-uclogic-make-template-placeholder-ids-generic.patch b/queue-5.10/hid-uclogic-make-template-placeholder-ids-generic.patch new file mode 100644 index 00000000000..fdb0dc88393 --- /dev/null +++ b/queue-5.10/hid-uclogic-make-template-placeholder-ids-generic.patch @@ -0,0 +1,132 @@ +From 19520242f5e333be327ebc7f1d3281cce61794cc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 11 Jun 2022 13:39:11 +0200 +Subject: HID: uclogic: Make template placeholder IDs generic +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: José Expósito + +[ Upstream commit 76e645be7ebecbf39ab2edd949ea7f1757f58900 ] + +Up until now, the report descriptor template parameter IDs were only +used with pen report descriptors and they were named accordingly. + +Rename the enum and the total number of IDs to make them interface +agnostic. + +Refactor, no functional changes. + +Signed-off-by: José Expósito +Signed-off-by: Jiri Kosina +Stable-dep-of: 609174edeb75 ("HID: uclogic: Fix warning in uclogic_rdesc_template_apply") +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-uclogic-params.c | 4 ++-- + drivers/hid/hid-uclogic-rdesc.c | 14 +++++++------- + drivers/hid/hid-uclogic-rdesc.h | 10 +++++----- + 3 files changed, 14 insertions(+), 14 deletions(-) + +diff --git a/drivers/hid/hid-uclogic-params.c b/drivers/hid/hid-uclogic-params.c +index 38f9bbad81c1..59a01f438e0a 100644 +--- a/drivers/hid/hid-uclogic-params.c ++++ b/drivers/hid/hid-uclogic-params.c +@@ -148,7 +148,7 @@ static int uclogic_params_pen_init_v1(struct uclogic_params_pen *pen, + const int len = 12; + s32 resolution; + /* Pen report descriptor template parameters */ +- s32 desc_params[UCLOGIC_RDESC_PEN_PH_ID_NUM]; ++ s32 desc_params[UCLOGIC_RDESC_PH_ID_NUM]; + __u8 *desc_ptr = NULL; + + /* Check arguments */ +@@ -276,7 +276,7 @@ static int uclogic_params_pen_init_v2(struct uclogic_params_pen *pen, + const int len = 18; + s32 resolution; + /* Pen report descriptor template parameters */ +- s32 desc_params[UCLOGIC_RDESC_PEN_PH_ID_NUM]; ++ s32 desc_params[UCLOGIC_RDESC_PH_ID_NUM]; + __u8 *desc_ptr = NULL; + + /* Check arguments */ +diff --git a/drivers/hid/hid-uclogic-rdesc.c b/drivers/hid/hid-uclogic-rdesc.c +index bf5da6de7bba..9d4b8ca77f91 100644 +--- a/drivers/hid/hid-uclogic-rdesc.c ++++ b/drivers/hid/hid-uclogic-rdesc.c +@@ -821,7 +821,7 @@ const size_t uclogic_rdesc_xppen_deco01_frame_size = + * uclogic_rdesc_template_apply() - apply report descriptor parameters to a + * report descriptor template, creating a report descriptor. Copies the + * template over to the new report descriptor and replaces every occurrence of +- * UCLOGIC_RDESC_PH_HEAD, followed by an index byte, with the value from the ++ * UCLOGIC_RDESC_PEN_PH_HEAD, followed by an index byte, with the value from the + * parameter list at that index. + * + * @template_ptr: Pointer to the template buffer. +@@ -838,7 +838,7 @@ __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr, + const s32 *param_list, + size_t param_num) + { +- static const __u8 head[] = {UCLOGIC_RDESC_PH_HEAD}; ++ static const __u8 pen_head[] = {UCLOGIC_RDESC_PEN_PH_HEAD}; + __u8 *rdesc_ptr; + __u8 *p; + s32 v; +@@ -847,12 +847,12 @@ __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr, + if (rdesc_ptr == NULL) + return NULL; + +- for (p = rdesc_ptr; p + sizeof(head) < rdesc_ptr + template_size;) { +- if (memcmp(p, head, sizeof(head)) == 0 && +- p[sizeof(head)] < param_num) { +- v = param_list[p[sizeof(head)]]; ++ for (p = rdesc_ptr; p + sizeof(pen_head) < rdesc_ptr + template_size;) { ++ if (memcmp(p, pen_head, sizeof(pen_head)) == 0 && ++ p[sizeof(pen_head)] < param_num) { ++ v = param_list[p[sizeof(pen_head)]]; + put_unaligned(cpu_to_le32(v), (s32 *)p); +- p += sizeof(head) + 1; ++ p += sizeof(pen_head) + 1; + } else { + p++; + } +diff --git a/drivers/hid/hid-uclogic-rdesc.h b/drivers/hid/hid-uclogic-rdesc.h +index c5da51055af3..1bb9c1220ea7 100644 +--- a/drivers/hid/hid-uclogic-rdesc.h ++++ b/drivers/hid/hid-uclogic-rdesc.h +@@ -81,7 +81,7 @@ extern __u8 uclogic_rdesc_twha60_fixed1_arr[]; + extern const size_t uclogic_rdesc_twha60_fixed1_size; + + /* Report descriptor template placeholder head */ +-#define UCLOGIC_RDESC_PH_HEAD 0xFE, 0xED, 0x1D ++#define UCLOGIC_RDESC_PEN_PH_HEAD 0xFE, 0xED, 0x1D + + /* Apply report descriptor parameters to a report descriptor template */ + extern __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr, +@@ -89,19 +89,19 @@ extern __u8 *uclogic_rdesc_template_apply(const __u8 *template_ptr, + const s32 *param_list, + size_t param_num); + +-/* Pen report descriptor template placeholder IDs */ +-enum uclogic_rdesc_pen_ph_id { ++/* Report descriptor template placeholder IDs */ ++enum uclogic_rdesc_ph_id { + UCLOGIC_RDESC_PEN_PH_ID_X_LM, + UCLOGIC_RDESC_PEN_PH_ID_X_PM, + UCLOGIC_RDESC_PEN_PH_ID_Y_LM, + UCLOGIC_RDESC_PEN_PH_ID_Y_PM, + UCLOGIC_RDESC_PEN_PH_ID_PRESSURE_LM, +- UCLOGIC_RDESC_PEN_PH_ID_NUM ++ UCLOGIC_RDESC_PH_ID_NUM + }; + + /* Report descriptor pen template placeholder */ + #define UCLOGIC_RDESC_PEN_PH(_ID) \ +- UCLOGIC_RDESC_PH_HEAD, UCLOGIC_RDESC_PEN_PH_ID_##_ID ++ UCLOGIC_RDESC_PEN_PH_HEAD, UCLOGIC_RDESC_PEN_PH_ID_##_ID + + /* Report ID for v1 pen reports */ + #define UCLOGIC_RDESC_PEN_V1_ID 0x07 +-- +2.35.1 + diff --git a/queue-5.10/hsi-omap_ssi-fix-refcount-leak-in-ssi_probe.patch b/queue-5.10/hsi-omap_ssi-fix-refcount-leak-in-ssi_probe.patch new file mode 100644 index 00000000000..966d4deb1cb --- /dev/null +++ b/queue-5.10/hsi-omap_ssi-fix-refcount-leak-in-ssi_probe.patch @@ -0,0 +1,36 @@ +From cc470a1ac204d60dac204036b22c70637cd69653 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Apr 2022 08:52:32 +0000 +Subject: HSI: omap_ssi: Fix refcount leak in ssi_probe + +From: Miaoqian Lin + +[ Upstream commit 9a2ea132df860177b33c9fd421b26c4e9a0a9396 ] + +When returning or breaking early from a +for_each_available_child_of_node() loop, we need to explicitly call +of_node_put() on the child node to possibly release the node. + +Fixes: b209e047bc74 ("HSI: Introduce OMAP SSI driver") +Signed-off-by: Miaoqian Lin +Signed-off-by: Sebastian Reichel +Signed-off-by: Sasha Levin +--- + drivers/hsi/controllers/omap_ssi_core.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/hsi/controllers/omap_ssi_core.c b/drivers/hsi/controllers/omap_ssi_core.c +index 44a3f5660c10..eb9820158318 100644 +--- a/drivers/hsi/controllers/omap_ssi_core.c ++++ b/drivers/hsi/controllers/omap_ssi_core.c +@@ -524,6 +524,7 @@ static int ssi_probe(struct platform_device *pd) + if (!childpdev) { + err = -ENODEV; + dev_err(&pd->dev, "failed to create ssi controller port\n"); ++ of_node_put(child); + goto out3; + } + } +-- +2.35.1 + diff --git a/queue-5.10/hsi-omap_ssi_port-fix-dma_map_sg-error-check.patch b/queue-5.10/hsi-omap_ssi_port-fix-dma_map_sg-error-check.patch new file mode 100644 index 00000000000..dc96714fdf0 --- /dev/null +++ b/queue-5.10/hsi-omap_ssi_port-fix-dma_map_sg-error-check.patch @@ -0,0 +1,55 @@ +From 2e4f7c9966f9b6b52ee98619196832de62caa1ad Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 12:12:27 +0200 +Subject: HSI: omap_ssi_port: Fix dma_map_sg error check + +From: Jack Wang + +[ Upstream commit 551e325bbd3fb8b5a686ac1e6cf76e5641461cf2 ] + +dma_map_sg return 0 on error, in case of error return -EIO +to caller. + +Cc: Sebastian Reichel +Cc: linux-kernel@vger.kernel.org (open list) +Fixes: b209e047bc74 ("HSI: Introduce OMAP SSI driver") +Signed-off-by: Jack Wang +Signed-off-by: Sebastian Reichel +Signed-off-by: Sasha Levin +--- + drivers/hsi/controllers/omap_ssi_port.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/hsi/controllers/omap_ssi_port.c b/drivers/hsi/controllers/omap_ssi_port.c +index a0cb5be246e1..b9495b720f1b 100644 +--- a/drivers/hsi/controllers/omap_ssi_port.c ++++ b/drivers/hsi/controllers/omap_ssi_port.c +@@ -230,10 +230,10 @@ static int ssi_start_dma(struct hsi_msg *msg, int lch) + if (msg->ttype == HSI_MSG_READ) { + err = dma_map_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents, + DMA_FROM_DEVICE); +- if (err < 0) { ++ if (!err) { + dev_dbg(&ssi->device, "DMA map SG failed !\n"); + pm_runtime_put_autosuspend(omap_port->pdev); +- return err; ++ return -EIO; + } + csdp = SSI_DST_BURST_4x32_BIT | SSI_DST_MEMORY_PORT | + SSI_SRC_SINGLE_ACCESS0 | SSI_SRC_PERIPHERAL_PORT | +@@ -247,10 +247,10 @@ static int ssi_start_dma(struct hsi_msg *msg, int lch) + } else { + err = dma_map_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents, + DMA_TO_DEVICE); +- if (err < 0) { ++ if (!err) { + dev_dbg(&ssi->device, "DMA map SG failed !\n"); + pm_runtime_put_autosuspend(omap_port->pdev); +- return err; ++ return -EIO; + } + csdp = SSI_SRC_BURST_4x32_BIT | SSI_SRC_MEMORY_PORT | + SSI_DST_SINGLE_ACCESS0 | SSI_DST_PERIPHERAL_PORT | +-- +2.35.1 + diff --git a/queue-5.10/hsi-ssi_protocol-fix-potential-resource-leak-in-ssip.patch b/queue-5.10/hsi-ssi_protocol-fix-potential-resource-leak-in-ssip.patch new file mode 100644 index 00000000000..b0252ec520a --- /dev/null +++ b/queue-5.10/hsi-ssi_protocol-fix-potential-resource-leak-in-ssip.patch @@ -0,0 +1,37 @@ +From b05b19e0de0e32ea68fe79a14bf8f2fba1abbe52 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Sep 2022 15:48:01 +0800 +Subject: HSI: ssi_protocol: fix potential resource leak in ssip_pn_open() + +From: Jianglei Nie + +[ Upstream commit b28dbcb379e6a7f80262c2732a57681b1ee548ca ] + +ssip_pn_open() claims the HSI client's port with hsi_claim_port(). When +hsi_register_port_event() gets some error and returns a negetive value, +the HSI client's port should be released with hsi_release_port(). + +Fix it by calling hsi_release_port() when hsi_register_port_event() fails. + +Signed-off-by: Jianglei Nie +Signed-off-by: Sebastian Reichel +Signed-off-by: Sasha Levin +--- + drivers/hsi/clients/ssi_protocol.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/hsi/clients/ssi_protocol.c b/drivers/hsi/clients/ssi_protocol.c +index 96d0eccca3aa..f202751484aa 100644 +--- a/drivers/hsi/clients/ssi_protocol.c ++++ b/drivers/hsi/clients/ssi_protocol.c +@@ -931,6 +931,7 @@ static int ssip_pn_open(struct net_device *dev) + if (err < 0) { + dev_err(&cl->device, "Register HSI port event failed (%d)\n", + err); ++ hsi_release_port(cl); + return err; + } + dev_dbg(&cl->device, "Configuring SSI port\n"); +-- +2.35.1 + diff --git a/queue-5.10/hwrng-imx-rngc-moving-irq-handler-registering-after-.patch b/queue-5.10/hwrng-imx-rngc-moving-irq-handler-registering-after-.patch new file mode 100644 index 00000000000..66f8e6a6134 --- /dev/null +++ b/queue-5.10/hwrng-imx-rngc-moving-irq-handler-registering-after-.patch @@ -0,0 +1,61 @@ +From 0bceec0c8d440530c868e7df0f5c554880f2be7a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 22 Aug 2022 13:19:03 +0200 +Subject: hwrng: imx-rngc - Moving IRQ handler registering after + imx_rngc_irq_mask_clear() + +From: Kshitiz Varshney + +[ Upstream commit 10a2199caf437e893d9027d97700b3c6010048b7 ] + +Issue: +While servicing interrupt, if the IRQ happens to be because of a SEED_DONE +due to a previous boot stage, you end up completing the completion +prematurely, hence causing kernel to crash while booting. + +Fix: +Moving IRQ handler registering after imx_rngc_irq_mask_clear() + +Fixes: 1d5449445bd0 (hwrng: mx-rngc - add a driver for Freescale RNGC) +Signed-off-by: Kshitiz Varshney +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/char/hw_random/imx-rngc.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c +index f63dd08a4f37..02665ccf6ae7 100644 +--- a/drivers/char/hw_random/imx-rngc.c ++++ b/drivers/char/hw_random/imx-rngc.c +@@ -266,13 +266,6 @@ static int imx_rngc_probe(struct platform_device *pdev) + if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) + return -ENODEV; + +- ret = devm_request_irq(&pdev->dev, +- irq, imx_rngc_irq, 0, pdev->name, (void *)rngc); +- if (ret) { +- dev_err(rngc->dev, "Can't get interrupt working.\n"); +- return ret; +- } +- + init_completion(&rngc->rng_op_done); + + rngc->rng.name = pdev->name; +@@ -286,6 +279,13 @@ static int imx_rngc_probe(struct platform_device *pdev) + + imx_rngc_irq_mask_clear(rngc); + ++ ret = devm_request_irq(&pdev->dev, ++ irq, imx_rngc_irq, 0, pdev->name, (void *)rngc); ++ if (ret) { ++ dev_err(rngc->dev, "Can't get interrupt working.\n"); ++ return ret; ++ } ++ + if (self_test) { + ret = imx_rngc_self_test(rngc); + if (ret) { +-- +2.35.1 + diff --git a/queue-5.10/hwrng-imx-rngc-use-devm_clk_get_enabled.patch b/queue-5.10/hwrng-imx-rngc-use-devm_clk_get_enabled.patch new file mode 100644 index 00000000000..9609146fe2e --- /dev/null +++ b/queue-5.10/hwrng-imx-rngc-use-devm_clk_get_enabled.patch @@ -0,0 +1,106 @@ +From 250c01ab3ce931002b51ce492b88a8bb596fd358 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Aug 2022 21:37:42 +0200 +Subject: hwrng: imx-rngc - use devm_clk_get_enabled + +From: Martin Kaiser + +[ Upstream commit 6a2bc448423cea44e7dba0f72d7c82ae04ab201e ] + +Use the new devm_clk_get_enabled function to get our clock. + +We don't have to disable and unprepare the clock ourselves any more in +error paths and in the remove function. + +Signed-off-by: Martin Kaiser +Signed-off-by: Herbert Xu +Stable-dep-of: 10a2199caf43 ("hwrng: imx-rngc - Moving IRQ handler registering after imx_rngc_irq_mask_clear()") +Signed-off-by: Sasha Levin +--- + drivers/char/hw_random/imx-rngc.c | 25 ++++++------------------- + 1 file changed, 6 insertions(+), 19 deletions(-) + +diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c +index 61c844baf26e..f63dd08a4f37 100644 +--- a/drivers/char/hw_random/imx-rngc.c ++++ b/drivers/char/hw_random/imx-rngc.c +@@ -245,7 +245,7 @@ static int imx_rngc_probe(struct platform_device *pdev) + if (IS_ERR(rngc->base)) + return PTR_ERR(rngc->base); + +- rngc->clk = devm_clk_get(&pdev->dev, NULL); ++ rngc->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(rngc->clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + return PTR_ERR(rngc->clk); +@@ -257,26 +257,20 @@ static int imx_rngc_probe(struct platform_device *pdev) + return irq; + } + +- ret = clk_prepare_enable(rngc->clk); +- if (ret) +- return ret; +- + ver_id = readl(rngc->base + RNGC_VER_ID); + rng_type = ver_id >> RNGC_TYPE_SHIFT; + /* + * This driver supports only RNGC and RNGB. (There's a different + * driver for RNGA.) + */ +- if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) { +- ret = -ENODEV; +- goto err; +- } ++ if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) ++ return -ENODEV; + + ret = devm_request_irq(&pdev->dev, + irq, imx_rngc_irq, 0, pdev->name, (void *)rngc); + if (ret) { + dev_err(rngc->dev, "Can't get interrupt working.\n"); +- goto err; ++ return ret; + } + + init_completion(&rngc->rng_op_done); +@@ -296,14 +290,14 @@ static int imx_rngc_probe(struct platform_device *pdev) + ret = imx_rngc_self_test(rngc); + if (ret) { + dev_err(rngc->dev, "self test failed\n"); +- goto err; ++ return ret; + } + } + + ret = hwrng_register(&rngc->rng); + if (ret) { + dev_err(&pdev->dev, "hwrng registration failed\n"); +- goto err; ++ return ret; + } + + dev_info(&pdev->dev, +@@ -311,11 +305,6 @@ static int imx_rngc_probe(struct platform_device *pdev) + rng_type == RNGC_TYPE_RNGB ? 'B' : 'C', + (ver_id >> RNGC_VER_MAJ_SHIFT) & 0xff, ver_id & 0xff); + return 0; +- +-err: +- clk_disable_unprepare(rngc->clk); +- +- return ret; + } + + static int __exit imx_rngc_remove(struct platform_device *pdev) +@@ -324,8 +313,6 @@ static int __exit imx_rngc_remove(struct platform_device *pdev) + + hwrng_unregister(&rngc->rng); + +- clk_disable_unprepare(rngc->clk); +- + return 0; + } + +-- +2.35.1 + diff --git a/queue-5.10/i2c-mlxbf-support-lock-mechanism.patch b/queue-5.10/i2c-mlxbf-support-lock-mechanism.patch new file mode 100644 index 00000000000..daa9276b7c3 --- /dev/null +++ b/queue-5.10/i2c-mlxbf-support-lock-mechanism.patch @@ -0,0 +1,121 @@ +From e915f1f255a4520e4d074caf02dabf6316980e48 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 15:45:04 -0400 +Subject: i2c: mlxbf: support lock mechanism + +From: Asmaa Mnebhi + +[ Upstream commit 86067ccfa1424a26491542d6f6d7546d40b61a10 ] + +Linux is not the only entity using the BlueField I2C busses so +support a lock mechanism provided by hardware to avoid issues +when multiple entities are trying to access the same bus. + +The lock is acquired whenever written explicitely or the lock +register is read. So make sure it is always released at the end +of a successful or failed transaction. + +Fixes: b5b5b32081cd206b (i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC) +Reviewed-by: Khalil Blaiech +Signed-off-by: Asmaa Mnebhi +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-mlxbf.c | 44 ++++++++++++++++++++++++++++++---- + 1 file changed, 39 insertions(+), 5 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c +index bea82a787b4f..90c488a60693 100644 +--- a/drivers/i2c/busses/i2c-mlxbf.c ++++ b/drivers/i2c/busses/i2c-mlxbf.c +@@ -312,6 +312,7 @@ static u64 mlxbf_i2c_corepll_frequency; + * exact. + */ + #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ ++#define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */ + + /* Encapsulates timing parameters. */ + struct mlxbf_i2c_timings { +@@ -520,6 +521,25 @@ static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv) + return false; + } + ++/* ++ * wait for the lock to be released before acquiring it. ++ */ ++static bool mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv *priv) ++{ ++ if (mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, ++ MLXBF_I2C_MASTER_LOCK_BIT, true, ++ MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT)) ++ return true; ++ ++ return false; ++} ++ ++static void mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv *priv) ++{ ++ /* Clear the gw to clear the lock */ ++ writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); ++} ++ + static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, + u32 cause_status) + { +@@ -711,10 +731,19 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, + slave = request->slave & GENMASK(6, 0); + addr = slave << 1; + +- /* First of all, check whether the HW is idle. */ +- if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) ++ /* ++ * Try to acquire the smbus gw lock before any reads of the GW register since ++ * a read sets the lock. ++ */ ++ if (WARN_ON(!mlxbf_i2c_smbus_master_lock(priv))) + return -EBUSY; + ++ /* Check whether the HW is idle */ ++ if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv))) { ++ ret = -EBUSY; ++ goto out_unlock; ++ } ++ + /* Set first byte. */ + data_desc[data_idx++] = addr; + +@@ -738,8 +767,10 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, + write_en = 1; + write_len += operation->length; + if (data_idx + operation->length > +- MLXBF_I2C_MASTER_DATA_DESC_SIZE) +- return -ENOBUFS; ++ MLXBF_I2C_MASTER_DATA_DESC_SIZE) { ++ ret = -ENOBUFS; ++ goto out_unlock; ++ } + memcpy(data_desc + data_idx, + operation->buffer, operation->length); + data_idx += operation->length; +@@ -771,7 +802,7 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, + ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, + pec_en, 0); + if (ret) +- return ret; ++ goto out_unlock; + } + + if (read_en) { +@@ -798,6 +829,9 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, + priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM); + } + ++out_unlock: ++ mlxbf_i2c_smbus_master_unlock(priv); ++ + return ret; + } + +-- +2.35.1 + diff --git a/queue-5.10/ia64-export-memory_add_physaddr_to_nid-to-fix-cxl-bu.patch b/queue-5.10/ia64-export-memory_add_physaddr_to_nid-to-fix-cxl-bu.patch new file mode 100644 index 00000000000..98a215f103a --- /dev/null +++ b/queue-5.10/ia64-export-memory_add_physaddr_to_nid-to-fix-cxl-bu.patch @@ -0,0 +1,46 @@ +From e0f37e8a99f986e38fb79aae5189d3ccfd584e90 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 10 Sep 2022 18:26:16 -0700 +Subject: ia64: export memory_add_physaddr_to_nid to fix cxl build error + +From: Randy Dunlap + +[ Upstream commit 97c318bfbe84efded246e80428054f300042f110 ] + +cxl_pmem.ko uses memory_add_physaddr_to_nid() but ia64 does not export it, +so this causes a build error: + +ERROR: modpost: "memory_add_physaddr_to_nid" [drivers/cxl/cxl_pmem.ko] undefined! + +Fix this by exporting that function. + +Fixes: 8c2676a5870a ("hot-add-mem x86_64: memory_add_physaddr_to_nid node fixup") +Reported-by: kernel test robot +Signed-off-by: Randy Dunlap +Cc: Dan Williams +Cc: Ben Widawsky +Cc: Jonathan Cameron +Cc: linux-ia64@vger.kernel.org +Cc: Arnd Bergmann +Cc: Keith Mannthey +Cc: Andrew Morton +Signed-off-by: Arnd Bergmann +Signed-off-by: Sasha Levin +--- + arch/ia64/mm/numa.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/ia64/mm/numa.c b/arch/ia64/mm/numa.c +index f34964271101..6cd002e8163d 100644 +--- a/arch/ia64/mm/numa.c ++++ b/arch/ia64/mm/numa.c +@@ -106,5 +106,6 @@ int memory_add_physaddr_to_nid(u64 addr) + return 0; + return nid; + } ++EXPORT_SYMBOL(memory_add_physaddr_to_nid); + #endif + #endif +-- +2.35.1 + diff --git a/queue-5.10/ib-rdmavt-add-__init-__exit-annotations-to-module-in.patch b/queue-5.10/ib-rdmavt-add-__init-__exit-annotations-to-module-in.patch new file mode 100644 index 00000000000..dc65900aade --- /dev/null +++ b/queue-5.10/ib-rdmavt-add-__init-__exit-annotations-to-module-in.patch @@ -0,0 +1,45 @@ +From 03fcf6a87ec290029fff7ebb86862056af9c901d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 24 Sep 2022 17:14:57 +0800 +Subject: IB/rdmavt: Add __init/__exit annotations to module init/exit funcs + +From: Xiu Jianfeng + +[ Upstream commit 78657a445ca7603024348781c921f8ecaee10a49 ] + +Add missing __init/__exit annotations to module init/exit funcs. + +Fixes: 0194621b2253 ("IB/rdmavt: Create module framework and handle driver registration") +Link: https://lore.kernel.org/r/20220924091457.52446-1-xiujianfeng@huawei.com +Signed-off-by: Xiu Jianfeng +Signed-off-by: Jason Gunthorpe +Signed-off-by: Sasha Levin +--- + drivers/infiniband/sw/rdmavt/vt.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/infiniband/sw/rdmavt/vt.c b/drivers/infiniband/sw/rdmavt/vt.c +index d1bbe66610cf..f2734809812d 100644 +--- a/drivers/infiniband/sw/rdmavt/vt.c ++++ b/drivers/infiniband/sw/rdmavt/vt.c +@@ -57,7 +57,7 @@ + MODULE_LICENSE("Dual BSD/GPL"); + MODULE_DESCRIPTION("RDMA Verbs Transport Library"); + +-static int rvt_init(void) ++static int __init rvt_init(void) + { + int ret = rvt_driver_cq_init(); + +@@ -68,7 +68,7 @@ static int rvt_init(void) + } + module_init(rvt_init); + +-static void rvt_cleanup(void) ++static void __exit rvt_cleanup(void) + { + rvt_cq_exit(); + } +-- +2.35.1 + diff --git a/queue-5.10/ib-set-iova-length-on-ib_mr-in-core-uverbs-layers.patch b/queue-5.10/ib-set-iova-length-on-ib_mr-in-core-uverbs-layers.patch new file mode 100644 index 00000000000..9e86ef89a6f --- /dev/null +++ b/queue-5.10/ib-set-iova-length-on-ib_mr-in-core-uverbs-layers.patch @@ -0,0 +1,93 @@ +From 45ffbf11622a9b1d0353236212861a0aeeb30370 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 17:08:43 +0900 +Subject: IB: Set IOVA/LENGTH on IB_MR in core/uverbs layers + +From: Daisuke Matsuda + +[ Upstream commit 241f9a27e0fc0eaf23e3d52c8450f10648cd11f1 ] + +Set 'iova' and 'length' on ib_mr in ib_uverbs and ib_core layers to let all +drivers have the members filled. Also, this commit removes redundancy in +the respective drivers. + +Previously, commit 04c0a5fcfcf65 ("IB/uverbs: Set IOVA on IB MR in uverbs +layer") changed to set 'iova', but seems to have missed 'length' and the +ib_core layer at that time. + +Fixes: 04c0a5fcfcf65 ("IB/uverbs: Set IOVA on IB MR in uverbs layer") +Signed-off-by: Daisuke Matsuda +Link: https://lore.kernel.org/r/20220921080844.1616883-1-matsuda-daisuke@fujitsu.com +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/core/uverbs_cmd.c | 5 ++++- + drivers/infiniband/core/verbs.c | 2 ++ + drivers/infiniband/hw/hns/hns_roce_mr.c | 1 - + drivers/infiniband/hw/mlx4/mr.c | 1 - + 4 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c +index 3e82469c851c..a704b8fbebc6 100644 +--- a/drivers/infiniband/core/uverbs_cmd.c ++++ b/drivers/infiniband/core/uverbs_cmd.c +@@ -749,6 +749,7 @@ static int ib_uverbs_reg_mr(struct uverbs_attr_bundle *attrs) + mr->uobject = uobj; + atomic_inc(&pd->usecnt); + mr->iova = cmd.hca_va; ++ mr->length = cmd.length; + + rdma_restrack_new(&mr->res, RDMA_RESTRACK_MR); + rdma_restrack_set_name(&mr->res, NULL); +@@ -872,8 +873,10 @@ static int ib_uverbs_rereg_mr(struct uverbs_attr_bundle *attrs) + mr->pd = new_pd; + atomic_inc(&new_pd->usecnt); + } +- if (cmd.flags & IB_MR_REREG_TRANS) ++ if (cmd.flags & IB_MR_REREG_TRANS) { + mr->iova = cmd.hca_va; ++ mr->length = cmd.length; ++ } + } + + memset(&resp, 0, sizeof(resp)); +diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c +index 597e889ba831..5889639e90a1 100644 +--- a/drivers/infiniband/core/verbs.c ++++ b/drivers/infiniband/core/verbs.c +@@ -2082,6 +2082,8 @@ struct ib_mr *ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, + mr->pd = pd; + mr->dm = NULL; + atomic_inc(&pd->usecnt); ++ mr->iova = virt_addr; ++ mr->length = length; + + rdma_restrack_new(&mr->res, RDMA_RESTRACK_MR); + rdma_restrack_parent_name(&mr->res, &pd->res); +diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c +index 2661dbbd7812..c94f564a5021 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_mr.c ++++ b/drivers/infiniband/hw/hns/hns_roce_mr.c +@@ -286,7 +286,6 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, + goto err_alloc_pbl; + + mr->ibmr.rkey = mr->ibmr.lkey = mr->key; +- mr->ibmr.length = length; + + return &mr->ibmr; + +diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c +index 50becc0e4b62..ccb9f9bbe59e 100644 +--- a/drivers/infiniband/hw/mlx4/mr.c ++++ b/drivers/infiniband/hw/mlx4/mr.c +@@ -439,7 +439,6 @@ struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, + goto err_mr; + + mr->ibmr.rkey = mr->ibmr.lkey = mr->mmr.key; +- mr->ibmr.length = length; + mr->ibmr.page_size = 1U << shift; + + return &mr->ibmr; +-- +2.35.1 + diff --git a/queue-5.10/iio-abi-fix-wrong-format-of-differential-capacitance.patch b/queue-5.10/iio-abi-fix-wrong-format-of-differential-capacitance.patch new file mode 100644 index 00000000000..fe31a34b48e --- /dev/null +++ b/queue-5.10/iio-abi-fix-wrong-format-of-differential-capacitance.patch @@ -0,0 +1,36 @@ +From 28297fd90d0cf5e4cd705789a009ca037a47997a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 26 Jun 2022 13:29:23 +0100 +Subject: iio: ABI: Fix wrong format of differential capacitance channel ABI. + +From: Jonathan Cameron + +[ Upstream commit 1efc41035f1841acf0af2bab153158e27ce94f10 ] + +in_ only occurs once in these attributes. + +Fixes: 0baf29d658c7 ("staging:iio:documentation Add abi docs for capacitance adcs.") +Signed-off-by: Jonathan Cameron +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220626122938.582107-3-jic23@kernel.org +Signed-off-by: Sasha Levin +--- + Documentation/ABI/testing/sysfs-bus-iio | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio +index df42bed09f25..53f07fc41b96 100644 +--- a/Documentation/ABI/testing/sysfs-bus-iio ++++ b/Documentation/ABI/testing/sysfs-bus-iio +@@ -142,7 +142,7 @@ Description: + Raw capacitance measurement from channel Y. Units after + application of scale and offset are nanofarads. + +-What: /sys/.../iio:deviceX/in_capacitanceY-in_capacitanceZ_raw ++What: /sys/.../iio:deviceX/in_capacitanceY-capacitanceZ_raw + KernelVersion: 3.2 + Contact: linux-iio@vger.kernel.org + Description: +-- +2.35.1 + diff --git a/queue-5.10/iio-adc-at91-sama5d2_adc-check-return-status-for-pre.patch b/queue-5.10/iio-adc-at91-sama5d2_adc-check-return-status-for-pre.patch new file mode 100644 index 00000000000..fae5d80e1b0 --- /dev/null +++ b/queue-5.10/iio-adc-at91-sama5d2_adc-check-return-status-for-pre.patch @@ -0,0 +1,53 @@ +From 365ef6f7c17551f775b8cb519b3688ef9ddf7647 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Aug 2022 13:28:38 +0300 +Subject: iio: adc: at91-sama5d2_adc: check return status for pressure and + touch + +From: Claudiu Beznea + +[ Upstream commit d84ace944a3b24529798dbae1340dea098473155 ] + +Check return status of at91_adc_read_position() and +at91_adc_read_pressure() in at91_adc_read_info_raw(). + +Fixes: 6794e23fa3fe ("iio: adc: at91-sama5d2_adc: add support for oversampling resolution") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220803102855.2191070-3-claudiu.beznea@microchip.com +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/at91-sama5d2_adc.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c +index 230e4111517e..fe41689c5da6 100644 +--- a/drivers/iio/adc/at91-sama5d2_adc.c ++++ b/drivers/iio/adc/at91-sama5d2_adc.c +@@ -1355,8 +1355,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, + *val = tmp_val; + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); ++ if (ret > 0) ++ ret = at91_adc_adjust_val_osr(st, val); + +- return at91_adc_adjust_val_osr(st, val); ++ return ret; + } + if (chan->type == IIO_PRESSURE) { + ret = iio_device_claim_direct_mode(indio_dev); +@@ -1369,8 +1371,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, + *val = tmp_val; + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); ++ if (ret > 0) ++ ret = at91_adc_adjust_val_osr(st, val); + +- return at91_adc_adjust_val_osr(st, val); ++ return ret; + } + + /* in this case we have a voltage channel */ +-- +2.35.1 + diff --git a/queue-5.10/iio-adc-at91-sama5d2_adc-disable-prepare-buffer-on-s.patch b/queue-5.10/iio-adc-at91-sama5d2_adc-disable-prepare-buffer-on-s.patch new file mode 100644 index 00000000000..aa73f032304 --- /dev/null +++ b/queue-5.10/iio-adc-at91-sama5d2_adc-disable-prepare-buffer-on-s.patch @@ -0,0 +1,62 @@ +From f811f5ff1d2f878de3ab4b2d003d7be526d6bd2a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Aug 2022 13:28:40 +0300 +Subject: iio: adc: at91-sama5d2_adc: disable/prepare buffer on suspend/resume + +From: Claudiu Beznea + +[ Upstream commit 808175e21d9b7f866eda742e8970f27b78afe5db ] + +In case triggered buffers are enabled while system is suspended they will +not work anymore after resume. For this call at91_adc_buffer_postdisable() +on suspend and at91_adc_buffer_prepare() on resume. On tests it has been +seen that at91_adc_buffer_postdisable() call is not necessary but it has +been kept because it also does the book keeping for DMA. On resume path +there is no need to call at91_adc_configure_touch() as it is embedded in +at91_adc_buffer_prepare(). + +Fixes: 073c662017f2f ("iio: adc: at91-sama5d2_adc: add support for DMA") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220803102855.2191070-5-claudiu.beznea@microchip.com +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/at91-sama5d2_adc.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c +index ef6dc85024c1..250b78ee1625 100644 +--- a/drivers/iio/adc/at91-sama5d2_adc.c ++++ b/drivers/iio/adc/at91-sama5d2_adc.c +@@ -1907,6 +1907,9 @@ static __maybe_unused int at91_adc_suspend(struct device *dev) + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct at91_adc_state *st = iio_priv(indio_dev); + ++ if (iio_buffer_enabled(indio_dev)) ++ at91_adc_buffer_postdisable(indio_dev); ++ + /* + * Do a sofware reset of the ADC before we go to suspend. + * this will ensure that all pins are free from being muxed by the ADC +@@ -1950,14 +1953,11 @@ static __maybe_unused int at91_adc_resume(struct device *dev) + if (!iio_buffer_enabled(indio_dev)) + return 0; + +- /* check if we are enabling triggered buffer or the touchscreen */ +- if (at91_adc_current_chan_is_touch(indio_dev)) +- return at91_adc_configure_touch(st, true); +- else +- return at91_adc_configure_trigger(st->trig, true); ++ ret = at91_adc_buffer_prepare(indio_dev); ++ if (ret) ++ goto vref_disable_resume; + +- /* not needed but more explicit */ +- return 0; ++ return at91_adc_configure_trigger(st->trig, true); + + vref_disable_resume: + regulator_disable(st->vref); +-- +2.35.1 + diff --git a/queue-5.10/iio-adc-at91-sama5d2_adc-fix-at91_sama5d2_mr_trackti.patch b/queue-5.10/iio-adc-at91-sama5d2_adc-fix-at91_sama5d2_mr_trackti.patch new file mode 100644 index 00000000000..f835f5c7bf5 --- /dev/null +++ b/queue-5.10/iio-adc-at91-sama5d2_adc-fix-at91_sama5d2_mr_trackti.patch @@ -0,0 +1,38 @@ +From da29d9a807c3ac9b901986808b098fe10fdacf76 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Aug 2022 13:28:37 +0300 +Subject: iio: adc: at91-sama5d2_adc: fix AT91_SAMA5D2_MR_TRACKTIM_MAX + +From: Claudiu Beznea + +[ Upstream commit bb73d5d9164c57c4bb916739a98e5cd8e0a5ed8c ] + +All ADC HW versions handled by this driver (SAMA5D2, SAM9X60, SAMA7G5) +have MR.TRACKTIM on 4 bits. Fix AT91_SAMA5D2_MR_TRACKTIM_MAX to reflect +this. + +Fixes: 27e177190891 ("iio:adc:at91_adc8xx: introduce new atmel adc driver") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220803102855.2191070-2-claudiu.beznea@microchip.com +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/at91-sama5d2_adc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c +index 4ede7e766765..230e4111517e 100644 +--- a/drivers/iio/adc/at91-sama5d2_adc.c ++++ b/drivers/iio/adc/at91-sama5d2_adc.c +@@ -74,7 +74,7 @@ + #define AT91_SAMA5D2_MR_ANACH BIT(23) + /* Tracking Time */ + #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) +-#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff ++#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf + /* Transfer Time */ + #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) + #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 +-- +2.35.1 + diff --git a/queue-5.10/iio-adc-at91-sama5d2_adc-lock-around-oversampling-an.patch b/queue-5.10/iio-adc-at91-sama5d2_adc-lock-around-oversampling-an.patch new file mode 100644 index 00000000000..8e829303264 --- /dev/null +++ b/queue-5.10/iio-adc-at91-sama5d2_adc-lock-around-oversampling-an.patch @@ -0,0 +1,79 @@ +From dca9f98686fe7c738c909ba792f47feb8c559597 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Aug 2022 13:28:39 +0300 +Subject: iio: adc: at91-sama5d2_adc: lock around oversampling and sample freq + +From: Claudiu Beznea + +[ Upstream commit 9780a23ed5a0a0a63683e078f576719a98d4fb70 ] + +.read_raw()/.write_raw() could be called asynchronously from user space +or other in kernel drivers. Without locking on st->lock these could be +called asynchronously while there is a conversion in progress. Read will +be harmless but changing registers while conversion is in progress may +lead to inconsistent results. Thus, to avoid this lock st->lock. + +Fixes: 27e177190891 ("iio:adc:at91_adc8xx: introduce new atmel adc driver") +Fixes: 6794e23fa3fe ("iio: adc: at91-sama5d2_adc: add support for oversampling resolution") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220803102855.2191070-4-claudiu.beznea@microchip.com +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/at91-sama5d2_adc.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c +index fe41689c5da6..ef6dc85024c1 100644 +--- a/drivers/iio/adc/at91-sama5d2_adc.c ++++ b/drivers/iio/adc/at91-sama5d2_adc.c +@@ -1353,10 +1353,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, + ret = at91_adc_read_position(st, chan->channel, + &tmp_val); + *val = tmp_val; +- mutex_unlock(&st->lock); +- iio_device_release_direct_mode(indio_dev); + if (ret > 0) + ret = at91_adc_adjust_val_osr(st, val); ++ mutex_unlock(&st->lock); ++ iio_device_release_direct_mode(indio_dev); + + return ret; + } +@@ -1369,10 +1369,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, + ret = at91_adc_read_pressure(st, chan->channel, + &tmp_val); + *val = tmp_val; +- mutex_unlock(&st->lock); +- iio_device_release_direct_mode(indio_dev); + if (ret > 0) + ret = at91_adc_adjust_val_osr(st, val); ++ mutex_unlock(&st->lock); ++ iio_device_release_direct_mode(indio_dev); + + return ret; + } +@@ -1465,16 +1465,20 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, + /* if no change, optimize out */ + if (val == st->oversampling_ratio) + return 0; ++ mutex_lock(&st->lock); + st->oversampling_ratio = val; + /* update ratio */ + at91_adc_config_emr(st); ++ mutex_unlock(&st->lock); + return 0; + case IIO_CHAN_INFO_SAMP_FREQ: + if (val < st->soc_info.min_sample_rate || + val > st->soc_info.max_sample_rate) + return -EINVAL; + ++ mutex_lock(&st->lock); + at91_adc_setup_samp_freq(indio_dev, val); ++ mutex_unlock(&st->lock); + return 0; + default: + return -EINVAL; +-- +2.35.1 + diff --git a/queue-5.10/iio-inkern-only-release-the-device-node-when-done-wi.patch b/queue-5.10/iio-inkern-only-release-the-device-node-when-done-wi.patch new file mode 100644 index 00000000000..ba55809f806 --- /dev/null +++ b/queue-5.10/iio-inkern-only-release-the-device-node-when-done-wi.patch @@ -0,0 +1,60 @@ +From db93aae1642281f169408ab67cce5e8d601848de Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Jul 2022 14:28:49 +0200 +Subject: iio: inkern: only release the device node when done with it +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nuno Sá + +[ Upstream commit 79c3e84874c7d14f04ad58313b64955a0d2e9437 ] + +'of_node_put()' can potentially release the memory pointed to by +'iiospec.np' which would leave us with an invalid pointer (and we would +still pass it in 'of_xlate()'). Note that it is not guaranteed for the +of_node lifespan to be attached to the device (to which is attached) +lifespan so that there is (even though very unlikely) the possibility +for the node to be freed while the device is still around. Thus, as there +are indeed some of_xlate users which do access the node, a race is indeed +possible. + +As such, we can only release the node after we are done with it. + +Fixes: 17d82b47a215d ("iio: Add OF support") +Signed-off-by: Nuno Sá +Link: https://lore.kernel.org/r/20220715122903.332535-2-nuno.sa@analog.com +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/inkern.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c +index 8c3faa797284..c32b2577dd99 100644 +--- a/drivers/iio/inkern.c ++++ b/drivers/iio/inkern.c +@@ -136,9 +136,10 @@ static int __of_iio_channel_get(struct iio_channel *channel, + + idev = bus_find_device(&iio_bus_type, NULL, iiospec.np, + iio_dev_node_match); +- of_node_put(iiospec.np); +- if (idev == NULL) ++ if (idev == NULL) { ++ of_node_put(iiospec.np); + return -EPROBE_DEFER; ++ } + + indio_dev = dev_to_iio_dev(idev); + channel->indio_dev = indio_dev; +@@ -146,6 +147,7 @@ static int __of_iio_channel_get(struct iio_channel *channel, + index = indio_dev->info->of_xlate(indio_dev, &iiospec); + else + index = __of_iio_simple_xlate(indio_dev, &iiospec); ++ of_node_put(iiospec.np); + if (index < 0) + goto err_put; + channel->channel = &indio_dev->channels[index]; +-- +2.35.1 + diff --git a/queue-5.10/iommu-iova-fix-module-config-properly.patch b/queue-5.10/iommu-iova-fix-module-config-properly.patch new file mode 100644 index 00000000000..ce3bf3750cd --- /dev/null +++ b/queue-5.10/iommu-iova-fix-module-config-properly.patch @@ -0,0 +1,43 @@ +From 0092b8083943aadc7e8f638f022a150fb6ce563f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 12:47:20 +0100 +Subject: iommu/iova: Fix module config properly + +From: Robin Murphy + +[ Upstream commit 4f58330fcc8482aa90674e1f40f601e82f18ed4a ] + +IOMMU_IOVA is intended to be an optional library for users to select as +and when they desire. Since it can be a module now, this means that +built-in code which has chosen not to select it should not fail to link +if it happens to have selected as a module by someone else. Replace +IS_ENABLED() with IS_REACHABLE() to do the right thing. + +CC: Thierry Reding +Reported-by: John Garry +Fixes: 15bbdec3931e ("iommu: Make the iova library a module") +Signed-off-by: Robin Murphy +Reviewed-by: Thierry Reding +Link: https://lore.kernel.org/r/548c2f683ca379aface59639a8f0cccc3a1ac050.1663069227.git.robin.murphy@arm.com +Signed-off-by: Joerg Roedel +Signed-off-by: Sasha Levin +--- + include/linux/iova.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/linux/iova.h b/include/linux/iova.h +index a0637abffee8..6c19b09e9663 100644 +--- a/include/linux/iova.h ++++ b/include/linux/iova.h +@@ -132,7 +132,7 @@ static inline unsigned long iova_pfn(struct iova_domain *iovad, dma_addr_t iova) + return iova >> iova_shift(iovad); + } + +-#if IS_ENABLED(CONFIG_IOMMU_IOVA) ++#if IS_REACHABLE(CONFIG_IOMMU_IOVA) + int iova_cache_get(void); + void iova_cache_put(void); + +-- +2.35.1 + diff --git a/queue-5.10/iommu-omap-fix-buffer-overflow-in-debugfs.patch b/queue-5.10/iommu-omap-fix-buffer-overflow-in-debugfs.patch new file mode 100644 index 00000000000..e1e223258e6 --- /dev/null +++ b/queue-5.10/iommu-omap-fix-buffer-overflow-in-debugfs.patch @@ -0,0 +1,53 @@ +From 007d341ed554fab9a50bf18ee0ac92811b3fced1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 4 Aug 2022 17:32:39 +0300 +Subject: iommu/omap: Fix buffer overflow in debugfs + +From: Dan Carpenter + +[ Upstream commit 184233a5202786b20220acd2d04ddf909ef18f29 ] + +There are two issues here: + +1) The "len" variable needs to be checked before the very first write. + Otherwise if omap2_iommu_dump_ctx() with "bytes" less than 32 it is a + buffer overflow. +2) The snprintf() function returns the number of bytes that *would* have + been copied if there were enough space. But we want to know the + number of bytes which were *actually* copied so use scnprintf() + instead. + +Fixes: bd4396f09a4a ("iommu/omap: Consolidate OMAP IOMMU modules") +Signed-off-by: Dan Carpenter +Reviewed-by: Robin Murphy +Reviewed-by: Laurent Pinchart +Link: https://lore.kernel.org/r/YuvYh1JbE3v+abd5@kili +Signed-off-by: Joerg Roedel +Signed-off-by: Sasha Levin +--- + drivers/iommu/omap-iommu-debug.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/iommu/omap-iommu-debug.c b/drivers/iommu/omap-iommu-debug.c +index a99afb5d9011..259f65291d90 100644 +--- a/drivers/iommu/omap-iommu-debug.c ++++ b/drivers/iommu/omap-iommu-debug.c +@@ -32,12 +32,12 @@ static inline bool is_omap_iommu_detached(struct omap_iommu *obj) + ssize_t bytes; \ + const char *str = "%20s: %08x\n"; \ + const int maxcol = 32; \ +- bytes = snprintf(p, maxcol, str, __stringify(name), \ ++ if (len < maxcol) \ ++ goto out; \ ++ bytes = scnprintf(p, maxcol, str, __stringify(name), \ + iommu_read_reg(obj, MMU_##name)); \ + p += bytes; \ + len -= bytes; \ +- if (len < maxcol) \ +- goto out; \ + } while (0) + + static ssize_t +-- +2.35.1 + diff --git a/queue-5.10/kbuild-remove-the-target-in-signal-traps-when-interr.patch b/queue-5.10/kbuild-remove-the-target-in-signal-traps-when-interr.patch new file mode 100644 index 00000000000..f8c8601df22 --- /dev/null +++ b/queue-5.10/kbuild-remove-the-target-in-signal-traps-when-interr.patch @@ -0,0 +1,172 @@ +From f2f0cba406747d7c4f5bb2c5b0ea8987058279b3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 7 Aug 2022 09:48:09 +0900 +Subject: kbuild: remove the target in signal traps when interrupted + +From: Masahiro Yamada + +[ Upstream commit a7f3257da8a86b96fb9bf1bba40ae0bbd7f1885a ] + +When receiving some signal, GNU Make automatically deletes the target if +it has already been changed by the interrupted recipe. + +If the target is possibly incomplete due to interruption, it must be +deleted so that it will be remade from scratch on the next run of make. +Otherwise, the target would remain corrupted permanently because its +timestamp had already been updated. + +Thanks to this behavior of Make, you can stop the build any time by +pressing Ctrl-C, and just run 'make' to resume it. + +Kbuild also relies on this feature, but it is equivalently important +for any build systems that make decisions based on timestamps (if you +want to support Ctrl-C reliably). + +However, this does not always work as claimed; Make immediately dies +with Ctrl-C if its stderr goes into a pipe. + + [Test Makefile] + + foo: + echo hello > $@ + sleep 3 + echo world >> $@ + + [Test Result] + + $ make # hit Ctrl-C + echo hello > foo + sleep 3 + ^Cmake: *** Deleting file 'foo' + make: *** [Makefile:3: foo] Interrupt + + $ make 2>&1 | cat # hit Ctrl-C + echo hello > foo + sleep 3 + ^C$ # 'foo' is often left-over + +The reason is because SIGINT is sent to the entire process group. +In this example, SIGINT kills 'cat', and 'make' writes the message to +the closed pipe, then dies with SIGPIPE before cleaning the target. + +A typical bad scenario (as reported by [1], [2]) is to save build log +by using the 'tee' command: + + $ make 2>&1 | tee log + +This can be problematic for any build systems based on Make, so I hope +it will be fixed in GNU Make. The maintainer of GNU Make stated this is +a long-standing issue and difficult to fix [3]. It has not been fixed +yet as of writing. + +So, we cannot rely on Make cleaning the target. We can do it by +ourselves, in signal traps. + +As far as I understand, Make takes care of SIGHUP, SIGINT, SIGQUIT, and +SITERM for the target removal. I added the traps for them, and also for +SIGPIPE just in case cmd_* rule prints something to stdout or stderr +(but I did not observe an actual case where SIGPIPE was triggered). + +[Note 1] + +The trap handler might be worth explaining. + + rm -f $@; trap - $(sig); kill -s $(sig) $$ + +This lets the shell kill itself by the signal it caught, so the parent +process can tell the child has exited on the signal. Generally, this is +a proper manner for handling signals, in case the calling program (like +Bash) may monitor WIFSIGNALED() and WTERMSIG() for WCE although this may +not be a big deal here because GNU Make handles SIGHUP, SIGINT, SIGQUIT +in WUE and SIGTERM in IUE. + + IUE - Immediate Unconditional Exit + WUE - Wait and Unconditional Exit + WCE - Wait and Cooperative Exit + +For details, see "Proper handling of SIGINT/SIGQUIT" [4]. + +[Note 2] + +Reverting 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd +files") would directly address [1], but it only saves if_changed_dep. +As reported in [2], all commands that use redirection can potentially +leave an empty (i.e. broken) target. + +[Note 3] + +Another (even safer) approach might be to always write to a temporary +file, and rename it to $@ at the end of the recipe. + + > $(tmp-target) + mv $(tmp-target) $@ + +It would require a lot of Makefile changes, and result in ugly code, +so I did not take it. + +[Note 4] + +A little more thoughts about a pattern rule with multiple targets (or +a grouped target). + + %.x %.y: %.z + + +When interrupted, GNU Make deletes both %.x and %.y, while this solution +only deletes $@. Probably, this is not a big deal. The next run of make +will execute the rule again to create $@ along with the other files. + +[1]: https://lore.kernel.org/all/YLeot94yAaM4xbMY@gmail.com/ +[2]: https://lore.kernel.org/all/20220510221333.2770571-1-robh@kernel.org/ +[3]: https://lists.gnu.org/archive/html/help-make/2021-06/msg00001.html +[4]: https://www.cons.org/cracauer/sigint.html + +Fixes: 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files") +Reported-by: Ingo Molnar +Reported-by: Rob Herring +Signed-off-by: Masahiro Yamada +Tested-by: Ingo Molnar +Reviewed-by: Nicolas Schier +Signed-off-by: Sasha Levin +--- + scripts/Kbuild.include | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include +index 0d6e11820791..25696de8114a 100644 +--- a/scripts/Kbuild.include ++++ b/scripts/Kbuild.include +@@ -179,8 +179,29 @@ echo-cmd = $(if $($(quiet)cmd_$(1)),\ + quiet_redirect := + silent_redirect := exec >/dev/null; + ++# Delete the target on interruption ++# ++# GNU Make automatically deletes the target if it has already been changed by ++# the interrupted recipe. So, you can safely stop the build by Ctrl-C (Make ++# will delete incomplete targets), and resume it later. ++# ++# However, this does not work when the stderr is piped to another program, like ++# $ make >&2 | tee log ++# Make dies with SIGPIPE before cleaning the targets. ++# ++# To address it, we clean the target in signal traps. ++# ++# Make deletes the target when it catches SIGHUP, SIGINT, SIGQUIT, SIGTERM. ++# So, we cover them, and also SIGPIPE just in case. ++# ++# Of course, this is unneeded for phony targets. ++delete-on-interrupt = \ ++ $(if $(filter-out $(PHONY), $@), \ ++ $(foreach sig, HUP INT QUIT TERM PIPE, \ ++ trap 'rm -f $@; trap - $(sig); kill -s $(sig) $$$$' $(sig);)) ++ + # printing commands +-cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(cmd_$(1)) ++cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(delete-on-interrupt) $(cmd_$(1)) + + ### + # if_changed - execute command if any prerequisite is newer than +-- +2.35.1 + diff --git a/queue-5.10/kbuild-rpm-pkg-fix-breakage-when-v-1-is-used.patch b/queue-5.10/kbuild-rpm-pkg-fix-breakage-when-v-1-is-used.patch new file mode 100644 index 00000000000..ba672fcb360 --- /dev/null +++ b/queue-5.10/kbuild-rpm-pkg-fix-breakage-when-v-1-is-used.patch @@ -0,0 +1,55 @@ +From 8c72a357e5c18c47f3ac5b66f6993bc24b653863 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 14:41:12 +0200 +Subject: kbuild: rpm-pkg: fix breakage when V=1 is used + +From: Janis Schoetterl-Glausch + +[ Upstream commit 2e07005f4813a9ff6e895787e0c2d1fea859b033 ] + +Doing make V=1 binrpm-pkg results in: + + Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.EgV6qJ + + umask 022 + + cd . + + /bin/rm -rf /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x + + /bin/mkdir -p /home/scgl/rpmbuild/BUILDROOT + + /bin/mkdir /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x + + mkdir -p /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x/boot + + make -f ./Makefile image_name + + cp test -e include/generated/autoconf.h -a -e include/config/auto.conf || ( \ echo >&2; \ echo >&2 " ERROR: Kernel configuration is invalid."; \ echo >&2 " include/generated/autoconf.h or include/config/auto.conf are missing.";\ echo >&2 " Run 'make oldconfig && make prepare' on kernel src to fix it."; \ echo >&2 ; \ /bin/false) arch/s390/boot/bzImage /home/scgl/rpmbuild/BUILDROOT/kernel-6.0.0_rc5+-1.s390x/boot/vmlinuz-6.0.0-rc5+ + cp: invalid option -- 'e' + Try 'cp --help' for more information. + error: Bad exit status from /var/tmp/rpm-tmp.EgV6qJ (%install) + +Because the make call to get the image name is verbose and prints +additional information. + +Fixes: 993bdde94547 ("kbuild: add image_name to no-sync-config-targets") +Signed-off-by: Janis Schoetterl-Glausch +Signed-off-by: Masahiro Yamada +Signed-off-by: Sasha Levin +--- + scripts/package/mkspec | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/scripts/package/mkspec b/scripts/package/mkspec +index 7c477ca7dc98..951cc60e5a90 100755 +--- a/scripts/package/mkspec ++++ b/scripts/package/mkspec +@@ -85,10 +85,10 @@ $S + mkdir -p %{buildroot}/boot + %ifarch ia64 + mkdir -p %{buildroot}/boot/efi +- cp \$($MAKE image_name) %{buildroot}/boot/efi/vmlinuz-$KERNELRELEASE ++ cp \$($MAKE -s image_name) %{buildroot}/boot/efi/vmlinuz-$KERNELRELEASE + ln -s efi/vmlinuz-$KERNELRELEASE %{buildroot}/boot/ + %else +- cp \$($MAKE image_name) %{buildroot}/boot/vmlinuz-$KERNELRELEASE ++ cp \$($MAKE -s image_name) %{buildroot}/boot/vmlinuz-$KERNELRELEASE + %endif + $M $MAKE %{?_smp_mflags} INSTALL_MOD_PATH=%{buildroot} modules_install + $MAKE %{?_smp_mflags} INSTALL_HDR_PATH=%{buildroot}/usr headers_install +-- +2.35.1 + diff --git a/queue-5.10/kernel-cgroup-mundane-spelling-fixes-throughout-the-.patch b/queue-5.10/kernel-cgroup-mundane-spelling-fixes-throughout-the-.patch new file mode 100644 index 00000000000..6da58948ccb --- /dev/null +++ b/queue-5.10/kernel-cgroup-mundane-spelling-fixes-throughout-the-.patch @@ -0,0 +1,125 @@ +From 1fad3a55dc0f84eb8ffe7ba543f23c27d118410e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 9 Nov 2020 16:01:11 +0530 +Subject: kernel: cgroup: Mundane spelling fixes throughout the file + +From: Bhaskar Chowdhury + +[ Upstream commit 58315c96651152b9f438e5e56c910994234e2c7a ] + +Few spelling fixes throughout the file. + +Signed-off-by: Bhaskar Chowdhury +Signed-off-by: Tejun Heo +Stable-dep-of: 74e4b956eb1c ("cgroup: Honor caller's cgroup NS when resolving path") +Signed-off-by: Sasha Levin +--- + kernel/cgroup/cgroup.c | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c +index 684c16849eff..0eb05cbafa71 100644 +--- a/kernel/cgroup/cgroup.c ++++ b/kernel/cgroup/cgroup.c +@@ -244,7 +244,7 @@ bool cgroup_ssid_enabled(int ssid) + * + * The default hierarchy is the v2 interface of cgroup and this function + * can be used to test whether a cgroup is on the default hierarchy for +- * cases where a subsystem should behave differnetly depending on the ++ * cases where a subsystem should behave differently depending on the + * interface version. + * + * List of changed behaviors: +@@ -262,7 +262,7 @@ bool cgroup_ssid_enabled(int ssid) + * "cgroup.procs" instead. + * + * - "cgroup.procs" is not sorted. pids will be unique unless they got +- * recycled inbetween reads. ++ * recycled in-between reads. + * + * - "release_agent" and "notify_on_release" are removed. Replacement + * notification mechanism will be implemented. +@@ -345,7 +345,7 @@ static bool cgroup_is_mixable(struct cgroup *cgrp) + return !cgroup_parent(cgrp); + } + +-/* can @cgrp become a thread root? should always be true for a thread root */ ++/* can @cgrp become a thread root? Should always be true for a thread root */ + static bool cgroup_can_be_thread_root(struct cgroup *cgrp) + { + /* mixables don't care */ +@@ -530,7 +530,7 @@ static struct cgroup_subsys_state *cgroup_e_css_by_mask(struct cgroup *cgrp, + * the root css is returned, so this function always returns a valid css. + * + * The returned css is not guaranteed to be online, and therefore it is the +- * callers responsiblity to tryget a reference for it. ++ * callers responsibility to try get a reference for it. + */ + struct cgroup_subsys_state *cgroup_e_css(struct cgroup *cgrp, + struct cgroup_subsys *ss) +@@ -702,7 +702,7 @@ EXPORT_SYMBOL_GPL(of_css); + ; \ + else + +-/* walk live descendants in preorder */ ++/* walk live descendants in pre order */ + #define cgroup_for_each_live_descendant_pre(dsct, d_css, cgrp) \ + css_for_each_descendant_pre((d_css), cgroup_css((cgrp), NULL)) \ + if (({ lockdep_assert_held(&cgroup_mutex); \ +@@ -937,7 +937,7 @@ void put_css_set_locked(struct css_set *cset) + + WARN_ON_ONCE(!list_empty(&cset->threaded_csets)); + +- /* This css_set is dead. unlink it and release cgroup and css refs */ ++ /* This css_set is dead. Unlink it and release cgroup and css refs */ + for_each_subsys(ss, ssid) { + list_del(&cset->e_cset_node[ssid]); + css_put(cset->subsys[ssid]); +@@ -1062,7 +1062,7 @@ static struct css_set *find_existing_css_set(struct css_set *old_cset, + + /* + * Build the set of subsystem state objects that we want to see in the +- * new css_set. while subsystems can change globally, the entries here ++ * new css_set. While subsystems can change globally, the entries here + * won't change, so no need for locking. + */ + for_each_subsys(ss, i) { +@@ -1152,7 +1152,7 @@ static void link_css_set(struct list_head *tmp_links, struct css_set *cset, + + /* + * Always add links to the tail of the lists so that the lists are +- * in choronological order. ++ * in chronological order. + */ + list_move_tail(&link->cset_link, &cgrp->cset_links); + list_add_tail(&link->cgrp_link, &cset->cgrp_links); +@@ -4242,7 +4242,7 @@ struct cgroup_subsys_state *css_next_child(struct cgroup_subsys_state *pos, + * implies that if we observe !CSS_RELEASED on @pos in this RCU + * critical section, the one pointed to by its next pointer is + * guaranteed to not have finished its RCU grace period even if we +- * have dropped rcu_read_lock() inbetween iterations. ++ * have dropped rcu_read_lock() in-between iterations. + * + * If @pos has CSS_RELEASED set, its next pointer can't be + * dereferenced; however, as each css is given a monotonically +@@ -4490,7 +4490,7 @@ static struct css_set *css_task_iter_next_css_set(struct css_task_iter *it) + } + + /** +- * css_task_iter_advance_css_set - advance a task itererator to the next css_set ++ * css_task_iter_advance_css_set - advance a task iterator to the next css_set + * @it: the iterator to advance + * + * Advance @it to the next css_set to walk. +@@ -6440,7 +6440,7 @@ struct cgroup_subsys_state *css_from_id(int id, struct cgroup_subsys *ss) + * + * Find the cgroup at @path on the default hierarchy, increment its + * reference count and return it. Returns pointer to the found cgroup on +- * success, ERR_PTR(-ENOENT) if @path doens't exist and ERR_PTR(-ENOTDIR) ++ * success, ERR_PTR(-ENOENT) if @path doesn't exist and ERR_PTR(-ENOTDIR) + * if @path points to a non-directory. + */ + struct cgroup *cgroup_get_from_path(const char *path) +-- +2.35.1 + diff --git a/queue-5.10/kselftest-arm64-fix-validatation-termination-record-.patch b/queue-5.10/kselftest-arm64-fix-validatation-termination-record-.patch new file mode 100644 index 00000000000..01a6649917d --- /dev/null +++ b/queue-5.10/kselftest-arm64-fix-validatation-termination-record-.patch @@ -0,0 +1,47 @@ +From 025ba01b5a4971ac91335b14e469ce706c55827b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 29 Aug 2022 17:06:56 +0100 +Subject: kselftest/arm64: Fix validatation termination record after + EXTRA_CONTEXT + +From: Mark Brown + +[ Upstream commit 5c152c2f66f9368394b89ac90dc7483476ef7b88 ] + +When arm64 signal context data overflows the base struct sigcontext it gets +placed in an extra buffer pointed to by a record of type EXTRA_CONTEXT in +the base struct sigcontext which is required to be the last record in the +base struct sigframe. The current validation code attempts to check this +by using GET_RESV_NEXT_HEAD() to step forward from the current record to +the next but that is a macro which assumes it is being provided with a +struct _aarch64_ctx and uses the size there to skip forward to the next +record. Instead validate_extra_context() passes it a struct extra_context +which has a separate size field. This compiles but results in us trying +to validate a termination record in completely the wrong place, at best +failing validation and at worst just segfaulting. Fix this by passing +the struct _aarch64_ctx we meant to into the macro. + +Signed-off-by: Mark Brown +Link: https://lore.kernel.org/r/20220829160703.874492-4-broonie@kernel.org +Signed-off-by: Catalin Marinas +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/arm64/signal/testcases/testcases.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.c b/tools/testing/selftests/arm64/signal/testcases/testcases.c +index 61ebcdf63831..a3ac5c2d8aac 100644 +--- a/tools/testing/selftests/arm64/signal/testcases/testcases.c ++++ b/tools/testing/selftests/arm64/signal/testcases/testcases.c +@@ -33,7 +33,7 @@ bool validate_extra_context(struct extra_context *extra, char **err) + return false; + + fprintf(stderr, "Validating EXTRA...\n"); +- term = GET_RESV_NEXT_HEAD(extra); ++ term = GET_RESV_NEXT_HEAD(&extra->head); + if (!term || term->magic || term->size) { + *err = "Missing terminator after EXTRA context"; + return false; +-- +2.35.1 + diff --git a/queue-5.10/kvm-nvmx-prioritize-tss-t-flag-dbs-over-monitor-trap.patch b/queue-5.10/kvm-nvmx-prioritize-tss-t-flag-dbs-over-monitor-trap.patch new file mode 100644 index 00000000000..899e0fb1dd8 --- /dev/null +++ b/queue-5.10/kvm-nvmx-prioritize-tss-t-flag-dbs-over-monitor-trap.patch @@ -0,0 +1,58 @@ +From 2d853043954ab12ddb74bedfbe14b11cb27722b4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 23:15:54 +0000 +Subject: KVM: nVMX: Prioritize TSS T-flag #DBs over Monitor Trap Flag + +From: Sean Christopherson + +[ Upstream commit b9d44f9091ac6c325fc2f7b7671b462fb36abbed ] + +Service TSS T-flag #DBs prior to pending MTFs, as such #DBs are higher +priority than MTF. KVM itself doesn't emulate TSS #DBs, and any such +exceptions injected from L1 will be handled by hardware (or morphed to +a fault-like exception if injection fails), but theoretically userspace +could pend a TSS T-flag #DB in conjunction with a pending MTF. + +Note, there's no known use case this fixes, it's purely to be technically +correct with respect to Intel's SDM. + +Cc: Oliver Upton +Cc: Peter Shier +Fixes: 5ef8acbdd687 ("KVM: nVMX: Emulate MTF when performing instruction emulation") +Signed-off-by: Sean Christopherson +Reviewed-by: Maxim Levitsky +Link: https://lore.kernel.org/r/20220830231614.3580124-8-seanjc@google.com +Signed-off-by: Paolo Bonzini +Signed-off-by: Sasha Levin +--- + arch/x86/kvm/vmx/nested.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c +index 9e17b7a89c4a..75117c625b62 100644 +--- a/arch/x86/kvm/vmx/nested.c ++++ b/arch/x86/kvm/vmx/nested.c +@@ -3875,15 +3875,17 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu) + } + + /* +- * Process any exceptions that are not debug traps before MTF. ++ * Process exceptions that are higher priority than Monitor Trap Flag: ++ * fault-like exceptions, TSS T flag #DB (not emulated by KVM, but ++ * could theoretically come in from userspace), and ICEBP (INT1). + * + * Note that only a pending nested run can block a pending exception. + * Otherwise an injected NMI/interrupt should either be + * lost or delivered to the nested hypervisor in the IDT_VECTORING_INFO, + * while delivering the pending exception. + */ +- +- if (vcpu->arch.exception.pending && !vmx_get_pending_dbg_trap(vcpu)) { ++ if (vcpu->arch.exception.pending && ++ !(vmx_get_pending_dbg_trap(vcpu) & ~DR6_BT)) { + if (vmx->nested.nested_run_pending) + return -EBUSY; + if (!nested_vmx_check_exception(vcpu, &exit_qual)) +-- +2.35.1 + diff --git a/queue-5.10/kvm-nvmx-treat-general-detect-db-dr7.gd-1-as-fault-l.patch b/queue-5.10/kvm-nvmx-treat-general-detect-db-dr7.gd-1-as-fault-l.patch new file mode 100644 index 00000000000..5f67aaf28b6 --- /dev/null +++ b/queue-5.10/kvm-nvmx-treat-general-detect-db-dr7.gd-1-as-fault-l.patch @@ -0,0 +1,95 @@ +From 9446b7ee3614175723ffa363b04b39867947ae15 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 23:15:53 +0000 +Subject: KVM: nVMX: Treat General Detect #DB (DR7.GD=1) as fault-like + +From: Sean Christopherson + +[ Upstream commit 8d178f460772ecdee8e6d72389b43a8d35a14ff5 ] + +Exclude General Detect #DBs, which have fault-like behavior but also have +a non-zero payload (DR6.BD=1), from nVMX's handling of pending debug +traps. Opportunistically rewrite the comment to better document what is +being checked, i.e. "has a non-zero payload" vs. "has a payload", and to +call out the many caveats surrounding #DBs that KVM dodges one way or +another. + +Cc: Oliver Upton +Cc: Peter Shier +Fixes: 684c0422da71 ("KVM: nVMX: Handle pending #DB when injecting INIT VM-exit") +Signed-off-by: Sean Christopherson +Reviewed-by: Maxim Levitsky +Link: https://lore.kernel.org/r/20220830231614.3580124-7-seanjc@google.com +Signed-off-by: Paolo Bonzini +Signed-off-by: Sasha Levin +--- + arch/x86/kvm/vmx/nested.c | 36 +++++++++++++++++++++++++----------- + 1 file changed, 25 insertions(+), 11 deletions(-) + +diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c +index 313ace5dc75b..9e17b7a89c4a 100644 +--- a/arch/x86/kvm/vmx/nested.c ++++ b/arch/x86/kvm/vmx/nested.c +@@ -3802,16 +3802,29 @@ static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, + } + + /* +- * Returns true if a debug trap is pending delivery. ++ * Returns true if a debug trap is (likely) pending delivery. Infer the class ++ * of a #DB (trap-like vs. fault-like) from the exception payload (to-be-DR6). ++ * Using the payload is flawed because code breakpoints (fault-like) and data ++ * breakpoints (trap-like) set the same bits in DR6 (breakpoint detected), i.e. ++ * this will return false positives if a to-be-injected code breakpoint #DB is ++ * pending (from KVM's perspective, but not "pending" across an instruction ++ * boundary). ICEBP, a.k.a. INT1, is also not reflected here even though it ++ * too is trap-like. + * +- * In KVM, debug traps bear an exception payload. As such, the class of a #DB +- * exception may be inferred from the presence of an exception payload. ++ * KVM "works" despite these flaws as ICEBP isn't currently supported by the ++ * emulator, Monitor Trap Flag is not marked pending on intercepted #DBs (the ++ * #DB has already happened), and MTF isn't marked pending on code breakpoints ++ * from the emulator (because such #DBs are fault-like and thus don't trigger ++ * actions that fire on instruction retire). + */ +-static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu) ++static inline unsigned long vmx_get_pending_dbg_trap(struct kvm_vcpu *vcpu) + { +- return vcpu->arch.exception.pending && +- vcpu->arch.exception.nr == DB_VECTOR && +- vcpu->arch.exception.payload; ++ if (!vcpu->arch.exception.pending || ++ vcpu->arch.exception.nr != DB_VECTOR) ++ return 0; ++ ++ /* General Detect #DBs are always fault-like. */ ++ return vcpu->arch.exception.payload & ~DR6_BD; + } + + /* +@@ -3823,9 +3836,10 @@ static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu) + */ + static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu) + { +- if (vmx_pending_dbg_trap(vcpu)) +- vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, +- vcpu->arch.exception.payload); ++ unsigned long pending_dbg = vmx_get_pending_dbg_trap(vcpu); ++ ++ if (pending_dbg) ++ vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, pending_dbg); + } + + static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu) +@@ -3869,7 +3883,7 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu) + * while delivering the pending exception. + */ + +- if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) { ++ if (vcpu->arch.exception.pending && !vmx_get_pending_dbg_trap(vcpu)) { + if (vmx->nested.nested_run_pending) + return -EBUSY; + if (!nested_vmx_check_exception(vcpu, &exit_qual)) +-- +2.35.1 + diff --git a/queue-5.10/kvm-x86-mmu-fix-memoryleak-in-kvm_mmu_vendor_module_.patch b/queue-5.10/kvm-x86-mmu-fix-memoryleak-in-kvm_mmu_vendor_module_.patch new file mode 100644 index 00000000000..888cd7b2547 --- /dev/null +++ b/queue-5.10/kvm-x86-mmu-fix-memoryleak-in-kvm_mmu_vendor_module_.patch @@ -0,0 +1,44 @@ +From 09a1003ff5a10abef7dafb153b0fea05c19e3ff9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 23 Aug 2022 14:32:37 +0800 +Subject: KVM: x86/mmu: fix memoryleak in kvm_mmu_vendor_module_init() + +From: Miaohe Lin + +[ Upstream commit d7c9bfb9caaffd496ae44b258ec7c793677d3eeb ] + +When register_shrinker() fails, KVM doesn't release the percpu counter +kvm_total_used_mmu_pages leading to memoryleak. Fix this issue by calling +percpu_counter_destroy() when register_shrinker() fails. + +Fixes: ab271bd4dfd5 ("x86: kvm: propagate register_shrinker return code") +Signed-off-by: Miaohe Lin +Link: https://lore.kernel.org/r/20220823063237.47299-1-linmiaohe@huawei.com +[sean: tweak shortlog and changelog] +Signed-off-by: Sean Christopherson +Signed-off-by: Sasha Levin +--- + arch/x86/kvm/mmu/mmu.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c +index 13bf3198d0ce..982529bcdf30 100644 +--- a/arch/x86/kvm/mmu/mmu.c ++++ b/arch/x86/kvm/mmu/mmu.c +@@ -5932,10 +5932,12 @@ int kvm_mmu_vendor_module_init(void) + + ret = register_shrinker(&mmu_shrinker); + if (ret) +- goto out; ++ goto out_shrinker; + + return 0; + ++out_shrinker: ++ percpu_counter_destroy(&kvm_total_used_mmu_pages); + out: + mmu_destroy_caches(); + return ret; +-- +2.35.1 + diff --git a/queue-5.10/kvm-x86-pending-exceptions-must-not-be-blocked-by-an.patch b/queue-5.10/kvm-x86-pending-exceptions-must-not-be-blocked-by-an.patch new file mode 100644 index 00000000000..e55ad891ffb --- /dev/null +++ b/queue-5.10/kvm-x86-pending-exceptions-must-not-be-blocked-by-an.patch @@ -0,0 +1,81 @@ +From d05bdb66e941d57a57168e4eb9f769add88a7afd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Apr 2021 17:38:14 +0300 +Subject: KVM: x86: pending exceptions must not be blocked by an injected event + +From: Maxim Levitsky + +[ Upstream commit 4020da3b9f0c7e403b654c43da989f8c0bb05b57 ] + +Injected interrupts/nmi should not block a pending exception, +but rather be either lost if nested hypervisor doesn't +intercept the pending exception (as in stock x86), or be delivered +in exitintinfo/IDT_VECTORING_INFO field, as a part of a VMexit +that corresponds to the pending exception. + +The only reason for an exception to be blocked is when nested run +is pending (and that can't really happen currently +but still worth checking for). + +Signed-off-by: Maxim Levitsky +Message-Id: <20210401143817.1030695-2-mlevitsk@redhat.com> +Signed-off-by: Paolo Bonzini +Stable-dep-of: 8d178f460772 ("KVM: nVMX: Treat General Detect #DB (DR7.GD=1) as fault-like") +Signed-off-by: Sasha Levin +--- + arch/x86/kvm/svm/nested.c | 8 +++++++- + arch/x86/kvm/vmx/nested.c | 10 ++++++++-- + 2 files changed, 15 insertions(+), 3 deletions(-) + +diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c +index e7feaa7910ab..5277edd4825f 100644 +--- a/arch/x86/kvm/svm/nested.c ++++ b/arch/x86/kvm/svm/nested.c +@@ -1025,7 +1025,13 @@ static int svm_check_nested_events(struct kvm_vcpu *vcpu) + } + + if (vcpu->arch.exception.pending) { +- if (block_nested_events) ++ /* ++ * Only a pending nested run can block a pending exception. ++ * Otherwise an injected NMI/interrupt should either be ++ * lost or delivered to the nested hypervisor in the EXITINTINFO ++ * vmcb field, while delivering the pending exception. ++ */ ++ if (svm->nested.nested_run_pending) + return -EBUSY; + if (!nested_exit_on_exception(svm)) + return 0; +diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c +index 7f15e2b2a0d6..313ace5dc75b 100644 +--- a/arch/x86/kvm/vmx/nested.c ++++ b/arch/x86/kvm/vmx/nested.c +@@ -3862,9 +3862,15 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu) + + /* + * Process any exceptions that are not debug traps before MTF. ++ * ++ * Note that only a pending nested run can block a pending exception. ++ * Otherwise an injected NMI/interrupt should either be ++ * lost or delivered to the nested hypervisor in the IDT_VECTORING_INFO, ++ * while delivering the pending exception. + */ ++ + if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) { +- if (block_nested_events) ++ if (vmx->nested.nested_run_pending) + return -EBUSY; + if (!nested_vmx_check_exception(vcpu, &exit_qual)) + goto no_vmexit; +@@ -3881,7 +3887,7 @@ static int vmx_check_nested_events(struct kvm_vcpu *vcpu) + } + + if (vcpu->arch.exception.pending) { +- if (block_nested_events) ++ if (vmx->nested.nested_run_pending) + return -EBUSY; + if (!nested_vmx_check_exception(vcpu, &exit_qual)) + goto no_vmexit; +-- +2.35.1 + diff --git a/queue-5.10/leds-lm3601x-don-t-use-mutex-after-it-was-destroyed.patch b/queue-5.10/leds-lm3601x-don-t-use-mutex-after-it-was-destroyed.patch new file mode 100644 index 00000000000..99b48ffd73a --- /dev/null +++ b/queue-5.10/leds-lm3601x-don-t-use-mutex-after-it-was-destroyed.patch @@ -0,0 +1,41 @@ +From a0f60f209cec870eb072c9918ad4d0a49ff21e56 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Aug 2022 10:02:27 +0200 +Subject: leds: lm3601x: Don't use mutex after it was destroyed +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +[ Upstream commit 32f7eed0c763a9b89f6b357ec54b48398fc7b99e ] + +The mutex might still be in use until the devm cleanup callback +devm_led_classdev_flash_release() is called. This only happens some time +after lm3601x_remove() completed. + +Fixes: e63a744871a3 ("leds: lm3601x: Convert class registration to device managed") +Acked-by: Pavel Machek +Signed-off-by: Uwe Kleine-König +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/leds/leds-lm3601x.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/leds/leds-lm3601x.c b/drivers/leds/leds-lm3601x.c +index d0e1d4814042..3d1272748201 100644 +--- a/drivers/leds/leds-lm3601x.c ++++ b/drivers/leds/leds-lm3601x.c +@@ -444,8 +444,6 @@ static int lm3601x_remove(struct i2c_client *client) + { + struct lm3601x_led *led = i2c_get_clientdata(client); + +- mutex_destroy(&led->lock); +- + return regmap_update_bits(led->regmap, LM3601X_ENABLE_REG, + LM3601X_ENABLE_MASK, + LM3601X_MODE_STANDBY); +-- +2.35.1 + diff --git a/queue-5.10/libbpf-fix-overrun-in-netlink-attribute-iteration.patch b/queue-5.10/libbpf-fix-overrun-in-netlink-attribute-iteration.patch new file mode 100644 index 00000000000..9f11dcc5b2e --- /dev/null +++ b/queue-5.10/libbpf-fix-overrun-in-netlink-attribute-iteration.patch @@ -0,0 +1,38 @@ +From 71d964580399a616a710452a3029771756c752e7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 17:07:08 +0800 +Subject: libbpf: Fix overrun in netlink attribute iteration + +From: Xin Liu + +[ Upstream commit 51e05a8cf8eb34da7473823b7f236a77adfef0b4 ] + +I accidentally found that a change in commit 1045b03e07d8 ("netlink: fix +overrun in attribute iteration") was not synchronized to the function +`nla_ok` in tools/lib/bpf/nlattr.c, I think it is necessary to modify, +this patch will do it. + +Signed-off-by: Xin Liu +Signed-off-by: Andrii Nakryiko +Link: https://lore.kernel.org/bpf/20220930090708.62394-1-liuxin350@huawei.com +Signed-off-by: Sasha Levin +--- + tools/lib/bpf/nlattr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/lib/bpf/nlattr.c b/tools/lib/bpf/nlattr.c +index b607fa9852b1..8f00a2ee5762 100644 +--- a/tools/lib/bpf/nlattr.c ++++ b/tools/lib/bpf/nlattr.c +@@ -32,7 +32,7 @@ static struct nlattr *nla_next(const struct nlattr *nla, int *remaining) + + static int nla_ok(const struct nlattr *nla, int remaining) + { +- return remaining >= sizeof(*nla) && ++ return remaining >= (int)sizeof(*nla) && + nla->nla_len >= sizeof(*nla) && + nla->nla_len <= remaining; + } +-- +2.35.1 + diff --git a/queue-5.10/mailbox-bcm-ferxrm-mailbox-fix-error-check-for-dma_m.patch b/queue-5.10/mailbox-bcm-ferxrm-mailbox-fix-error-check-for-dma_m.patch new file mode 100644 index 00000000000..a685cbbc835 --- /dev/null +++ b/queue-5.10/mailbox-bcm-ferxrm-mailbox-fix-error-check-for-dma_m.patch @@ -0,0 +1,47 @@ +From 8b407e5ab0abe5da3726216105819d1a1ff57ed8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Aug 2022 12:13:35 +0200 +Subject: mailbox: bcm-ferxrm-mailbox: Fix error check for dma_map_sg + +From: Jack Wang + +[ Upstream commit 6b207ce8a96a71e966831e3a13c38143ba9a73c1 ] + +dma_map_sg return 0 on error, fix the error check, and return -EIO +to caller. + +Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager") +Signed-off-by: Jack Wang +Signed-off-by: Jassi Brar +Signed-off-by: Sasha Levin +--- + drivers/mailbox/bcm-flexrm-mailbox.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/mailbox/bcm-flexrm-mailbox.c b/drivers/mailbox/bcm-flexrm-mailbox.c +index bee33abb5308..e913ed1e34c6 100644 +--- a/drivers/mailbox/bcm-flexrm-mailbox.c ++++ b/drivers/mailbox/bcm-flexrm-mailbox.c +@@ -632,15 +632,15 @@ static int flexrm_spu_dma_map(struct device *dev, struct brcm_message *msg) + + rc = dma_map_sg(dev, msg->spu.src, sg_nents(msg->spu.src), + DMA_TO_DEVICE); +- if (rc < 0) +- return rc; ++ if (!rc) ++ return -EIO; + + rc = dma_map_sg(dev, msg->spu.dst, sg_nents(msg->spu.dst), + DMA_FROM_DEVICE); +- if (rc < 0) { ++ if (!rc) { + dma_unmap_sg(dev, msg->spu.src, sg_nents(msg->spu.src), + DMA_TO_DEVICE); +- return rc; ++ return -EIO; + } + + return 0; +-- +2.35.1 + diff --git a/queue-5.10/md-add-support-for-req_nowait.patch b/queue-5.10/md-add-support-for-req_nowait.patch new file mode 100644 index 00000000000..62dd91abc21 --- /dev/null +++ b/queue-5.10/md-add-support-for-req_nowait.patch @@ -0,0 +1,125 @@ +From 929292d385fdaedbcf18f678274decba022cdac8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Dec 2021 20:06:19 +0000 +Subject: md: add support for REQ_NOWAIT + +From: Vishal Verma + +[ Upstream commit f51d46d0e7cb5b8494aa534d276a9d8915a2443d ] + +commit 021a24460dc2 ("block: add QUEUE_FLAG_NOWAIT") added support +for checking whether a given bdev supports handling of REQ_NOWAIT or not. +Since then commit 6abc49468eea ("dm: add support for REQ_NOWAIT and enable +it for linear target") added support for REQ_NOWAIT for dm. This uses +a similar approach to incorporate REQ_NOWAIT for md based bios. + +This patch was tested using t/io_uring tool within FIO. A nvme drive +was partitioned into 2 partitions and a simple raid 0 configuration +/dev/md0 was created. + +md0 : active raid0 nvme4n1p1[1] nvme4n1p2[0] + 937423872 blocks super 1.2 512k chunks + +Before patch: + +$ ./t/io_uring /dev/md0 -p 0 -a 0 -d 1 -r 100 + +Running top while the above runs: + +$ ps -eL | grep $(pidof io_uring) + + 38396 38396 pts/2 00:00:00 io_uring + 38396 38397 pts/2 00:00:15 io_uring + 38396 38398 pts/2 00:00:13 iou-wrk-38397 + +We can see iou-wrk-38397 io worker thread created which gets created +when io_uring sees that the underlying device (/dev/md0 in this case) +doesn't support nowait. + +After patch: + +$ ./t/io_uring /dev/md0 -p 0 -a 0 -d 1 -r 100 + +Running top while the above runs: + +$ ps -eL | grep $(pidof io_uring) + + 38341 38341 pts/2 00:10:22 io_uring + 38341 38342 pts/2 00:10:37 io_uring + +After running this patch, we don't see any io worker thread +being created which indicated that io_uring saw that the +underlying device does support nowait. This is the exact behaviour +noticed on a dm device which also supports nowait. + +For all the other raid personalities except raid0, we would need +to train pieces which involves make_request fn in order for them +to correctly handle REQ_NOWAIT. + +Reviewed-by: Jens Axboe +Signed-off-by: Vishal Verma +Signed-off-by: Song Liu +Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf") +Signed-off-by: Sasha Levin +--- + drivers/md/md.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/drivers/md/md.c b/drivers/md/md.c +index 0043dec37a87..c5363d2310e9 100644 +--- a/drivers/md/md.c ++++ b/drivers/md/md.c +@@ -434,6 +434,12 @@ void md_handle_request(struct mddev *mddev, struct bio *bio) + rcu_read_lock(); + if (is_suspended(mddev, bio)) { + DEFINE_WAIT(__wait); ++ /* Bail out if REQ_NOWAIT is set for the bio */ ++ if (bio->bi_opf & REQ_NOWAIT) { ++ rcu_read_unlock(); ++ bio_wouldblock_error(bio); ++ return; ++ } + for (;;) { + prepare_to_wait(&mddev->sb_wait, &__wait, + TASK_UNINTERRUPTIBLE); +@@ -5817,6 +5823,7 @@ int md_run(struct mddev *mddev) + int err; + struct md_rdev *rdev; + struct md_personality *pers; ++ bool nowait = true; + + if (list_empty(&mddev->disks)) + /* cannot run an array with no devices.. */ +@@ -5889,8 +5896,13 @@ int md_run(struct mddev *mddev) + } + } + sysfs_notify_dirent_safe(rdev->sysfs_state); ++ nowait = nowait && blk_queue_nowait(bdev_get_queue(rdev->bdev)); + } + ++ /* Set the NOWAIT flags if all underlying devices support it */ ++ if (nowait) ++ blk_queue_flag_set(QUEUE_FLAG_NOWAIT, mddev->queue); ++ + if (!bioset_initialized(&mddev->bio_set)) { + err = bioset_init(&mddev->bio_set, BIO_POOL_SIZE, 0, BIOSET_NEED_BVECS); + if (err) +@@ -7023,6 +7035,15 @@ static int hot_add_disk(struct mddev *mddev, dev_t dev) + set_bit(MD_SB_CHANGE_DEVS, &mddev->sb_flags); + if (!mddev->thread) + md_update_sb(mddev, 1); ++ /* ++ * If the new disk does not support REQ_NOWAIT, ++ * disable on the whole MD. ++ */ ++ if (!blk_queue_nowait(bdev_get_queue(rdev->bdev))) { ++ pr_info("%s: Disabling nowait because %s does not support nowait\n", ++ mdname(mddev), bdevname(rdev->bdev, b)); ++ blk_queue_flag_clear(QUEUE_FLAG_NOWAIT, mddev->queue); ++ } + /* + * Kick recovery, maybe this spare has to be added to the + * array immediately. +-- +2.35.1 + diff --git a/queue-5.10/md-raid1-rename-print_msg-with-r1bio_existed.patch b/queue-5.10/md-raid1-rename-print_msg-with-r1bio_existed.patch new file mode 100644 index 00000000000..e389ae02f47 --- /dev/null +++ b/queue-5.10/md-raid1-rename-print_msg-with-r1bio_existed.patch @@ -0,0 +1,64 @@ +From 6e1e82a8c27fbabd5ccde79138067a6be4a09373 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 May 2021 17:46:20 +0800 +Subject: md/raid1: rename print_msg with r1bio_existed + +From: Guoqing Jiang + +[ Upstream commit 9b8ae7b938235229ccb112c4e887ff1bcc232836 ] + +The caller of raid1_read_request could pass NULL or a valid pointer for +"struct r1bio *r1_bio", so it actually means whether r1_bio is existed +or not. + +Signed-off-by: Guoqing Jiang +Signed-off-by: Song Liu +Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf") +Signed-off-by: Sasha Levin +--- + drivers/md/raid1.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c +index fb31e5dd54a6..b08f44c791fa 100644 +--- a/drivers/md/raid1.c ++++ b/drivers/md/raid1.c +@@ -1208,7 +1208,7 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio, + const unsigned long do_sync = (bio->bi_opf & REQ_SYNC); + int max_sectors; + int rdisk; +- bool print_msg = !!r1_bio; ++ bool r1bio_existed = !!r1_bio; + char b[BDEVNAME_SIZE]; + + /* +@@ -1218,7 +1218,7 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio, + */ + gfp_t gfp = r1_bio ? (GFP_NOIO | __GFP_HIGH) : GFP_NOIO; + +- if (print_msg) { ++ if (r1bio_existed) { + /* Need to get the block device name carefully */ + struct md_rdev *rdev; + rcu_read_lock(); +@@ -1250,7 +1250,7 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio, + + if (rdisk < 0) { + /* couldn't find anywhere to read from */ +- if (print_msg) { ++ if (r1bio_existed) { + pr_crit_ratelimited("md/raid1:%s: %s: unrecoverable I/O read error for block %llu\n", + mdname(mddev), + b, +@@ -1261,7 +1261,7 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio, + } + mirror = conf->mirrors + rdisk; + +- if (print_msg) ++ if (r1bio_existed) + pr_info_ratelimited("md/raid1:%s: redirecting sector %llu to other mirror: %s\n", + mdname(mddev), + (unsigned long long)r1_bio->sector, +-- +2.35.1 + diff --git a/queue-5.10/md-raid5-add-__rcu-annotation-to-struct-disk_info.patch b/queue-5.10/md-raid5-add-__rcu-annotation-to-struct-disk_info.patch new file mode 100644 index 00000000000..9502e4bd7b9 --- /dev/null +++ b/queue-5.10/md-raid5-add-__rcu-annotation-to-struct-disk_info.patch @@ -0,0 +1,189 @@ +From 15c650ecd97cf5cb7fceed12dfb2d0561eb4353b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Apr 2022 10:57:09 -0600 +Subject: md/raid5: Add __rcu annotation to struct disk_info + +From: Logan Gunthorpe + +[ Upstream commit b0920ede081b3f1659872f80ce552305610675a6 ] + +rdev and replacement are protected in some circumstances with +rcu_dereference and synchronize_rcu (in raid5_remove_disk()). However, +they were not annotated with __rcu so a sparse warning is emitted for +every rcu_dereference() call. + +Add the __rcu annotation and fix up the initialization with +RCU_INIT_POINTER, all pointer modifications with rcu_assign_pointer(), +a few cases where the pointer value is tested with rcu_access_pointer() +and one case where READ_ONCE() is used instead of rcu_dereference(), +a case in print_raid5_conf() that should have rcu_dereference() and +rcu_read_[un]lock() calls. + +Additional sparse issues will be fixed up in further commits. + +Signed-off-by: Logan Gunthorpe +Reviewed-by: Christoph Hellwig +Signed-off-by: Song Liu +Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf") +Signed-off-by: Sasha Levin +--- + drivers/md/raid5.c | 46 ++++++++++++++++++++++++++-------------------- + drivers/md/raid5.h | 3 ++- + 2 files changed, 28 insertions(+), 21 deletions(-) + +diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c +index 01c7edf32936..0a941d62398f 100644 +--- a/drivers/md/raid5.c ++++ b/drivers/md/raid5.c +@@ -6282,7 +6282,7 @@ static inline sector_t raid5_sync_request(struct mddev *mddev, sector_t sector_n + */ + rcu_read_lock(); + for (i = 0; i < conf->raid_disks; i++) { +- struct md_rdev *rdev = READ_ONCE(conf->disks[i].rdev); ++ struct md_rdev *rdev = rcu_dereference(conf->disks[i].rdev); + + if (rdev == NULL || test_bit(Faulty, &rdev->flags)) + still_degraded = 1; +@@ -7310,11 +7310,11 @@ static struct r5conf *setup_conf(struct mddev *mddev) + if (test_bit(Replacement, &rdev->flags)) { + if (disk->replacement) + goto abort; +- disk->replacement = rdev; ++ RCU_INIT_POINTER(disk->replacement, rdev); + } else { + if (disk->rdev) + goto abort; +- disk->rdev = rdev; ++ RCU_INIT_POINTER(disk->rdev, rdev); + } + + if (test_bit(In_sync, &rdev->flags)) { +@@ -7605,11 +7605,11 @@ static int raid5_run(struct mddev *mddev) + rdev = conf->disks[i].replacement; + conf->disks[i].replacement = NULL; + clear_bit(Replacement, &rdev->flags); +- conf->disks[i].rdev = rdev; ++ rcu_assign_pointer(conf->disks[i].rdev, rdev); + } + if (!rdev) + continue; +- if (conf->disks[i].replacement && ++ if (rcu_access_pointer(conf->disks[i].replacement) && + conf->reshape_progress != MaxSector) { + /* replacements and reshape simply do not mix. */ + pr_warn("md: cannot handle concurrent replacement and reshape.\n"); +@@ -7810,8 +7810,8 @@ static void raid5_status(struct seq_file *seq, struct mddev *mddev) + + static void print_raid5_conf (struct r5conf *conf) + { ++ struct md_rdev *rdev; + int i; +- struct disk_info *tmp; + + pr_debug("RAID conf printout:\n"); + if (!conf) { +@@ -7822,14 +7822,16 @@ static void print_raid5_conf (struct r5conf *conf) + conf->raid_disks, + conf->raid_disks - conf->mddev->degraded); + ++ rcu_read_lock(); + for (i = 0; i < conf->raid_disks; i++) { + char b[BDEVNAME_SIZE]; +- tmp = conf->disks + i; +- if (tmp->rdev) ++ rdev = rcu_dereference(conf->disks[i].rdev); ++ if (rdev) + pr_debug(" disk %d, o:%d, dev:%s\n", +- i, !test_bit(Faulty, &tmp->rdev->flags), +- bdevname(tmp->rdev->bdev, b)); ++ i, !test_bit(Faulty, &rdev->flags), ++ bdevname(rdev->bdev, b)); + } ++ rcu_read_unlock(); + } + + static int raid5_spare_active(struct mddev *mddev) +@@ -7880,8 +7882,9 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev) + struct r5conf *conf = mddev->private; + int err = 0; + int number = rdev->raid_disk; +- struct md_rdev **rdevp; ++ struct md_rdev __rcu **rdevp; + struct disk_info *p = conf->disks + number; ++ struct md_rdev *tmp; + + print_raid5_conf(conf); + if (test_bit(Journal, &rdev->flags) && conf->log) { +@@ -7899,9 +7902,9 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev) + log_exit(conf); + return 0; + } +- if (rdev == p->rdev) ++ if (rdev == rcu_access_pointer(p->rdev)) + rdevp = &p->rdev; +- else if (rdev == p->replacement) ++ else if (rdev == rcu_access_pointer(p->replacement)) + rdevp = &p->replacement; + else + return 0; +@@ -7921,7 +7924,8 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev) + if (!test_bit(Faulty, &rdev->flags) && + mddev->recovery_disabled != conf->recovery_disabled && + !has_failed(conf) && +- (!p->replacement || p->replacement == rdev) && ++ (!rcu_access_pointer(p->replacement) || ++ rcu_access_pointer(p->replacement) == rdev) && + number < conf->raid_disks) { + err = -EBUSY; + goto abort; +@@ -7932,7 +7936,7 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev) + if (atomic_read(&rdev->nr_pending)) { + /* lost the race, try later */ + err = -EBUSY; +- *rdevp = rdev; ++ rcu_assign_pointer(*rdevp, rdev); + } + } + if (!err) { +@@ -7940,17 +7944,19 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev) + if (err) + goto abort; + } +- if (p->replacement) { ++ ++ tmp = rcu_access_pointer(p->replacement); ++ if (tmp) { + /* We must have just cleared 'rdev' */ +- p->rdev = p->replacement; +- clear_bit(Replacement, &p->replacement->flags); ++ rcu_assign_pointer(p->rdev, tmp); ++ clear_bit(Replacement, &tmp->flags); + smp_mb(); /* Make sure other CPUs may see both as identical + * but will never see neither - if they are careful + */ +- p->replacement = NULL; ++ rcu_assign_pointer(p->replacement, NULL); + + if (!err) +- err = log_modify(conf, p->rdev, true); ++ err = log_modify(conf, tmp, true); + } + + clear_bit(WantReplacement, &rdev->flags); +diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h +index 5c05acf20e1f..666943926554 100644 +--- a/drivers/md/raid5.h ++++ b/drivers/md/raid5.h +@@ -472,7 +472,8 @@ enum { + */ + + struct disk_info { +- struct md_rdev *rdev, *replacement; ++ struct md_rdev __rcu *rdev; ++ struct md_rdev __rcu *replacement; + struct page *extra_page; /* extra page to use in prexor */ + }; + +-- +2.35.1 + diff --git a/queue-5.10/md-raid5-ensure-stripe_fill-happens-on-non-read-io-w.patch b/queue-5.10/md-raid5-ensure-stripe_fill-happens-on-non-read-io-w.patch new file mode 100644 index 00000000000..dd76992bd1d --- /dev/null +++ b/queue-5.10/md-raid5-ensure-stripe_fill-happens-on-non-read-io-w.patch @@ -0,0 +1,48 @@ +From e499964e145e49c2ca2564e71d649eebd2e9c677 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 09:46:27 -0600 +Subject: md/raid5: Ensure stripe_fill happens on non-read IO with journal + +From: Logan Gunthorpe + +[ Upstream commit e2eed85bc75138a9eeb63863d20f8904ac42a577 ] + +When doing degrade/recover tests using the journal a kernel BUG +is hit at drivers/md/raid5.c:4381 in handle_parity_checks5(): + + BUG_ON(!test_bit(R5_UPTODATE, &dev->flags)); + +This was found to occur because handle_stripe_fill() was skipped +for stripes in the journal due to a condition in that function. +Thus blocks were not fetched and R5_UPTODATE was not set when +the code reached handle_parity_checks5(). + +To fix this, don't skip handle_stripe_fill() unless the stripe is +for read. + +Fixes: 07e83364845e ("md/r5cache: shift complex rmw from read path to write path") +Link: https://lore.kernel.org/linux-raid/e05c4239-41a9-d2f7-3cfa-4aa9d2cea8c1@deltatee.com/ +Suggested-by: Song Liu +Signed-off-by: Logan Gunthorpe +Signed-off-by: Song Liu +Signed-off-by: Sasha Levin +--- + drivers/md/raid5.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c +index ee0746fef417..ecc6214b8e43 100644 +--- a/drivers/md/raid5.c ++++ b/drivers/md/raid5.c +@@ -3933,7 +3933,7 @@ static void handle_stripe_fill(struct stripe_head *sh, + * back cache (prexor with orig_page, and then xor with + * page) in the read path + */ +- if (s->injournal && s->failed) { ++ if (s->to_read && s->injournal && s->failed) { + if (test_bit(STRIPE_R5C_CACHING, &sh->state)) + r5c_make_stripe_write_out(sh); + goto out; +-- +2.35.1 + diff --git a/queue-5.10/md-raid5-wait-for-md_sb_change_pending-in-raid5d.patch b/queue-5.10/md-raid5-wait-for-md_sb_change_pending-in-raid5d.patch new file mode 100644 index 00000000000..a90fb53a457 --- /dev/null +++ b/queue-5.10/md-raid5-wait-for-md_sb_change_pending-in-raid5d.patch @@ -0,0 +1,145 @@ +From 0f1e87415edd0395817b5e0180a1cca80f72e7e7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 10:28:37 -0600 +Subject: md/raid5: Wait for MD_SB_CHANGE_PENDING in raid5d + +From: Logan Gunthorpe + +[ Upstream commit 5e2cf333b7bd5d3e62595a44d598a254c697cd74 ] + +A complicated deadlock exists when using the journal and an elevated +group_thrtead_cnt. It was found with loop devices, but its not clear +whether it can be seen with real disks. The deadlock can occur simply +by writing data with an fio script. + +When the deadlock occurs, multiple threads will hang in different ways: + + 1) The group threads will hang in the blk-wbt code with bios waiting to + be submitted to the block layer: + + io_schedule+0x70/0xb0 + rq_qos_wait+0x153/0x210 + wbt_wait+0x115/0x1b0 + io_schedule+0x70/0xb0 + rq_qos_wait+0x153/0x210 + wbt_wait+0x115/0x1b0 + __rq_qos_throttle+0x38/0x60 + blk_mq_submit_bio+0x589/0xcd0 + wbt_wait+0x115/0x1b0 + __rq_qos_throttle+0x38/0x60 + blk_mq_submit_bio+0x589/0xcd0 + __submit_bio+0xe6/0x100 + submit_bio_noacct_nocheck+0x42e/0x470 + submit_bio_noacct+0x4c2/0xbb0 + ops_run_io+0x46b/0x1a30 + handle_stripe+0xcd3/0x36b0 + handle_active_stripes.constprop.0+0x6f6/0xa60 + raid5_do_work+0x177/0x330 + + Or: + io_schedule+0x70/0xb0 + rq_qos_wait+0x153/0x210 + wbt_wait+0x115/0x1b0 + __rq_qos_throttle+0x38/0x60 + blk_mq_submit_bio+0x589/0xcd0 + __submit_bio+0xe6/0x100 + submit_bio_noacct_nocheck+0x42e/0x470 + submit_bio_noacct+0x4c2/0xbb0 + flush_deferred_bios+0x136/0x170 + raid5_do_work+0x262/0x330 + + 2) The r5l_reclaim thread will hang in the same way, submitting a + bio to the block layer: + + io_schedule+0x70/0xb0 + rq_qos_wait+0x153/0x210 + wbt_wait+0x115/0x1b0 + __rq_qos_throttle+0x38/0x60 + blk_mq_submit_bio+0x589/0xcd0 + __submit_bio+0xe6/0x100 + submit_bio_noacct_nocheck+0x42e/0x470 + submit_bio_noacct+0x4c2/0xbb0 + submit_bio+0x3f/0xf0 + md_super_write+0x12f/0x1b0 + md_update_sb.part.0+0x7c6/0xff0 + md_update_sb+0x30/0x60 + r5l_do_reclaim+0x4f9/0x5e0 + r5l_reclaim_thread+0x69/0x30b + + However, before hanging, the MD_SB_CHANGE_PENDING flag will be + set for sb_flags in r5l_write_super_and_discard_space(). This + flag will never be cleared because the submit_bio() call never + returns. + + 3) Due to the MD_SB_CHANGE_PENDING flag being set, handle_stripe() + will do no processing on any pending stripes and re-set + STRIPE_HANDLE. This will cause the raid5d thread to enter an + infinite loop, constantly trying to handle the same stripes + stuck in the queue. + + The raid5d thread has a blk_plug that holds a number of bios + that are also stuck waiting seeing the thread is in a loop + that never schedules. These bios have been accounted for by + blk-wbt thus preventing the other threads above from + continuing when they try to submit bios. --Deadlock. + +To fix this, add the same wait_event() that is used in raid5_do_work() +to raid5d() such that if MD_SB_CHANGE_PENDING is set, the thread will +schedule and wait until the flag is cleared. The schedule action will +flush the plug which will allow the r5l_reclaim thread to continue, +thus preventing the deadlock. + +However, md_check_recovery() calls can also clear MD_SB_CHANGE_PENDING +from the same thread and can thus deadlock if the thread is put to +sleep. So avoid waiting if md_check_recovery() is being called in the +loop. + +It's not clear when the deadlock was introduced, but the similar +wait_event() call in raid5_do_work() was added in 2017 by this +commit: + + 16d997b78b15 ("md/raid5: simplfy delaying of writes while metadata + is updated.") + +Link: https://lore.kernel.org/r/7f3b87b6-b52a-f737-51d7-a4eec5c44112@deltatee.com +Signed-off-by: Logan Gunthorpe +Signed-off-by: Song Liu +Signed-off-by: Sasha Levin +--- + drivers/md/raid5.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c +index ecc6214b8e43..8eca638e6896 100644 +--- a/drivers/md/raid5.c ++++ b/drivers/md/raid5.c +@@ -36,6 +36,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -6516,7 +6517,18 @@ static void raid5d(struct md_thread *thread) + spin_unlock_irq(&conf->device_lock); + md_check_recovery(mddev); + spin_lock_irq(&conf->device_lock); ++ ++ /* ++ * Waiting on MD_SB_CHANGE_PENDING below may deadlock ++ * seeing md_check_recovery() is needed to clear ++ * the flag when using mdmon. ++ */ ++ continue; + } ++ ++ wait_event_lock_irq(mddev->sb_wait, ++ !test_bit(MD_SB_CHANGE_PENDING, &mddev->sb_flags), ++ conf->device_lock); + } + pr_debug("%d stripes handled\n", handled); + +-- +2.35.1 + diff --git a/queue-5.10/md-remove-most-calls-to-bdevname.patch b/queue-5.10/md-remove-most-calls-to-bdevname.patch new file mode 100644 index 00000000000..cd4b00e38e4 --- /dev/null +++ b/queue-5.10/md-remove-most-calls-to-bdevname.patch @@ -0,0 +1,1133 @@ +From a47a2963f62ad1048077c56887c3e89dee6c6d48 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 12 May 2022 08:19:13 +0200 +Subject: md: remove most calls to bdevname + +From: Christoph Hellwig + +[ Upstream commit 913cce5a1e588e3470ea064fe4ea336037d3a454 ] + +Use the %pg format specifier to save on stack consumption and code size. + +Signed-off-by: Christoph Hellwig +Signed-off-by: Song Liu +Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf") +Signed-off-by: Sasha Levin +--- + drivers/md/md-linear.c | 5 +- + drivers/md/md-multipath.c | 15 ++-- + drivers/md/md.c | 152 ++++++++++++++++---------------------- + drivers/md/raid0.c | 28 +++---- + drivers/md/raid1.c | 24 +++--- + drivers/md/raid10.c | 54 ++++++-------- + drivers/md/raid5-cache.c | 5 +- + drivers/md/raid5-ppl.c | 27 +++---- + drivers/md/raid5.c | 37 ++++------ + 9 files changed, 147 insertions(+), 200 deletions(-) + +diff --git a/drivers/md/md-linear.c b/drivers/md/md-linear.c +index 5ab22069b5be..3460ff7cb657 100644 +--- a/drivers/md/md-linear.c ++++ b/drivers/md/md-linear.c +@@ -216,7 +216,6 @@ static void linear_free(struct mddev *mddev, void *priv) + + static bool linear_make_request(struct mddev *mddev, struct bio *bio) + { +- char b[BDEVNAME_SIZE]; + struct dev_info *tmp_dev; + sector_t start_sector, end_sector, data_offset; + sector_t bio_sector = bio->bi_iter.bi_sector; +@@ -268,10 +267,10 @@ static bool linear_make_request(struct mddev *mddev, struct bio *bio) + return true; + + out_of_bounds: +- pr_err("md/linear:%s: make_request: Sector %llu out of bounds on dev %s: %llu sectors, offset %llu\n", ++ pr_err("md/linear:%s: make_request: Sector %llu out of bounds on dev %pg: %llu sectors, offset %llu\n", + mdname(mddev), + (unsigned long long)bio->bi_iter.bi_sector, +- bdevname(tmp_dev->rdev->bdev, b), ++ tmp_dev->rdev->bdev, + (unsigned long long)tmp_dev->rdev->sectors, + (unsigned long long)start_sector); + bio_io_error(bio); +diff --git a/drivers/md/md-multipath.c b/drivers/md/md-multipath.c +index 776bbe542db5..9f1b2f38a05d 100644 +--- a/drivers/md/md-multipath.c ++++ b/drivers/md/md-multipath.c +@@ -87,10 +87,9 @@ static void multipath_end_request(struct bio *bio) + /* + * oops, IO error: + */ +- char b[BDEVNAME_SIZE]; + md_error (mp_bh->mddev, rdev); +- pr_info("multipath: %s: rescheduling sector %llu\n", +- bdevname(rdev->bdev,b), ++ pr_info("multipath: %pg: rescheduling sector %llu\n", ++ rdev->bdev, + (unsigned long long)bio->bi_iter.bi_sector); + multipath_reschedule_retry(mp_bh); + } else +@@ -157,7 +156,6 @@ static void multipath_status(struct seq_file *seq, struct mddev *mddev) + static void multipath_error (struct mddev *mddev, struct md_rdev *rdev) + { + struct mpconf *conf = mddev->private; +- char b[BDEVNAME_SIZE]; + + if (conf->raid_disks - mddev->degraded <= 1) { + /* +@@ -180,9 +178,9 @@ static void multipath_error (struct mddev *mddev, struct md_rdev *rdev) + } + set_bit(Faulty, &rdev->flags); + set_bit(MD_SB_CHANGE_DEVS, &mddev->sb_flags); +- pr_err("multipath: IO failure on %s, disabling IO path.\n" ++ pr_err("multipath: IO failure on %pg, disabling IO path.\n" + "multipath: Operation continuing on %d IO paths.\n", +- bdevname(rdev->bdev, b), ++ rdev->bdev, + conf->raid_disks - mddev->degraded); + } + +@@ -200,12 +198,11 @@ static void print_multipath_conf (struct mpconf *conf) + conf->raid_disks); + + for (i = 0; i < conf->raid_disks; i++) { +- char b[BDEVNAME_SIZE]; + tmp = conf->multipaths + i; + if (tmp->rdev) +- pr_debug(" disk%d, o:%d, dev:%s\n", ++ pr_debug(" disk%d, o:%d, dev:%pg\n", + i,!test_bit(Faulty, &tmp->rdev->flags), +- bdevname(tmp->rdev->bdev,b)); ++ tmp->rdev->bdev); + } + } + +diff --git a/drivers/md/md.c b/drivers/md/md.c +index 1410c550c0ff..4b5fb5c304f3 100644 +--- a/drivers/md/md.c ++++ b/drivers/md/md.c +@@ -1056,8 +1056,6 @@ EXPORT_SYMBOL_GPL(sync_page_io); + + static int read_disk_sb(struct md_rdev *rdev, int size) + { +- char b[BDEVNAME_SIZE]; +- + if (rdev->sb_loaded) + return 0; + +@@ -1067,8 +1065,8 @@ static int read_disk_sb(struct md_rdev *rdev, int size) + return 0; + + fail: +- pr_err("md: disabled device %s, could not read superblock.\n", +- bdevname(rdev->bdev,b)); ++ pr_err("md: disabled device %pg, could not read superblock.\n", ++ rdev->bdev); + return -EINVAL; + } + +@@ -1214,7 +1212,6 @@ EXPORT_SYMBOL(md_check_no_bitmap); + */ + static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_version) + { +- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE]; + mdp_super_t *sb; + int ret; + bool spare_disk = true; +@@ -1233,19 +1230,19 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor + + ret = -EINVAL; + +- bdevname(rdev->bdev, b); + sb = page_address(rdev->sb_page); + + if (sb->md_magic != MD_SB_MAGIC) { +- pr_warn("md: invalid raid superblock magic on %s\n", b); ++ pr_warn("md: invalid raid superblock magic on %pg\n", ++ rdev->bdev); + goto abort; + } + + if (sb->major_version != 0 || + sb->minor_version < 90 || + sb->minor_version > 91) { +- pr_warn("Bad version number %d.%d on %s\n", +- sb->major_version, sb->minor_version, b); ++ pr_warn("Bad version number %d.%d on %pg\n", ++ sb->major_version, sb->minor_version, rdev->bdev); + goto abort; + } + +@@ -1253,7 +1250,7 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor + goto abort; + + if (md_csum_fold(calc_sb_csum(sb)) != md_csum_fold(sb->sb_csum)) { +- pr_warn("md: invalid superblock checksum on %s\n", b); ++ pr_warn("md: invalid superblock checksum on %pg\n", rdev->bdev); + goto abort; + } + +@@ -1285,13 +1282,13 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor + __u64 ev1, ev2; + mdp_super_t *refsb = page_address(refdev->sb_page); + if (!md_uuid_equal(refsb, sb)) { +- pr_warn("md: %s has different UUID to %s\n", +- b, bdevname(refdev->bdev,b2)); ++ pr_warn("md: %pg has different UUID to %pg\n", ++ rdev->bdev, refdev->bdev); + goto abort; + } + if (!md_sb_equal(refsb, sb)) { +- pr_warn("md: %s has same UUID but different superblock to %s\n", +- b, bdevname(refdev->bdev, b2)); ++ pr_warn("md: %pg has same UUID but different superblock to %pg\n", ++ rdev->bdev, refdev->bdev); + goto abort; + } + ev1 = md_event(sb); +@@ -1655,7 +1652,6 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_ + int ret; + sector_t sb_start; + sector_t sectors; +- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE]; + int bmask; + bool spare_disk = true; + +@@ -1700,13 +1696,13 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_ + return -EINVAL; + + if (calc_sb_1_csum(sb) != sb->sb_csum) { +- pr_warn("md: invalid superblock checksum on %s\n", +- bdevname(rdev->bdev,b)); ++ pr_warn("md: invalid superblock checksum on %pg\n", ++ rdev->bdev); + return -EINVAL; + } + if (le64_to_cpu(sb->data_size) < 10) { +- pr_warn("md: data_size too small on %s\n", +- bdevname(rdev->bdev,b)); ++ pr_warn("md: data_size too small on %pg\n", ++ rdev->bdev); + return -EINVAL; + } + if (sb->pad0 || +@@ -1812,9 +1808,9 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_ + sb->level != refsb->level || + sb->layout != refsb->layout || + sb->chunksize != refsb->chunksize) { +- pr_warn("md: %s has strangely different superblock to %s\n", +- bdevname(rdev->bdev,b), +- bdevname(refdev->bdev,b2)); ++ pr_warn("md: %pg has strangely different superblock to %pg\n", ++ rdev->bdev, ++ refdev->bdev); + return -EINVAL; + } + ev1 = le64_to_cpu(sb->events); +@@ -2395,7 +2391,6 @@ EXPORT_SYMBOL(md_integrity_register); + int md_integrity_add_rdev(struct md_rdev *rdev, struct mddev *mddev) + { + struct blk_integrity *bi_mddev; +- char name[BDEVNAME_SIZE]; + + if (!mddev->gendisk) + return 0; +@@ -2406,8 +2401,8 @@ int md_integrity_add_rdev(struct md_rdev *rdev, struct mddev *mddev) + return 0; + + if (blk_integrity_compare(mddev->gendisk, rdev->bdev->bd_disk) != 0) { +- pr_err("%s: incompatible integrity profile for %s\n", +- mdname(mddev), bdevname(rdev->bdev, name)); ++ pr_err("%s: incompatible integrity profile for %pg\n", ++ mdname(mddev), rdev->bdev); + return -ENXIO; + } + +@@ -2513,11 +2508,9 @@ static void rdev_delayed_delete(struct work_struct *ws) + + static void unbind_rdev_from_array(struct md_rdev *rdev) + { +- char b[BDEVNAME_SIZE]; +- + bd_unlink_disk_holder(rdev->bdev, rdev->mddev->gendisk); + list_del_rcu(&rdev->same_set); +- pr_debug("md: unbind<%s>\n", bdevname(rdev->bdev,b)); ++ pr_debug("md: unbind<%pg>\n", rdev->bdev); + mddev_destroy_serial_pool(rdev->mddev, rdev, false); + rdev->mddev = NULL; + sysfs_remove_link(&rdev->kobj, "block"); +@@ -2570,9 +2563,7 @@ void md_autodetect_dev(dev_t dev); + + static void export_rdev(struct md_rdev *rdev) + { +- char b[BDEVNAME_SIZE]; +- +- pr_debug("md: export_rdev(%s)\n", bdevname(rdev->bdev,b)); ++ pr_debug("md: export_rdev(%pg)\n", rdev->bdev); + md_rdev_clear(rdev); + #ifndef MODULE + if (test_bit(AutoDetected, &rdev->flags)) +@@ -2830,8 +2821,6 @@ void md_update_sb(struct mddev *mddev, int force_change) + rewrite: + md_bitmap_update_sb(mddev->bitmap); + rdev_for_each(rdev, mddev) { +- char b[BDEVNAME_SIZE]; +- + if (rdev->sb_loaded != 1) + continue; /* no noise on spare devices */ + +@@ -2839,8 +2828,8 @@ void md_update_sb(struct mddev *mddev, int force_change) + md_super_write(mddev,rdev, + rdev->sb_start, rdev->sb_size, + rdev->sb_page); +- pr_debug("md: (write) %s's sb offset: %llu\n", +- bdevname(rdev->bdev, b), ++ pr_debug("md: (write) %pg's sb offset: %llu\n", ++ rdev->bdev, + (unsigned long long)rdev->sb_start); + rdev->sb_events = mddev->events; + if (rdev->badblocks.size) { +@@ -2852,8 +2841,8 @@ void md_update_sb(struct mddev *mddev, int force_change) + } + + } else +- pr_debug("md: %s (skipping faulty)\n", +- bdevname(rdev->bdev, b)); ++ pr_debug("md: %pg (skipping faulty)\n", ++ rdev->bdev); + + if (mddev->level == LEVEL_MULTIPATH) + /* only need to write one superblock... */ +@@ -3726,7 +3715,6 @@ EXPORT_SYMBOL_GPL(md_rdev_init); + */ + static struct md_rdev *md_import_device(dev_t newdev, int super_format, int super_minor) + { +- char b[BDEVNAME_SIZE]; + int err; + struct md_rdev *rdev; + sector_t size; +@@ -3750,8 +3738,8 @@ static struct md_rdev *md_import_device(dev_t newdev, int super_format, int supe + + size = i_size_read(rdev->bdev->bd_inode) >> BLOCK_SIZE_BITS; + if (!size) { +- pr_warn("md: %s has zero or unknown size, marking faulty!\n", +- bdevname(rdev->bdev,b)); ++ pr_warn("md: %pg has zero or unknown size, marking faulty!\n", ++ rdev->bdev); + err = -EINVAL; + goto abort_free; + } +@@ -3760,14 +3748,14 @@ static struct md_rdev *md_import_device(dev_t newdev, int super_format, int supe + err = super_types[super_format]. + load_super(rdev, NULL, super_minor); + if (err == -EINVAL) { +- pr_warn("md: %s does not have a valid v%d.%d superblock, not importing!\n", +- bdevname(rdev->bdev,b), ++ pr_warn("md: %pg does not have a valid v%d.%d superblock, not importing!\n", ++ rdev->bdev, + super_format, super_minor); + goto abort_free; + } + if (err < 0) { +- pr_warn("md: could not read %s's sb, not importing!\n", +- bdevname(rdev->bdev,b)); ++ pr_warn("md: could not read %pg's sb, not importing!\n", ++ rdev->bdev); + goto abort_free; + } + } +@@ -3790,7 +3778,6 @@ static int analyze_sbs(struct mddev *mddev) + { + int i; + struct md_rdev *rdev, *freshest, *tmp; +- char b[BDEVNAME_SIZE]; + + freshest = NULL; + rdev_for_each_safe(rdev, tmp, mddev) +@@ -3802,8 +3789,8 @@ static int analyze_sbs(struct mddev *mddev) + case 0: + break; + default: +- pr_warn("md: fatal superblock inconsistency in %s -- removing from array\n", +- bdevname(rdev->bdev,b)); ++ pr_warn("md: fatal superblock inconsistency in %pg -- removing from array\n", ++ rdev->bdev); + md_kick_rdev_from_array(rdev); + } + +@@ -3821,8 +3808,8 @@ static int analyze_sbs(struct mddev *mddev) + if (mddev->max_disks && + (rdev->desc_nr >= mddev->max_disks || + i > mddev->max_disks)) { +- pr_warn("md: %s: %s: only %d devices permitted\n", +- mdname(mddev), bdevname(rdev->bdev, b), ++ pr_warn("md: %s: %pg: only %d devices permitted\n", ++ mdname(mddev), rdev->bdev, + mddev->max_disks); + md_kick_rdev_from_array(rdev); + continue; +@@ -3830,8 +3817,8 @@ static int analyze_sbs(struct mddev *mddev) + if (rdev != freshest) { + if (super_types[mddev->major_version]. + validate_super(mddev, rdev)) { +- pr_warn("md: kicking non-fresh %s from array!\n", +- bdevname(rdev->bdev,b)); ++ pr_warn("md: kicking non-fresh %pg from array!\n", ++ rdev->bdev); + md_kick_rdev_from_array(rdev); + continue; + } +@@ -5946,7 +5933,6 @@ int md_run(struct mddev *mddev) + /* Warn if this is a potentially silly + * configuration. + */ +- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE]; + struct md_rdev *rdev2; + int warned = 0; + +@@ -5955,10 +5941,10 @@ int md_run(struct mddev *mddev) + if (rdev < rdev2 && + rdev->bdev->bd_disk == + rdev2->bdev->bd_disk) { +- pr_warn("%s: WARNING: %s appears to be on the same physical disk as %s.\n", ++ pr_warn("%s: WARNING: %pg appears to be on the same physical disk as %pg.\n", + mdname(mddev), +- bdevname(rdev->bdev,b), +- bdevname(rdev2->bdev,b2)); ++ rdev->bdev, ++ rdev2->bdev); + warned = 1; + } + } +@@ -6481,8 +6467,7 @@ static void autorun_array(struct mddev *mddev) + pr_info("md: running: "); + + rdev_for_each(rdev, mddev) { +- char b[BDEVNAME_SIZE]; +- pr_cont("<%s>", bdevname(rdev->bdev,b)); ++ pr_cont("<%pg>", rdev->bdev); + } + pr_cont("\n"); + +@@ -6509,7 +6494,6 @@ static void autorun_devices(int part) + { + struct md_rdev *rdev0, *rdev, *tmp; + struct mddev *mddev; +- char b[BDEVNAME_SIZE]; + + pr_info("md: autorun ...\n"); + while (!list_empty(&pending_raid_disks)) { +@@ -6519,12 +6503,12 @@ static void autorun_devices(int part) + rdev0 = list_entry(pending_raid_disks.next, + struct md_rdev, same_set); + +- pr_debug("md: considering %s ...\n", bdevname(rdev0->bdev,b)); ++ pr_debug("md: considering %pg ...\n", rdev0->bdev); + INIT_LIST_HEAD(&candidates); + rdev_for_each_list(rdev, tmp, &pending_raid_disks) + if (super_90_load(rdev, rdev0, 0) >= 0) { +- pr_debug("md: adding %s ...\n", +- bdevname(rdev->bdev,b)); ++ pr_debug("md: adding %pg ...\n", ++ rdev->bdev); + list_move(&rdev->same_set, &candidates); + } + /* +@@ -6541,8 +6525,8 @@ static void autorun_devices(int part) + unit = MINOR(dev); + } + if (rdev0->preferred_minor != unit) { +- pr_warn("md: unit number in %s is bad: %d\n", +- bdevname(rdev0->bdev, b), rdev0->preferred_minor); ++ pr_warn("md: unit number in %pg is bad: %d\n", ++ rdev0->bdev, rdev0->preferred_minor); + break; + } + +@@ -6555,8 +6539,8 @@ static void autorun_devices(int part) + pr_warn("md: %s locked, cannot run\n", mdname(mddev)); + else if (mddev->raid_disks || mddev->major_version + || !list_empty(&mddev->disks)) { +- pr_warn("md: %s already running, cannot run %s\n", +- mdname(mddev), bdevname(rdev0->bdev,b)); ++ pr_warn("md: %s already running, cannot run %pg\n", ++ mdname(mddev), rdev0->bdev); + mddev_unlock(mddev); + } else { + pr_debug("md: created %s\n", mdname(mddev)); +@@ -6730,7 +6714,6 @@ static int get_disk_info(struct mddev *mddev, void __user * arg) + + int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info) + { +- char b[BDEVNAME_SIZE], b2[BDEVNAME_SIZE]; + struct md_rdev *rdev; + dev_t dev = MKDEV(info->major,info->minor); + +@@ -6760,9 +6743,9 @@ int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info) + err = super_types[mddev->major_version] + .load_super(rdev, rdev0, mddev->minor_version); + if (err < 0) { +- pr_warn("md: %s has different UUID to %s\n", +- bdevname(rdev->bdev,b), +- bdevname(rdev0->bdev,b2)); ++ pr_warn("md: %pg has different UUID to %pg\n", ++ rdev->bdev, ++ rdev0->bdev); + export_rdev(rdev); + return -EINVAL; + } +@@ -6937,7 +6920,6 @@ int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info) + + static int hot_remove_disk(struct mddev *mddev, dev_t dev) + { +- char b[BDEVNAME_SIZE]; + struct md_rdev *rdev; + + if (!mddev->pers) +@@ -6972,14 +6954,13 @@ static int hot_remove_disk(struct mddev *mddev, dev_t dev) + + return 0; + busy: +- pr_debug("md: cannot remove active disk %s from %s ...\n", +- bdevname(rdev->bdev,b), mdname(mddev)); ++ pr_debug("md: cannot remove active disk %pg from %s ...\n", ++ rdev->bdev, mdname(mddev)); + return -EBUSY; + } + + static int hot_add_disk(struct mddev *mddev, dev_t dev) + { +- char b[BDEVNAME_SIZE]; + int err; + struct md_rdev *rdev; + +@@ -7012,8 +6993,8 @@ static int hot_add_disk(struct mddev *mddev, dev_t dev) + rdev->sectors = rdev->sb_start; + + if (test_bit(Faulty, &rdev->flags)) { +- pr_warn("md: can not hot-add faulty %s disk to %s!\n", +- bdevname(rdev->bdev,b), mdname(mddev)); ++ pr_warn("md: can not hot-add faulty %pg disk to %s!\n", ++ rdev->bdev, mdname(mddev)); + err = -EINVAL; + goto abort_export; + } +@@ -7040,8 +7021,8 @@ static int hot_add_disk(struct mddev *mddev, dev_t dev) + * disable on the whole MD. + */ + if (!blk_queue_nowait(bdev_get_queue(rdev->bdev))) { +- pr_info("%s: Disabling nowait because %s does not support nowait\n", +- mdname(mddev), bdevname(rdev->bdev, b)); ++ pr_info("%s: Disabling nowait because %pg does not support nowait\n", ++ mdname(mddev), rdev->bdev); + blk_queue_flag_clear(QUEUE_FLAG_NOWAIT, mddev->queue); + } + /* +@@ -8043,10 +8024,8 @@ static void status_unused(struct seq_file *seq) + seq_printf(seq, "unused devices: "); + + list_for_each_entry(rdev, &pending_raid_disks, same_set) { +- char b[BDEVNAME_SIZE]; + i++; +- seq_printf(seq, "%s ", +- bdevname(rdev->bdev,b)); ++ seq_printf(seq, "%pg ", rdev->bdev); + } + if (!i) + seq_printf(seq, ""); +@@ -8286,9 +8265,8 @@ static int md_seq_show(struct seq_file *seq, void *v) + sectors = 0; + rcu_read_lock(); + rdev_for_each_rcu(rdev, mddev) { +- char b[BDEVNAME_SIZE]; +- seq_printf(seq, " %s[%d]", +- bdevname(rdev->bdev,b), rdev->desc_nr); ++ seq_printf(seq, " %pg[%d]", rdev->bdev, rdev->desc_nr); ++ + if (test_bit(WriteMostly, &rdev->flags)) + seq_printf(seq, "(W)"); + if (test_bit(Journal, &rdev->flags)) +@@ -9615,7 +9593,6 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev) + struct mdp_superblock_1 *sb = page_address(rdev->sb_page); + struct md_rdev *rdev2, *tmp; + int role, ret; +- char b[BDEVNAME_SIZE]; + + /* + * If size is changed in another node then we need to +@@ -9639,7 +9616,8 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev) + + if (test_bit(Candidate, &rdev2->flags)) { + if (role == MD_DISK_ROLE_FAULTY) { +- pr_info("md: Removing Candidate device %s because add failed\n", bdevname(rdev2->bdev,b)); ++ pr_info("md: Removing Candidate device %pg because add failed\n", ++ rdev2->bdev); + md_kick_rdev_from_array(rdev2); + continue; + } +@@ -9656,8 +9634,8 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev) + MD_FEATURE_RESHAPE_ACTIVE)) { + rdev2->saved_raid_disk = role; + ret = remove_and_add_spares(mddev, rdev2); +- pr_info("Activated spare: %s\n", +- bdevname(rdev2->bdev,b)); ++ pr_info("Activated spare: %pg\n", ++ rdev2->bdev); + /* wakeup mddev->thread here, so array could + * perform resync with the new activated disk */ + set_bit(MD_RECOVERY_NEEDED, &mddev->recovery); +diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c +index a4c0cafa6010..4a80cf43304b 100644 +--- a/drivers/md/raid0.c ++++ b/drivers/md/raid0.c +@@ -37,7 +37,6 @@ static void dump_zones(struct mddev *mddev) + int j, k; + sector_t zone_size = 0; + sector_t zone_start = 0; +- char b[BDEVNAME_SIZE]; + struct r0conf *conf = mddev->private; + int raid_disks = conf->strip_zone[0].nb_dev; + pr_debug("md: RAID0 configuration for %s - %d zone%s\n", +@@ -48,9 +47,8 @@ static void dump_zones(struct mddev *mddev) + int len = 0; + + for (k = 0; k < conf->strip_zone[j].nb_dev; k++) +- len += snprintf(line+len, 200-len, "%s%s", k?"/":"", +- bdevname(conf->devlist[j*raid_disks +- + k]->bdev, b)); ++ len += snprintf(line+len, 200-len, "%s%pg", k?"/":"", ++ conf->devlist[j * raid_disks + k]->bdev); + pr_debug("md: zone%d=[%s]\n", j, line); + + zone_size = conf->strip_zone[j].zone_end - zone_start; +@@ -69,8 +67,6 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) + struct md_rdev *smallest, *rdev1, *rdev2, *rdev, **dev; + struct strip_zone *zone; + int cnt; +- char b[BDEVNAME_SIZE]; +- char b2[BDEVNAME_SIZE]; + struct r0conf *conf = kzalloc(sizeof(*conf), GFP_KERNEL); + unsigned blksize = 512; + +@@ -78,9 +74,9 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) + if (!conf) + return -ENOMEM; + rdev_for_each(rdev1, mddev) { +- pr_debug("md/raid0:%s: looking at %s\n", ++ pr_debug("md/raid0:%s: looking at %pg\n", + mdname(mddev), +- bdevname(rdev1->bdev, b)); ++ rdev1->bdev); + c = 0; + + /* round size to chunk_size */ +@@ -92,12 +88,12 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) + rdev1->bdev->bd_disk->queue)); + + rdev_for_each(rdev2, mddev) { +- pr_debug("md/raid0:%s: comparing %s(%llu)" +- " with %s(%llu)\n", ++ pr_debug("md/raid0:%s: comparing %pg(%llu)" ++ " with %pg(%llu)\n", + mdname(mddev), +- bdevname(rdev1->bdev,b), ++ rdev1->bdev, + (unsigned long long)rdev1->sectors, +- bdevname(rdev2->bdev,b2), ++ rdev2->bdev, + (unsigned long long)rdev2->sectors); + if (rdev2 == rdev1) { + pr_debug("md/raid0:%s: END\n", +@@ -225,15 +221,15 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) + for (j=0; jdevlist[j]; + if (rdev->sectors <= zone->dev_start) { +- pr_debug("md/raid0:%s: checking %s ... nope\n", ++ pr_debug("md/raid0:%s: checking %pg ... nope\n", + mdname(mddev), +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + continue; + } +- pr_debug("md/raid0:%s: checking %s ..." ++ pr_debug("md/raid0:%s: checking %pg ..." + " contained as device %d\n", + mdname(mddev), +- bdevname(rdev->bdev, b), c); ++ rdev->bdev, c); + dev[c] = rdev; + c++; + if (!smallest || rdev->sectors < smallest->sectors) { +diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c +index b08f44c791fa..8e6c2c29022a 100644 +--- a/drivers/md/raid1.c ++++ b/drivers/md/raid1.c +@@ -396,10 +396,9 @@ static void raid1_end_read_request(struct bio *bio) + /* + * oops, read error: + */ +- char b[BDEVNAME_SIZE]; +- pr_err_ratelimited("md/raid1:%s: %s: rescheduling sector %llu\n", ++ pr_err_ratelimited("md/raid1:%s: %pg: rescheduling sector %llu\n", + mdname(conf->mddev), +- bdevname(rdev->bdev, b), ++ rdev->bdev, + (unsigned long long)r1_bio->sector); + set_bit(R1BIO_ReadError, &r1_bio->state); + reschedule_retry(r1_bio); +@@ -1262,10 +1261,10 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio, + mirror = conf->mirrors + rdisk; + + if (r1bio_existed) +- pr_info_ratelimited("md/raid1:%s: redirecting sector %llu to other mirror: %s\n", ++ pr_info_ratelimited("md/raid1:%s: redirecting sector %llu to other mirror: %pg\n", + mdname(mddev), + (unsigned long long)r1_bio->sector, +- bdevname(mirror->rdev->bdev, b)); ++ mirror->rdev->bdev); + + if (test_bit(WriteMostly, &mirror->rdev->flags) && + bitmap) { +@@ -1593,7 +1592,6 @@ static void raid1_status(struct seq_file *seq, struct mddev *mddev) + + static void raid1_error(struct mddev *mddev, struct md_rdev *rdev) + { +- char b[BDEVNAME_SIZE]; + struct r1conf *conf = mddev->private; + unsigned long flags; + +@@ -1627,9 +1625,9 @@ static void raid1_error(struct mddev *mddev, struct md_rdev *rdev) + set_bit(MD_RECOVERY_INTR, &mddev->recovery); + set_mask_bits(&mddev->sb_flags, 0, + BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); +- pr_crit("md/raid1:%s: Disk failure on %s, disabling device.\n" ++ pr_crit("md/raid1:%s: Disk failure on %pg, disabling device.\n" + "md/raid1:%s: Operation continuing on %d devices.\n", +- mdname(mddev), bdevname(rdev->bdev, b), ++ mdname(mddev), rdev->bdev, + mdname(mddev), conf->raid_disks - mddev->degraded); + } + +@@ -1647,13 +1645,12 @@ static void print_conf(struct r1conf *conf) + + rcu_read_lock(); + for (i = 0; i < conf->raid_disks; i++) { +- char b[BDEVNAME_SIZE]; + struct md_rdev *rdev = rcu_dereference(conf->mirrors[i].rdev); + if (rdev) +- pr_debug(" disk %d, wo:%d, o:%d, dev:%s\n", ++ pr_debug(" disk %d, wo:%d, o:%d, dev:%pg\n", + i, !test_bit(In_sync, &rdev->flags), + !test_bit(Faulty, &rdev->flags), +- bdevname(rdev->bdev,b)); ++ rdev->bdev); + } + rcu_read_unlock(); + } +@@ -2292,7 +2289,6 @@ static void fix_read_error(struct r1conf *conf, int read_disk, + } + d = start; + while (d != read_disk) { +- char b[BDEVNAME_SIZE]; + if (d==0) + d = conf->raid_disks * 2; + d--; +@@ -2305,11 +2301,11 @@ static void fix_read_error(struct r1conf *conf, int read_disk, + if (r1_sync_page_io(rdev, sect, s, + conf->tmppage, READ)) { + atomic_add(s, &rdev->corrected_errors); +- pr_info("md/raid1:%s: read error corrected (%d sectors at %llu on %s)\n", ++ pr_info("md/raid1:%s: read error corrected (%d sectors at %llu on %pg)\n", + mdname(mddev), s, + (unsigned long long)(sect + + rdev->data_offset), +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + } + rdev_dec_pending(rdev, mddev); + } else +diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c +index 0e741a8d278d..dd066d1ed145 100644 +--- a/drivers/md/raid10.c ++++ b/drivers/md/raid10.c +@@ -389,10 +389,9 @@ static void raid10_end_read_request(struct bio *bio) + /* + * oops, read error - keep the refcount on the rdev + */ +- char b[BDEVNAME_SIZE]; +- pr_err_ratelimited("md/raid10:%s: %s: rescheduling sector %llu\n", ++ pr_err_ratelimited("md/raid10:%s: %pg: rescheduling sector %llu\n", + mdname(conf->mddev), +- bdevname(rdev->bdev, b), ++ rdev->bdev, + (unsigned long long)r10_bio->sector); + set_bit(R10BIO_ReadError, &r10_bio->state); + reschedule_retry(r10_bio); +@@ -1168,9 +1167,9 @@ static void raid10_read_request(struct mddev *mddev, struct bio *bio, + return; + } + if (err_rdev) +- pr_err_ratelimited("md/raid10:%s: %s: redirecting sector %llu to another mirror\n", ++ pr_err_ratelimited("md/raid10:%s: %pg: redirecting sector %llu to another mirror\n", + mdname(mddev), +- bdevname(rdev->bdev, b), ++ rdev->bdev, + (unsigned long long)r10_bio->sector); + if (max_sectors < bio_sectors(bio)) { + struct bio *split = bio_split(bio, max_sectors, +@@ -1617,7 +1616,6 @@ static int enough(struct r10conf *conf, int ignore) + + static void raid10_error(struct mddev *mddev, struct md_rdev *rdev) + { +- char b[BDEVNAME_SIZE]; + struct r10conf *conf = mddev->private; + unsigned long flags; + +@@ -1647,9 +1645,9 @@ static void raid10_error(struct mddev *mddev, struct md_rdev *rdev) + set_mask_bits(&mddev->sb_flags, 0, + BIT(MD_SB_CHANGE_DEVS) | BIT(MD_SB_CHANGE_PENDING)); + spin_unlock_irqrestore(&conf->device_lock, flags); +- pr_crit("md/raid10:%s: Disk failure on %s, disabling device.\n" ++ pr_crit("md/raid10:%s: Disk failure on %pg, disabling device.\n" + "md/raid10:%s: Operation continuing on %d devices.\n", +- mdname(mddev), bdevname(rdev->bdev, b), ++ mdname(mddev), rdev->bdev, + mdname(mddev), conf->geo.raid_disks - mddev->degraded); + } + +@@ -1669,13 +1667,12 @@ static void print_conf(struct r10conf *conf) + /* This is only called with ->reconfix_mutex held, so + * rcu protection of rdev is not needed */ + for (i = 0; i < conf->geo.raid_disks; i++) { +- char b[BDEVNAME_SIZE]; + rdev = conf->mirrors[i].rdev; + if (rdev) +- pr_debug(" disk %d, wo:%d, o:%d, dev:%s\n", ++ pr_debug(" disk %d, wo:%d, o:%d, dev:%pg\n", + i, !test_bit(In_sync, &rdev->flags), + !test_bit(Faulty, &rdev->flags), +- bdevname(rdev->bdev,b)); ++ rdev->bdev); + } + } + +@@ -2335,14 +2332,11 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10 + check_decay_read_errors(mddev, rdev); + atomic_inc(&rdev->read_errors); + if (atomic_read(&rdev->read_errors) > max_read_errors) { +- char b[BDEVNAME_SIZE]; +- bdevname(rdev->bdev, b); +- +- pr_notice("md/raid10:%s: %s: Raid device exceeded read_error threshold [cur %d:max %d]\n", +- mdname(mddev), b, ++ pr_notice("md/raid10:%s: %pg: Raid device exceeded read_error threshold [cur %d:max %d]\n", ++ mdname(mddev), rdev->bdev, + atomic_read(&rdev->read_errors), max_read_errors); +- pr_notice("md/raid10:%s: %s: Failing raid device\n", +- mdname(mddev), b); ++ pr_notice("md/raid10:%s: %pg: Failing raid device\n", ++ mdname(mddev), rdev->bdev); + md_error(mddev, rdev); + r10_bio->devs[r10_bio->read_slot].bio = IO_BLOCKED; + return; +@@ -2412,8 +2406,6 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10 + /* write it back and re-read */ + rcu_read_lock(); + while (sl != r10_bio->read_slot) { +- char b[BDEVNAME_SIZE]; +- + if (sl==0) + sl = conf->copies; + sl--; +@@ -2432,24 +2424,22 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10 + s, conf->tmppage, WRITE) + == 0) { + /* Well, this device is dead */ +- pr_notice("md/raid10:%s: read correction write failed (%d sectors at %llu on %s)\n", ++ pr_notice("md/raid10:%s: read correction write failed (%d sectors at %llu on %pg)\n", + mdname(mddev), s, + (unsigned long long)( + sect + + choose_data_offset(r10_bio, + rdev)), +- bdevname(rdev->bdev, b)); +- pr_notice("md/raid10:%s: %s: failing drive\n", ++ rdev->bdev); ++ pr_notice("md/raid10:%s: %pg: failing drive\n", + mdname(mddev), +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + } + rdev_dec_pending(rdev, mddev); + rcu_read_lock(); + } + sl = start; + while (sl != r10_bio->read_slot) { +- char b[BDEVNAME_SIZE]; +- + if (sl==0) + sl = conf->copies; + sl--; +@@ -2469,23 +2459,23 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10 + READ)) { + case 0: + /* Well, this device is dead */ +- pr_notice("md/raid10:%s: unable to read back corrected sectors (%d sectors at %llu on %s)\n", ++ pr_notice("md/raid10:%s: unable to read back corrected sectors (%d sectors at %llu on %pg)\n", + mdname(mddev), s, + (unsigned long long)( + sect + + choose_data_offset(r10_bio, rdev)), +- bdevname(rdev->bdev, b)); +- pr_notice("md/raid10:%s: %s: failing drive\n", ++ rdev->bdev); ++ pr_notice("md/raid10:%s: %pg: failing drive\n", + mdname(mddev), +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + break; + case 1: +- pr_info("md/raid10:%s: read error corrected (%d sectors at %llu on %s)\n", ++ pr_info("md/raid10:%s: read error corrected (%d sectors at %llu on %pg)\n", + mdname(mddev), s, + (unsigned long long)( + sect + + choose_data_offset(r10_bio, rdev)), +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + atomic_add(s, &rdev->corrected_errors); + } + +diff --git a/drivers/md/raid5-cache.c b/drivers/md/raid5-cache.c +index 4337ae0e6af2..3194bc64fca2 100644 +--- a/drivers/md/raid5-cache.c ++++ b/drivers/md/raid5-cache.c +@@ -3067,11 +3067,10 @@ int r5l_init_log(struct r5conf *conf, struct md_rdev *rdev) + { + struct request_queue *q = bdev_get_queue(rdev->bdev); + struct r5l_log *log; +- char b[BDEVNAME_SIZE]; + int ret; + +- pr_debug("md/raid:%s: using device %s as journal\n", +- mdname(conf->mddev), bdevname(rdev->bdev, b)); ++ pr_debug("md/raid:%s: using device %pg as journal\n", ++ mdname(conf->mddev), rdev->bdev); + + if (PAGE_SIZE != 4096) + return -EINVAL; +diff --git a/drivers/md/raid5-ppl.c b/drivers/md/raid5-ppl.c +index d0f540296fe9..761fb9bab67a 100644 +--- a/drivers/md/raid5-ppl.c ++++ b/drivers/md/raid5-ppl.c +@@ -807,7 +807,6 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e, + int data_disks; + int i; + int ret = 0; +- char b[BDEVNAME_SIZE]; + unsigned int pp_size = le32_to_cpu(e->pp_size); + unsigned int data_size = le32_to_cpu(e->data_size); + +@@ -901,8 +900,8 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e, + break; + } + +- pr_debug("%s:%*s reading data member disk %s sector %llu\n", +- __func__, indent, "", bdevname(rdev->bdev, b), ++ pr_debug("%s:%*s reading data member disk %pg sector %llu\n", ++ __func__, indent, "", rdev->bdev, + (unsigned long long)sector); + if (!sync_page_io(rdev, sector, block_size, page2, + REQ_OP_READ, 0, false)) { +@@ -946,10 +945,10 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e, + parity_rdev = conf->disks[sh.pd_idx].rdev; + + BUG_ON(parity_rdev->bdev->bd_dev != log->rdev->bdev->bd_dev); +- pr_debug("%s:%*s write parity at sector %llu, disk %s\n", ++ pr_debug("%s:%*s write parity at sector %llu, disk %pg\n", + __func__, indent, "", + (unsigned long long)parity_sector, +- bdevname(parity_rdev->bdev, b)); ++ parity_rdev->bdev); + if (!sync_page_io(parity_rdev, parity_sector, block_size, + page1, REQ_OP_WRITE, 0, false)) { + pr_debug("%s:%*s parity write error!\n", __func__, +@@ -1261,7 +1260,6 @@ void ppl_exit_log(struct r5conf *conf) + + static int ppl_validate_rdev(struct md_rdev *rdev) + { +- char b[BDEVNAME_SIZE]; + int ppl_data_sectors; + int ppl_size_new; + +@@ -1278,8 +1276,8 @@ static int ppl_validate_rdev(struct md_rdev *rdev) + RAID5_STRIPE_SECTORS((struct r5conf *)rdev->mddev->private)); + + if (ppl_data_sectors <= 0) { +- pr_warn("md/raid:%s: PPL space too small on %s\n", +- mdname(rdev->mddev), bdevname(rdev->bdev, b)); ++ pr_warn("md/raid:%s: PPL space too small on %pg\n", ++ mdname(rdev->mddev), rdev->bdev); + return -ENOSPC; + } + +@@ -1289,16 +1287,16 @@ static int ppl_validate_rdev(struct md_rdev *rdev) + rdev->ppl.sector + ppl_size_new > rdev->data_offset) || + (rdev->ppl.sector >= rdev->data_offset && + rdev->data_offset + rdev->sectors > rdev->ppl.sector)) { +- pr_warn("md/raid:%s: PPL space overlaps with data on %s\n", +- mdname(rdev->mddev), bdevname(rdev->bdev, b)); ++ pr_warn("md/raid:%s: PPL space overlaps with data on %pg\n", ++ mdname(rdev->mddev), rdev->bdev); + return -EINVAL; + } + + if (!rdev->mddev->external && + ((rdev->ppl.offset > 0 && rdev->ppl.offset < (rdev->sb_size >> 9)) || + (rdev->ppl.offset <= 0 && rdev->ppl.offset + ppl_size_new > 0))) { +- pr_warn("md/raid:%s: PPL space overlaps with superblock on %s\n", +- mdname(rdev->mddev), bdevname(rdev->bdev, b)); ++ pr_warn("md/raid:%s: PPL space overlaps with superblock on %pg\n", ++ mdname(rdev->mddev), rdev->bdev); + return -EINVAL; + } + +@@ -1468,14 +1466,13 @@ int ppl_modify_log(struct r5conf *conf, struct md_rdev *rdev, bool add) + struct ppl_conf *ppl_conf = conf->log_private; + struct ppl_log *log; + int ret = 0; +- char b[BDEVNAME_SIZE]; + + if (!rdev) + return -EINVAL; + +- pr_debug("%s: disk: %d operation: %s dev: %s\n", ++ pr_debug("%s: disk: %d operation: %s dev: %pg\n", + __func__, rdev->raid_disk, add ? "add" : "remove", +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + + if (rdev->raid_disk < 0) + return 0; +diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c +index 0a941d62398f..ee0746fef417 100644 +--- a/drivers/md/raid5.c ++++ b/drivers/md/raid5.c +@@ -2665,7 +2665,6 @@ static void raid5_end_read_request(struct bio * bi) + struct stripe_head *sh = bi->bi_private; + struct r5conf *conf = sh->raid_conf; + int disks = sh->disks, i; +- char b[BDEVNAME_SIZE]; + struct md_rdev *rdev = NULL; + sector_t s; + +@@ -2703,10 +2702,10 @@ static void raid5_end_read_request(struct bio * bi) + * any error + */ + pr_info_ratelimited( +- "md/raid:%s: read error corrected (%lu sectors at %llu on %s)\n", ++ "md/raid:%s: read error corrected (%lu sectors at %llu on %pg)\n", + mdname(conf->mddev), RAID5_STRIPE_SECTORS(conf), + (unsigned long long)s, +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + atomic_add(RAID5_STRIPE_SECTORS(conf), &rdev->corrected_errors); + clear_bit(R5_ReadError, &sh->dev[i].flags); + clear_bit(R5_ReWrite, &sh->dev[i].flags); +@@ -2723,7 +2722,6 @@ static void raid5_end_read_request(struct bio * bi) + if (atomic_read(&rdev->read_errors)) + atomic_set(&rdev->read_errors, 0); + } else { +- const char *bdn = bdevname(rdev->bdev, b); + int retry = 0; + int set_bad = 0; + +@@ -2732,25 +2730,25 @@ static void raid5_end_read_request(struct bio * bi) + atomic_inc(&rdev->read_errors); + if (test_bit(R5_ReadRepl, &sh->dev[i].flags)) + pr_warn_ratelimited( +- "md/raid:%s: read error on replacement device (sector %llu on %s).\n", ++ "md/raid:%s: read error on replacement device (sector %llu on %pg).\n", + mdname(conf->mddev), + (unsigned long long)s, +- bdn); ++ rdev->bdev); + else if (conf->mddev->degraded >= conf->max_degraded) { + set_bad = 1; + pr_warn_ratelimited( +- "md/raid:%s: read error not correctable (sector %llu on %s).\n", ++ "md/raid:%s: read error not correctable (sector %llu on %pg).\n", + mdname(conf->mddev), + (unsigned long long)s, +- bdn); ++ rdev->bdev); + } else if (test_bit(R5_ReWrite, &sh->dev[i].flags)) { + /* Oh, no!!! */ + set_bad = 1; + pr_warn_ratelimited( +- "md/raid:%s: read error NOT corrected!! (sector %llu on %s).\n", ++ "md/raid:%s: read error NOT corrected!! (sector %llu on %pg).\n", + mdname(conf->mddev), + (unsigned long long)s, +- bdn); ++ rdev->bdev); + } else if (atomic_read(&rdev->read_errors) + > conf->max_nr_stripes) { + if (!test_bit(Faulty, &rdev->flags)) { +@@ -2758,8 +2756,8 @@ static void raid5_end_read_request(struct bio * bi) + mdname(conf->mddev), + atomic_read(&rdev->read_errors), + conf->max_nr_stripes); +- pr_warn("md/raid:%s: Too many read errors, failing device %s.\n", +- mdname(conf->mddev), bdn); ++ pr_warn("md/raid:%s: Too many read errors, failing device %pg.\n", ++ mdname(conf->mddev), rdev->bdev); + } + } else + retry = 1; +@@ -2872,13 +2870,12 @@ static void raid5_end_write_request(struct bio *bi) + + static void raid5_error(struct mddev *mddev, struct md_rdev *rdev) + { +- char b[BDEVNAME_SIZE]; + struct r5conf *conf = mddev->private; + unsigned long flags; + pr_debug("raid456: error called\n"); + +- pr_crit("md/raid:%s: Disk failure on %s, disabling device.\n", +- mdname(mddev), bdevname(rdev->bdev, b)); ++ pr_crit("md/raid:%s: Disk failure on %pg, disabling device.\n", ++ mdname(mddev), rdev->bdev); + + spin_lock_irqsave(&conf->device_lock, flags); + set_bit(Faulty, &rdev->flags); +@@ -7318,9 +7315,8 @@ static struct r5conf *setup_conf(struct mddev *mddev) + } + + if (test_bit(In_sync, &rdev->flags)) { +- char b[BDEVNAME_SIZE]; +- pr_info("md/raid:%s: device %s operational as raid disk %d\n", +- mdname(mddev), bdevname(rdev->bdev, b), raid_disk); ++ pr_info("md/raid:%s: device %pg operational as raid disk %d\n", ++ mdname(mddev), rdev->bdev, raid_disk); + } else if (rdev->saved_raid_disk != raid_disk) + /* Cannot rely on bitmap to complete recovery */ + conf->fullsync = 1; +@@ -7824,12 +7820,11 @@ static void print_raid5_conf (struct r5conf *conf) + + rcu_read_lock(); + for (i = 0; i < conf->raid_disks; i++) { +- char b[BDEVNAME_SIZE]; + rdev = rcu_dereference(conf->disks[i].rdev); + if (rdev) +- pr_debug(" disk %d, o:%d, dev:%s\n", ++ pr_debug(" disk %d, o:%d, dev:%pg\n", + i, !test_bit(Faulty, &rdev->flags), +- bdevname(rdev->bdev, b)); ++ rdev->bdev); + } + rcu_read_unlock(); + } +-- +2.35.1 + diff --git a/queue-5.10/md-replace-role-magic-numbers-with-defined-constants.patch b/queue-5.10/md-replace-role-magic-numbers-with-defined-constants.patch new file mode 100644 index 00000000000..065eab6edd1 --- /dev/null +++ b/queue-5.10/md-replace-role-magic-numbers-with-defined-constants.patch @@ -0,0 +1,72 @@ +From 10459eb3e2eebfb11434219747c73bab16dbd4dc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Apr 2022 13:45:58 -0600 +Subject: md: Replace role magic numbers with defined constants + +From: David Sloan + +[ Upstream commit 9151ad5d8676a89cf1b6a4051037ab3ca077d938 ] + +There are several instances where magic numbers are used in md.c instead +of the defined constants in md_p.h. This patch set improves code +readability by replacing all occurrences of 0xffff, 0xfffe, and 0xfffd when +relating to md roles with their equivalent defined constant. + +Signed-off-by: David Sloan +Reviewed-by: Logan Gunthorpe +Signed-off-by: Song Liu +Stable-dep-of: 1727fd5015d8 ("md: Replace snprintf with scnprintf") +Signed-off-by: Sasha Levin +--- + drivers/md/md.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/md/md.c b/drivers/md/md.c +index c5363d2310e9..1410c550c0ff 100644 +--- a/drivers/md/md.c ++++ b/drivers/md/md.c +@@ -2674,11 +2674,11 @@ static bool does_sb_need_changing(struct mddev *mddev) + rdev_for_each(rdev, mddev) { + role = le16_to_cpu(sb->dev_roles[rdev->desc_nr]); + /* Device activated? */ +- if (role == 0xffff && rdev->raid_disk >=0 && ++ if (role == MD_DISK_ROLE_SPARE && rdev->raid_disk >= 0 && + !test_bit(Faulty, &rdev->flags)) + return true; + /* Device turned faulty? */ +- if (test_bit(Faulty, &rdev->flags) && (role < 0xfffd)) ++ if (test_bit(Faulty, &rdev->flags) && (role < MD_DISK_ROLE_MAX)) + return true; + } + +@@ -9638,7 +9638,7 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev) + role = le16_to_cpu(sb->dev_roles[rdev2->desc_nr]); + + if (test_bit(Candidate, &rdev2->flags)) { +- if (role == 0xfffe) { ++ if (role == MD_DISK_ROLE_FAULTY) { + pr_info("md: Removing Candidate device %s because add failed\n", bdevname(rdev2->bdev,b)); + md_kick_rdev_from_array(rdev2); + continue; +@@ -9651,7 +9651,7 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev) + /* + * got activated except reshape is happening. + */ +- if (rdev2->raid_disk == -1 && role != 0xffff && ++ if (rdev2->raid_disk == -1 && role != MD_DISK_ROLE_SPARE && + !(le32_to_cpu(sb->feature_map) & + MD_FEATURE_RESHAPE_ACTIVE)) { + rdev2->saved_raid_disk = role; +@@ -9668,7 +9668,8 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev) + * as faulty. The recovery is performed by the + * one who initiated the error. + */ +- if ((role == 0xfffe) || (role == 0xfffd)) { ++ if (role == MD_DISK_ROLE_FAULTY || ++ role == MD_DISK_ROLE_JOURNAL) { + md_error(mddev, rdev2); + clear_bit(Blocked, &rdev2->flags); + } +-- +2.35.1 + diff --git a/queue-5.10/md-replace-snprintf-with-scnprintf.patch b/queue-5.10/md-replace-snprintf-with-scnprintf.patch new file mode 100644 index 00000000000..416622a8151 --- /dev/null +++ b/queue-5.10/md-replace-snprintf-with-scnprintf.patch @@ -0,0 +1,71 @@ +From 523ba87cb0a82486c3db217581501415d68c549a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 23 Aug 2022 11:51:04 -0700 +Subject: md: Replace snprintf with scnprintf +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Saurabh Sengar + +[ Upstream commit 1727fd5015d8f93474148f94e34cda5aa6ad4a43 ] + +Current code produces a warning as shown below when total characters +in the constituent block device names plus the slashes exceeds 200. +snprintf() returns the number of characters generated from the given +input, which could cause the expression “200 – len” to wrap around +to a large positive number. Fix this by using scnprintf() instead, +which returns the actual number of characters written into the buffer. + +[ 1513.267938] ------------[ cut here ]------------ +[ 1513.267943] WARNING: CPU: 15 PID: 37247 at /lib/vsprintf.c:2509 vsnprintf+0x2c8/0x510 +[ 1513.267944] Modules linked in: +[ 1513.267969] CPU: 15 PID: 37247 Comm: mdadm Not tainted 5.4.0-1085-azure #90~18.04.1-Ubuntu +[ 1513.267969] Hardware name: Microsoft Corporation Virtual Machine/Virtual Machine, BIOS Hyper-V UEFI Release v4.1 05/09/2022 +[ 1513.267971] RIP: 0010:vsnprintf+0x2c8/0x510 +<-snip-> +[ 1513.267982] Call Trace: +[ 1513.267986] snprintf+0x45/0x70 +[ 1513.267990] ? disk_name+0x71/0xa0 +[ 1513.267993] dump_zones+0x114/0x240 [raid0] +[ 1513.267996] ? _cond_resched+0x19/0x40 +[ 1513.267998] raid0_run+0x19e/0x270 [raid0] +[ 1513.268000] md_run+0x5e0/0xc50 +[ 1513.268003] ? security_capable+0x3f/0x60 +[ 1513.268005] do_md_run+0x19/0x110 +[ 1513.268006] md_ioctl+0x195e/0x1f90 +[ 1513.268007] blkdev_ioctl+0x91f/0x9f0 +[ 1513.268010] block_ioctl+0x3d/0x50 +[ 1513.268012] do_vfs_ioctl+0xa9/0x640 +[ 1513.268014] ? __fput+0x162/0x260 +[ 1513.268016] ksys_ioctl+0x75/0x80 +[ 1513.268017] __x64_sys_ioctl+0x1a/0x20 +[ 1513.268019] do_syscall_64+0x5e/0x200 +[ 1513.268021] entry_SYSCALL_64_after_hwframe+0x44/0xa9 + +Fixes: 766038846e875 ("md/raid0: replace printk() with pr_*()") +Reviewed-by: Michael Kelley +Acked-by: Guoqing Jiang +Signed-off-by: Saurabh Sengar +Signed-off-by: Song Liu +Signed-off-by: Sasha Levin +--- + drivers/md/raid0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c +index 4a80cf43304b..823ea5cca774 100644 +--- a/drivers/md/raid0.c ++++ b/drivers/md/raid0.c +@@ -47,7 +47,7 @@ static void dump_zones(struct mddev *mddev) + int len = 0; + + for (k = 0; k < conf->strip_zone[j].nb_dev; k++) +- len += snprintf(line+len, 200-len, "%s%pg", k?"/":"", ++ len += scnprintf(line+len, 200-len, "%s%pg", k?"/":"", + conf->devlist[j * raid_disks + k]->bdev); + pr_debug("md: zone%d=[%s]\n", j, line); + +-- +2.35.1 + diff --git a/queue-5.10/media-cx88-fix-a-null-ptr-deref-bug-in-buffer_prepar.patch b/queue-5.10/media-cx88-fix-a-null-ptr-deref-bug-in-buffer_prepar.patch new file mode 100644 index 00000000000..20f2256cb28 --- /dev/null +++ b/queue-5.10/media-cx88-fix-a-null-ptr-deref-bug-in-buffer_prepar.patch @@ -0,0 +1,141 @@ +From 9e9ebc4f5ff48ca8e85acba1d4e85285b4d562d9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Jul 2022 04:23:38 +0200 +Subject: media: cx88: Fix a null-ptr-deref bug in buffer_prepare() + +From: Zheyu Ma + +[ Upstream commit 2b064d91440b33fba5b452f2d1b31f13ae911d71 ] + +When the driver calls cx88_risc_buffer() to prepare the buffer, the +function call may fail, resulting in a empty buffer and null-ptr-deref +later in buffer_queue(). + +The following log can reveal it: + +[ 41.822762] general protection fault, probably for non-canonical address 0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN PTI +[ 41.824488] KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007] +[ 41.828027] RIP: 0010:buffer_queue+0xc2/0x500 +[ 41.836311] Call Trace: +[ 41.836945] __enqueue_in_driver+0x141/0x360 +[ 41.837262] vb2_start_streaming+0x62/0x4a0 +[ 41.838216] vb2_core_streamon+0x1da/0x2c0 +[ 41.838516] __vb2_init_fileio+0x981/0xbc0 +[ 41.839141] __vb2_perform_fileio+0xbf9/0x1120 +[ 41.840072] vb2_fop_read+0x20e/0x400 +[ 41.840346] v4l2_read+0x215/0x290 +[ 41.840603] vfs_read+0x162/0x4c0 + +Fix this by checking the return value of cx88_risc_buffer() + +[hverkuil: fix coding style issues] + +Signed-off-by: Zheyu Ma +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +--- + drivers/media/pci/cx88/cx88-vbi.c | 9 +++--- + drivers/media/pci/cx88/cx88-video.c | 43 +++++++++++++++-------------- + 2 files changed, 26 insertions(+), 26 deletions(-) + +diff --git a/drivers/media/pci/cx88/cx88-vbi.c b/drivers/media/pci/cx88/cx88-vbi.c +index 58489ea0c1da..7cf2271866d0 100644 +--- a/drivers/media/pci/cx88/cx88-vbi.c ++++ b/drivers/media/pci/cx88/cx88-vbi.c +@@ -144,11 +144,10 @@ static int buffer_prepare(struct vb2_buffer *vb) + return -EINVAL; + vb2_set_plane_payload(vb, 0, size); + +- cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl, +- 0, VBI_LINE_LENGTH * lines, +- VBI_LINE_LENGTH, 0, +- lines); +- return 0; ++ return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl, ++ 0, VBI_LINE_LENGTH * lines, ++ VBI_LINE_LENGTH, 0, ++ lines); + } + + static void buffer_finish(struct vb2_buffer *vb) +diff --git a/drivers/media/pci/cx88/cx88-video.c b/drivers/media/pci/cx88/cx88-video.c +index 8cffdacf6007..e5adffa3a99a 100644 +--- a/drivers/media/pci/cx88/cx88-video.c ++++ b/drivers/media/pci/cx88/cx88-video.c +@@ -431,6 +431,7 @@ static int queue_setup(struct vb2_queue *q, + + static int buffer_prepare(struct vb2_buffer *vb) + { ++ int ret; + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct cx8800_dev *dev = vb->vb2_queue->drv_priv; + struct cx88_core *core = dev->core; +@@ -445,35 +446,35 @@ static int buffer_prepare(struct vb2_buffer *vb) + + switch (core->field) { + case V4L2_FIELD_TOP: +- cx88_risc_buffer(dev->pci, &buf->risc, +- sgt->sgl, 0, UNSET, +- buf->bpl, 0, core->height); ++ ret = cx88_risc_buffer(dev->pci, &buf->risc, ++ sgt->sgl, 0, UNSET, ++ buf->bpl, 0, core->height); + break; + case V4L2_FIELD_BOTTOM: +- cx88_risc_buffer(dev->pci, &buf->risc, +- sgt->sgl, UNSET, 0, +- buf->bpl, 0, core->height); ++ ret = cx88_risc_buffer(dev->pci, &buf->risc, ++ sgt->sgl, UNSET, 0, ++ buf->bpl, 0, core->height); + break; + case V4L2_FIELD_SEQ_TB: +- cx88_risc_buffer(dev->pci, &buf->risc, +- sgt->sgl, +- 0, buf->bpl * (core->height >> 1), +- buf->bpl, 0, +- core->height >> 1); ++ ret = cx88_risc_buffer(dev->pci, &buf->risc, ++ sgt->sgl, ++ 0, buf->bpl * (core->height >> 1), ++ buf->bpl, 0, ++ core->height >> 1); + break; + case V4L2_FIELD_SEQ_BT: +- cx88_risc_buffer(dev->pci, &buf->risc, +- sgt->sgl, +- buf->bpl * (core->height >> 1), 0, +- buf->bpl, 0, +- core->height >> 1); ++ ret = cx88_risc_buffer(dev->pci, &buf->risc, ++ sgt->sgl, ++ buf->bpl * (core->height >> 1), 0, ++ buf->bpl, 0, ++ core->height >> 1); + break; + case V4L2_FIELD_INTERLACED: + default: +- cx88_risc_buffer(dev->pci, &buf->risc, +- sgt->sgl, 0, buf->bpl, +- buf->bpl, buf->bpl, +- core->height >> 1); ++ ret = cx88_risc_buffer(dev->pci, &buf->risc, ++ sgt->sgl, 0, buf->bpl, ++ buf->bpl, buf->bpl, ++ core->height >> 1); + break; + } + dprintk(2, +@@ -481,7 +482,7 @@ static int buffer_prepare(struct vb2_buffer *vb) + buf, buf->vb.vb2_buf.index, __func__, + core->width, core->height, dev->fmt->depth, dev->fmt->fourcc, + (unsigned long)buf->risc.dma); +- return 0; ++ return ret; + } + + static void buffer_finish(struct vb2_buffer *vb) +-- +2.35.1 + diff --git a/queue-5.10/media-exynos4-is-fimc-is-add-of_node_put-when-breaki.patch b/queue-5.10/media-exynos4-is-fimc-is-add-of_node_put-when-breaki.patch new file mode 100644 index 00000000000..5104e8fd74a --- /dev/null +++ b/queue-5.10/media-exynos4-is-fimc-is-add-of_node_put-when-breaki.patch @@ -0,0 +1,38 @@ +From 09c5ff452651ac33048d48f84baa3473b9aa14ab Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Jul 2022 16:30:03 +0200 +Subject: media: exynos4-is: fimc-is: Add of_node_put() when breaking out of + loop + +From: Liang He + +[ Upstream commit 211f8304fa21aaedc2c247f0c9d6c7f1aaa61ad7 ] + +In fimc_is_register_subdevs(), we need to call of_node_put() for +the reference 'i2c_bus' when breaking out of the +for_each_compatible_node() which has increased the refcount. + +Fixes: 9a761e436843 ("[media] exynos4-is: Add Exynos4x12 FIMC-IS driver") +Signed-off-by: Liang He +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +--- + drivers/media/platform/exynos4-is/fimc-is.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c +index dc2a144cd29b..b52d2203eac5 100644 +--- a/drivers/media/platform/exynos4-is/fimc-is.c ++++ b/drivers/media/platform/exynos4-is/fimc-is.c +@@ -213,6 +213,7 @@ static int fimc_is_register_subdevs(struct fimc_is *is) + + if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) { + of_node_put(child); ++ of_node_put(i2c_bus); + return ret; + } + index++; +-- +2.35.1 + diff --git a/queue-5.10/media-meson-vdec-add-missing-clk_disable_unprepare-o.patch b/queue-5.10/media-meson-vdec-add-missing-clk_disable_unprepare-o.patch new file mode 100644 index 00000000000..54c312f9b43 --- /dev/null +++ b/queue-5.10/media-meson-vdec-add-missing-clk_disable_unprepare-o.patch @@ -0,0 +1,47 @@ +From bb5fbf765fd5a5b82ae12a4882884402362aa9fe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 18 Aug 2022 08:57:53 +0200 +Subject: media: meson: vdec: add missing clk_disable_unprepare on error in + vdec_hevc_start() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Xu Qiang + +[ Upstream commit 4029372233e13e281f8c387f279f9f064ced3810 ] + +Add the missing clk_disable_unprepare() before return +from vdec_hevc_start() in the error handling case. + +Fixes: 823a7300340e (“media: meson: vdec: add common HEVC decoder support”) +Signed-off-by: Xu Qiang +Reviewed-by: Neil Armstrong +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +--- + drivers/staging/media/meson/vdec/vdec_hevc.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/media/meson/vdec/vdec_hevc.c b/drivers/staging/media/meson/vdec/vdec_hevc.c +index 9530e580e57a..afced435c907 100644 +--- a/drivers/staging/media/meson/vdec/vdec_hevc.c ++++ b/drivers/staging/media/meson/vdec/vdec_hevc.c +@@ -167,8 +167,12 @@ static int vdec_hevc_start(struct amvdec_session *sess) + + clk_set_rate(core->vdec_hevc_clk, 666666666); + ret = clk_prepare_enable(core->vdec_hevc_clk); +- if (ret) ++ if (ret) { ++ if (core->platform->revision == VDEC_REVISION_G12A || ++ core->platform->revision == VDEC_REVISION_SM1) ++ clk_disable_unprepare(core->vdec_hevcf_clk); + return ret; ++ } + + if (core->platform->revision == VDEC_REVISION_SM1) + regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, +-- +2.35.1 + diff --git a/queue-5.10/media-tm6000-fix-unused-value-in-vidioc_try_fmt_vid_.patch b/queue-5.10/media-tm6000-fix-unused-value-in-vidioc_try_fmt_vid_.patch new file mode 100644 index 00000000000..152507a0986 --- /dev/null +++ b/queue-5.10/media-tm6000-fix-unused-value-in-vidioc_try_fmt_vid_.patch @@ -0,0 +1,46 @@ +From d767858779c1055ab7996f631754d5316dcfc1b6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Jul 2022 18:12:36 +0800 +Subject: media: tm6000: Fix unused value in vidioc_try_fmt_vid_cap() + +From: Zeng Jingxiang + +[ Upstream commit d682869daa23938b5e8919db45c4b5b227749712 ] + +Coverity warns of an unused value: + +assigned_value: Assign the value of the variable f->fmt.pix.field +to field here, but that stored value is overwritten. +before it can be used. +919 field = f->fmt.pix.field; +920 + +value_overwrite: Overwriting previous write to field with +the value of V4L2_FIELD_INTERLACED. +921 field = V4L2_FIELD_INTERLACED; + +Fixes: ed57256f6fe8 ("[media] tm6000: fix G/TRY_FMT") +Signed-off-by: Zeng Jingxiang +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +--- + drivers/media/usb/tm6000/tm6000-video.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/media/usb/tm6000/tm6000-video.c b/drivers/media/usb/tm6000/tm6000-video.c +index 01071e6cd757..b01d3aa6d037 100644 +--- a/drivers/media/usb/tm6000/tm6000-video.c ++++ b/drivers/media/usb/tm6000/tm6000-video.c +@@ -918,8 +918,6 @@ static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, + return -EINVAL; + } + +- field = f->fmt.pix.field; +- + field = V4L2_FIELD_INTERLACED; + + tm6000_get_std_res(dev); +-- +2.35.1 + diff --git a/queue-5.10/media-xilinx-vipp-fix-refcount-leak-in-xvip_graph_dm.patch b/queue-5.10/media-xilinx-vipp-fix-refcount-leak-in-xvip_graph_dm.patch new file mode 100644 index 00000000000..a3868601d2f --- /dev/null +++ b/queue-5.10/media-xilinx-vipp-fix-refcount-leak-in-xvip_graph_dm.patch @@ -0,0 +1,56 @@ +From d08fc21049e823332ae39947e1da872292bb72ed Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 1 Jun 2022 06:25:14 +0200 +Subject: media: xilinx: vipp: Fix refcount leak in xvip_graph_dma_init + +From: Miaoqian Lin + +[ Upstream commit 1c78f19c3a0ea312a8178a6bfd8934eb93e9b10a ] + +of_get_child_by_name() returns a node pointer with refcount +incremented, we should use of_node_put() on it when not need anymore. +Add missing of_node_put() to avoid refcount leak. + +Fixes: df3305156f98 ("[media] v4l: xilinx: Add Xilinx Video IP core") +Signed-off-by: Miaoqian Lin +Signed-off-by: Laurent Pinchart +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +--- + drivers/media/platform/xilinx/xilinx-vipp.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c b/drivers/media/platform/xilinx/xilinx-vipp.c +index cc2856efea59..f2b0c490187c 100644 +--- a/drivers/media/platform/xilinx/xilinx-vipp.c ++++ b/drivers/media/platform/xilinx/xilinx-vipp.c +@@ -472,7 +472,7 @@ static int xvip_graph_dma_init(struct xvip_composite_device *xdev) + { + struct device_node *ports; + struct device_node *port; +- int ret; ++ int ret = 0; + + ports = of_get_child_by_name(xdev->dev->of_node, "ports"); + if (ports == NULL) { +@@ -482,13 +482,14 @@ static int xvip_graph_dma_init(struct xvip_composite_device *xdev) + + for_each_child_of_node(ports, port) { + ret = xvip_graph_dma_init_one(xdev, port); +- if (ret < 0) { ++ if (ret) { + of_node_put(port); +- return ret; ++ break; + } + } + +- return 0; ++ of_node_put(ports); ++ return ret; + } + + static void xvip_graph_cleanup(struct xvip_composite_device *xdev) +-- +2.35.1 + diff --git a/queue-5.10/memory-of-fix-refcount-leak-bug-in-of_get_ddr_timing.patch b/queue-5.10/memory-of-fix-refcount-leak-bug-in-of_get_ddr_timing.patch new file mode 100644 index 00000000000..775157cfefe --- /dev/null +++ b/queue-5.10/memory-of-fix-refcount-leak-bug-in-of_get_ddr_timing.patch @@ -0,0 +1,37 @@ +From 3611d3b5d8aa8f85678e1a80fbe13fd4bdf01850 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Jul 2022 16:56:39 +0800 +Subject: memory: of: Fix refcount leak bug in of_get_ddr_timings() + +From: Liang He + +[ Upstream commit 05215fb32010d4afb68fbdbb4d237df6e2d4567b ] + +We should add the of_node_put() when breaking out of +for_each_child_of_node() as it will automatically increase +and decrease the refcount. + +Fixes: e6b42eb6a66c ("memory: emif: add device tree support to emif driver") +Signed-off-by: Liang He +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220719085640.1210583-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/memory/of_memory.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c +index d9f5437d3bce..d0a80aefdea8 100644 +--- a/drivers/memory/of_memory.c ++++ b/drivers/memory/of_memory.c +@@ -134,6 +134,7 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr, + for_each_child_of_node(np_ddr, np_tim) { + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_do_get_timings(np_tim, &timings[i])) { ++ of_node_put(np_tim); + devm_kfree(dev, timings); + goto default_timings; + } +-- +2.35.1 + diff --git a/queue-5.10/memory-of-fix-refcount-leak-bug-in-of_lpddr3_get_ddr.patch b/queue-5.10/memory-of-fix-refcount-leak-bug-in-of_lpddr3_get_ddr.patch new file mode 100644 index 00000000000..92a159dcb4f --- /dev/null +++ b/queue-5.10/memory-of-fix-refcount-leak-bug-in-of_lpddr3_get_ddr.patch @@ -0,0 +1,37 @@ +From 6b0fd19b648e4a6994762b5b1cf3b548fd4a55bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Jul 2022 16:56:40 +0800 +Subject: memory: of: Fix refcount leak bug in of_lpddr3_get_ddr_timings() + +From: Liang He + +[ Upstream commit 48af14fb0eaa63d9aa68f59fb0b205ec55a95636 ] + +We should add the of_node_put() when breaking out of +for_each_child_of_node() as it will automatically increase +and decrease the refcount. + +Fixes: 976897dd96db ("memory: Extend of_memory with LPDDR3 support") +Signed-off-by: Liang He +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220719085640.1210583-2-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/memory/of_memory.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c +index d0a80aefdea8..1791614f324b 100644 +--- a/drivers/memory/of_memory.c ++++ b/drivers/memory/of_memory.c +@@ -283,6 +283,7 @@ const struct lpddr3_timings + if (of_device_is_compatible(np_tim, tim_compat)) { + if (of_lpddr3_do_get_timings(np_tim, &timings[i])) { + devm_kfree(dev, timings); ++ of_node_put(np_tim); + goto default_timings; + } + i++; +-- +2.35.1 + diff --git a/queue-5.10/memory-pl353-smc-fix-refcount-leak-bug-in-pl353_smc_.patch b/queue-5.10/memory-pl353-smc-fix-refcount-leak-bug-in-pl353_smc_.patch new file mode 100644 index 00000000000..f66a0b87269 --- /dev/null +++ b/queue-5.10/memory-pl353-smc-fix-refcount-leak-bug-in-pl353_smc_.patch @@ -0,0 +1,41 @@ +From 33d6c7c12932bd5a7bd842a32a5afe667d384207 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 16 Jul 2022 11:13:24 +0800 +Subject: memory: pl353-smc: Fix refcount leak bug in pl353_smc_probe() + +From: Liang He + +[ Upstream commit 61b3c876c1cbdb1efd1f52a1f348580e6e14efb6 ] + +The break of for_each_available_child_of_node() needs a +corresponding of_node_put() when the reference 'child' is not +used anymore. Here we do not need to call of_node_put() in +fail path as '!match' means no break. + +While the of_platform_device_create() will created a new +reference by 'child' but it has considered the refcounting. + +Fixes: fee10bd22678 ("memory: pl353: Add driver for arm pl353 static memory controller") +Signed-off-by: Liang He +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220716031324.447680-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/memory/pl353-smc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c +index b0b251bb207f..1a6964f1ba6a 100644 +--- a/drivers/memory/pl353-smc.c ++++ b/drivers/memory/pl353-smc.c +@@ -416,6 +416,7 @@ static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id) + if (init) + init(adev, child); + of_platform_device_create(child, NULL, &adev->dev); ++ of_node_put(child); + + return 0; + +-- +2.35.1 + diff --git a/queue-5.10/mfd-fsl-imx25-fix-an-error-handling-path-in-mx25_tsa.patch b/queue-5.10/mfd-fsl-imx25-fix-an-error-handling-path-in-mx25_tsa.patch new file mode 100644 index 00000000000..513a7de711b --- /dev/null +++ b/queue-5.10/mfd-fsl-imx25-fix-an-error-handling-path-in-mx25_tsa.patch @@ -0,0 +1,82 @@ +From 5ca99a5c4f16c8060522005b65970435395c09b8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 31 Jul 2022 14:06:23 +0200 +Subject: mfd: fsl-imx25: Fix an error handling path in mx25_tsadc_setup_irq() + +From: Christophe JAILLET + +[ Upstream commit 3fa9e4cfb55da512ebfd57336fde468830719298 ] + +If devm_of_platform_populate() fails, some resources need to be +released. + +Introduce a mx25_tsadc_unset_irq() function that undoes +mx25_tsadc_setup_irq() and call it both from the new error handling path +of the probe and in the remove function. + +Fixes: a55196eff6d6 ("mfd: fsl-imx25: Use devm_of_platform_populate()") +Signed-off-by: Christophe JAILLET +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/d404e04828fc06bcfddf81f9f3e9b4babbe35415.1659269156.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Sasha Levin +--- + drivers/mfd/fsl-imx25-tsadc.c | 32 ++++++++++++++++++++++++-------- + 1 file changed, 24 insertions(+), 8 deletions(-) + +diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c +index a016b39fe9b0..95103b2cc471 100644 +--- a/drivers/mfd/fsl-imx25-tsadc.c ++++ b/drivers/mfd/fsl-imx25-tsadc.c +@@ -84,6 +84,19 @@ static int mx25_tsadc_setup_irq(struct platform_device *pdev, + return 0; + } + ++static int mx25_tsadc_unset_irq(struct platform_device *pdev) ++{ ++ struct mx25_tsadc *tsadc = platform_get_drvdata(pdev); ++ int irq = platform_get_irq(pdev, 0); ++ ++ if (irq) { ++ irq_set_chained_handler_and_data(irq, NULL, NULL); ++ irq_domain_remove(tsadc->domain); ++ } ++ ++ return 0; ++} ++ + static void mx25_tsadc_setup_clk(struct platform_device *pdev, + struct mx25_tsadc *tsadc) + { +@@ -171,18 +184,21 @@ static int mx25_tsadc_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, tsadc); + +- return devm_of_platform_populate(dev); ++ ret = devm_of_platform_populate(dev); ++ if (ret) ++ goto err_irq; ++ ++ return 0; ++ ++err_irq: ++ mx25_tsadc_unset_irq(pdev); ++ ++ return ret; + } + + static int mx25_tsadc_remove(struct platform_device *pdev) + { +- struct mx25_tsadc *tsadc = platform_get_drvdata(pdev); +- int irq = platform_get_irq(pdev, 0); +- +- if (irq) { +- irq_set_chained_handler_and_data(irq, NULL, NULL); +- irq_domain_remove(tsadc->domain); +- } ++ mx25_tsadc_unset_irq(pdev); + + return 0; + } +-- +2.35.1 + diff --git a/queue-5.10/mfd-fsl-imx25-fix-check-for-platform_get_irq-errors.patch b/queue-5.10/mfd-fsl-imx25-fix-check-for-platform_get_irq-errors.patch new file mode 100644 index 00000000000..eb99da90699 --- /dev/null +++ b/queue-5.10/mfd-fsl-imx25-fix-check-for-platform_get_irq-errors.patch @@ -0,0 +1,49 @@ +From bb2ba24f58ab96cc71d1bcb09a5a81837701d98e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Aug 2022 13:53:05 +0300 +Subject: mfd: fsl-imx25: Fix check for platform_get_irq() errors + +From: Dan Carpenter + +[ Upstream commit 75db7907355ca5e2ff606e9dd3e86b6c3a455fe2 ] + +The mx25_tsadc_remove() function assumes all non-zero returns are success +but the platform_get_irq() function returns negative on error and +positive non-zero values on success. It never returns zero, but if it +did then treat that as a success. + +Fixes: 18f773937968 ("mfd: fsl-imx25: Clean up irq settings during removal") +Signed-off-by: Dan Carpenter +Reviewed-by: Martin Kaiser +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/YvTfkbVQWYKMKS/t@kili +Signed-off-by: Sasha Levin +--- + drivers/mfd/fsl-imx25-tsadc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c +index 95103b2cc471..5f1f6f3a0696 100644 +--- a/drivers/mfd/fsl-imx25-tsadc.c ++++ b/drivers/mfd/fsl-imx25-tsadc.c +@@ -69,7 +69,7 @@ static int mx25_tsadc_setup_irq(struct platform_device *pdev, + int irq; + + irq = platform_get_irq(pdev, 0); +- if (irq <= 0) ++ if (irq < 0) + return irq; + + tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops, +@@ -89,7 +89,7 @@ static int mx25_tsadc_unset_irq(struct platform_device *pdev) + struct mx25_tsadc *tsadc = platform_get_drvdata(pdev); + int irq = platform_get_irq(pdev, 0); + +- if (irq) { ++ if (irq >= 0) { + irq_set_chained_handler_and_data(irq, NULL, NULL); + irq_domain_remove(tsadc->domain); + } +-- +2.35.1 + diff --git a/queue-5.10/mfd-intel_soc_pmic-fix-an-error-handling-path-in-int.patch b/queue-5.10/mfd-intel_soc_pmic-fix-an-error-handling-path-in-int.patch new file mode 100644 index 00000000000..f90fad582f3 --- /dev/null +++ b/queue-5.10/mfd-intel_soc_pmic-fix-an-error-handling-path-in-int.patch @@ -0,0 +1,42 @@ +From 6f656f380befee322557bb0d0fe25dbb685aa8e4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 1 Aug 2022 14:42:02 +0300 +Subject: mfd: intel_soc_pmic: Fix an error handling path in + intel_soc_pmic_i2c_probe() + +From: Christophe JAILLET + +[ Upstream commit 48749cabba109397b4e7dd556e85718ec0ec114d ] + +The commit in Fixes: has added a pwm_add_table() call in the probe() and +a pwm_remove_table() call in the remove(), but forget to update the error +handling path of the probe. + +Add the missing pwm_remove_table() call. + +Fixes: a3aa9a93df9f ("mfd: intel_soc_pmic_core: ADD PWM lookup table for CRC PMIC based PWM") +Signed-off-by: Christophe JAILLET +Signed-off-by: Andy Shevchenko +Reviewed-by: Hans de Goede +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/20220801114211.36267-1-andriy.shevchenko@linux.intel.com +Signed-off-by: Sasha Levin +--- + drivers/mfd/intel_soc_pmic_core.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c +index ddd64f9e3341..926653e1f603 100644 +--- a/drivers/mfd/intel_soc_pmic_core.c ++++ b/drivers/mfd/intel_soc_pmic_core.c +@@ -95,6 +95,7 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c, + return 0; + + err_del_irq_chip: ++ pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup)); + regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); + return ret; + } +-- +2.35.1 + diff --git a/queue-5.10/mfd-lp8788-fix-an-error-handling-path-in-lp8788_irq_.patch b/queue-5.10/mfd-lp8788-fix-an-error-handling-path-in-lp8788_irq_.patch new file mode 100644 index 00000000000..0e160ea5754 --- /dev/null +++ b/queue-5.10/mfd-lp8788-fix-an-error-handling-path-in-lp8788_irq_.patch @@ -0,0 +1,48 @@ +From 8f319a52277b4c784ebe3b7d931d26d0e529d9af Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 31 Jul 2022 11:55:38 +0200 +Subject: mfd: lp8788: Fix an error handling path in lp8788_irq_init() and + lp8788_irq_init() + +From: Christophe JAILLET + +[ Upstream commit 557244f6284f30613f2d61f14b579303165876c3 ] + +In lp8788_irq_init(), if an error occurs after a successful +irq_domain_add_linear() call, it must be undone by a corresponding +irq_domain_remove() call. + +irq_domain_remove() should also be called in lp8788_irq_exit() for the same +reason. + +Fixes: eea6b7cc53aa ("mfd: Add lp8788 mfd driver") +Signed-off-by: Christophe JAILLET +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/bcd5a72c9c1c383dd6324680116426e32737655a.1659261275.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Sasha Levin +--- + drivers/mfd/lp8788-irq.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/mfd/lp8788-irq.c b/drivers/mfd/lp8788-irq.c +index 348439a3fbbd..39006297f3d2 100644 +--- a/drivers/mfd/lp8788-irq.c ++++ b/drivers/mfd/lp8788-irq.c +@@ -175,6 +175,7 @@ int lp8788_irq_init(struct lp8788 *lp, int irq) + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "lp8788-irq", irqd); + if (ret) { ++ irq_domain_remove(lp->irqdm); + dev_err(lp->dev, "failed to create a thread for IRQ_N\n"); + return ret; + } +@@ -188,4 +189,6 @@ void lp8788_irq_exit(struct lp8788 *lp) + { + if (lp->irq) + free_irq(lp->irq, lp->irqdm); ++ if (lp->irqdm) ++ irq_domain_remove(lp->irqdm); + } +-- +2.35.1 + diff --git a/queue-5.10/mfd-lp8788-fix-an-error-handling-path-in-lp8788_prob.patch b/queue-5.10/mfd-lp8788-fix-an-error-handling-path-in-lp8788_prob.patch new file mode 100644 index 00000000000..889cd809287 --- /dev/null +++ b/queue-5.10/mfd-lp8788-fix-an-error-handling-path-in-lp8788_prob.patch @@ -0,0 +1,50 @@ +From 6445d4644b15780a03d3e0fb2733dd59de26aece Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 31 Jul 2022 11:55:27 +0200 +Subject: mfd: lp8788: Fix an error handling path in lp8788_probe() + +From: Christophe JAILLET + +[ Upstream commit becfdcd75126b20b8ec10066c5e85b34f8994ad5 ] + +Should an error occurs in mfd_add_devices(), some resources need to be +released, as already done in the .remove() function. + +Add an error handling path and a lp8788_irq_exit() call to undo a previous +lp8788_irq_init(). + +Fixes: eea6b7cc53aa ("mfd: Add lp8788 mfd driver") +Signed-off-by: Christophe JAILLET +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/18398722da9df9490722d853e4797350189ae79b.1659261275.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Sasha Levin +--- + drivers/mfd/lp8788.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/mfd/lp8788.c b/drivers/mfd/lp8788.c +index 768d556b3fe9..5c3d642c8e3a 100644 +--- a/drivers/mfd/lp8788.c ++++ b/drivers/mfd/lp8788.c +@@ -195,8 +195,16 @@ static int lp8788_probe(struct i2c_client *cl, const struct i2c_device_id *id) + if (ret) + return ret; + +- return mfd_add_devices(lp->dev, -1, lp8788_devs, +- ARRAY_SIZE(lp8788_devs), NULL, 0, NULL); ++ ret = mfd_add_devices(lp->dev, -1, lp8788_devs, ++ ARRAY_SIZE(lp8788_devs), NULL, 0, NULL); ++ if (ret) ++ goto err_exit_irq; ++ ++ return 0; ++ ++err_exit_irq: ++ lp8788_irq_exit(lp); ++ return ret; + } + + static int lp8788_remove(struct i2c_client *cl) +-- +2.35.1 + diff --git a/queue-5.10/mfd-sm501-add-check-for-platform_driver_register.patch b/queue-5.10/mfd-sm501-add-check-for-platform_driver_register.patch new file mode 100644 index 00000000000..b062598849d --- /dev/null +++ b/queue-5.10/mfd-sm501-add-check-for-platform_driver_register.patch @@ -0,0 +1,43 @@ +From c9c71226808180a88059797bbe1d9881e6f8f417 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 17:11:12 +0800 +Subject: mfd: sm501: Add check for platform_driver_register() + +From: Jiasheng Jiang + +[ Upstream commit 8325a6c24ad78b8c1acc3c42b098ee24105d68e5 ] + +As platform_driver_register() can return error numbers, +it should be better to check platform_driver_register() +and deal with the exception. + +Fixes: b6d6454fdb66 ("[PATCH] mfd: SM501 core driver") +Signed-off-by: Jiasheng Jiang +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/20220913091112.1739138-1-jiasheng@iscas.ac.cn +Signed-off-by: Sasha Levin +--- + drivers/mfd/sm501.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c +index 6d2f4a0a901d..37ad72d8cde2 100644 +--- a/drivers/mfd/sm501.c ++++ b/drivers/mfd/sm501.c +@@ -1720,7 +1720,12 @@ static struct platform_driver sm501_plat_driver = { + + static int __init sm501_base_init(void) + { +- platform_driver_register(&sm501_plat_driver); ++ int ret; ++ ++ ret = platform_driver_register(&sm501_plat_driver); ++ if (ret < 0) ++ return ret; ++ + return pci_register_driver(&sm501_pci_driver); + } + +-- +2.35.1 + diff --git a/queue-5.10/micrel-ksz8851-fixes-struct-pointer-issue.patch b/queue-5.10/micrel-ksz8851-fixes-struct-pointer-issue.patch new file mode 100644 index 00000000000..9b19df2c356 --- /dev/null +++ b/queue-5.10/micrel-ksz8851-fixes-struct-pointer-issue.patch @@ -0,0 +1,54 @@ +From 15a12840d96b2caa1c2b21308cbf8777c5aefaa6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 22 Aug 2022 16:39:32 -0500 +Subject: micrel: ksz8851: fixes struct pointer issue + +From: Jerry Ray + +[ Upstream commit fef5de753ff01887cfa50990532c3890fccb9338 ] + +Issue found during code review. This bug has no impact as long as the +ks8851_net structure is the first element of the ks8851_net_spi structure. +As long as the offset to the ks8851_net struct is zero, the container_of() +macro is subtracting 0 and therefore no damage done. But if the +ks8851_net_spi struct is ever modified such that the ks8851_net struct +within it is no longer the first element of the struct, then the bug would +manifest itself and cause problems. + +struct ks8851_net is contained within ks8851_net_spi. +ks is contained within kss. +kss is the priv_data of the netdev structure. + +Signed-off-by: Jerry Ray +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/micrel/ks8851_spi.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/micrel/ks8851_spi.c b/drivers/net/ethernet/micrel/ks8851_spi.c +index 4ec7f1615977..8327e7f30476 100644 +--- a/drivers/net/ethernet/micrel/ks8851_spi.c ++++ b/drivers/net/ethernet/micrel/ks8851_spi.c +@@ -415,7 +415,8 @@ static int ks8851_probe_spi(struct spi_device *spi) + + spi->bits_per_word = 8; + +- ks = netdev_priv(netdev); ++ kss = netdev_priv(netdev); ++ ks = &kss->ks8851; + + ks->lock = ks8851_lock_spi; + ks->unlock = ks8851_unlock_spi; +@@ -435,8 +436,6 @@ static int ks8851_probe_spi(struct spi_device *spi) + IRQ_RXPSI) /* RX process stop */ + ks->rc_ier = STD_IRQ; + +- kss = to_ks8851_spi(ks); +- + kss->spidev = spi; + mutex_init(&kss->lock); + INIT_WORK(&kss->tx_work, ks8851_tx_work); +-- +2.35.1 + diff --git a/queue-5.10/mips-bcm47xx-cast-memcmp-of-function-to-void.patch b/queue-5.10/mips-bcm47xx-cast-memcmp-of-function-to-void.patch new file mode 100644 index 00000000000..6d0548f9707 --- /dev/null +++ b/queue-5.10/mips-bcm47xx-cast-memcmp-of-function-to-void.patch @@ -0,0 +1,62 @@ +From e66549ccd6e1f7f2dc6aae778e0dcd2d2a317679 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 16:05:56 -0700 +Subject: MIPS: BCM47XX: Cast memcmp() of function to (void *) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Kees Cook + +[ Upstream commit 0dedcf6e3301836eb70cfa649052e7ce4fcd13ba ] + +Clang is especially sensitive about argument type matching when using +__overloaded functions (like memcmp(), etc). Help it see that function +pointers are just "void *". Avoids this error: + +arch/mips/bcm47xx/prom.c:89:8: error: no matching function for call to 'memcmp' + if (!memcmp(prom_init, prom_init + mem, 32)) + ^~~~~~ +include/linux/string.h:156:12: note: candidate function not viable: no known conversion from 'void (void)' to 'const void *' for 1st argument extern int memcmp(const void *,const void *,__kernel_size_t); + +Cc: Hauke Mehrtens +Cc: "Rafał Miłecki" +Cc: Thomas Bogendoerfer +Cc: linux-mips@vger.kernel.org +Cc: Nathan Chancellor +Cc: Nick Desaulniers +Cc: llvm@lists.linux.dev +Reported-by: kernel test robot +Link: https://lore.kernel.org/lkml/202209080652.sz2d68e5-lkp@intel.com +Signed-off-by: Kees Cook +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Sasha Levin +--- + arch/mips/bcm47xx/prom.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c +index 3e2a8166377f..22509b5fab74 100644 +--- a/arch/mips/bcm47xx/prom.c ++++ b/arch/mips/bcm47xx/prom.c +@@ -86,7 +86,7 @@ static __init void prom_init_mem(void) + pr_debug("Assume 128MB RAM\n"); + break; + } +- if (!memcmp(prom_init, prom_init + mem, 32)) ++ if (!memcmp((void *)prom_init, (void *)prom_init + mem, 32)) + break; + } + lowmem = mem; +@@ -163,7 +163,7 @@ void __init bcm47xx_prom_highmem_init(void) + + off = EXTVBASE + __pa(off); + for (extmem = 128 << 20; extmem < 512 << 20; extmem <<= 1) { +- if (!memcmp(prom_init, (void *)(off + extmem), 16)) ++ if (!memcmp((void *)prom_init, (void *)(off + extmem), 16)) + break; + } + extmem -= lowmem; +-- +2.35.1 + diff --git a/queue-5.10/mips-sgi-ip27-fix-platform-device-leak-in-bridge_pla.patch b/queue-5.10/mips-sgi-ip27-fix-platform-device-leak-in-bridge_pla.patch new file mode 100644 index 00000000000..d0a7b2bc1af --- /dev/null +++ b/queue-5.10/mips-sgi-ip27-fix-platform-device-leak-in-bridge_pla.patch @@ -0,0 +1,141 @@ +From 544d3181afcf2a4560cc11b3791b63b1c8862bc5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 14 Sep 2022 11:29:17 +0800 +Subject: MIPS: SGI-IP27: Fix platform-device leak in bridge_platform_create() + +From: Lin Yujun + +[ Upstream commit 11bec9cba4de06b3c0e9e4041453c2caaa1cbec1 ] + +In error case in bridge_platform_create after calling +platform_device_add()/platform_device_add_data()/ +platform_device_add_resources(), release the failed +'pdev' or it will be leak, call platform_device_put() +to fix this problem. + +Besides, 'pdev' is divided into 'pdev_wd' and 'pdev_bd', +use platform_device_unregister() to release sgi_w1 +resources when xtalk-bridge registration fails. + +Fixes: 5dc76a96e95a ("MIPS: PCI: use information from 1-wire PROM for IOC3 detection") +Signed-off-by: Lin Yujun +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Sasha Levin +--- + arch/mips/sgi-ip27/ip27-xtalk.c | 70 +++++++++++++++++++++++---------- + 1 file changed, 50 insertions(+), 20 deletions(-) + +diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c +index e762886d1dda..5143d1cf8984 100644 +--- a/arch/mips/sgi-ip27/ip27-xtalk.c ++++ b/arch/mips/sgi-ip27/ip27-xtalk.c +@@ -27,15 +27,18 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid) + { + struct xtalk_bridge_platform_data *bd; + struct sgi_w1_platform_data *wd; +- struct platform_device *pdev; ++ struct platform_device *pdev_wd; ++ struct platform_device *pdev_bd; + struct resource w1_res; + unsigned long offset; + + offset = NODE_OFFSET(nasid); + + wd = kzalloc(sizeof(*wd), GFP_KERNEL); +- if (!wd) +- goto no_mem; ++ if (!wd) { ++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget); ++ return; ++ } + + snprintf(wd->dev_id, sizeof(wd->dev_id), "bridge-%012lx", + offset + (widget << SWIN_SIZE_BITS)); +@@ -46,24 +49,35 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid) + w1_res.end = w1_res.start + 3; + w1_res.flags = IORESOURCE_MEM; + +- pdev = platform_device_alloc("sgi_w1", PLATFORM_DEVID_AUTO); +- if (!pdev) { +- kfree(wd); +- goto no_mem; ++ pdev_wd = platform_device_alloc("sgi_w1", PLATFORM_DEVID_AUTO); ++ if (!pdev_wd) { ++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget); ++ goto err_kfree_wd; ++ } ++ if (platform_device_add_resources(pdev_wd, &w1_res, 1)) { ++ pr_warn("xtalk:n%d/%x bridge failed to add platform resources.\n", nasid, widget); ++ goto err_put_pdev_wd; ++ } ++ if (platform_device_add_data(pdev_wd, wd, sizeof(*wd))) { ++ pr_warn("xtalk:n%d/%x bridge failed to add platform data.\n", nasid, widget); ++ goto err_put_pdev_wd; ++ } ++ if (platform_device_add(pdev_wd)) { ++ pr_warn("xtalk:n%d/%x bridge failed to add platform device.\n", nasid, widget); ++ goto err_put_pdev_wd; + } +- platform_device_add_resources(pdev, &w1_res, 1); +- platform_device_add_data(pdev, wd, sizeof(*wd)); + /* platform_device_add_data() duplicates the data */ + kfree(wd); +- platform_device_add(pdev); + + bd = kzalloc(sizeof(*bd), GFP_KERNEL); +- if (!bd) +- goto no_mem; +- pdev = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO); +- if (!pdev) { +- kfree(bd); +- goto no_mem; ++ if (!bd) { ++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget); ++ goto err_unregister_pdev_wd; ++ } ++ pdev_bd = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO); ++ if (!pdev_bd) { ++ pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget); ++ goto err_kfree_bd; + } + + +@@ -84,15 +98,31 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid) + bd->io.flags = IORESOURCE_IO; + bd->io_offset = offset; + +- platform_device_add_data(pdev, bd, sizeof(*bd)); ++ if (platform_device_add_data(pdev_bd, bd, sizeof(*bd))) { ++ pr_warn("xtalk:n%d/%x bridge failed to add platform data.\n", nasid, widget); ++ goto err_put_pdev_bd; ++ } ++ if (platform_device_add(pdev_bd)) { ++ pr_warn("xtalk:n%d/%x bridge failed to add platform device.\n", nasid, widget); ++ goto err_put_pdev_bd; ++ } + /* platform_device_add_data() duplicates the data */ + kfree(bd); +- platform_device_add(pdev); + pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget); + return; + +-no_mem: +- pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget); ++err_put_pdev_bd: ++ platform_device_put(pdev_bd); ++err_kfree_bd: ++ kfree(bd); ++err_unregister_pdev_wd: ++ platform_device_unregister(pdev_wd); ++ return; ++err_put_pdev_wd: ++ platform_device_put(pdev_wd); ++err_kfree_wd: ++ kfree(wd); ++ return; + } + + static int probe_one_port(nasid_t nasid, int widget, int masterwid) +-- +2.35.1 + diff --git a/queue-5.10/mips-sgi-ip27-free-some-unused-memory.patch b/queue-5.10/mips-sgi-ip27-free-some-unused-memory.patch new file mode 100644 index 00000000000..042bab2f027 --- /dev/null +++ b/queue-5.10/mips-sgi-ip27-free-some-unused-memory.patch @@ -0,0 +1,45 @@ +From 99a022102d97a202434408b7e032a36d6cd8639d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 23 Apr 2022 15:24:03 +0200 +Subject: MIPS: SGI-IP27: Free some unused memory + +From: Christophe JAILLET + +[ Upstream commit 33d7085682b4aa212ebfadbc21da81dfefaaac16 ] + +platform_device_add_data() duplicates the memory it is passed. So we can +free some memory to save a few bytes that would remain unused otherwise. + +Signed-off-by: Christophe JAILLET +Signed-off-by: Thomas Bogendoerfer +Stable-dep-of: 11bec9cba4de ("MIPS: SGI-IP27: Fix platform-device leak in bridge_platform_create()") +Signed-off-by: Sasha Levin +--- + arch/mips/sgi-ip27/ip27-xtalk.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c +index 000ede156bdc..e762886d1dda 100644 +--- a/arch/mips/sgi-ip27/ip27-xtalk.c ++++ b/arch/mips/sgi-ip27/ip27-xtalk.c +@@ -53,6 +53,8 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid) + } + platform_device_add_resources(pdev, &w1_res, 1); + platform_device_add_data(pdev, wd, sizeof(*wd)); ++ /* platform_device_add_data() duplicates the data */ ++ kfree(wd); + platform_device_add(pdev); + + bd = kzalloc(sizeof(*bd), GFP_KERNEL); +@@ -83,6 +85,8 @@ static void bridge_platform_create(nasid_t nasid, int widget, int masterwid) + bd->io_offset = offset; + + platform_device_add_data(pdev, bd, sizeof(*bd)); ++ /* platform_device_add_data() duplicates the data */ ++ kfree(bd); + platform_device_add(pdev); + pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget); + return; +-- +2.35.1 + diff --git a/queue-5.10/misc-ocxl-fix-possible-refcount-leak-in-afu_ioctl.patch b/queue-5.10/misc-ocxl-fix-possible-refcount-leak-in-afu_ioctl.patch new file mode 100644 index 00000000000..dfaac97e198 --- /dev/null +++ b/queue-5.10/misc-ocxl-fix-possible-refcount-leak-in-afu_ioctl.patch @@ -0,0 +1,38 @@ +From 09f77559cf8bb0d1d5fa950e15981e615538f235 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 16:26:00 +0800 +Subject: misc: ocxl: fix possible refcount leak in afu_ioctl() + +From: Hangyu Hua + +[ Upstream commit c3b69ba5114c860d730870c03ab4ee45276e5e35 ] + +eventfd_ctx_put need to be called to put the refcount that gotten by +eventfd_ctx_fdget when ocxl_irq_set_handler fails. + +Fixes: 060146614643 ("ocxl: move event_fd handling to frontend") +Acked-by: Frederic Barrat +Signed-off-by: Hangyu Hua +Link: https://lore.kernel.org/r/20220824082600.36159-1-hbh25y@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/misc/ocxl/file.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/misc/ocxl/file.c b/drivers/misc/ocxl/file.c +index c742ab02ae18..e094809b54ff 100644 +--- a/drivers/misc/ocxl/file.c ++++ b/drivers/misc/ocxl/file.c +@@ -259,6 +259,8 @@ static long afu_ioctl(struct file *file, unsigned int cmd, + if (IS_ERR(ev_ctx)) + return PTR_ERR(ev_ctx); + rc = ocxl_irq_set_handler(ctx, irq_id, irq_handler, irq_free, ev_ctx); ++ if (rc) ++ eventfd_ctx_put(ev_ctx); + break; + + case OCXL_IOCTL_GET_METADATA: +-- +2.35.1 + diff --git a/queue-5.10/misdn-fix-use-after-free-bugs-in-l1oip-timer-handler.patch b/queue-5.10/misdn-fix-use-after-free-bugs-in-l1oip-timer-handler.patch new file mode 100644 index 00000000000..f507f1fbccf --- /dev/null +++ b/queue-5.10/misdn-fix-use-after-free-bugs-in-l1oip-timer-handler.patch @@ -0,0 +1,97 @@ +From 5748aa8c213e329949357155f9f19d23d37e7e2f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 28 Sep 2022 21:39:38 +0800 +Subject: mISDN: fix use-after-free bugs in l1oip timer handlers + +From: Duoming Zhou + +[ Upstream commit 2568a7e0832ee30b0a351016d03062ab4e0e0a3f ] + +The l1oip_cleanup() traverses the l1oip_ilist and calls +release_card() to cleanup module and stack. However, +release_card() calls del_timer() to delete the timers +such as keep_tl and timeout_tl. If the timer handler is +running, the del_timer() will not stop it and result in +UAF bugs. One of the processes is shown below: + + (cleanup routine) | (timer handler) +release_card() | l1oip_timeout() + ... | + del_timer() | ... + ... | + kfree(hc) //FREE | + | hc->timeout_on = 0 //USE + +Fix by calling del_timer_sync() in release_card(), which +makes sure the timer handlers have finished before the +resources, such as l1oip and so on, have been deallocated. + +What's more, the hc->workq and hc->socket_thread can kick +those timers right back in. We add a bool flag to show +if card is released. Then, check this flag in hc->workq +and hc->socket_thread. + +Fixes: 3712b42d4b1b ("Add layer1 over IP support") +Signed-off-by: Duoming Zhou +Reviewed-by: Leon Romanovsky +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/isdn/mISDN/l1oip.h | 1 + + drivers/isdn/mISDN/l1oip_core.c | 13 +++++++------ + 2 files changed, 8 insertions(+), 6 deletions(-) + +diff --git a/drivers/isdn/mISDN/l1oip.h b/drivers/isdn/mISDN/l1oip.h +index 7ea10db20e3a..48133d022812 100644 +--- a/drivers/isdn/mISDN/l1oip.h ++++ b/drivers/isdn/mISDN/l1oip.h +@@ -59,6 +59,7 @@ struct l1oip { + int bundle; /* bundle channels in one frm */ + int codec; /* codec to use for transmis. */ + int limit; /* limit number of bchannels */ ++ bool shutdown; /* if card is released */ + + /* timer */ + struct timer_list keep_tl; +diff --git a/drivers/isdn/mISDN/l1oip_core.c b/drivers/isdn/mISDN/l1oip_core.c +index b57dcb834594..aec4f2a69c3b 100644 +--- a/drivers/isdn/mISDN/l1oip_core.c ++++ b/drivers/isdn/mISDN/l1oip_core.c +@@ -275,7 +275,7 @@ l1oip_socket_send(struct l1oip *hc, u8 localcodec, u8 channel, u32 chanmask, + p = frame; + + /* restart timer */ +- if (time_before(hc->keep_tl.expires, jiffies + 5 * HZ)) ++ if (time_before(hc->keep_tl.expires, jiffies + 5 * HZ) && !hc->shutdown) + mod_timer(&hc->keep_tl, jiffies + L1OIP_KEEPALIVE * HZ); + else + hc->keep_tl.expires = jiffies + L1OIP_KEEPALIVE * HZ; +@@ -601,7 +601,9 @@ l1oip_socket_parse(struct l1oip *hc, struct sockaddr_in *sin, u8 *buf, int len) + goto multiframe; + + /* restart timer */ +- if (time_before(hc->timeout_tl.expires, jiffies + 5 * HZ) || !hc->timeout_on) { ++ if ((time_before(hc->timeout_tl.expires, jiffies + 5 * HZ) || ++ !hc->timeout_on) && ++ !hc->shutdown) { + hc->timeout_on = 1; + mod_timer(&hc->timeout_tl, jiffies + L1OIP_TIMEOUT * HZ); + } else /* only adjust timer */ +@@ -1232,11 +1234,10 @@ release_card(struct l1oip *hc) + { + int ch; + +- if (timer_pending(&hc->keep_tl)) +- del_timer(&hc->keep_tl); ++ hc->shutdown = true; + +- if (timer_pending(&hc->timeout_tl)) +- del_timer(&hc->timeout_tl); ++ del_timer_sync(&hc->keep_tl); ++ del_timer_sync(&hc->timeout_tl); + + cancel_work_sync(&hc->workq); + +-- +2.35.1 + diff --git a/queue-5.10/mmc-au1xmmc-fix-an-error-handling-path-in-au1xmmc_pr.patch b/queue-5.10/mmc-au1xmmc-fix-an-error-handling-path-in-au1xmmc_pr.patch new file mode 100644 index 00000000000..ba1b0c71b37 --- /dev/null +++ b/queue-5.10/mmc-au1xmmc-fix-an-error-handling-path-in-au1xmmc_pr.patch @@ -0,0 +1,41 @@ +From ff70f01ccf503e5d904cd609aa20011241a3efa9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 09:33:57 +0200 +Subject: mmc: au1xmmc: Fix an error handling path in au1xmmc_probe() + +From: Christophe JAILLET + +[ Upstream commit 5cbedf52608cc3cbc1c2a9a861fb671620427a20 ] + +If clk_prepare_enable() fails, there is no point in calling +clk_disable_unprepare() in the error handling path. + +Move the out_clk label at the right place. + +Fixes: b6507596dfd6 ("MIPS: Alchemy: au1xmmc: use clk framework") +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/21d99886d07fa7fcbec74992657dabad98c935c4.1661412818.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/au1xmmc.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c +index bd00515fbaba..56a3bf51d446 100644 +--- a/drivers/mmc/host/au1xmmc.c ++++ b/drivers/mmc/host/au1xmmc.c +@@ -1097,8 +1097,9 @@ static int au1xmmc_probe(struct platform_device *pdev) + if (host->platdata && host->platdata->cd_setup && + !(mmc->caps & MMC_CAP_NEEDS_POLL)) + host->platdata->cd_setup(mmc, 0); +-out_clk: ++ + clk_disable_unprepare(host->clk); ++out_clk: + clk_put(host->clk); + out_irq: + free_irq(host->irq, host); +-- +2.35.1 + diff --git a/queue-5.10/mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch b/queue-5.10/mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch new file mode 100644 index 00000000000..9cbff040403 --- /dev/null +++ b/queue-5.10/mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch @@ -0,0 +1,38 @@ +From 8a94677272523de08dba26b0ca6398a1fb49f009 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 21:43:22 -0400 +Subject: mmc: sdhci-msm: add compatible string check for sdm670 + +From: Richard Acayan + +[ Upstream commit 4de95950d970c71a9e82a24573bb7a44fd95baa1 ] + +The Snapdragon 670 has the same quirk as Snapdragon 845 (needing to +restore the dll config). Add a compatible string check to detect the need +for this. + +Signed-off-by: Richard Acayan +Reviewed-by: Bhupesh Sharma +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220923014322.33620-3-mailingradian@gmail.com +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/sdhci-msm.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c +index 192cb8b20b47..ad2e73f9a58f 100644 +--- a/drivers/mmc/host/sdhci-msm.c ++++ b/drivers/mmc/host/sdhci-msm.c +@@ -2182,6 +2182,7 @@ static const struct sdhci_msm_variant_info sm8250_sdhci_var = { + static const struct of_device_id sdhci_msm_dt_match[] = { + {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var}, ++ {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var}, + {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var}, + {.compatible = "qcom,sm8250-sdhci", .data = &sm8250_sdhci_var}, + {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var}, +-- +2.35.1 + diff --git a/queue-5.10/mmc-wmt-sdmmc-fix-an-error-handling-path-in-wmt_mci_.patch b/queue-5.10/mmc-wmt-sdmmc-fix-an-error-handling-path-in-wmt_mci_.patch new file mode 100644 index 00000000000..bd48c6fe0bc --- /dev/null +++ b/queue-5.10/mmc-wmt-sdmmc-fix-an-error-handling-path-in-wmt_mci_.patch @@ -0,0 +1,48 @@ +From e71ab110daa0956a2b1eae5383871a67b0dcb9ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 21:06:40 +0200 +Subject: mmc: wmt-sdmmc: Fix an error handling path in wmt_mci_probe() + +From: Christophe JAILLET + +[ Upstream commit cb58188ad90a61784a56a64f5107faaf2ad323e7 ] + +A dma_free_coherent() call is missing in the error handling path of the +probe, as already done in the remove function. + +Fixes: 3a96dff0f828 ("mmc: SD/MMC Host Controller for Wondermedia WM8505/WM8650") +Signed-off-by: Christophe JAILLET +Reviewed-by: Dan Carpenter +Link: https://lore.kernel.org/r/53fc6ffa5d1c428fefeae7d313cf4a669c3a1e98.1663873255.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/wmt-sdmmc.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/wmt-sdmmc.c b/drivers/mmc/host/wmt-sdmmc.c +index cf10949fb0ac..8df722ec57ed 100644 +--- a/drivers/mmc/host/wmt-sdmmc.c ++++ b/drivers/mmc/host/wmt-sdmmc.c +@@ -849,7 +849,7 @@ static int wmt_mci_probe(struct platform_device *pdev) + if (IS_ERR(priv->clk_sdmmc)) { + dev_err(&pdev->dev, "Error getting clock\n"); + ret = PTR_ERR(priv->clk_sdmmc); +- goto fail5; ++ goto fail5_and_a_half; + } + + ret = clk_prepare_enable(priv->clk_sdmmc); +@@ -866,6 +866,9 @@ static int wmt_mci_probe(struct platform_device *pdev) + return 0; + fail6: + clk_put(priv->clk_sdmmc); ++fail5_and_a_half: ++ dma_free_coherent(&pdev->dev, mmc->max_blk_count * 16, ++ priv->dma_desc_buffer, priv->dma_desc_device_addr); + fail5: + free_irq(dma_irq, priv); + fail4: +-- +2.35.1 + diff --git a/queue-5.10/mtd-devices-docg3-check-the-return-value-of-devm_ior.patch b/queue-5.10/mtd-devices-docg3-check-the-return-value-of-devm_ior.patch new file mode 100644 index 00000000000..fc03ed5730a --- /dev/null +++ b/queue-5.10/mtd-devices-docg3-check-the-return-value-of-devm_ior.patch @@ -0,0 +1,46 @@ +From a34bd2403e23ca6871e4356c6681f40f1fe8f0d8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Jul 2022 17:16:44 +0800 +Subject: mtd: devices: docg3: check the return value of devm_ioremap() in the + probe + +From: William Dean + +[ Upstream commit 26e784433e6c65735cd6d93a8db52531970d9a60 ] + +The function devm_ioremap() in docg3_probe() can fail, so +its return value should be checked. + +Fixes: 82402aeb8c81e ("mtd: docg3: Use devm_*() functions") +Reported-by: Hacash Robot +Signed-off-by: William Dean +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220722091644.2937953-1-williamsukatube@163.com +Signed-off-by: Sasha Levin +--- + drivers/mtd/devices/docg3.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c +index a030792115bc..fa42473d04c1 100644 +--- a/drivers/mtd/devices/docg3.c ++++ b/drivers/mtd/devices/docg3.c +@@ -1975,9 +1975,14 @@ static int __init docg3_probe(struct platform_device *pdev) + dev_err(dev, "No I/O memory resource defined\n"); + return ret; + } +- base = devm_ioremap(dev, ress->start, DOC_IOSPACE_SIZE); + + ret = -ENOMEM; ++ base = devm_ioremap(dev, ress->start, DOC_IOSPACE_SIZE); ++ if (!base) { ++ dev_err(dev, "devm_ioremap dev failed\n"); ++ return ret; ++ } ++ + cascade = devm_kcalloc(dev, DOC_MAX_NBFLOORS, sizeof(*cascade), + GFP_KERNEL); + if (!cascade) +-- +2.35.1 + diff --git a/queue-5.10/mtd-rawnand-fsl_elbc-fix-none-ecc-mode.patch b/queue-5.10/mtd-rawnand-fsl_elbc-fix-none-ecc-mode.patch new file mode 100644 index 00000000000..497875220c1 --- /dev/null +++ b/queue-5.10/mtd-rawnand-fsl_elbc-fix-none-ecc-mode.patch @@ -0,0 +1,98 @@ +From 0f21d9b84bdd02e66097ecde54e2d1f295d69e9b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Jul 2022 20:43:28 +0200 +Subject: mtd: rawnand: fsl_elbc: Fix none ECC mode +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +[ Upstream commit 049e43b9fd8fd2966940485da163d67e96ee3fea ] + +Commit f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") added +support for specifying ECC mode via DTS and skipping autodetection. + +But it broke explicit specification of HW ECC mode in DTS as correct +settings for HW ECC mode are applied only when NONE mode or nothing was +specified in DTS file. + +Also it started aliasing NONE mode to be same as when ECC mode was not +specified and disallowed usage of ON_DIE mode. + +Fix all these issues. Use autodetection of ECC mode only in case when mode +was really not specified in DTS file by checking that ecc value is invalid. +Set HW ECC settings either when HW ECC was specified in DTS or it was +autodetected. And do not fail when ON_DIE mode is set. + +Fixes: f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") +Signed-off-by: Pali Rohár +Reviewed-by: Marek Behún +Reviewed-by: Marek Behún +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20220707184328.3845-1-pali@kernel.org +Signed-off-by: Sasha Levin +--- + drivers/mtd/nand/raw/fsl_elbc_nand.c | 28 ++++++++++++++++------------ + 1 file changed, 16 insertions(+), 12 deletions(-) + +diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c +index b2af7f81fdf8..c174b6dc3c6b 100644 +--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c ++++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c +@@ -727,36 +727,40 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) + struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + unsigned int al; + +- switch (chip->ecc.engine_type) { + /* + * if ECC was not chosen in DT, decide whether to use HW or SW ECC from + * CS Base Register + */ +- case NAND_ECC_ENGINE_TYPE_NONE: ++ if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) { + /* If CS Base Register selects full hardware ECC then use it */ + if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == + BR_DECC_CHK_GEN) { +- chip->ecc.read_page = fsl_elbc_read_page; +- chip->ecc.write_page = fsl_elbc_write_page; +- chip->ecc.write_subpage = fsl_elbc_write_subpage; +- + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; +- mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops); +- chip->ecc.size = 512; +- chip->ecc.bytes = 3; +- chip->ecc.strength = 1; + } else { + /* otherwise fall back to default software ECC */ + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; + } ++ } ++ ++ switch (chip->ecc.engine_type) { ++ /* if HW ECC was chosen, setup ecc and oob layout */ ++ case NAND_ECC_ENGINE_TYPE_ON_HOST: ++ chip->ecc.read_page = fsl_elbc_read_page; ++ chip->ecc.write_page = fsl_elbc_write_page; ++ chip->ecc.write_subpage = fsl_elbc_write_subpage; ++ mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops); ++ chip->ecc.size = 512; ++ chip->ecc.bytes = 3; ++ chip->ecc.strength = 1; + break; + +- /* if SW ECC was chosen in DT, we do not need to set anything here */ ++ /* if none or SW ECC was chosen, we do not need to set anything here */ ++ case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_SOFT: ++ case NAND_ECC_ENGINE_TYPE_ON_DIE: + break; + +- /* should we also implement *_ECC_ENGINE_CONTROLLER to do as above? */ + default: + return -EINVAL; + } +-- +2.35.1 + diff --git a/queue-5.10/mtd-rawnand-meson-fix-bit-map-use-in-meson_nfc_ecc_c.patch b/queue-5.10/mtd-rawnand-meson-fix-bit-map-use-in-meson_nfc_ecc_c.patch new file mode 100644 index 00000000000..7628a9fe0e4 --- /dev/null +++ b/queue-5.10/mtd-rawnand-meson-fix-bit-map-use-in-meson_nfc_ecc_c.patch @@ -0,0 +1,49 @@ +From 1c84bd7f627b1fd7714fdccebf5dd3cc7573ee15 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 28 Jul 2022 10:12:12 +0300 +Subject: mtd: rawnand: meson: fix bit map use in meson_nfc_ecc_correct() + +From: Dan Carpenter + +[ Upstream commit 3e4ad3212cf22687410b1e8f4e68feec50646113 ] + +The meson_nfc_ecc_correct() function accidentally does a right shift +instead of a left shift so it only works for BIT(0). Also use +BIT_ULL() because "correct_bitmap" is a u64 and we want to avoid +shift wrapping bugs. + +Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") +Signed-off-by: Dan Carpenter +Acked-by: Liang Yang +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/YuI2zF1hP65+LE7r@kili +Signed-off-by: Sasha Levin +--- + drivers/mtd/nand/raw/meson_nand.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c +index 327a2257ec26..38f490088d76 100644 +--- a/drivers/mtd/nand/raw/meson_nand.c ++++ b/drivers/mtd/nand/raw/meson_nand.c +@@ -454,7 +454,7 @@ static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips, + if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) { + mtd->ecc_stats.corrected += ECC_ERR_CNT(*info); + *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info)); +- *correct_bitmap |= 1 >> i; ++ *correct_bitmap |= BIT_ULL(i); + continue; + } + if ((nand->options & NAND_NEED_SCRAMBLING) && +@@ -800,7 +800,7 @@ static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf, + u8 *data = buf + i * ecc->size; + u8 *oob = nand->oob_poi + i * (ecc->bytes + 2); + +- if (correct_bitmap & (1 << i)) ++ if (correct_bitmap & BIT_ULL(i)) + continue; + ret = nand_check_erased_ecc_chunk(data, ecc->size, + oob, ecc->bytes + 2, +-- +2.35.1 + diff --git a/queue-5.10/nbd-fix-hung-when-signal-interrupts-nbd_start_device.patch b/queue-5.10/nbd-fix-hung-when-signal-interrupts-nbd_start_device.patch new file mode 100644 index 00000000000..7d3eb75c3b2 --- /dev/null +++ b/queue-5.10/nbd-fix-hung-when-signal-interrupts-nbd_start_device.patch @@ -0,0 +1,69 @@ +From f241011d70cd05fd48ae5a49089b736eb0ddc19f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 01:35:02 +0900 +Subject: nbd: Fix hung when signal interrupts nbd_start_device_ioctl() + +From: Shigeru Yoshida + +[ Upstream commit 1de7c3cf48fc41cd95adb12bd1ea9033a917798a ] + +syzbot reported hung task [1]. The following program is a simplified +version of the reproducer: + +int main(void) +{ + int sv[2], fd; + + if (socketpair(AF_UNIX, SOCK_STREAM, 0, sv) < 0) + return 1; + if ((fd = open("/dev/nbd0", 0)) < 0) + return 1; + if (ioctl(fd, NBD_SET_SIZE_BLOCKS, 0x81) < 0) + return 1; + if (ioctl(fd, NBD_SET_SOCK, sv[0]) < 0) + return 1; + if (ioctl(fd, NBD_DO_IT) < 0) + return 1; + return 0; +} + +When signal interrupt nbd_start_device_ioctl() waiting the condition +atomic_read(&config->recv_threads) == 0, the task can hung because it +waits the completion of the inflight IOs. + +This patch fixes the issue by clearing queue, not just shutdown, when +signal interrupt nbd_start_device_ioctl(). + +Link: https://syzkaller.appspot.com/bug?id=7d89a3ffacd2b83fdd39549bc4d8e0a89ef21239 [1] +Reported-by: syzbot+38e6c55d4969a14c1534@syzkaller.appspotmail.com +Signed-off-by: Shigeru Yoshida +Reviewed-by: Josef Bacik +Link: https://lore.kernel.org/r/20220907163502.577561-1-syoshida@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + drivers/block/nbd.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c +index 4a6b82d434ee..b0d3dadeb964 100644 +--- a/drivers/block/nbd.c ++++ b/drivers/block/nbd.c +@@ -1342,10 +1342,12 @@ static int nbd_start_device_ioctl(struct nbd_device *nbd, struct block_device *b + mutex_unlock(&nbd->config_lock); + ret = wait_event_interruptible(config->recv_wq, + atomic_read(&config->recv_threads) == 0); +- if (ret) ++ if (ret) { + sock_shutdown(nbd); +- flush_workqueue(nbd->recv_workq); ++ nbd_clear_que(nbd); ++ } + ++ flush_workqueue(nbd->recv_workq); + mutex_lock(&nbd->config_lock); + nbd_bdev_reset(bdev); + /* user requested, ignore socket errors */ +-- +2.35.1 + diff --git a/queue-5.10/net-davicom-fix-return-type-of-dm9000_start_xmit.patch b/queue-5.10/net-davicom-fix-return-type-of-dm9000_start_xmit.patch new file mode 100644 index 00000000000..18f7349727d --- /dev/null +++ b/queue-5.10/net-davicom-fix-return-type-of-dm9000_start_xmit.patch @@ -0,0 +1,46 @@ +From 0ce129fff05513ef0e2cf594131b5110a5de59c3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Sep 2022 12:47:19 -0700 +Subject: net: davicom: Fix return type of dm9000_start_xmit + +From: Nathan Huckleberry + +[ Upstream commit 0191580b000d50089a0b351f7cdbec4866e3d0d2 ] + +The ndo_start_xmit field in net_device_ops is expected to be of type +netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev). + +The mismatched return type breaks forward edge kCFI since the underlying +function definition does not match the function hook definition. + +The return type of dm9000_start_xmit should be changed from int to +netdev_tx_t. + +Reported-by: Dan Carpenter +Link: https://github.com/ClangBuiltLinux/linux/issues/1703 +Cc: llvm@lists.linux.dev +Signed-off-by: Nathan Huckleberry +Reviewed-by: Nathan Chancellor +Link: https://lore.kernel.org/r/20220912194722.809525-1-nhuck@google.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/davicom/dm9000.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c +index afc4a103c508..c9ee5185e73e 100644 +--- a/drivers/net/ethernet/davicom/dm9000.c ++++ b/drivers/net/ethernet/davicom/dm9000.c +@@ -1015,7 +1015,7 @@ static void dm9000_send_packet(struct net_device *dev, + * Hardware start transmission. + * Send a packet to media from the upper layer. + */ +-static int ++static netdev_tx_t + dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) + { + unsigned long flags; +-- +2.35.1 + diff --git a/queue-5.10/net-ethernet-ti-davinci_emac-fix-return-type-of-emac.patch b/queue-5.10/net-ethernet-ti-davinci_emac-fix-return-type-of-emac.patch new file mode 100644 index 00000000000..242a96057e8 --- /dev/null +++ b/queue-5.10/net-ethernet-ti-davinci_emac-fix-return-type-of-emac.patch @@ -0,0 +1,46 @@ +From a2a2442084cb620dc363e83410ee3fbdfecc6afe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Sep 2022 12:50:19 -0700 +Subject: net: ethernet: ti: davinci_emac: Fix return type of emac_dev_xmit + +From: Nathan Huckleberry + +[ Upstream commit 5972ca946098487c5155fe13654743f9010f5ed5 ] + +The ndo_start_xmit field in net_device_ops is expected to be of type +netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev). + +The mismatched return type breaks forward edge kCFI since the underlying +function definition does not match the function hook definition. + +The return type of emac_dev_xmit should be changed from int to +netdev_tx_t. + +Reported-by: Dan Carpenter +Link: https://github.com/ClangBuiltLinux/linux/issues/1703 +Cc: llvm@lists.linux.dev +Signed-off-by: Nathan Huckleberry +Reviewed-by: Nathan Chancellor +Link: https://lore.kernel.org/r/20220912195023.810319-1-nhuck@google.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/ti/davinci_emac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c +index ad5293571af4..1dbba3e8ce50 100644 +--- a/drivers/net/ethernet/ti/davinci_emac.c ++++ b/drivers/net/ethernet/ti/davinci_emac.c +@@ -942,7 +942,7 @@ static void emac_tx_handler(void *token, int len, int status) + * + * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) + */ +-static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) ++static netdev_tx_t emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) + { + struct device *emac_dev = &ndev->dev; + int ret_code; +-- +2.35.1 + diff --git a/queue-5.10/net-fs_enet-fix-wrong-check-in-do_pd_setup.patch b/queue-5.10/net-fs_enet-fix-wrong-check-in-do_pd_setup.patch new file mode 100644 index 00000000000..f944ee19886 --- /dev/null +++ b/queue-5.10/net-fs_enet-fix-wrong-check-in-do_pd_setup.patch @@ -0,0 +1,36 @@ +From 059521866006adc4b570157f2fc3be909727ed2e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 13:55:13 +0000 +Subject: net: fs_enet: Fix wrong check in do_pd_setup + +From: Zheng Yongjun + +[ Upstream commit ec3f06b542a960806a81345042e4eee3f8c5dec4 ] + +Should check of_iomap return value 'fep->fec.fecp' instead of 'fep->fcc.fccp' + +Fixes: 976de6a8c304 ("fs_enet: Be an of_platform device when CONFIG_PPC_CPM_NEW_BINDING is set.") +Signed-off-by: Zheng Yongjun +Reviewed-by: Christophe Leroy +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c +index 99fe2c210d0f..61f4b6e50d29 100644 +--- a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c ++++ b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c +@@ -98,7 +98,7 @@ static int do_pd_setup(struct fs_enet_private *fep) + return -EINVAL; + + fep->fec.fecp = of_iomap(ofdev->dev.of_node, 0); +- if (!fep->fcc.fccp) ++ if (!fep->fec.fecp) + return -EINVAL; + + return 0; +-- +2.35.1 + diff --git a/queue-5.10/net-ftmac100-fix-endianness-related-issues-from-spar.patch b/queue-5.10/net-ftmac100-fix-endianness-related-issues-from-spar.patch new file mode 100644 index 00000000000..39fc6d47167 --- /dev/null +++ b/queue-5.10/net-ftmac100-fix-endianness-related-issues-from-spar.patch @@ -0,0 +1,67 @@ +From ad00610fb05f28a177eb3eba499ff8602bbef5f5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 14:37:49 +0300 +Subject: net: ftmac100: fix endianness-related issues from 'sparse' + +From: Sergei Antonov + +[ Upstream commit 9df696b3b3a4c96c3219eb87c7bf03fb50e490b8 ] + +Sparse found a number of endianness-related issues of these kinds: + +.../ftmac100.c:192:32: warning: restricted __le32 degrades to integer + +.../ftmac100.c:208:23: warning: incorrect type in assignment (different base types) +.../ftmac100.c:208:23: expected unsigned int rxdes0 +.../ftmac100.c:208:23: got restricted __le32 [usertype] + +.../ftmac100.c:249:23: warning: invalid assignment: &= +.../ftmac100.c:249:23: left side has type unsigned int +.../ftmac100.c:249:23: right side has type restricted __le32 + +.../ftmac100.c:527:16: warning: cast to restricted __le32 + +Change type of some fields from 'unsigned int' to '__le32' to fix it. + +Signed-off-by: Sergei Antonov +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20220902113749.1408562-1-saproj@gmail.com +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/faraday/ftmac100.h | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/faraday/ftmac100.h b/drivers/net/ethernet/faraday/ftmac100.h +index fe986f1673fc..8af32f9070f4 100644 +--- a/drivers/net/ethernet/faraday/ftmac100.h ++++ b/drivers/net/ethernet/faraday/ftmac100.h +@@ -122,9 +122,9 @@ + * Transmit descriptor, aligned to 16 bytes + */ + struct ftmac100_txdes { +- unsigned int txdes0; +- unsigned int txdes1; +- unsigned int txdes2; /* TXBUF_BADR */ ++ __le32 txdes0; ++ __le32 txdes1; ++ __le32 txdes2; /* TXBUF_BADR */ + unsigned int txdes3; /* not used by HW */ + } __attribute__ ((aligned(16))); + +@@ -143,9 +143,9 @@ struct ftmac100_txdes { + * Receive descriptor, aligned to 16 bytes + */ + struct ftmac100_rxdes { +- unsigned int rxdes0; +- unsigned int rxdes1; +- unsigned int rxdes2; /* RXBUF_BADR */ ++ __le32 rxdes0; ++ __le32 rxdes1; ++ __le32 rxdes2; /* RXBUF_BADR */ + unsigned int rxdes3; /* not used by HW */ + } __attribute__ ((aligned(16))); + +-- +2.35.1 + diff --git a/queue-5.10/net-ieee802154-reject-zero-sized-raw_sendmsg.patch b/queue-5.10/net-ieee802154-reject-zero-sized-raw_sendmsg.patch new file mode 100644 index 00000000000..e5d8e87ca1c --- /dev/null +++ b/queue-5.10/net-ieee802154-reject-zero-sized-raw_sendmsg.patch @@ -0,0 +1,40 @@ +From eb13284e2fddc4123ade1f516ad40797110e95c0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 2 Oct 2022 01:43:44 +0900 +Subject: net/ieee802154: reject zero-sized raw_sendmsg() + +From: Tetsuo Handa + +[ Upstream commit 3a4d061c699bd3eedc80dc97a4b2a2e1af83c6f5 ] + +syzbot is hitting skb_assert_len() warning at raw_sendmsg() for ieee802154 +socket. What commit dc633700f00f726e ("net/af_packet: check len when +min_header_len equals to 0") does also applies to ieee802154 socket. + +Link: https://syzkaller.appspot.com/bug?extid=5ea725c25d06fb9114c4 +Reported-by: syzbot +Fixes: fd1894224407c484 ("bpf: Don't redirect packets with invalid pkt_len") +Signed-off-by: Tetsuo Handa +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/ieee802154/socket.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/net/ieee802154/socket.c b/net/ieee802154/socket.c +index 7edec210780a..d4c162d63634 100644 +--- a/net/ieee802154/socket.c ++++ b/net/ieee802154/socket.c +@@ -252,6 +252,9 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t size) + return -EOPNOTSUPP; + } + ++ if (!size) ++ return -EINVAL; ++ + lock_sock(sk); + if (!sk->sk_bound_dev_if) + dev = dev_getfirstbyhwtype(sock_net(sk), ARPHRD_IEEE802154); +-- +2.35.1 + diff --git a/queue-5.10/net-if-sock-is-dead-don-t-access-sock-s-sk_wq-in-sk_.patch b/queue-5.10/net-if-sock-is-dead-don-t-access-sock-s-sk_wq-in-sk_.patch new file mode 100644 index 00000000000..10a56facefd --- /dev/null +++ b/queue-5.10/net-if-sock-is-dead-don-t-access-sock-s-sk_wq-in-sk_.patch @@ -0,0 +1,107 @@ +From a8de46729bde717623c21c60a906920858bdeb3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 23 Aug 2022 21:37:54 +0800 +Subject: net: If sock is dead don't access sock's sk_wq in + sk_stream_wait_memory + +From: Liu Jian + +[ Upstream commit 3f8ef65af927db247418d4e1db49164d7a158fc5 ] + +Fixes the below NULL pointer dereference: + + [...] + [ 14.471200] Call Trace: + [ 14.471562] + [ 14.471882] lock_acquire+0x245/0x2e0 + [ 14.472416] ? remove_wait_queue+0x12/0x50 + [ 14.473014] ? _raw_spin_lock_irqsave+0x17/0x50 + [ 14.473681] _raw_spin_lock_irqsave+0x3d/0x50 + [ 14.474318] ? remove_wait_queue+0x12/0x50 + [ 14.474907] remove_wait_queue+0x12/0x50 + [ 14.475480] sk_stream_wait_memory+0x20d/0x340 + [ 14.476127] ? do_wait_intr_irq+0x80/0x80 + [ 14.476704] do_tcp_sendpages+0x287/0x600 + [ 14.477283] tcp_bpf_push+0xab/0x260 + [ 14.477817] tcp_bpf_sendmsg_redir+0x297/0x500 + [ 14.478461] ? __local_bh_enable_ip+0x77/0xe0 + [ 14.479096] tcp_bpf_send_verdict+0x105/0x470 + [ 14.479729] tcp_bpf_sendmsg+0x318/0x4f0 + [ 14.480311] sock_sendmsg+0x2d/0x40 + [ 14.480822] ____sys_sendmsg+0x1b4/0x1c0 + [ 14.481390] ? copy_msghdr_from_user+0x62/0x80 + [ 14.482048] ___sys_sendmsg+0x78/0xb0 + [ 14.482580] ? vmf_insert_pfn_prot+0x91/0x150 + [ 14.483215] ? __do_fault+0x2a/0x1a0 + [ 14.483738] ? do_fault+0x15e/0x5d0 + [ 14.484246] ? __handle_mm_fault+0x56b/0x1040 + [ 14.484874] ? lock_is_held_type+0xdf/0x130 + [ 14.485474] ? find_held_lock+0x2d/0x90 + [ 14.486046] ? __sys_sendmsg+0x41/0x70 + [ 14.486587] __sys_sendmsg+0x41/0x70 + [ 14.487105] ? intel_pmu_drain_pebs_core+0x350/0x350 + [ 14.487822] do_syscall_64+0x34/0x80 + [ 14.488345] entry_SYSCALL_64_after_hwframe+0x63/0xcd + [...] + +The test scenario has the following flow: + +thread1 thread2 +----------- --------------- + tcp_bpf_sendmsg + tcp_bpf_send_verdict + tcp_bpf_sendmsg_redir sock_close + tcp_bpf_push_locked __sock_release + tcp_bpf_push //inet_release + do_tcp_sendpages sock->ops->release + sk_stream_wait_memory // tcp_close + sk_wait_event sk->sk_prot->close + release_sock(__sk); + *** + lock_sock(sk); + __tcp_close + sock_orphan(sk) + sk->sk_wq = NULL + release_sock + **** + lock_sock(__sk); + remove_wait_queue(sk_sleep(sk), &wait); + sk_sleep(sk) + //NULL pointer dereference + &rcu_dereference_raw(sk->sk_wq)->wait + +While waiting for memory in thread1, the socket is released with its wait +queue because thread2 has closed it. This caused by tcp_bpf_send_verdict +didn't increase the f_count of psock->sk_redir->sk_socket->file in thread1. + +We should check if SOCK_DEAD flag is set on wakeup in sk_stream_wait_memory +before accessing the wait queue. + +Suggested-by: Jakub Sitnicki +Signed-off-by: Liu Jian +Signed-off-by: Daniel Borkmann +Acked-by: John Fastabend +Cc: Eric Dumazet +Link: https://lore.kernel.org/bpf/20220823133755.314697-2-liujian56@huawei.com +Signed-off-by: Sasha Levin +--- + net/core/stream.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/net/core/stream.c b/net/core/stream.c +index a166a32b411f..a61130504827 100644 +--- a/net/core/stream.c ++++ b/net/core/stream.c +@@ -159,7 +159,8 @@ int sk_stream_wait_memory(struct sock *sk, long *timeo_p) + *timeo_p = current_timeo; + } + out: +- remove_wait_queue(sk_sleep(sk), &wait); ++ if (!sock_flag(sk, SOCK_DEAD)) ++ remove_wait_queue(sk_sleep(sk), &wait); + return err; + + do_error: +-- +2.35.1 + diff --git a/queue-5.10/net-korina-fix-return-type-of-korina_send_packet.patch b/queue-5.10/net-korina-fix-return-type-of-korina_send_packet.patch new file mode 100644 index 00000000000..ab978c924f1 --- /dev/null +++ b/queue-5.10/net-korina-fix-return-type-of-korina_send_packet.patch @@ -0,0 +1,47 @@ +From 38f4e2fc311463efb20aacbd18ec31bee4abb49a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Sep 2022 14:43:40 -0700 +Subject: net: korina: Fix return type of korina_send_packet + +From: Nathan Huckleberry + +[ Upstream commit 106c67ce46f3c82dd276e983668a91d6ed631173 ] + +The ndo_start_xmit field in net_device_ops is expected to be of type +netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev). + +The mismatched return type breaks forward edge kCFI since the underlying +function definition does not match the function hook definition. + +The return type of korina_send_packet should be changed from int to +netdev_tx_t. + +Reported-by: Dan Carpenter +Link: https://github.com/ClangBuiltLinux/linux/issues/1703 +Cc: llvm@lists.linux.dev +Signed-off-by: Nathan Huckleberry +Reviewed-by: Nathan Chancellor +Link: https://lore.kernel.org/r/20220912214344.928925-1-nhuck@google.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/korina.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/korina.c b/drivers/net/ethernet/korina.c +index 925161959b9b..7d74bb932ee1 100644 +--- a/drivers/net/ethernet/korina.c ++++ b/drivers/net/ethernet/korina.c +@@ -196,7 +196,8 @@ static void korina_chain_rx(struct korina_private *lp, + } + + /* transmit packet */ +-static int korina_send_packet(struct sk_buff *skb, struct net_device *dev) ++static netdev_tx_t korina_send_packet(struct sk_buff *skb, ++ struct net_device *dev) + { + struct korina_private *lp = netdev_priv(dev); + unsigned long flags; +-- +2.35.1 + diff --git a/queue-5.10/net-lantiq_etop-fix-return-type-for-implementation-o.patch b/queue-5.10/net-lantiq_etop-fix-return-type-for-implementation-o.patch new file mode 100644 index 00000000000..7a1111a033a --- /dev/null +++ b/queue-5.10/net-lantiq_etop-fix-return-type-for-implementation-o.patch @@ -0,0 +1,41 @@ +From a48d3081c2e884f6ccef5a7a1eb58744e006c481 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 16:15:21 +0800 +Subject: net: lantiq_etop: Fix return type for implementation of + ndo_start_xmit + +From: GUO Zihua + +[ Upstream commit c8ef3c94bda0e21123202d057d4a299698fa0ed9 ] + +Since Linux now supports CFI, it will be a good idea to fix mismatched +return type for implementation of hooks. Otherwise this might get +cought out by CFI and cause a panic. + +ltq_etop_tx() would return either NETDEV_TX_BUSY or NETDEV_TX_OK, so +change the return type to netdev_tx_t directly. + +Signed-off-by: GUO Zihua +Link: https://lore.kernel.org/r/20220902081521.59867-1-guozihua@huawei.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/lantiq_etop.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c +index 2d0c52f7106b..14c35ca72b75 100644 +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -451,7 +451,7 @@ ltq_etop_stop(struct net_device *dev) + return 0; + } + +-static int ++static netdev_tx_t + ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) + { + int queue = skb_get_queue_mapping(skb); +-- +2.35.1 + diff --git a/queue-5.10/net-mvpp2-fix-mvpp2-debugfs-leak.patch b/queue-5.10/net-mvpp2-fix-mvpp2-debugfs-leak.patch new file mode 100644 index 00000000000..fa74bff489a --- /dev/null +++ b/queue-5.10/net-mvpp2-fix-mvpp2-debugfs-leak.patch @@ -0,0 +1,108 @@ +From c35d95c86fd57c3ee96712691471cc825a84a82d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Oct 2022 17:19:27 +0100 +Subject: net: mvpp2: fix mvpp2 debugfs leak + +From: Russell King (Oracle) + +[ Upstream commit 0152dfee235e87660f52a117fc9f70dc55956bb4 ] + +When mvpp2 is unloaded, the driver specific debugfs directory is not +removed, which technically leads to a memory leak. However, this +directory is only created when the first device is probed, so the +hardware is present. Removing the module is only something a developer +would to when e.g. testing out changes, so the module would be +reloaded. So this memory leak is minor. + +The original attempt in commit fe2c9c61f668 ("net: mvpp2: debugfs: fix +memory leak when using debugfs_lookup()") that was labelled as a memory +leak fix was not, it fixed a refcount leak, but in doing so created a +problem when the module is reloaded - the directory already exists, but +mvpp2_root is NULL, so we lose all debugfs entries. This fix has been +reverted. + +This is the alternative fix, where we remove the offending directory +whenever the driver is unloaded. + +Fixes: 21da57a23125 ("net: mvpp2: add a debugfs interface for the Header Parser") +Signed-off-by: Russell King (Oracle) +Reviewed-by: Greg Kroah-Hartman +Reviewed-by: Marcin Wojtas +Link: https://lore.kernel.org/r/E1ofOAB-00CzkG-UO@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 + + drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c | 10 ++++++++-- + drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 13 ++++++++++++- + 3 files changed, 21 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +index d825eb021b22..e999ac2de34e 100644 +--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h ++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +@@ -1434,6 +1434,7 @@ u32 mvpp2_read(struct mvpp2 *priv, u32 offset); + void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); + + void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); ++void mvpp2_dbgfs_exit(void); + + #ifdef CONFIG_MVPP2_PTP + int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv); +diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c +index 4a3baa7e0142..75e83ea2a926 100644 +--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c ++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c +@@ -691,6 +691,13 @@ static int mvpp2_dbgfs_port_init(struct dentry *parent, + return 0; + } + ++static struct dentry *mvpp2_root; ++ ++void mvpp2_dbgfs_exit(void) ++{ ++ debugfs_remove(mvpp2_root); ++} ++ + void mvpp2_dbgfs_cleanup(struct mvpp2 *priv) + { + debugfs_remove_recursive(priv->dbgfs_dir); +@@ -700,10 +707,9 @@ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv) + + void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name) + { +- struct dentry *mvpp2_dir, *mvpp2_root; ++ struct dentry *mvpp2_dir; + int ret, i; + +- mvpp2_root = debugfs_lookup(MVPP2_DRIVER_NAME, NULL); + if (!mvpp2_root) + mvpp2_root = debugfs_create_dir(MVPP2_DRIVER_NAME, NULL); + +diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +index 542cd6f2c9bd..68c5ed8716c8 100644 +--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +@@ -7155,7 +7155,18 @@ static struct platform_driver mvpp2_driver = { + }, + }; + +-module_platform_driver(mvpp2_driver); ++static int __init mvpp2_driver_init(void) ++{ ++ return platform_driver_register(&mvpp2_driver); ++} ++module_init(mvpp2_driver_init); ++ ++static void __exit mvpp2_driver_exit(void) ++{ ++ platform_driver_unregister(&mvpp2_driver); ++ mvpp2_dbgfs_exit(); ++} ++module_exit(mvpp2_driver_exit); + + MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); + MODULE_AUTHOR("Marcin Wojtas "); +-- +2.35.1 + diff --git a/queue-5.10/net-rds-don-t-hold-sock-lock-when-cancelling-work-fr.patch b/queue-5.10/net-rds-don-t-hold-sock-lock-when-cancelling-work-fr.patch new file mode 100644 index 00000000000..46e12905e04 --- /dev/null +++ b/queue-5.10/net-rds-don-t-hold-sock-lock-when-cancelling-work-fr.patch @@ -0,0 +1,54 @@ +From a0eaeaee98b74cefd6bfd33d7708740b4209c059 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 00:25:37 +0900 +Subject: net: rds: don't hold sock lock when cancelling work from + rds_tcp_reset_callbacks() + +From: Tetsuo Handa + +[ Upstream commit a91b750fd6629354460282bbf5146c01b05c4859 ] + +syzbot is reporting lockdep warning at rds_tcp_reset_callbacks() [1], for +commit ac3615e7f3cffe2a ("RDS: TCP: Reduce code duplication in +rds_tcp_reset_callbacks()") added cancel_delayed_work_sync() into a section +protected by lock_sock() without realizing that rds_send_xmit() might call +lock_sock(). + +We don't need to protect cancel_delayed_work_sync() using lock_sock(), for +even if rds_{send,recv}_worker() re-queued this work while __flush_work() + from cancel_delayed_work_sync() was waiting for this work to complete, +retried rds_{send,recv}_worker() is no-op due to the absence of RDS_CONN_UP +bit. + +Link: https://syzkaller.appspot.com/bug?extid=78c55c7bc6f66e53dce2 [1] +Reported-by: syzbot +Co-developed-by: Hillf Danton +Signed-off-by: Hillf Danton +Signed-off-by: Tetsuo Handa +Tested-by: syzbot +Fixes: ac3615e7f3cffe2a ("RDS: TCP: Reduce code duplication in rds_tcp_reset_callbacks()") +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/rds/tcp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/net/rds/tcp.c b/net/rds/tcp.c +index 5327d130c4b5..b560d06e6d96 100644 +--- a/net/rds/tcp.c ++++ b/net/rds/tcp.c +@@ -166,10 +166,10 @@ void rds_tcp_reset_callbacks(struct socket *sock, + */ + atomic_set(&cp->cp_state, RDS_CONN_RESETTING); + wait_event(cp->cp_waitq, !test_bit(RDS_IN_XMIT, &cp->cp_flags)); +- lock_sock(osock->sk); + /* reset receive side state for rds_tcp_data_recv() for osock */ + cancel_delayed_work_sync(&cp->cp_send_w); + cancel_delayed_work_sync(&cp->cp_recv_w); ++ lock_sock(osock->sk); + if (tc->t_tinc) { + rds_inc_put(&tc->t_tinc->ti_inc); + tc->t_tinc = NULL; +-- +2.35.1 + diff --git a/queue-5.10/net-wwan-t7xx-add-control-dma-interface.patch b/queue-5.10/net-wwan-t7xx-add-control-dma-interface.patch new file mode 100644 index 00000000000..ff1f88e190f --- /dev/null +++ b/queue-5.10/net-wwan-t7xx-add-control-dma-interface.patch @@ -0,0 +1,1908 @@ +From 9440a65e8e13ed8cb353b44182ce6c51d154e08a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 6 May 2022 11:12:59 -0700 +Subject: net: wwan: t7xx: Add control DMA interface +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Haijun Liu + +[ Upstream commit 39d439047f1dc88f98b755d6f3a53a4ef8f0de21 ] + +Cross Layer DMA (CLDMA) Hardware interface (HIF) enables the control +path of Host-Modem data transfers. CLDMA HIF layer provides a common +interface to the Port Layer. + +CLDMA manages 8 independent RX/TX physical channels with data flow +control in HW queues. CLDMA uses ring buffers of General Packet +Descriptors (GPD) for TX/RX. GPDs can represent multiple or single +data buffers (DB). + +CLDMA HIF initializes GPD rings, registers ISR handlers for CLDMA +interrupts, and initializes CLDMA HW registers. + +CLDMA TX flow: +1. Port Layer write +2. Get DB address +3. Configure GPD +4. Triggering processing via HW register write + +CLDMA RX flow: +1. CLDMA HW sends a RX "done" to host +2. Driver starts thread to safely read GPD +3. DB is sent to Port layer +4. Create a new buffer for GPD ring + +Note: This patch does not enable compilation since it has dependencies +such as t7xx_pcie_mac_clear_int()/t7xx_pcie_mac_set_int() and +struct t7xx_pci_dev which are added by the core patch. + +Signed-off-by: Haijun Liu +Signed-off-by: Chandrashekar Devegowda +Co-developed-by: Ricardo Martinez +Signed-off-by: Ricardo Martinez +Reviewed-by: Loic Poulain +Reviewed-by: Ilpo Järvinen +Reviewed-by: Sergey Ryazanov +Signed-off-by: David S. Miller +Stable-dep-of: 2ac6cdd581f4 ("drm/dp_mst: fix drm_dp_dpcd_read return value checks") +Signed-off-by: Sasha Levin +--- + drivers/net/wwan/t7xx/t7xx_cldma.c | 281 ++++++ + drivers/net/wwan/t7xx/t7xx_cldma.h | 180 ++++ + drivers/net/wwan/t7xx/t7xx_hif_cldma.c | 1192 ++++++++++++++++++++++++ + drivers/net/wwan/t7xx/t7xx_hif_cldma.h | 126 +++ + drivers/net/wwan/t7xx/t7xx_reg.h | 33 + + 5 files changed, 1812 insertions(+) + create mode 100644 drivers/net/wwan/t7xx/t7xx_cldma.c + create mode 100644 drivers/net/wwan/t7xx/t7xx_cldma.h + create mode 100644 drivers/net/wwan/t7xx/t7xx_hif_cldma.c + create mode 100644 drivers/net/wwan/t7xx/t7xx_hif_cldma.h + create mode 100644 drivers/net/wwan/t7xx/t7xx_reg.h + +diff --git a/drivers/net/wwan/t7xx/t7xx_cldma.c b/drivers/net/wwan/t7xx/t7xx_cldma.c +new file mode 100644 +index 000000000000..9f43f256db1d +--- /dev/null ++++ b/drivers/net/wwan/t7xx/t7xx_cldma.c +@@ -0,0 +1,281 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2021, MediaTek Inc. ++ * Copyright (c) 2021-2022, Intel Corporation. ++ * ++ * Authors: ++ * Haijun Liu ++ * Moises Veleta ++ * Ricardo Martinez ++ * ++ * Contributors: ++ * Amir Hanania ++ * Andy Shevchenko ++ * Eliot Lee ++ * Sreehari Kancharla ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "t7xx_cldma.h" ++ ++#define ADDR_SIZE 8 ++ ++void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info) ++{ ++ u32 val; ++ ++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY); ++ val |= IP_BUSY_WAKEUP; ++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY); ++} ++ ++/** ++ * t7xx_cldma_hw_restore() - Restore CLDMA HW registers. ++ * @hw_info: Pointer to struct t7xx_cldma_hw. ++ * ++ * Restore HW after resume. Writes uplink configuration for CLDMA HW. ++ */ ++void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info) ++{ ++ u32 ul_cfg; ++ ++ ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG); ++ ul_cfg &= ~UL_CFG_BIT_MODE_MASK; ++ ++ if (hw_info->hw_mode == MODE_BIT_64) ++ ul_cfg |= UL_CFG_BIT_MODE_64; ++ else if (hw_info->hw_mode == MODE_BIT_40) ++ ul_cfg |= UL_CFG_BIT_MODE_40; ++ else if (hw_info->hw_mode == MODE_BIT_36) ++ ul_cfg |= UL_CFG_BIT_MODE_36; ++ ++ iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG); ++ /* Disable TX and RX invalid address check */ ++ iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM); ++ iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM); ++} ++ ++void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 val; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD : ++ hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD; ++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno); ++ iowrite32(val, reg); ++} ++ ++void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info) ++{ ++ /* Enable the TX & RX interrupts */ ++ iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0); ++ iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0); ++ /* Enable the empty queue interrupt */ ++ iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0); ++ iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0); ++} ++ ++void t7xx_cldma_hw_reset(void __iomem *ao_base) ++{ ++ u32 val; ++ ++ val = ioread32(ao_base + REG_INFRA_RST2_SET); ++ val |= RST2_PMIC_SW_RST_SET; ++ iowrite32(val, ao_base + REG_INFRA_RST2_SET); ++ val = ioread32(ao_base + REG_INFRA_RST4_SET); ++ val |= RST4_CLDMA1_SW_RST_SET; ++ iowrite32(val, ao_base + REG_INFRA_RST4_SET); ++ udelay(1); ++ ++ val = ioread32(ao_base + REG_INFRA_RST4_CLR); ++ val |= RST4_CLDMA1_SW_RST_CLR; ++ iowrite32(val, ao_base + REG_INFRA_RST4_CLR); ++ val = ioread32(ao_base + REG_INFRA_RST2_CLR); ++ val |= RST2_PMIC_SW_RST_CLR; ++ iowrite32(val, ao_base + REG_INFRA_RST2_CLR); ++} ++ ++bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno) ++{ ++ u32 offset = REG_CLDMA_UL_START_ADDRL_0 + qno * ADDR_SIZE; ++ ++ return ioread64(hw_info->ap_pdn_base + offset); ++} ++ ++void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address, ++ enum mtk_txrx tx_rx) ++{ ++ u32 offset = qno * ADDR_SIZE; ++ void __iomem *reg; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_START_ADDRL_0 : ++ hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0; ++ iowrite64(address, reg + offset); ++} ++ ++void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx) ++{ ++ void __iomem *base = hw_info->ap_pdn_base; ++ ++ if (tx_rx == MTK_RX) ++ iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD); ++ else ++ iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD); ++} ++ ++unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 mask, val; ++ ++ mask = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno); ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_STATUS : ++ hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS; ++ val = ioread32(reg); ++ ++ return val & mask; ++} ++ ++void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask) ++{ ++ unsigned int ch_id; ++ ++ ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0); ++ ch_id &= bitmask; ++ /* Clear the ch IDs in the TX interrupt status register */ ++ iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0); ++ ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0); ++} ++ ++void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask) ++{ ++ unsigned int ch_id; ++ ++ ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0); ++ ch_id &= bitmask; ++ /* Clear the ch IDs in the RX interrupt status register */ ++ iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0); ++ ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0); ++} ++ ++unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask, ++ enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 val; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 : ++ hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0; ++ val = ioread32(reg); ++ return val & bitmask; ++} ++ ++void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 val; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 : ++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0; ++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno); ++ iowrite32(val, reg); ++} ++ ++void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 val; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 : ++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0; ++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno); ++ iowrite32(val << EQ_STA_BIT_OFFSET, reg); ++} ++ ++void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 val; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 : ++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0; ++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno); ++ iowrite32(val, reg); ++} ++ ++void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ u32 val; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 : ++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0; ++ val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno); ++ iowrite32(val << EQ_STA_BIT_OFFSET, reg); ++} ++ ++/** ++ * t7xx_cldma_hw_init() - Initialize CLDMA HW. ++ * @hw_info: Pointer to struct t7xx_cldma_hw. ++ * ++ * Write uplink and downlink configuration to CLDMA HW. ++ */ ++void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info) ++{ ++ u32 ul_cfg, dl_cfg; ++ ++ ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG); ++ dl_cfg = ioread32(hw_info->ap_ao_base + REG_CLDMA_DL_CFG); ++ /* Configure the DRAM address mode */ ++ ul_cfg &= ~UL_CFG_BIT_MODE_MASK; ++ dl_cfg &= ~DL_CFG_BIT_MODE_MASK; ++ ++ if (hw_info->hw_mode == MODE_BIT_64) { ++ ul_cfg |= UL_CFG_BIT_MODE_64; ++ dl_cfg |= DL_CFG_BIT_MODE_64; ++ } else if (hw_info->hw_mode == MODE_BIT_40) { ++ ul_cfg |= UL_CFG_BIT_MODE_40; ++ dl_cfg |= DL_CFG_BIT_MODE_40; ++ } else if (hw_info->hw_mode == MODE_BIT_36) { ++ ul_cfg |= UL_CFG_BIT_MODE_36; ++ dl_cfg |= DL_CFG_BIT_MODE_36; ++ } ++ ++ iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG); ++ dl_cfg |= DL_CFG_UP_HW_LAST; ++ iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG); ++ iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK); ++ iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK); ++ iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM); ++ iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM); ++} ++ ++void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD : ++ hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD; ++ iowrite32(CLDMA_ALL_Q, reg); ++} ++ ++void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx) ++{ ++ void __iomem *reg; ++ ++ reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 : ++ hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0; ++ iowrite32(TXRX_STATUS_BITMASK, reg); ++ iowrite32(EMPTY_STATUS_BITMASK, reg); ++} +diff --git a/drivers/net/wwan/t7xx/t7xx_cldma.h b/drivers/net/wwan/t7xx/t7xx_cldma.h +new file mode 100644 +index 000000000000..8949e8377fb0 +--- /dev/null ++++ b/drivers/net/wwan/t7xx/t7xx_cldma.h +@@ -0,0 +1,180 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2021, MediaTek Inc. ++ * Copyright (c) 2021-2022, Intel Corporation. ++ * ++ * Authors: ++ * Haijun Liu ++ * Moises Veleta ++ * Ricardo Martinez ++ * ++ * Contributors: ++ * Amir Hanania ++ * Andy Shevchenko ++ * Sreehari Kancharla ++ */ ++ ++#ifndef __T7XX_CLDMA_H__ ++#define __T7XX_CLDMA_H__ ++ ++#include ++#include ++ ++#define CLDMA_TXQ_NUM 8 ++#define CLDMA_RXQ_NUM 8 ++#define CLDMA_ALL_Q GENMASK(7, 0) ++ ++/* Interrupt status bits */ ++#define EMPTY_STATUS_BITMASK GENMASK(15, 8) ++#define TXRX_STATUS_BITMASK GENMASK(7, 0) ++#define EQ_STA_BIT_OFFSET 8 ++#define L2_INT_BIT_COUNT 16 ++#define EQ_STA_BIT(index) (BIT((index) + EQ_STA_BIT_OFFSET) & EMPTY_STATUS_BITMASK) ++ ++#define TQ_ERR_INT_BITMASK GENMASK(23, 16) ++#define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24) ++ ++#define RQ_ERR_INT_BITMASK GENMASK(23, 16) ++#define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24) ++ ++#define CLDMA0_AO_BASE 0x10049000 ++#define CLDMA0_PD_BASE 0x1021d000 ++#define CLDMA1_AO_BASE 0x1004b000 ++#define CLDMA1_PD_BASE 0x1021f000 ++ ++#define CLDMA_R_AO_BASE 0x10023000 ++#define CLDMA_R_PD_BASE 0x1023d000 ++ ++/* CLDMA TX */ ++#define REG_CLDMA_UL_START_ADDRL_0 0x0004 ++#define REG_CLDMA_UL_START_ADDRH_0 0x0008 ++#define REG_CLDMA_UL_CURRENT_ADDRL_0 0x0044 ++#define REG_CLDMA_UL_CURRENT_ADDRH_0 0x0048 ++#define REG_CLDMA_UL_STATUS 0x0084 ++#define REG_CLDMA_UL_START_CMD 0x0088 ++#define REG_CLDMA_UL_RESUME_CMD 0x008c ++#define REG_CLDMA_UL_STOP_CMD 0x0090 ++#define REG_CLDMA_UL_ERROR 0x0094 ++#define REG_CLDMA_UL_CFG 0x0098 ++#define UL_CFG_BIT_MODE_36 BIT(5) ++#define UL_CFG_BIT_MODE_40 BIT(6) ++#define UL_CFG_BIT_MODE_64 BIT(7) ++#define UL_CFG_BIT_MODE_MASK GENMASK(7, 5) ++ ++#define REG_CLDMA_UL_MEM 0x009c ++#define UL_MEM_CHECK_DIS BIT(0) ++ ++/* CLDMA RX */ ++#define REG_CLDMA_DL_START_CMD 0x05bc ++#define REG_CLDMA_DL_RESUME_CMD 0x05c0 ++#define REG_CLDMA_DL_STOP_CMD 0x05c4 ++#define REG_CLDMA_DL_MEM 0x0508 ++#define DL_MEM_CHECK_DIS BIT(0) ++ ++#define REG_CLDMA_DL_CFG 0x0404 ++#define DL_CFG_UP_HW_LAST BIT(2) ++#define DL_CFG_BIT_MODE_36 BIT(10) ++#define DL_CFG_BIT_MODE_40 BIT(11) ++#define DL_CFG_BIT_MODE_64 BIT(12) ++#define DL_CFG_BIT_MODE_MASK GENMASK(12, 10) ++ ++#define REG_CLDMA_DL_START_ADDRL_0 0x0478 ++#define REG_CLDMA_DL_START_ADDRH_0 0x047c ++#define REG_CLDMA_DL_CURRENT_ADDRL_0 0x04b8 ++#define REG_CLDMA_DL_CURRENT_ADDRH_0 0x04bc ++#define REG_CLDMA_DL_STATUS 0x04f8 ++ ++/* CLDMA MISC */ ++#define REG_CLDMA_L2TISAR0 0x0810 ++#define REG_CLDMA_L2TISAR1 0x0814 ++#define REG_CLDMA_L2TIMR0 0x0818 ++#define REG_CLDMA_L2TIMR1 0x081c ++#define REG_CLDMA_L2TIMCR0 0x0820 ++#define REG_CLDMA_L2TIMCR1 0x0824 ++#define REG_CLDMA_L2TIMSR0 0x0828 ++#define REG_CLDMA_L2TIMSR1 0x082c ++#define REG_CLDMA_L3TISAR0 0x0830 ++#define REG_CLDMA_L3TISAR1 0x0834 ++#define REG_CLDMA_L2RISAR0 0x0850 ++#define REG_CLDMA_L2RISAR1 0x0854 ++#define REG_CLDMA_L3RISAR0 0x0870 ++#define REG_CLDMA_L3RISAR1 0x0874 ++#define REG_CLDMA_IP_BUSY 0x08b4 ++#define IP_BUSY_WAKEUP BIT(0) ++#define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0) ++#define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0) ++ ++/* CLDMA MISC */ ++#define REG_CLDMA_L2RIMR0 0x0858 ++#define REG_CLDMA_L2RIMR1 0x085c ++#define REG_CLDMA_L2RIMCR0 0x0860 ++#define REG_CLDMA_L2RIMCR1 0x0864 ++#define REG_CLDMA_L2RIMSR0 0x0868 ++#define REG_CLDMA_L2RIMSR1 0x086c ++#define REG_CLDMA_BUSY_MASK 0x0954 ++#define BUSY_MASK_PCIE BIT(0) ++#define BUSY_MASK_AP BIT(1) ++#define BUSY_MASK_MD BIT(2) ++ ++#define REG_CLDMA_INT_MASK 0x0960 ++ ++/* CLDMA RESET */ ++#define REG_INFRA_RST4_SET 0x0730 ++#define RST4_CLDMA1_SW_RST_SET BIT(20) ++ ++#define REG_INFRA_RST4_CLR 0x0734 ++#define RST4_CLDMA1_SW_RST_CLR BIT(20) ++ ++#define REG_INFRA_RST2_SET 0x0140 ++#define RST2_PMIC_SW_RST_SET BIT(18) ++ ++#define REG_INFRA_RST2_CLR 0x0144 ++#define RST2_PMIC_SW_RST_CLR BIT(18) ++ ++enum mtk_txrx { ++ MTK_TX, ++ MTK_RX, ++}; ++ ++enum t7xx_hw_mode { ++ MODE_BIT_32, ++ MODE_BIT_36, ++ MODE_BIT_40, ++ MODE_BIT_64, ++}; ++ ++struct t7xx_cldma_hw { ++ enum t7xx_hw_mode hw_mode; ++ void __iomem *ap_ao_base; ++ void __iomem *ap_pdn_base; ++ u32 phy_interrupt_id; ++}; ++ ++void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); ++unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info); ++void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info); ++void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask); ++void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask); ++void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, ++ unsigned int qno, u64 address, enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_reset(void __iomem *ao_base); ++void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx); ++unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask, ++ enum mtk_txrx tx_rx); ++void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info); ++void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info); ++bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno); ++#endif +diff --git a/drivers/net/wwan/t7xx/t7xx_hif_cldma.c b/drivers/net/wwan/t7xx/t7xx_hif_cldma.c +new file mode 100644 +index 000000000000..c756b1d0b519 +--- /dev/null ++++ b/drivers/net/wwan/t7xx/t7xx_hif_cldma.c +@@ -0,0 +1,1192 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2021, MediaTek Inc. ++ * Copyright (c) 2021-2022, Intel Corporation. ++ * ++ * Authors: ++ * Amir Hanania ++ * Haijun Liu ++ * Moises Veleta ++ * Ricardo Martinez ++ * Sreehari Kancharla ++ * ++ * Contributors: ++ * Andy Shevchenko ++ * Chiranjeevi Rapolu ++ * Eliot Lee ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "t7xx_cldma.h" ++#include "t7xx_hif_cldma.h" ++#include "t7xx_mhccif.h" ++#include "t7xx_pci.h" ++#include "t7xx_pcie_mac.h" ++#include "t7xx_reg.h" ++#include "t7xx_state_monitor.h" ++ ++#define MAX_TX_BUDGET 16 ++#define MAX_RX_BUDGET 16 ++ ++#define CHECK_Q_STOP_TIMEOUT_US 1000000 ++#define CHECK_Q_STOP_STEP_US 10000 ++ ++#define CLDMA_JUMBO_BUFF_SZ 64528 /* 63kB + CCCI header */ ++ ++static void md_cd_queue_struct_reset(struct cldma_queue *queue, struct cldma_ctrl *md_ctrl, ++ enum mtk_txrx tx_rx, unsigned int index) ++{ ++ queue->dir = tx_rx; ++ queue->index = index; ++ queue->md_ctrl = md_ctrl; ++ queue->tr_ring = NULL; ++ queue->tr_done = NULL; ++ queue->tx_next = NULL; ++} ++ ++static void md_cd_queue_struct_init(struct cldma_queue *queue, struct cldma_ctrl *md_ctrl, ++ enum mtk_txrx tx_rx, unsigned int index) ++{ ++ md_cd_queue_struct_reset(queue, md_ctrl, tx_rx, index); ++ init_waitqueue_head(&queue->req_wq); ++ spin_lock_init(&queue->ring_lock); ++} ++ ++static void t7xx_cldma_gpd_set_data_ptr(struct cldma_gpd *gpd, dma_addr_t data_ptr) ++{ ++ gpd->data_buff_bd_ptr_h = cpu_to_le32(upper_32_bits(data_ptr)); ++ gpd->data_buff_bd_ptr_l = cpu_to_le32(lower_32_bits(data_ptr)); ++} ++ ++static void t7xx_cldma_gpd_set_next_ptr(struct cldma_gpd *gpd, dma_addr_t next_ptr) ++{ ++ gpd->next_gpd_ptr_h = cpu_to_le32(upper_32_bits(next_ptr)); ++ gpd->next_gpd_ptr_l = cpu_to_le32(lower_32_bits(next_ptr)); ++} ++ ++static int t7xx_cldma_alloc_and_map_skb(struct cldma_ctrl *md_ctrl, struct cldma_request *req, ++ size_t size) ++{ ++ req->skb = __dev_alloc_skb(size, GFP_KERNEL); ++ if (!req->skb) ++ return -ENOMEM; ++ ++ req->mapped_buff = dma_map_single(md_ctrl->dev, req->skb->data, ++ skb_data_area_size(req->skb), DMA_FROM_DEVICE); ++ if (dma_mapping_error(md_ctrl->dev, req->mapped_buff)) { ++ dev_kfree_skb_any(req->skb); ++ req->skb = NULL; ++ req->mapped_buff = 0; ++ dev_err(md_ctrl->dev, "DMA mapping failed\n"); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int t7xx_cldma_gpd_rx_from_q(struct cldma_queue *queue, int budget, bool *over_budget) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ unsigned int hwo_polling_count = 0; ++ struct t7xx_cldma_hw *hw_info; ++ bool rx_not_done = true; ++ unsigned long flags; ++ int count = 0; ++ ++ hw_info = &md_ctrl->hw_info; ++ ++ do { ++ struct cldma_request *req; ++ struct cldma_gpd *gpd; ++ struct sk_buff *skb; ++ int ret; ++ ++ req = queue->tr_done; ++ if (!req) ++ return -ENODATA; ++ ++ gpd = req->gpd; ++ if ((gpd->flags & GPD_FLAGS_HWO) || !req->skb) { ++ dma_addr_t gpd_addr; ++ ++ if (!pci_device_is_present(to_pci_dev(md_ctrl->dev))) { ++ dev_err(md_ctrl->dev, "PCIe Link disconnected\n"); ++ return -ENODEV; ++ } ++ ++ gpd_addr = ioread64(hw_info->ap_pdn_base + REG_CLDMA_DL_CURRENT_ADDRL_0 + ++ queue->index * sizeof(u64)); ++ if (req->gpd_addr == gpd_addr || hwo_polling_count++ >= 100) ++ return 0; ++ ++ udelay(1); ++ continue; ++ } ++ ++ hwo_polling_count = 0; ++ skb = req->skb; ++ ++ if (req->mapped_buff) { ++ dma_unmap_single(md_ctrl->dev, req->mapped_buff, ++ skb_data_area_size(skb), DMA_FROM_DEVICE); ++ req->mapped_buff = 0; ++ } ++ ++ skb->len = 0; ++ skb_reset_tail_pointer(skb); ++ skb_put(skb, le16_to_cpu(gpd->data_buff_len)); ++ ++ ret = md_ctrl->recv_skb(queue, skb); ++ /* Break processing, will try again later */ ++ if (ret < 0) ++ return ret; ++ ++ req->skb = NULL; ++ t7xx_cldma_gpd_set_data_ptr(gpd, 0); ++ ++ spin_lock_irqsave(&queue->ring_lock, flags); ++ queue->tr_done = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry); ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ req = queue->rx_refill; ++ ++ ret = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, queue->tr_ring->pkt_size); ++ if (ret) ++ return ret; ++ ++ gpd = req->gpd; ++ t7xx_cldma_gpd_set_data_ptr(gpd, req->mapped_buff); ++ gpd->data_buff_len = 0; ++ gpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO; ++ ++ spin_lock_irqsave(&queue->ring_lock, flags); ++ queue->rx_refill = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry); ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ ++ rx_not_done = ++count < budget || !need_resched(); ++ } while (rx_not_done); ++ ++ *over_budget = true; ++ return 0; ++} ++ ++static int t7xx_cldma_gpd_rx_collect(struct cldma_queue *queue, int budget) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ struct t7xx_cldma_hw *hw_info; ++ unsigned int pending_rx_int; ++ bool over_budget = false; ++ unsigned long flags; ++ int ret; ++ ++ hw_info = &md_ctrl->hw_info; ++ ++ do { ++ ret = t7xx_cldma_gpd_rx_from_q(queue, budget, &over_budget); ++ if (ret == -ENODATA) ++ return 0; ++ else if (ret) ++ return ret; ++ ++ pending_rx_int = 0; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ if (md_ctrl->rxq_active & BIT(queue->index)) { ++ if (!t7xx_cldma_hw_queue_status(hw_info, queue->index, MTK_RX)) ++ t7xx_cldma_hw_resume_queue(hw_info, queue->index, MTK_RX); ++ ++ pending_rx_int = t7xx_cldma_hw_int_status(hw_info, BIT(queue->index), ++ MTK_RX); ++ if (pending_rx_int) { ++ t7xx_cldma_hw_rx_done(hw_info, pending_rx_int); ++ ++ if (over_budget) { ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ return -EAGAIN; ++ } ++ } ++ } ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ } while (pending_rx_int); ++ ++ return 0; ++} ++ ++static void t7xx_cldma_rx_done(struct work_struct *work) ++{ ++ struct cldma_queue *queue = container_of(work, struct cldma_queue, cldma_work); ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ int value; ++ ++ value = t7xx_cldma_gpd_rx_collect(queue, queue->budget); ++ if (value && md_ctrl->rxq_active & BIT(queue->index)) { ++ queue_work(queue->worker, &queue->cldma_work); ++ return; ++ } ++ ++ t7xx_cldma_clear_ip_busy(&md_ctrl->hw_info); ++ t7xx_cldma_hw_irq_en_txrx(&md_ctrl->hw_info, queue->index, MTK_RX); ++ t7xx_cldma_hw_irq_en_eq(&md_ctrl->hw_info, queue->index, MTK_RX); ++} ++ ++static int t7xx_cldma_gpd_tx_collect(struct cldma_queue *queue) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ unsigned int dma_len, count = 0; ++ struct cldma_request *req; ++ struct cldma_gpd *gpd; ++ unsigned long flags; ++ dma_addr_t dma_free; ++ struct sk_buff *skb; ++ ++ while (!kthread_should_stop()) { ++ spin_lock_irqsave(&queue->ring_lock, flags); ++ req = queue->tr_done; ++ if (!req) { ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ break; ++ } ++ gpd = req->gpd; ++ if ((gpd->flags & GPD_FLAGS_HWO) || !req->skb) { ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ break; ++ } ++ queue->budget++; ++ dma_free = req->mapped_buff; ++ dma_len = le16_to_cpu(gpd->data_buff_len); ++ skb = req->skb; ++ req->skb = NULL; ++ queue->tr_done = list_next_entry_circular(req, &queue->tr_ring->gpd_ring, entry); ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ ++ count++; ++ dma_unmap_single(md_ctrl->dev, dma_free, dma_len, DMA_TO_DEVICE); ++ dev_kfree_skb_any(skb); ++ } ++ ++ if (count) ++ wake_up_nr(&queue->req_wq, count); ++ ++ return count; ++} ++ ++static void t7xx_cldma_txq_empty_hndl(struct cldma_queue *queue) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ struct cldma_request *req; ++ dma_addr_t ul_curr_addr; ++ unsigned long flags; ++ bool pending_gpd; ++ ++ if (!(md_ctrl->txq_active & BIT(queue->index))) ++ return; ++ ++ spin_lock_irqsave(&queue->ring_lock, flags); ++ req = list_prev_entry_circular(queue->tx_next, &queue->tr_ring->gpd_ring, entry); ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ ++ pending_gpd = (req->gpd->flags & GPD_FLAGS_HWO) && req->skb; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ if (pending_gpd) { ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ ++ /* Check current processing TGPD, 64-bit address is in a table by Q index */ ++ ul_curr_addr = ioread64(hw_info->ap_pdn_base + REG_CLDMA_UL_CURRENT_ADDRL_0 + ++ queue->index * sizeof(u64)); ++ if (req->gpd_addr != ul_curr_addr) { ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ dev_err(md_ctrl->dev, "CLDMA%d queue %d is not empty\n", ++ md_ctrl->hif_id, queue->index); ++ return; ++ } ++ ++ t7xx_cldma_hw_resume_queue(hw_info, queue->index, MTK_TX); ++ } ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++} ++ ++static void t7xx_cldma_tx_done(struct work_struct *work) ++{ ++ struct cldma_queue *queue = container_of(work, struct cldma_queue, cldma_work); ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ struct t7xx_cldma_hw *hw_info; ++ unsigned int l2_tx_int; ++ unsigned long flags; ++ ++ hw_info = &md_ctrl->hw_info; ++ t7xx_cldma_gpd_tx_collect(queue); ++ l2_tx_int = t7xx_cldma_hw_int_status(hw_info, BIT(queue->index) | EQ_STA_BIT(queue->index), ++ MTK_TX); ++ if (l2_tx_int & EQ_STA_BIT(queue->index)) { ++ t7xx_cldma_hw_tx_done(hw_info, EQ_STA_BIT(queue->index)); ++ t7xx_cldma_txq_empty_hndl(queue); ++ } ++ ++ if (l2_tx_int & BIT(queue->index)) { ++ t7xx_cldma_hw_tx_done(hw_info, BIT(queue->index)); ++ queue_work(queue->worker, &queue->cldma_work); ++ return; ++ } ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ if (md_ctrl->txq_active & BIT(queue->index)) { ++ t7xx_cldma_clear_ip_busy(hw_info); ++ t7xx_cldma_hw_irq_en_eq(hw_info, queue->index, MTK_TX); ++ t7xx_cldma_hw_irq_en_txrx(hw_info, queue->index, MTK_TX); ++ } ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++} ++ ++static void t7xx_cldma_ring_free(struct cldma_ctrl *md_ctrl, ++ struct cldma_ring *ring, enum dma_data_direction tx_rx) ++{ ++ struct cldma_request *req_cur, *req_next; ++ ++ list_for_each_entry_safe(req_cur, req_next, &ring->gpd_ring, entry) { ++ if (req_cur->mapped_buff && req_cur->skb) { ++ dma_unmap_single(md_ctrl->dev, req_cur->mapped_buff, ++ skb_data_area_size(req_cur->skb), tx_rx); ++ req_cur->mapped_buff = 0; ++ } ++ ++ dev_kfree_skb_any(req_cur->skb); ++ ++ if (req_cur->gpd) ++ dma_pool_free(md_ctrl->gpd_dmapool, req_cur->gpd, req_cur->gpd_addr); ++ ++ list_del(&req_cur->entry); ++ kfree(req_cur); ++ } ++} ++ ++static struct cldma_request *t7xx_alloc_rx_request(struct cldma_ctrl *md_ctrl, size_t pkt_size) ++{ ++ struct cldma_request *req; ++ int val; ++ ++ req = kzalloc(sizeof(*req), GFP_KERNEL); ++ if (!req) ++ return NULL; ++ ++ req->gpd = dma_pool_zalloc(md_ctrl->gpd_dmapool, GFP_KERNEL, &req->gpd_addr); ++ if (!req->gpd) ++ goto err_free_req; ++ ++ val = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, pkt_size); ++ if (val) ++ goto err_free_pool; ++ ++ return req; ++ ++err_free_pool: ++ dma_pool_free(md_ctrl->gpd_dmapool, req->gpd, req->gpd_addr); ++ ++err_free_req: ++ kfree(req); ++ ++ return NULL; ++} ++ ++static int t7xx_cldma_rx_ring_init(struct cldma_ctrl *md_ctrl, struct cldma_ring *ring) ++{ ++ struct cldma_request *req; ++ struct cldma_gpd *gpd; ++ int i; ++ ++ INIT_LIST_HEAD(&ring->gpd_ring); ++ ring->length = MAX_RX_BUDGET; ++ ++ for (i = 0; i < ring->length; i++) { ++ req = t7xx_alloc_rx_request(md_ctrl, ring->pkt_size); ++ if (!req) { ++ t7xx_cldma_ring_free(md_ctrl, ring, DMA_FROM_DEVICE); ++ return -ENOMEM; ++ } ++ ++ gpd = req->gpd; ++ t7xx_cldma_gpd_set_data_ptr(gpd, req->mapped_buff); ++ gpd->rx_data_allow_len = cpu_to_le16(ring->pkt_size); ++ gpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO; ++ INIT_LIST_HEAD(&req->entry); ++ list_add_tail(&req->entry, &ring->gpd_ring); ++ } ++ ++ /* Link previous GPD to next GPD, circular */ ++ list_for_each_entry(req, &ring->gpd_ring, entry) { ++ t7xx_cldma_gpd_set_next_ptr(gpd, req->gpd_addr); ++ gpd = req->gpd; ++ } ++ ++ return 0; ++} ++ ++static struct cldma_request *t7xx_alloc_tx_request(struct cldma_ctrl *md_ctrl) ++{ ++ struct cldma_request *req; ++ ++ req = kzalloc(sizeof(*req), GFP_KERNEL); ++ if (!req) ++ return NULL; ++ ++ req->gpd = dma_pool_zalloc(md_ctrl->gpd_dmapool, GFP_KERNEL, &req->gpd_addr); ++ if (!req->gpd) { ++ kfree(req); ++ return NULL; ++ } ++ ++ return req; ++} ++ ++static int t7xx_cldma_tx_ring_init(struct cldma_ctrl *md_ctrl, struct cldma_ring *ring) ++{ ++ struct cldma_request *req; ++ struct cldma_gpd *gpd; ++ int i; ++ ++ INIT_LIST_HEAD(&ring->gpd_ring); ++ ring->length = MAX_TX_BUDGET; ++ ++ for (i = 0; i < ring->length; i++) { ++ req = t7xx_alloc_tx_request(md_ctrl); ++ if (!req) { ++ t7xx_cldma_ring_free(md_ctrl, ring, DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ ++ gpd = req->gpd; ++ gpd->flags = GPD_FLAGS_IOC; ++ INIT_LIST_HEAD(&req->entry); ++ list_add_tail(&req->entry, &ring->gpd_ring); ++ } ++ ++ /* Link previous GPD to next GPD, circular */ ++ list_for_each_entry(req, &ring->gpd_ring, entry) { ++ t7xx_cldma_gpd_set_next_ptr(gpd, req->gpd_addr); ++ gpd = req->gpd; ++ } ++ ++ return 0; ++} ++ ++/** ++ * t7xx_cldma_q_reset() - Reset CLDMA request pointers to their initial values. ++ * @queue: Pointer to the queue structure. ++ * ++ * Called with ring_lock (unless called during initialization phase) ++ */ ++static void t7xx_cldma_q_reset(struct cldma_queue *queue) ++{ ++ struct cldma_request *req; ++ ++ req = list_first_entry(&queue->tr_ring->gpd_ring, struct cldma_request, entry); ++ queue->tr_done = req; ++ queue->budget = queue->tr_ring->length; ++ ++ if (queue->dir == MTK_TX) ++ queue->tx_next = req; ++ else ++ queue->rx_refill = req; ++} ++ ++static void t7xx_cldma_rxq_init(struct cldma_queue *queue) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ ++ queue->dir = MTK_RX; ++ queue->tr_ring = &md_ctrl->rx_ring[queue->index]; ++ t7xx_cldma_q_reset(queue); ++} ++ ++static void t7xx_cldma_txq_init(struct cldma_queue *queue) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ ++ queue->dir = MTK_TX; ++ queue->tr_ring = &md_ctrl->tx_ring[queue->index]; ++ t7xx_cldma_q_reset(queue); ++} ++ ++static void t7xx_cldma_enable_irq(struct cldma_ctrl *md_ctrl) ++{ ++ t7xx_pcie_mac_set_int(md_ctrl->t7xx_dev, md_ctrl->hw_info.phy_interrupt_id); ++} ++ ++static void t7xx_cldma_disable_irq(struct cldma_ctrl *md_ctrl) ++{ ++ t7xx_pcie_mac_clear_int(md_ctrl->t7xx_dev, md_ctrl->hw_info.phy_interrupt_id); ++} ++ ++static void t7xx_cldma_irq_work_cb(struct cldma_ctrl *md_ctrl) ++{ ++ unsigned long l2_tx_int_msk, l2_rx_int_msk, l2_tx_int, l2_rx_int, val; ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ int i; ++ ++ /* L2 raw interrupt status */ ++ l2_tx_int = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0); ++ l2_rx_int = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0); ++ l2_tx_int_msk = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TIMR0); ++ l2_rx_int_msk = ioread32(hw_info->ap_ao_base + REG_CLDMA_L2RIMR0); ++ l2_tx_int &= ~l2_tx_int_msk; ++ l2_rx_int &= ~l2_rx_int_msk; ++ ++ if (l2_tx_int) { ++ if (l2_tx_int & (TQ_ERR_INT_BITMASK | TQ_ACTIVE_START_ERR_INT_BITMASK)) { ++ /* Read and clear L3 TX interrupt status */ ++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3TISAR0); ++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3TISAR0); ++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3TISAR1); ++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3TISAR1); ++ } ++ ++ t7xx_cldma_hw_tx_done(hw_info, l2_tx_int); ++ if (l2_tx_int & (TXRX_STATUS_BITMASK | EMPTY_STATUS_BITMASK)) { ++ for_each_set_bit(i, &l2_tx_int, L2_INT_BIT_COUNT) { ++ if (i < CLDMA_TXQ_NUM) { ++ t7xx_cldma_hw_irq_dis_eq(hw_info, i, MTK_TX); ++ t7xx_cldma_hw_irq_dis_txrx(hw_info, i, MTK_TX); ++ queue_work(md_ctrl->txq[i].worker, ++ &md_ctrl->txq[i].cldma_work); ++ } else { ++ t7xx_cldma_txq_empty_hndl(&md_ctrl->txq[i - CLDMA_TXQ_NUM]); ++ } ++ } ++ } ++ } ++ ++ if (l2_rx_int) { ++ if (l2_rx_int & (RQ_ERR_INT_BITMASK | RQ_ACTIVE_START_ERR_INT_BITMASK)) { ++ /* Read and clear L3 RX interrupt status */ ++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3RISAR0); ++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3RISAR0); ++ val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L3RISAR1); ++ iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_L3RISAR1); ++ } ++ ++ t7xx_cldma_hw_rx_done(hw_info, l2_rx_int); ++ if (l2_rx_int & (TXRX_STATUS_BITMASK | EMPTY_STATUS_BITMASK)) { ++ l2_rx_int |= l2_rx_int >> CLDMA_RXQ_NUM; ++ for_each_set_bit(i, &l2_rx_int, CLDMA_RXQ_NUM) { ++ t7xx_cldma_hw_irq_dis_eq(hw_info, i, MTK_RX); ++ t7xx_cldma_hw_irq_dis_txrx(hw_info, i, MTK_RX); ++ queue_work(md_ctrl->rxq[i].worker, &md_ctrl->rxq[i].cldma_work); ++ } ++ } ++ } ++} ++ ++static bool t7xx_cldma_qs_are_active(struct cldma_ctrl *md_ctrl) ++{ ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ unsigned int tx_active; ++ unsigned int rx_active; ++ ++ if (!pci_device_is_present(to_pci_dev(md_ctrl->dev))) ++ return false; ++ ++ tx_active = t7xx_cldma_hw_queue_status(hw_info, CLDMA_ALL_Q, MTK_TX); ++ rx_active = t7xx_cldma_hw_queue_status(hw_info, CLDMA_ALL_Q, MTK_RX); ++ ++ return tx_active || rx_active; ++} ++ ++/** ++ * t7xx_cldma_stop() - Stop CLDMA. ++ * @md_ctrl: CLDMA context structure. ++ * ++ * Stop TX and RX queues. Disable L1 and L2 interrupts. ++ * Clear status registers. ++ * ++ * Return: ++ * * 0 - Success. ++ * * -ERROR - Error code from polling cldma_queues_active. ++ */ ++int t7xx_cldma_stop(struct cldma_ctrl *md_ctrl) ++{ ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ bool active; ++ int i, ret; ++ ++ md_ctrl->rxq_active = 0; ++ t7xx_cldma_hw_stop_all_qs(hw_info, MTK_RX); ++ md_ctrl->txq_active = 0; ++ t7xx_cldma_hw_stop_all_qs(hw_info, MTK_TX); ++ md_ctrl->txq_started = 0; ++ t7xx_cldma_disable_irq(md_ctrl); ++ t7xx_cldma_hw_stop(hw_info, MTK_RX); ++ t7xx_cldma_hw_stop(hw_info, MTK_TX); ++ t7xx_cldma_hw_tx_done(hw_info, CLDMA_L2TISAR0_ALL_INT_MASK); ++ t7xx_cldma_hw_rx_done(hw_info, CLDMA_L2RISAR0_ALL_INT_MASK); ++ ++ if (md_ctrl->is_late_init) { ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) ++ flush_work(&md_ctrl->txq[i].cldma_work); ++ ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) ++ flush_work(&md_ctrl->rxq[i].cldma_work); ++ } ++ ++ ret = read_poll_timeout(t7xx_cldma_qs_are_active, active, !active, CHECK_Q_STOP_STEP_US, ++ CHECK_Q_STOP_TIMEOUT_US, true, md_ctrl); ++ if (ret) ++ dev_err(md_ctrl->dev, "Could not stop CLDMA%d queues", md_ctrl->hif_id); ++ ++ return ret; ++} ++ ++static void t7xx_cldma_late_release(struct cldma_ctrl *md_ctrl) ++{ ++ int i; ++ ++ if (!md_ctrl->is_late_init) ++ return; ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) ++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->tx_ring[i], DMA_TO_DEVICE); ++ ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) ++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->rx_ring[i], DMA_FROM_DEVICE); ++ ++ dma_pool_destroy(md_ctrl->gpd_dmapool); ++ md_ctrl->gpd_dmapool = NULL; ++ md_ctrl->is_late_init = false; ++} ++ ++void t7xx_cldma_reset(struct cldma_ctrl *md_ctrl) ++{ ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ md_ctrl->txq_active = 0; ++ md_ctrl->rxq_active = 0; ++ t7xx_cldma_disable_irq(md_ctrl); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) { ++ cancel_work_sync(&md_ctrl->txq[i].cldma_work); ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ md_cd_queue_struct_reset(&md_ctrl->txq[i], md_ctrl, MTK_TX, i); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ } ++ ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) { ++ cancel_work_sync(&md_ctrl->rxq[i].cldma_work); ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ md_cd_queue_struct_reset(&md_ctrl->rxq[i], md_ctrl, MTK_RX, i); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ } ++ ++ t7xx_cldma_late_release(md_ctrl); ++} ++ ++/** ++ * t7xx_cldma_start() - Start CLDMA. ++ * @md_ctrl: CLDMA context structure. ++ * ++ * Set TX/RX start address. ++ * Start all RX queues and enable L2 interrupt. ++ */ ++void t7xx_cldma_start(struct cldma_ctrl *md_ctrl) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ if (md_ctrl->is_late_init) { ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ int i; ++ ++ t7xx_cldma_enable_irq(md_ctrl); ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) { ++ if (md_ctrl->txq[i].tr_done) ++ t7xx_cldma_hw_set_start_addr(hw_info, i, ++ md_ctrl->txq[i].tr_done->gpd_addr, ++ MTK_TX); ++ } ++ ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) { ++ if (md_ctrl->rxq[i].tr_done) ++ t7xx_cldma_hw_set_start_addr(hw_info, i, ++ md_ctrl->rxq[i].tr_done->gpd_addr, ++ MTK_RX); ++ } ++ ++ /* Enable L2 interrupt */ ++ t7xx_cldma_hw_start_queue(hw_info, CLDMA_ALL_Q, MTK_RX); ++ t7xx_cldma_hw_start(hw_info); ++ md_ctrl->txq_started = 0; ++ md_ctrl->txq_active |= TXRX_STATUS_BITMASK; ++ md_ctrl->rxq_active |= TXRX_STATUS_BITMASK; ++ } ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++} ++ ++static void t7xx_cldma_clear_txq(struct cldma_ctrl *md_ctrl, int qnum) ++{ ++ struct cldma_queue *txq = &md_ctrl->txq[qnum]; ++ struct cldma_request *req; ++ struct cldma_gpd *gpd; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&txq->ring_lock, flags); ++ t7xx_cldma_q_reset(txq); ++ list_for_each_entry(req, &txq->tr_ring->gpd_ring, entry) { ++ gpd = req->gpd; ++ gpd->flags &= ~GPD_FLAGS_HWO; ++ t7xx_cldma_gpd_set_data_ptr(gpd, 0); ++ gpd->data_buff_len = 0; ++ dev_kfree_skb_any(req->skb); ++ req->skb = NULL; ++ } ++ spin_unlock_irqrestore(&txq->ring_lock, flags); ++} ++ ++static int t7xx_cldma_clear_rxq(struct cldma_ctrl *md_ctrl, int qnum) ++{ ++ struct cldma_queue *rxq = &md_ctrl->rxq[qnum]; ++ struct cldma_request *req; ++ struct cldma_gpd *gpd; ++ unsigned long flags; ++ int ret = 0; ++ ++ spin_lock_irqsave(&rxq->ring_lock, flags); ++ t7xx_cldma_q_reset(rxq); ++ list_for_each_entry(req, &rxq->tr_ring->gpd_ring, entry) { ++ gpd = req->gpd; ++ gpd->flags = GPD_FLAGS_IOC | GPD_FLAGS_HWO; ++ gpd->data_buff_len = 0; ++ ++ if (req->skb) { ++ req->skb->len = 0; ++ skb_reset_tail_pointer(req->skb); ++ } ++ } ++ ++ list_for_each_entry(req, &rxq->tr_ring->gpd_ring, entry) { ++ if (req->skb) ++ continue; ++ ++ ret = t7xx_cldma_alloc_and_map_skb(md_ctrl, req, rxq->tr_ring->pkt_size); ++ if (ret) ++ break; ++ ++ t7xx_cldma_gpd_set_data_ptr(req->gpd, req->mapped_buff); ++ } ++ spin_unlock_irqrestore(&rxq->ring_lock, flags); ++ ++ return ret; ++} ++ ++void t7xx_cldma_clear_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx) ++{ ++ int i; ++ ++ if (tx_rx == MTK_TX) { ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) ++ t7xx_cldma_clear_txq(md_ctrl, i); ++ } else { ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) ++ t7xx_cldma_clear_rxq(md_ctrl, i); ++ } ++} ++ ++void t7xx_cldma_stop_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx) ++{ ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ t7xx_cldma_hw_irq_dis_eq(hw_info, CLDMA_ALL_Q, tx_rx); ++ t7xx_cldma_hw_irq_dis_txrx(hw_info, CLDMA_ALL_Q, tx_rx); ++ if (tx_rx == MTK_RX) ++ md_ctrl->rxq_active &= ~TXRX_STATUS_BITMASK; ++ else ++ md_ctrl->txq_active &= ~TXRX_STATUS_BITMASK; ++ t7xx_cldma_hw_stop_all_qs(hw_info, tx_rx); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++} ++ ++static int t7xx_cldma_gpd_handle_tx_request(struct cldma_queue *queue, struct cldma_request *tx_req, ++ struct sk_buff *skb) ++{ ++ struct cldma_ctrl *md_ctrl = queue->md_ctrl; ++ struct cldma_gpd *gpd = tx_req->gpd; ++ unsigned long flags; ++ ++ /* Update GPD */ ++ tx_req->mapped_buff = dma_map_single(md_ctrl->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(md_ctrl->dev, tx_req->mapped_buff)) { ++ dev_err(md_ctrl->dev, "DMA mapping failed\n"); ++ return -ENOMEM; ++ } ++ ++ t7xx_cldma_gpd_set_data_ptr(gpd, tx_req->mapped_buff); ++ gpd->data_buff_len = cpu_to_le16(skb->len); ++ ++ /* This lock must cover TGPD setting, as even without a resume operation, ++ * CLDMA can send next HWO=1 if last TGPD just finished. ++ */ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ if (md_ctrl->txq_active & BIT(queue->index)) ++ gpd->flags |= GPD_FLAGS_HWO; ++ ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ ++ tx_req->skb = skb; ++ return 0; ++} ++ ++/* Called with cldma_lock */ ++static void t7xx_cldma_hw_start_send(struct cldma_ctrl *md_ctrl, int qno, ++ struct cldma_request *prev_req) ++{ ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ ++ /* Check whether the device was powered off (CLDMA start address is not set) */ ++ if (!t7xx_cldma_tx_addr_is_set(hw_info, qno)) { ++ t7xx_cldma_hw_init(hw_info); ++ t7xx_cldma_hw_set_start_addr(hw_info, qno, prev_req->gpd_addr, MTK_TX); ++ md_ctrl->txq_started &= ~BIT(qno); ++ } ++ ++ if (!t7xx_cldma_hw_queue_status(hw_info, qno, MTK_TX)) { ++ if (md_ctrl->txq_started & BIT(qno)) ++ t7xx_cldma_hw_resume_queue(hw_info, qno, MTK_TX); ++ else ++ t7xx_cldma_hw_start_queue(hw_info, qno, MTK_TX); ++ ++ md_ctrl->txq_started |= BIT(qno); ++ } ++} ++ ++/** ++ * t7xx_cldma_set_recv_skb() - Set the callback to handle RX packets. ++ * @md_ctrl: CLDMA context structure. ++ * @recv_skb: Receiving skb callback. ++ */ ++void t7xx_cldma_set_recv_skb(struct cldma_ctrl *md_ctrl, ++ int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb)) ++{ ++ md_ctrl->recv_skb = recv_skb; ++} ++ ++/** ++ * t7xx_cldma_send_skb() - Send control data to modem. ++ * @md_ctrl: CLDMA context structure. ++ * @qno: Queue number. ++ * @skb: Socket buffer. ++ * ++ * Return: ++ * * 0 - Success. ++ * * -ENOMEM - Allocation failure. ++ * * -EINVAL - Invalid queue request. ++ * * -EIO - Queue is not active. ++ * * -ETIMEDOUT - Timeout waiting for the device to wake up. ++ */ ++int t7xx_cldma_send_skb(struct cldma_ctrl *md_ctrl, int qno, struct sk_buff *skb) ++{ ++ struct cldma_request *tx_req; ++ struct cldma_queue *queue; ++ unsigned long flags; ++ int ret; ++ ++ if (qno >= CLDMA_TXQ_NUM) ++ return -EINVAL; ++ ++ queue = &md_ctrl->txq[qno]; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ if (!(md_ctrl->txq_active & BIT(qno))) { ++ ret = -EIO; ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ goto allow_sleep; ++ } ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ ++ do { ++ spin_lock_irqsave(&queue->ring_lock, flags); ++ tx_req = queue->tx_next; ++ if (queue->budget > 0 && !tx_req->skb) { ++ struct list_head *gpd_ring = &queue->tr_ring->gpd_ring; ++ ++ queue->budget--; ++ t7xx_cldma_gpd_handle_tx_request(queue, tx_req, skb); ++ queue->tx_next = list_next_entry_circular(tx_req, gpd_ring, entry); ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ ++ /* Protect the access to the modem for queues operations (resume/start) ++ * which access shared locations by all the queues. ++ * cldma_lock is independent of ring_lock which is per queue. ++ */ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ t7xx_cldma_hw_start_send(md_ctrl, qno, tx_req); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ ++ break; ++ } ++ spin_unlock_irqrestore(&queue->ring_lock, flags); ++ ++ if (!t7xx_cldma_hw_queue_status(&md_ctrl->hw_info, qno, MTK_TX)) { ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ t7xx_cldma_hw_resume_queue(&md_ctrl->hw_info, qno, MTK_TX); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++ } ++ ++ ret = wait_event_interruptible_exclusive(queue->req_wq, queue->budget > 0); ++ } while (!ret); ++ ++allow_sleep: ++ return ret; ++} ++ ++static int t7xx_cldma_late_init(struct cldma_ctrl *md_ctrl) ++{ ++ char dma_pool_name[32]; ++ int i, j, ret; ++ ++ if (md_ctrl->is_late_init) { ++ dev_err(md_ctrl->dev, "CLDMA late init was already done\n"); ++ return -EALREADY; ++ } ++ ++ snprintf(dma_pool_name, sizeof(dma_pool_name), "cldma_req_hif%d", md_ctrl->hif_id); ++ ++ md_ctrl->gpd_dmapool = dma_pool_create(dma_pool_name, md_ctrl->dev, ++ sizeof(struct cldma_gpd), GPD_DMAPOOL_ALIGN, 0); ++ if (!md_ctrl->gpd_dmapool) { ++ dev_err(md_ctrl->dev, "DMA pool alloc fail\n"); ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) { ++ ret = t7xx_cldma_tx_ring_init(md_ctrl, &md_ctrl->tx_ring[i]); ++ if (ret) { ++ dev_err(md_ctrl->dev, "control TX ring init fail\n"); ++ goto err_free_tx_ring; ++ } ++ } ++ ++ for (j = 0; j < CLDMA_RXQ_NUM; j++) { ++ md_ctrl->rx_ring[j].pkt_size = CLDMA_MTU; ++ ++ if (j == CLDMA_RXQ_NUM - 1) ++ md_ctrl->rx_ring[j].pkt_size = CLDMA_JUMBO_BUFF_SZ; ++ ++ ret = t7xx_cldma_rx_ring_init(md_ctrl, &md_ctrl->rx_ring[j]); ++ if (ret) { ++ dev_err(md_ctrl->dev, "Control RX ring init fail\n"); ++ goto err_free_rx_ring; ++ } ++ } ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) ++ t7xx_cldma_txq_init(&md_ctrl->txq[i]); ++ ++ for (j = 0; j < CLDMA_RXQ_NUM; j++) ++ t7xx_cldma_rxq_init(&md_ctrl->rxq[j]); ++ ++ md_ctrl->is_late_init = true; ++ return 0; ++ ++err_free_rx_ring: ++ while (j--) ++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->rx_ring[j], DMA_FROM_DEVICE); ++ ++err_free_tx_ring: ++ while (i--) ++ t7xx_cldma_ring_free(md_ctrl, &md_ctrl->tx_ring[i], DMA_TO_DEVICE); ++ ++ return ret; ++} ++ ++static void __iomem *t7xx_pcie_addr_transfer(void __iomem *addr, u32 addr_trs1, u32 phy_addr) ++{ ++ return addr + phy_addr - addr_trs1; ++} ++ ++static void t7xx_hw_info_init(struct cldma_ctrl *md_ctrl) ++{ ++ struct t7xx_addr_base *pbase = &md_ctrl->t7xx_dev->base_addr; ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ u32 phy_ao_base, phy_pd_base; ++ ++ if (md_ctrl->hif_id != CLDMA_ID_MD) ++ return; ++ ++ phy_ao_base = CLDMA1_AO_BASE; ++ phy_pd_base = CLDMA1_PD_BASE; ++ hw_info->phy_interrupt_id = CLDMA1_INT; ++ hw_info->hw_mode = MODE_BIT_64; ++ hw_info->ap_ao_base = t7xx_pcie_addr_transfer(pbase->pcie_ext_reg_base, ++ pbase->pcie_dev_reg_trsl_addr, phy_ao_base); ++ hw_info->ap_pdn_base = t7xx_pcie_addr_transfer(pbase->pcie_ext_reg_base, ++ pbase->pcie_dev_reg_trsl_addr, phy_pd_base); ++} ++ ++static int t7xx_cldma_default_recv_skb(struct cldma_queue *queue, struct sk_buff *skb) ++{ ++ dev_kfree_skb_any(skb); ++ return 0; ++} ++ ++int t7xx_cldma_alloc(enum cldma_id hif_id, struct t7xx_pci_dev *t7xx_dev) ++{ ++ struct device *dev = &t7xx_dev->pdev->dev; ++ struct cldma_ctrl *md_ctrl; ++ ++ md_ctrl = devm_kzalloc(dev, sizeof(*md_ctrl), GFP_KERNEL); ++ if (!md_ctrl) ++ return -ENOMEM; ++ ++ md_ctrl->t7xx_dev = t7xx_dev; ++ md_ctrl->dev = dev; ++ md_ctrl->hif_id = hif_id; ++ md_ctrl->recv_skb = t7xx_cldma_default_recv_skb; ++ t7xx_hw_info_init(md_ctrl); ++ t7xx_dev->md->md_ctrl[hif_id] = md_ctrl; ++ return 0; ++} ++ ++void t7xx_cldma_hif_hw_init(struct cldma_ctrl *md_ctrl) ++{ ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&md_ctrl->cldma_lock, flags); ++ t7xx_cldma_hw_stop(hw_info, MTK_TX); ++ t7xx_cldma_hw_stop(hw_info, MTK_RX); ++ t7xx_cldma_hw_rx_done(hw_info, EMPTY_STATUS_BITMASK | TXRX_STATUS_BITMASK); ++ t7xx_cldma_hw_tx_done(hw_info, EMPTY_STATUS_BITMASK | TXRX_STATUS_BITMASK); ++ t7xx_cldma_hw_init(hw_info); ++ spin_unlock_irqrestore(&md_ctrl->cldma_lock, flags); ++} ++ ++static irqreturn_t t7xx_cldma_isr_handler(int irq, void *data) ++{ ++ struct cldma_ctrl *md_ctrl = data; ++ u32 interrupt; ++ ++ interrupt = md_ctrl->hw_info.phy_interrupt_id; ++ t7xx_pcie_mac_clear_int(md_ctrl->t7xx_dev, interrupt); ++ t7xx_cldma_irq_work_cb(md_ctrl); ++ t7xx_pcie_mac_clear_int_status(md_ctrl->t7xx_dev, interrupt); ++ t7xx_pcie_mac_set_int(md_ctrl->t7xx_dev, interrupt); ++ return IRQ_HANDLED; ++} ++ ++static void t7xx_cldma_destroy_wqs(struct cldma_ctrl *md_ctrl) ++{ ++ int i; ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) { ++ if (md_ctrl->txq[i].worker) { ++ destroy_workqueue(md_ctrl->txq[i].worker); ++ md_ctrl->txq[i].worker = NULL; ++ } ++ } ++ ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) { ++ if (md_ctrl->rxq[i].worker) { ++ destroy_workqueue(md_ctrl->rxq[i].worker); ++ md_ctrl->rxq[i].worker = NULL; ++ } ++ } ++} ++ ++/** ++ * t7xx_cldma_init() - Initialize CLDMA. ++ * @md_ctrl: CLDMA context structure. ++ * ++ * Initialize HIF TX/RX queue structure. ++ * Register CLDMA callback ISR with PCIe driver. ++ * ++ * Return: ++ * * 0 - Success. ++ * * -ERROR - Error code from failure sub-initializations. ++ */ ++int t7xx_cldma_init(struct cldma_ctrl *md_ctrl) ++{ ++ struct t7xx_cldma_hw *hw_info = &md_ctrl->hw_info; ++ int i; ++ ++ md_ctrl->txq_active = 0; ++ md_ctrl->rxq_active = 0; ++ md_ctrl->is_late_init = false; ++ ++ spin_lock_init(&md_ctrl->cldma_lock); ++ ++ for (i = 0; i < CLDMA_TXQ_NUM; i++) { ++ md_cd_queue_struct_init(&md_ctrl->txq[i], md_ctrl, MTK_TX, i); ++ md_ctrl->txq[i].worker = ++ alloc_workqueue("md_hif%d_tx%d_worker", ++ WQ_UNBOUND | WQ_MEM_RECLAIM | (i ? 0 : WQ_HIGHPRI), ++ 1, md_ctrl->hif_id, i); ++ if (!md_ctrl->txq[i].worker) ++ goto err_workqueue; ++ ++ INIT_WORK(&md_ctrl->txq[i].cldma_work, t7xx_cldma_tx_done); ++ } ++ ++ for (i = 0; i < CLDMA_RXQ_NUM; i++) { ++ md_cd_queue_struct_init(&md_ctrl->rxq[i], md_ctrl, MTK_RX, i); ++ INIT_WORK(&md_ctrl->rxq[i].cldma_work, t7xx_cldma_rx_done); ++ ++ md_ctrl->rxq[i].worker = alloc_workqueue("md_hif%d_rx%d_worker", ++ WQ_UNBOUND | WQ_MEM_RECLAIM, ++ 1, md_ctrl->hif_id, i); ++ if (!md_ctrl->rxq[i].worker) ++ goto err_workqueue; ++ } ++ ++ t7xx_pcie_mac_clear_int(md_ctrl->t7xx_dev, hw_info->phy_interrupt_id); ++ md_ctrl->t7xx_dev->intr_handler[hw_info->phy_interrupt_id] = t7xx_cldma_isr_handler; ++ md_ctrl->t7xx_dev->intr_thread[hw_info->phy_interrupt_id] = NULL; ++ md_ctrl->t7xx_dev->callback_param[hw_info->phy_interrupt_id] = md_ctrl; ++ t7xx_pcie_mac_clear_int_status(md_ctrl->t7xx_dev, hw_info->phy_interrupt_id); ++ return 0; ++ ++err_workqueue: ++ t7xx_cldma_destroy_wqs(md_ctrl); ++ return -ENOMEM; ++} ++ ++void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl) ++{ ++ t7xx_cldma_late_release(md_ctrl); ++ t7xx_cldma_late_init(md_ctrl); ++} ++ ++void t7xx_cldma_exit(struct cldma_ctrl *md_ctrl) ++{ ++ t7xx_cldma_stop(md_ctrl); ++ t7xx_cldma_late_release(md_ctrl); ++ t7xx_cldma_destroy_wqs(md_ctrl); ++} +diff --git a/drivers/net/wwan/t7xx/t7xx_hif_cldma.h b/drivers/net/wwan/t7xx/t7xx_hif_cldma.h +new file mode 100644 +index 000000000000..deb239e4f803 +--- /dev/null ++++ b/drivers/net/wwan/t7xx/t7xx_hif_cldma.h +@@ -0,0 +1,126 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2021, MediaTek Inc. ++ * Copyright (c) 2021-2022, Intel Corporation. ++ * ++ * Authors: ++ * Haijun Liu ++ * Moises Veleta ++ * Ricardo Martinez ++ * Sreehari Kancharla ++ * ++ * Contributors: ++ * Amir Hanania ++ * Chiranjeevi Rapolu ++ * Eliot Lee ++ */ ++ ++#ifndef __T7XX_HIF_CLDMA_H__ ++#define __T7XX_HIF_CLDMA_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "t7xx_cldma.h" ++#include "t7xx_pci.h" ++ ++/** ++ * enum cldma_id - Identifiers for CLDMA HW units. ++ * @CLDMA_ID_MD: Modem control channel. ++ * @CLDMA_ID_AP: Application Processor control channel (not used at the moment). ++ * @CLDMA_NUM: Number of CLDMA HW units available. ++ */ ++enum cldma_id { ++ CLDMA_ID_MD, ++ CLDMA_ID_AP, ++ CLDMA_NUM ++}; ++ ++struct cldma_gpd { ++ u8 flags; ++ u8 not_used1; ++ __le16 rx_data_allow_len; ++ __le32 next_gpd_ptr_h; ++ __le32 next_gpd_ptr_l; ++ __le32 data_buff_bd_ptr_h; ++ __le32 data_buff_bd_ptr_l; ++ __le16 data_buff_len; ++ __le16 not_used2; ++}; ++ ++struct cldma_request { ++ struct cldma_gpd *gpd; /* Virtual address for CPU */ ++ dma_addr_t gpd_addr; /* Physical address for DMA */ ++ struct sk_buff *skb; ++ dma_addr_t mapped_buff; ++ struct list_head entry; ++}; ++ ++struct cldma_ring { ++ struct list_head gpd_ring; /* Ring of struct cldma_request */ ++ unsigned int length; /* Number of struct cldma_request */ ++ int pkt_size; ++}; ++ ++struct cldma_queue { ++ struct cldma_ctrl *md_ctrl; ++ enum mtk_txrx dir; ++ unsigned int index; ++ struct cldma_ring *tr_ring; ++ struct cldma_request *tr_done; ++ struct cldma_request *rx_refill; ++ struct cldma_request *tx_next; ++ int budget; /* Same as ring buffer size by default */ ++ spinlock_t ring_lock; ++ wait_queue_head_t req_wq; /* Only for TX */ ++ struct workqueue_struct *worker; ++ struct work_struct cldma_work; ++}; ++ ++struct cldma_ctrl { ++ enum cldma_id hif_id; ++ struct device *dev; ++ struct t7xx_pci_dev *t7xx_dev; ++ struct cldma_queue txq[CLDMA_TXQ_NUM]; ++ struct cldma_queue rxq[CLDMA_RXQ_NUM]; ++ unsigned short txq_active; ++ unsigned short rxq_active; ++ unsigned short txq_started; ++ spinlock_t cldma_lock; /* Protects CLDMA structure */ ++ /* Assumes T/R GPD/BD/SPD have the same size */ ++ struct dma_pool *gpd_dmapool; ++ struct cldma_ring tx_ring[CLDMA_TXQ_NUM]; ++ struct cldma_ring rx_ring[CLDMA_RXQ_NUM]; ++ struct t7xx_cldma_hw hw_info; ++ bool is_late_init; ++ int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb); ++}; ++ ++#define GPD_FLAGS_HWO BIT(0) ++#define GPD_FLAGS_IOC BIT(7) ++#define GPD_DMAPOOL_ALIGN 16 ++ ++#define CLDMA_MTU 3584 /* 3.5kB */ ++ ++int t7xx_cldma_alloc(enum cldma_id hif_id, struct t7xx_pci_dev *t7xx_dev); ++void t7xx_cldma_hif_hw_init(struct cldma_ctrl *md_ctrl); ++int t7xx_cldma_init(struct cldma_ctrl *md_ctrl); ++void t7xx_cldma_exit(struct cldma_ctrl *md_ctrl); ++void t7xx_cldma_switch_cfg(struct cldma_ctrl *md_ctrl); ++void t7xx_cldma_start(struct cldma_ctrl *md_ctrl); ++int t7xx_cldma_stop(struct cldma_ctrl *md_ctrl); ++void t7xx_cldma_reset(struct cldma_ctrl *md_ctrl); ++void t7xx_cldma_set_recv_skb(struct cldma_ctrl *md_ctrl, ++ int (*recv_skb)(struct cldma_queue *queue, struct sk_buff *skb)); ++int t7xx_cldma_send_skb(struct cldma_ctrl *md_ctrl, int qno, struct sk_buff *skb); ++void t7xx_cldma_stop_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx); ++void t7xx_cldma_clear_all_qs(struct cldma_ctrl *md_ctrl, enum mtk_txrx tx_rx); ++ ++#endif /* __T7XX_HIF_CLDMA_H__ */ +diff --git a/drivers/net/wwan/t7xx/t7xx_reg.h b/drivers/net/wwan/t7xx/t7xx_reg.h +new file mode 100644 +index 000000000000..7dc6c77a59e3 +--- /dev/null ++++ b/drivers/net/wwan/t7xx/t7xx_reg.h +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only ++ * ++ * Copyright (c) 2021, MediaTek Inc. ++ * Copyright (c) 2021-2022, Intel Corporation. ++ * ++ * Authors: ++ * Haijun Liu ++ * Chiranjeevi Rapolu ++ * ++ * Contributors: ++ * Amir Hanania ++ * Andy Shevchenko ++ * Eliot Lee ++ * Moises Veleta ++ * Ricardo Martinez ++ * Sreehari Kancharla ++ */ ++ ++#ifndef __T7XX_REG_H__ ++#define __T7XX_REG_H__ ++ ++enum t7xx_int { ++ DPMAIF_INT, ++ CLDMA0_INT, ++ CLDMA1_INT, ++ CLDMA2_INT, ++ MHCCIF_INT, ++ DPMAIF2_INT, ++ SAP_RGU_INT, ++ CLDMA3_INT, ++}; ++ ++#endif /* __T7XX_REG_H__ */ +-- +2.35.1 + diff --git a/queue-5.10/net-xscale-fix-return-type-for-implementation-of-ndo.patch b/queue-5.10/net-xscale-fix-return-type-for-implementation-of-ndo.patch new file mode 100644 index 00000000000..4e9ffde057b --- /dev/null +++ b/queue-5.10/net-xscale-fix-return-type-for-implementation-of-ndo.patch @@ -0,0 +1,40 @@ +From 6b2e641ecb246b0108a2790a73aa5e031f74d754 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 16:16:12 +0800 +Subject: net: xscale: Fix return type for implementation of ndo_start_xmit + +From: GUO Zihua + +[ Upstream commit 0dbaf0fa62329d9fe452d9041a707a33f6274f1f ] + +Since Linux now supports CFI, it will be a good idea to fix mismatched +return type for implementation of hooks. Otherwise this might get +cought out by CFI and cause a panic. + +eth_xmit() would return either NETDEV_TX_BUSY or NETDEV_TX_OK, so +change the return type to netdev_tx_t directly. + +Signed-off-by: GUO Zihua +Link: https://lore.kernel.org/r/20220902081612.60405-1-guozihua@huawei.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c +index 403358f2c853..5775e58b0745 100644 +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -820,7 +820,7 @@ static void eth_txdone_irq(void *unused) + } + } + +-static int eth_xmit(struct sk_buff *skb, struct net_device *dev) ++static netdev_tx_t eth_xmit(struct sk_buff *skb, struct net_device *dev) + { + struct port *port = netdev_priv(dev); + unsigned int txreadyq = port->plat->txreadyq; +-- +2.35.1 + diff --git a/queue-5.10/netfilter-nft_fib-fix-for-rpath-check-with-vrf-devic.patch b/queue-5.10/netfilter-nft_fib-fix-for-rpath-check-with-vrf-devic.patch new file mode 100644 index 00000000000..c44e8894fc5 --- /dev/null +++ b/queue-5.10/netfilter-nft_fib-fix-for-rpath-check-with-vrf-devic.patch @@ -0,0 +1,64 @@ +From 7c96377fba01f8f7eb26f55107400feff342d334 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 13:07:31 +0200 +Subject: netfilter: nft_fib: Fix for rpath check with VRF devices + +From: Phil Sutter + +[ Upstream commit 2a8a7c0eaa8747c16aa4a48d573aa920d5c00a5c ] + +Analogous to commit b575b24b8eee3 ("netfilter: Fix rpfilter +dropping vrf packets by mistake") but for nftables fib expression: +Add special treatment of VRF devices so that typical reverse path +filtering via 'fib saddr . iif oif' expression works as expected. + +Fixes: f6d0cbcf09c50 ("netfilter: nf_tables: add fib expression") +Signed-off-by: Phil Sutter +Signed-off-by: Florian Westphal +Signed-off-by: Sasha Levin +--- + net/ipv4/netfilter/nft_fib_ipv4.c | 3 +++ + net/ipv6/netfilter/nft_fib_ipv6.c | 6 +++++- + 2 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/net/ipv4/netfilter/nft_fib_ipv4.c b/net/ipv4/netfilter/nft_fib_ipv4.c +index 03df986217b7..9e6f0f1275e2 100644 +--- a/net/ipv4/netfilter/nft_fib_ipv4.c ++++ b/net/ipv4/netfilter/nft_fib_ipv4.c +@@ -83,6 +83,9 @@ void nft_fib4_eval(const struct nft_expr *expr, struct nft_regs *regs, + else + oif = NULL; + ++ if (priv->flags & NFTA_FIB_F_IIF) ++ fl4.flowi4_oif = l3mdev_master_ifindex_rcu(oif); ++ + if (nft_hook(pkt) == NF_INET_PRE_ROUTING && + nft_fib_is_loopback(pkt->skb, nft_in(pkt))) { + nft_fib_store_result(dest, priv, nft_in(pkt)); +diff --git a/net/ipv6/netfilter/nft_fib_ipv6.c b/net/ipv6/netfilter/nft_fib_ipv6.c +index 92f3235fa287..602743f6dcee 100644 +--- a/net/ipv6/netfilter/nft_fib_ipv6.c ++++ b/net/ipv6/netfilter/nft_fib_ipv6.c +@@ -37,6 +37,9 @@ static int nft_fib6_flowi_init(struct flowi6 *fl6, const struct nft_fib *priv, + if (ipv6_addr_type(&fl6->daddr) & IPV6_ADDR_LINKLOCAL) { + lookup_flags |= RT6_LOOKUP_F_IFACE; + fl6->flowi6_oif = get_ifindex(dev ? dev : pkt->skb->dev); ++ } else if ((priv->flags & NFTA_FIB_F_IIF) && ++ (netif_is_l3_master(dev) || netif_is_l3_slave(dev))) { ++ fl6->flowi6_oif = dev->ifindex; + } + + if (ipv6_addr_type(&fl6->saddr) & IPV6_ADDR_UNICAST) +@@ -193,7 +196,8 @@ void nft_fib6_eval(const struct nft_expr *expr, struct nft_regs *regs, + if (rt->rt6i_flags & (RTF_REJECT | RTF_ANYCAST | RTF_LOCAL)) + goto put_rt_err; + +- if (oif && oif != rt->rt6i_idev->dev) ++ if (oif && oif != rt->rt6i_idev->dev && ++ l3mdev_master_ifindex_rcu(rt->rt6i_idev->dev) != oif->ifindex) + goto put_rt_err; + + nft_fib_store_result(dest, priv, rt->rt6i_idev->dev); +-- +2.35.1 + diff --git a/queue-5.10/nfsd-fix-a-memory-leak-in-an-error-handling-path.patch b/queue-5.10/nfsd-fix-a-memory-leak-in-an-error-handling-path.patch new file mode 100644 index 00000000000..6579dbfd590 --- /dev/null +++ b/queue-5.10/nfsd-fix-a-memory-leak-in-an-error-handling-path.patch @@ -0,0 +1,40 @@ +From 1a1bfbe487ed67b5182e3b7ea42eee8554b5e934 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 07:27:04 +0200 +Subject: nfsd: Fix a memory leak in an error handling path + +From: Christophe JAILLET + +[ Upstream commit fd1ef88049de09bc70d60b549992524cfc0e66ff ] + +If this memdup_user() call fails, the memory allocated in a previous call +a few lines above should be freed. Otherwise it leaks. + +Fixes: 6ee95d1c8991 ("nfsd: add support for upcall version 2") +Signed-off-by: Christophe JAILLET +Reviewed-by: Jeff Layton +Signed-off-by: Chuck Lever +Signed-off-by: Sasha Levin +--- + fs/nfsd/nfs4recover.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/fs/nfsd/nfs4recover.c b/fs/nfsd/nfs4recover.c +index f9b730c43192..83c4e6883953 100644 +--- a/fs/nfsd/nfs4recover.c ++++ b/fs/nfsd/nfs4recover.c +@@ -815,8 +815,10 @@ __cld_pipe_inprogress_downcall(const struct cld_msg_v2 __user *cmsg, + princhash.data = memdup_user( + &ci->cc_princhash.cp_data, + princhashlen); +- if (IS_ERR_OR_NULL(princhash.data)) ++ if (IS_ERR_OR_NULL(princhash.data)) { ++ kfree(name.data); + return -EFAULT; ++ } + princhash.len = princhashlen; + } else + princhash.len = 0; +-- +2.35.1 + diff --git a/queue-5.10/nfsd-fix-use-after-free-on-source-server-when-doing-.patch b/queue-5.10/nfsd-fix-use-after-free-on-source-server-when-doing-.patch new file mode 100644 index 00000000000..75b2833774a --- /dev/null +++ b/queue-5.10/nfsd-fix-use-after-free-on-source-server-when-doing-.patch @@ -0,0 +1,79 @@ +From 6e619292d1ba4d61935c70adb52cd408a8012a15 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 26 Sep 2022 10:59:16 -0700 +Subject: NFSD: fix use-after-free on source server when doing inter-server + copy + +From: Dai Ngo + +[ Upstream commit 019805fea91599b22dfa62ffb29c022f35abeb06 ] + +Use-after-free occurred when the laundromat tried to free expired +cpntf_state entry on the s2s_cp_stateids list after inter-server +copy completed. The sc_cp_list that the expired copy state was +inserted on was already freed. + +When COPY completes, the Linux client normally sends LOCKU(lock_state x), +FREE_STATEID(lock_state x) and CLOSE(open_state y) to the source server. +The nfs4_put_stid call from nfsd4_free_stateid cleans up the copy state +from the s2s_cp_stateids list before freeing the lock state's stid. + +However, sometimes the CLOSE was sent before the FREE_STATEID request. +When this happens, the nfsd4_close_open_stateid call from nfsd4_close +frees all lock states on its st_locks list without cleaning up the copy +state on the sc_cp_list list. When the time the FREE_STATEID arrives the +server returns BAD_STATEID since the lock state was freed. This causes +the use-after-free error to occur when the laundromat tries to free +the expired cpntf_state. + +This patch adds a call to nfs4_free_cpntf_statelist in +nfsd4_close_open_stateid to clean up the copy state before calling +free_ol_stateid_reaplist to free the lock state's stid on the reaplist. + +Signed-off-by: Dai Ngo +Signed-off-by: Chuck Lever +Signed-off-by: Sasha Levin +--- + fs/nfsd/nfs4state.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c +index f1b503bec222..665d0eaeb8db 100644 +--- a/fs/nfsd/nfs4state.c ++++ b/fs/nfsd/nfs4state.c +@@ -843,6 +843,7 @@ static struct nfs4_ol_stateid * nfs4_alloc_open_stateid(struct nfs4_client *clp) + + static void nfs4_free_deleg(struct nfs4_stid *stid) + { ++ WARN_ON(!list_empty(&stid->sc_cp_list)); + kmem_cache_free(deleg_slab, stid); + atomic_long_dec(&num_delegations); + } +@@ -1358,6 +1359,7 @@ static void nfs4_free_ol_stateid(struct nfs4_stid *stid) + release_all_access(stp); + if (stp->st_stateowner) + nfs4_put_stateowner(stp->st_stateowner); ++ WARN_ON(!list_empty(&stid->sc_cp_list)); + kmem_cache_free(stateid_slab, stid); + } + +@@ -6207,6 +6209,7 @@ static void nfsd4_close_open_stateid(struct nfs4_ol_stateid *s) + struct nfs4_client *clp = s->st_stid.sc_client; + bool unhashed; + LIST_HEAD(reaplist); ++ struct nfs4_ol_stateid *stp; + + spin_lock(&clp->cl_lock); + unhashed = unhash_open_stateid(s, &reaplist); +@@ -6215,6 +6218,8 @@ static void nfsd4_close_open_stateid(struct nfs4_ol_stateid *s) + if (unhashed) + put_ol_stateid_locked(s, &reaplist); + spin_unlock(&clp->cl_lock); ++ list_for_each_entry(stp, &reaplist, st_locks) ++ nfs4_free_cpntf_statelist(clp->net, &stp->st_stid); + free_ol_stateid_reaplist(&reaplist); + } else { + spin_unlock(&clp->cl_lock); +-- +2.35.1 + diff --git a/queue-5.10/nfsd-return-nfserr_serverfault-if-splice_ok-but-buf-.patch b/queue-5.10/nfsd-return-nfserr_serverfault-if-splice_ok-but-buf-.patch new file mode 100644 index 00000000000..8aa35f27e56 --- /dev/null +++ b/queue-5.10/nfsd-return-nfserr_serverfault-if-splice_ok-but-buf-.patch @@ -0,0 +1,37 @@ +From 9cb950e882709cf3ed1c0ed659f26159a7b1e6b6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 14:01:50 -0400 +Subject: NFSD: Return nfserr_serverfault if splice_ok but buf->pages have data + +From: Anna Schumaker + +[ Upstream commit 06981d560606ac48d61e5f4fff6738b925c93173 ] + +This was discussed with Chuck as part of this patch set. Returning +nfserr_resource was decided to not be the best error message here, and +he suggested changing to nfserr_serverfault instead. + +Signed-off-by: Anna Schumaker +Link: https://lore.kernel.org/linux-nfs/20220907195259.926736-1-anna@kernel.org/T/#t +Signed-off-by: Chuck Lever +Signed-off-by: Sasha Levin +--- + fs/nfsd/nfs4xdr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c +index 46f825cf53f4..cc605ee0b2fa 100644 +--- a/fs/nfsd/nfs4xdr.c ++++ b/fs/nfsd/nfs4xdr.c +@@ -3871,7 +3871,7 @@ nfsd4_encode_read(struct nfsd4_compoundres *resp, __be32 nfserr, + if (resp->xdr.buf->page_len && + test_bit(RQ_SPLICE_OK, &resp->rqstp->rq_flags)) { + WARN_ON_ONCE(1); +- return nfserr_resource; ++ return nfserr_serverfault; + } + xdr_commit_encode(xdr); + +-- +2.35.1 + diff --git a/queue-5.10/nvme-copy-firmware_rev-on-each-init.patch b/queue-5.10/nvme-copy-firmware_rev-on-each-init.patch new file mode 100644 index 00000000000..dad4e2a0c13 --- /dev/null +++ b/queue-5.10/nvme-copy-firmware_rev-on-each-init.patch @@ -0,0 +1,48 @@ +From 8385be3745254e7911c532f874658c9d001c2d6d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 12:45:08 -0700 +Subject: nvme: copy firmware_rev on each init + +From: Keith Busch + +[ Upstream commit a8eb6c1ba48bddea82e8d74cbe6e119f006be97d ] + +The firmware revision can change on after a reset so copy the most +recent info each time instead of just the first time, otherwise the +sysfs firmware_rev entry may contain stale data. + +Reported-by: Jeff Lien +Signed-off-by: Keith Busch +Reviewed-by: Sagi Grimberg +Reviewed-by: Chaitanya Kulkarni +Reviewed-by: Chao Leng +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + drivers/nvme/host/core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c +index 265d9199b657..e9c13804760e 100644 +--- a/drivers/nvme/host/core.c ++++ b/drivers/nvme/host/core.c +@@ -2949,7 +2949,6 @@ static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) + nvme_init_subnqn(subsys, ctrl, id); + memcpy(subsys->serial, id->sn, sizeof(subsys->serial)); + memcpy(subsys->model, id->mn, sizeof(subsys->model)); +- memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev)); + subsys->vendor_id = le16_to_cpu(id->vid); + subsys->cmic = id->cmic; + subsys->awupf = le16_to_cpu(id->awupf); +@@ -3110,6 +3109,8 @@ int nvme_init_identify(struct nvme_ctrl *ctrl) + ctrl->quirks |= core_quirks[i].quirks; + } + } ++ memcpy(ctrl->subsys->firmware_rev, id->fr, ++ sizeof(ctrl->subsys->firmware_rev)); + + if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) { + dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n"); +-- +2.35.1 + diff --git a/queue-5.10/nvmet-tcp-add-bounds-check-on-transfer-tag.patch b/queue-5.10/nvmet-tcp-add-bounds-check-on-transfer-tag.patch new file mode 100644 index 00000000000..2a585a6f562 --- /dev/null +++ b/queue-5.10/nvmet-tcp-add-bounds-check-on-transfer-tag.patch @@ -0,0 +1,47 @@ +From df08ec9a52a708cc67ca453473c39359f436af94 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 00:06:49 +0530 +Subject: nvmet-tcp: add bounds check on Transfer Tag + +From: Varun Prakash + +[ Upstream commit b6a545ffa2c192b1e6da4a7924edac5ba9f4ea2b ] + +ttag is used as an index to get cmd in nvmet_tcp_handle_h2c_data_pdu(), +add a bounds check to avoid out-of-bounds access. + +Signed-off-by: Varun Prakash +Reviewed-by: Sagi Grimberg +Signed-off-by: Christoph Hellwig +Signed-off-by: Sasha Levin +--- + drivers/nvme/target/tcp.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/nvme/target/tcp.c b/drivers/nvme/target/tcp.c +index e3e35b9bd684..2ddbd4f4f628 100644 +--- a/drivers/nvme/target/tcp.c ++++ b/drivers/nvme/target/tcp.c +@@ -922,10 +922,17 @@ static int nvmet_tcp_handle_h2c_data_pdu(struct nvmet_tcp_queue *queue) + struct nvme_tcp_data_pdu *data = &queue->pdu.data; + struct nvmet_tcp_cmd *cmd; + +- if (likely(queue->nr_cmds)) ++ if (likely(queue->nr_cmds)) { ++ if (unlikely(data->ttag >= queue->nr_cmds)) { ++ pr_err("queue %d: received out of bound ttag %u, nr_cmds %u\n", ++ queue->idx, data->ttag, queue->nr_cmds); ++ nvmet_tcp_fatal_error(queue); ++ return -EPROTO; ++ } + cmd = &queue->cmds[data->ttag]; +- else ++ } else { + cmd = &queue->connect; ++ } + + if (le32_to_cpu(data->data_offset) != cmd->rbytes_done) { + pr_err("ttag %u unexpected data offset %u (expected %u)\n", +-- +2.35.1 + diff --git a/queue-5.10/objtool-preserve-special-st_shndx-indexes-in-elf_upd.patch b/queue-5.10/objtool-preserve-special-st_shndx-indexes-in-elf_upd.patch new file mode 100644 index 00000000000..a894ad33d4d --- /dev/null +++ b/queue-5.10/objtool-preserve-special-st_shndx-indexes-in-elf_upd.patch @@ -0,0 +1,54 @@ +From c462dca169eb91466a26b6dcbee8be616ead3e48 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 14:54:58 -0700 +Subject: objtool: Preserve special st_shndx indexes in elf_update_symbol + +From: Sami Tolvanen + +[ Upstream commit 5141d3a06b2da1731ac82091298b766a1f95d3d8 ] + +elf_update_symbol fails to preserve the special st_shndx values +between [SHN_LORESERVE, SHN_HIRESERVE], which results in it +converting SHN_ABS entries into SHN_UNDEF, for example. Explicitly +check for the special indexes and ensure these symbols are not +marked undefined. + +Fixes: ead165fa1042 ("objtool: Fix symbol creation") +Signed-off-by: Sami Tolvanen +Acked-by: Peter Zijlstra (Intel) +Tested-by: Peter Zijlstra (Intel) +Signed-off-by: Kees Cook +Link: https://lore.kernel.org/r/20220908215504.3686827-17-samitolvanen@google.com +Signed-off-by: Sasha Levin +--- + tools/objtool/elf.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/tools/objtool/elf.c b/tools/objtool/elf.c +index 5aa3b4e76479..a2ea3931e01d 100644 +--- a/tools/objtool/elf.c ++++ b/tools/objtool/elf.c +@@ -578,6 +578,11 @@ static int elf_update_symbol(struct elf *elf, struct section *symtab, + Elf64_Xword entsize = symtab->sh.sh_entsize; + int max_idx, idx = sym->idx; + Elf_Scn *s, *t = NULL; ++ bool is_special_shndx = sym->sym.st_shndx >= SHN_LORESERVE && ++ sym->sym.st_shndx != SHN_XINDEX; ++ ++ if (is_special_shndx) ++ shndx = sym->sym.st_shndx; + + s = elf_getscn(elf->elf, symtab->idx); + if (!s) { +@@ -663,7 +668,7 @@ static int elf_update_symbol(struct elf *elf, struct section *symtab, + } + + /* setup extended section index magic and write the symbol */ +- if (shndx >= SHN_UNDEF && shndx < SHN_LORESERVE) { ++ if ((shndx >= SHN_UNDEF && shndx < SHN_LORESERVE) || is_special_shndx) { + sym->sym.st_shndx = shndx; + if (!shndx_data) + shndx = 0; +-- +2.35.1 + diff --git a/queue-5.10/once-add-do_once_slow-for-sleepable-contexts.patch b/queue-5.10/once-add-do_once_slow-for-sleepable-contexts.patch new file mode 100644 index 00000000000..d904c5a7f47 --- /dev/null +++ b/queue-5.10/once-add-do_once_slow-for-sleepable-contexts.patch @@ -0,0 +1,149 @@ +From b1d6684936753503304abbce07918fc4b1fdea2b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 1 Oct 2022 13:51:02 -0700 +Subject: once: add DO_ONCE_SLOW() for sleepable contexts + +From: Eric Dumazet + +[ Upstream commit 62c07983bef9d3e78e71189441e1a470f0d1e653 ] + +Christophe Leroy reported a ~80ms latency spike +happening at first TCP connect() time. + +This is because __inet_hash_connect() uses get_random_once() +to populate a perturbation table which became quite big +after commit 4c2c8f03a5ab ("tcp: increase source port perturb table to 2^16") + +get_random_once() uses DO_ONCE(), which block hard irqs for the duration +of the operation. + +This patch adds DO_ONCE_SLOW() which uses a mutex instead of a spinlock +for operations where we prefer to stay in process context. + +Then __inet_hash_connect() can use get_random_slow_once() +to populate its perturbation table. + +Fixes: 4c2c8f03a5ab ("tcp: increase source port perturb table to 2^16") +Fixes: 190cc82489f4 ("tcp: change source port randomizarion at connect() time") +Reported-by: Christophe Leroy +Link: https://lore.kernel.org/netdev/CANn89iLAEYBaoYajy0Y9UmGFff5GPxDUoG-ErVB2jDdRNQ5Tug@mail.gmail.com/T/#t +Signed-off-by: Eric Dumazet +Cc: Willy Tarreau +Tested-by: Christophe Leroy +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + include/linux/once.h | 28 ++++++++++++++++++++++++++++ + lib/once.c | 30 ++++++++++++++++++++++++++++++ + net/ipv4/inet_hashtables.c | 4 ++-- + 3 files changed, 60 insertions(+), 2 deletions(-) + +diff --git a/include/linux/once.h b/include/linux/once.h +index ae6f4eb41cbe..bb58e1c3aa03 100644 +--- a/include/linux/once.h ++++ b/include/linux/once.h +@@ -5,10 +5,18 @@ + #include + #include + ++/* Helpers used from arbitrary contexts. ++ * Hard irqs are blocked, be cautious. ++ */ + bool __do_once_start(bool *done, unsigned long *flags); + void __do_once_done(bool *done, struct static_key_true *once_key, + unsigned long *flags, struct module *mod); + ++/* Variant for process contexts only. */ ++bool __do_once_slow_start(bool *done); ++void __do_once_slow_done(bool *done, struct static_key_true *once_key, ++ struct module *mod); ++ + /* Call a function exactly once. The idea of DO_ONCE() is to perform + * a function call such as initialization of random seeds, etc, only + * once, where DO_ONCE() can live in the fast-path. After @func has +@@ -52,9 +60,29 @@ void __do_once_done(bool *done, struct static_key_true *once_key, + ___ret; \ + }) + ++/* Variant of DO_ONCE() for process/sleepable contexts. */ ++#define DO_ONCE_SLOW(func, ...) \ ++ ({ \ ++ bool ___ret = false; \ ++ static bool __section(".data.once") ___done = false; \ ++ static DEFINE_STATIC_KEY_TRUE(___once_key); \ ++ if (static_branch_unlikely(&___once_key)) { \ ++ ___ret = __do_once_slow_start(&___done); \ ++ if (unlikely(___ret)) { \ ++ func(__VA_ARGS__); \ ++ __do_once_slow_done(&___done, &___once_key, \ ++ THIS_MODULE); \ ++ } \ ++ } \ ++ ___ret; \ ++ }) ++ + #define get_random_once(buf, nbytes) \ + DO_ONCE(get_random_bytes, (buf), (nbytes)) + #define get_random_once_wait(buf, nbytes) \ + DO_ONCE(get_random_bytes_wait, (buf), (nbytes)) \ + ++#define get_random_slow_once(buf, nbytes) \ ++ DO_ONCE_SLOW(get_random_bytes, (buf), (nbytes)) ++ + #endif /* _LINUX_ONCE_H */ +diff --git a/lib/once.c b/lib/once.c +index 59149bf3bfb4..351f66aad310 100644 +--- a/lib/once.c ++++ b/lib/once.c +@@ -66,3 +66,33 @@ void __do_once_done(bool *done, struct static_key_true *once_key, + once_disable_jump(once_key, mod); + } + EXPORT_SYMBOL(__do_once_done); ++ ++static DEFINE_MUTEX(once_mutex); ++ ++bool __do_once_slow_start(bool *done) ++ __acquires(once_mutex) ++{ ++ mutex_lock(&once_mutex); ++ if (*done) { ++ mutex_unlock(&once_mutex); ++ /* Keep sparse happy by restoring an even lock count on ++ * this mutex. In case we return here, we don't call into ++ * __do_once_done but return early in the DO_ONCE_SLOW() macro. ++ */ ++ __acquire(once_mutex); ++ return false; ++ } ++ ++ return true; ++} ++EXPORT_SYMBOL(__do_once_slow_start); ++ ++void __do_once_slow_done(bool *done, struct static_key_true *once_key, ++ struct module *mod) ++ __releases(once_mutex) ++{ ++ *done = true; ++ mutex_unlock(&once_mutex); ++ once_disable_jump(once_key, mod); ++} ++EXPORT_SYMBOL(__do_once_slow_done); +diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c +index feb7f072f2b2..c0de655fffd7 100644 +--- a/net/ipv4/inet_hashtables.c ++++ b/net/ipv4/inet_hashtables.c +@@ -771,8 +771,8 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row, + if (likely(remaining > 1)) + remaining &= ~1U; + +- net_get_random_once(table_perturb, +- INET_TABLE_PERTURB_SIZE * sizeof(*table_perturb)); ++ get_random_slow_once(table_perturb, ++ INET_TABLE_PERTURB_SIZE * sizeof(*table_perturb)); + index = port_offset & (INET_TABLE_PERTURB_SIZE - 1); + + offset = READ_ONCE(table_perturb[index]) + (port_offset >> 32); +-- +2.35.1 + diff --git a/queue-5.10/openvswitch-fix-double-reporting-of-drops-in-dropwat.patch b/queue-5.10/openvswitch-fix-double-reporting-of-drops-in-dropwat.patch new file mode 100644 index 00000000000..a86bdd0ff81 --- /dev/null +++ b/queue-5.10/openvswitch-fix-double-reporting-of-drops-in-dropwat.patch @@ -0,0 +1,52 @@ +From f67a1131f4464c67bad327cd7a26dd558a0ad301 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 17 Aug 2022 11:06:34 -0400 +Subject: openvswitch: Fix double reporting of drops in dropwatch + +From: Mike Pattrick + +[ Upstream commit 1100248a5c5ccd57059eb8d02ec077e839a23826 ] + +Frames sent to userspace can be reported as dropped in +ovs_dp_process_packet, however, if they are dropped in the netlink code +then netlink_attachskb will report the same frame as dropped. + +This patch checks for error codes which indicate that the frame has +already been freed. + +Signed-off-by: Mike Pattrick +Link: https://bugzilla.redhat.com/show_bug.cgi?id=2109946 +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/openvswitch/datapath.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c +index 9d6ef6cb9b26..4d2d91d6f990 100644 +--- a/net/openvswitch/datapath.c ++++ b/net/openvswitch/datapath.c +@@ -241,10 +241,17 @@ void ovs_dp_process_packet(struct sk_buff *skb, struct sw_flow_key *key) + upcall.portid = ovs_vport_find_upcall_portid(p, skb); + upcall.mru = OVS_CB(skb)->mru; + error = ovs_dp_upcall(dp, skb, key, &upcall, 0); +- if (unlikely(error)) +- kfree_skb(skb); +- else ++ switch (error) { ++ case 0: ++ case -EAGAIN: ++ case -ERESTARTSYS: ++ case -EINTR: + consume_skb(skb); ++ break; ++ default: ++ kfree_skb(skb); ++ break; ++ } + stats_counter = &stats->n_missed; + goto out; + } +-- +2.35.1 + diff --git a/queue-5.10/openvswitch-fix-overreporting-of-drops-in-dropwatch.patch b/queue-5.10/openvswitch-fix-overreporting-of-drops-in-dropwatch.patch new file mode 100644 index 00000000000..ff00487f24b --- /dev/null +++ b/queue-5.10/openvswitch-fix-overreporting-of-drops-in-dropwatch.patch @@ -0,0 +1,42 @@ +From f296549d94f1d3adc305ac0dfd406a12cb41da46 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 17 Aug 2022 11:06:35 -0400 +Subject: openvswitch: Fix overreporting of drops in dropwatch + +From: Mike Pattrick + +[ Upstream commit c21ab2afa2c64896a7f0e3cbc6845ec63dcfad2e ] + +Currently queue_userspace_packet will call kfree_skb for all frames, +whether or not an error occurred. This can result in a single dropped +frame being reported as multiple drops in dropwatch. This functions +caller may also call kfree_skb in case of an error. This patch will +consume the skbs instead and allow caller's to use kfree_skb. + +Signed-off-by: Mike Pattrick +Link: https://bugzilla.redhat.com/show_bug.cgi?id=2109957 +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/openvswitch/datapath.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c +index 4d2d91d6f990..6b5c0abf7f1b 100644 +--- a/net/openvswitch/datapath.c ++++ b/net/openvswitch/datapath.c +@@ -544,8 +544,9 @@ static int queue_userspace_packet(struct datapath *dp, struct sk_buff *skb, + out: + if (err) + skb_tx_error(skb); +- kfree_skb(user_skb); +- kfree_skb(nskb); ++ consume_skb(user_skb); ++ consume_skb(nskb); ++ + return err; + } + +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-combo-disable-runtime-pm-on-unbind.patch b/queue-5.10/phy-qcom-qmp-combo-disable-runtime-pm-on-unbind.patch new file mode 100644 index 00000000000..265b87ba73d --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-combo-disable-runtime-pm-on-unbind.patch @@ -0,0 +1,53 @@ +From 5b35a2e119083cddd0e476946d63eb12ac862804 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 13:07:13 +0200 +Subject: phy: qcom-qmp-combo: disable runtime PM on unbind + +From: Johan Hovold + +[ Upstream commit 4382d518d1887e62234560ea08a0203d11d28cc1 ] + +Make sure to disable runtime PM also on driver unbind. + +Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). +Signed-off-by: Johan Hovold +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220907110728.19092-2-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +index c7309e981bfb..dcf8a8764e17 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +@@ -6273,7 +6273,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + return -ENOMEM; + + pm_runtime_set_active(dev); +- pm_runtime_enable(dev); ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ return ret; + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. +@@ -6323,13 +6325,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); +- else +- pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + + err_node_put: +- pm_runtime_disable(dev); + of_node_put(child); + return ret; + } +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-combo-fix-memleak-on-probe-deferral.patch b/queue-5.10/phy-qcom-qmp-combo-fix-memleak-on-probe-deferral.patch new file mode 100644 index 00000000000..f1a6e5fd00d --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-combo-fix-memleak-on-probe-deferral.patch @@ -0,0 +1,92 @@ +From d7cbec12d6dc1abc8a49c609cdc305967c586a47 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 12:23:33 +0200 +Subject: phy: qcom-qmp-combo: fix memleak on probe deferral + +From: Johan Hovold + +[ Upstream commit 2de8a325b1084330ae500380cc27edc39f488c30 ] + +Switch to using the device-managed of_iomap helper to avoid leaking +memory on probe deferral and driver unbind. + +Note that this helper checks for already reserved regions and may fail +if there are multiple devices claiming the same memory. + +Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20220916102340.11520-5-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 32 ++++++++++++----------- + 1 file changed, 17 insertions(+), 15 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +index dcf8a8764e17..5606b25ea229 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +@@ -5919,17 +5919,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ +- qphy->tx = of_iomap(np, 0); +- if (!qphy->tx) +- return -ENOMEM; ++ qphy->tx = devm_of_iomap(dev, np, 0, NULL); ++ if (IS_ERR(qphy->tx)) ++ return PTR_ERR(qphy->tx); + +- qphy->rx = of_iomap(np, 1); +- if (!qphy->rx) +- return -ENOMEM; ++ qphy->rx = devm_of_iomap(dev, np, 1, NULL); ++ if (IS_ERR(qphy->rx)) ++ return PTR_ERR(qphy->rx); + +- qphy->pcs = of_iomap(np, 2); +- if (!qphy->pcs) +- return -ENOMEM; ++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL); ++ if (IS_ERR(qphy->pcs)) ++ return PTR_ERR(qphy->pcs); + + /* + * If this is a dual-lane PHY, then there should be registers for the +@@ -5938,9 +5938,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { +- qphy->tx2 = of_iomap(np, 3); +- qphy->rx2 = of_iomap(np, 4); +- if (!qphy->tx2 || !qphy->rx2) { ++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); ++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); ++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + +@@ -5950,15 +5950,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { +- qphy->pcs_misc = of_iomap(np, 5); ++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); + } + + } else { +- qphy->pcs_misc = of_iomap(np, 3); ++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); + } + +- if (!qphy->pcs_misc) ++ if (IS_ERR(qphy->pcs_misc)) { + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ qphy->pcs_misc = NULL; ++ } + + /* + * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch b/queue-5.10/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch new file mode 100644 index 00000000000..825f98d8f7c --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch @@ -0,0 +1,31819 @@ +From 7e70a5189bac48492d93da79cafced4d5ef44e16 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:35:32 +0300 +Subject: phy: qcom-qmp: create copies of QMP PHY driver + +From: Dmitry Baryshkov + +[ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ] + +In order to split and cleanup the single monstrous QMP PHY driver, +create blind copies of the current file. They will be used for: +- PCIe (and a separate msm8996 PCIe PHY driver) +- UFS +- USB +- Combo DP + USB + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: 4382d518d188 ("phy: qcom-qmp-combo: disable runtime PM on unbind") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6350 +++++++++++++++++ + .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 6350 +++++++++++++++++ + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6350 +++++++++++++++++ + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 6350 +++++++++++++++++ + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 6350 +++++++++++++++++ + 5 files changed, 31750 insertions(+) + create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c + create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c + create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c + create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c + create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +new file mode 100644 +index 000000000000..c7309e981bfb +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +@@ -0,0 +1,6350 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-qcom-qmp.h" ++ ++/* QPHY_SW_RESET bit */ ++#define SW_RESET BIT(0) ++/* QPHY_POWER_DOWN_CONTROL */ ++#define SW_PWRDN BIT(0) ++#define REFCLK_DRV_DSBL BIT(1) ++/* QPHY_START_CONTROL bits */ ++#define SERDES_START BIT(0) ++#define PCS_START BIT(1) ++#define PLL_READY_GATE_EN BIT(3) ++/* QPHY_PCS_STATUS bit */ ++#define PHYSTATUS BIT(6) ++#define PHYSTATUS_4_20 BIT(7) ++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ ++#define PCS_READY BIT(0) ++ ++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ ++/* DP PHY soft reset */ ++#define SW_DPPHY_RESET BIT(0) ++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ ++#define SW_DPPHY_RESET_MUX BIT(1) ++/* USB3 PHY soft reset */ ++#define SW_USB3PHY_RESET BIT(2) ++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ ++#define SW_USB3PHY_RESET_MUX BIT(3) ++ ++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ ++#define USB3_MODE BIT(0) /* enables USB3 mode */ ++#define DP_MODE BIT(1) /* enables DP mode */ ++ ++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ ++#define ARCVR_DTCT_EN BIT(0) ++#define ALFPS_DTCT_EN BIT(1) ++#define ARCVR_DTCT_EVENT_SEL BIT(4) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ ++#define IRQ_CLEAR BIT(0) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ ++#define RCVR_DETECT BIT(0) ++ ++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ ++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ ++ ++#define PHY_INIT_COMPLETE_TIMEOUT 10000 ++#define POWER_DOWN_DELAY_US_MIN 10 ++#define POWER_DOWN_DELAY_US_MAX 11 ++ ++#define MAX_PROP_NAME 32 ++ ++/* Define the assumed distance between lanes for underspecified device trees. */ ++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 ++ ++struct qmp_phy_init_tbl { ++ unsigned int offset; ++ unsigned int val; ++ /* ++ * register part of layout ? ++ * if yes, then offset gives index in the reg-layout ++ */ ++ bool in_layout; ++ /* ++ * mask of lanes for which this register is written ++ * for cases when second lane needs different values ++ */ ++ u8 lane_mask; ++}; ++ ++#define QMP_PHY_INIT_CFG(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_L(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .in_layout = true, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = l, \ ++ } ++ ++/* set of registers with offsets different per-PHY */ ++enum qphy_reg_layout { ++ /* Common block control registers */ ++ QPHY_COM_SW_RESET, ++ QPHY_COM_POWER_DOWN_CONTROL, ++ QPHY_COM_START_CONTROL, ++ QPHY_COM_PCS_READY_STATUS, ++ /* PCS registers */ ++ QPHY_PLL_LOCK_CHK_DLY_TIME, ++ QPHY_FLL_CNTRL1, ++ QPHY_FLL_CNTRL2, ++ QPHY_FLL_CNT_VAL_L, ++ QPHY_FLL_CNT_VAL_H_TOL, ++ QPHY_FLL_MAN_CODE, ++ QPHY_SW_RESET, ++ QPHY_START_CTRL, ++ QPHY_PCS_READY_STATUS, ++ QPHY_PCS_STATUS, ++ QPHY_PCS_AUTONOMOUS_MODE_CTRL, ++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, ++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, ++ QPHY_PCS_POWER_DOWN_CONTROL, ++ /* PCS_MISC registers */ ++ QPHY_PCS_MISC_TYPEC_CTRL, ++ /* Keep last to ensure regs_layout arrays are properly initialized */ ++ QPHY_LAYOUT_SIZE ++}; ++ ++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_COM_SW_RESET] = 0x400, ++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, ++ [QPHY_COM_START_CONTROL] = 0x408, ++ [QPHY_COM_PCS_READY_STATUS] = 0x448, ++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, ++ [QPHY_FLL_CNTRL1] = 0xc4, ++ [QPHY_FLL_CNTRL2] = 0xc8, ++ [QPHY_FLL_CNT_VAL_L] = 0xcc, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, ++ [QPHY_FLL_MAN_CODE] = 0xd4, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_FLL_CNTRL1] = 0xc0, ++ [QPHY_FLL_CNTRL2] = 0xc4, ++ [QPHY_FLL_CNT_VAL_L] = 0xc8, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, ++ [QPHY_FLL_MAN_CODE] = 0xd0, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x17c, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, ++}; ++ ++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, ++}; ++ ++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x2ac, ++}; ++ ++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, ++}; ++ ++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, ++}; ++ ++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, ++}; ++ ++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, ++}; ++ ++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x160, ++}; ++ ++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, ++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, ++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), ++ ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), ++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), ++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), ++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), ++}; ++ ++/* Register names should be validated, they might be different for this PHY */ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), ++}; ++ ++struct qmp_phy; ++ ++/* struct qmp_phy_cfg - per-PHY initialization config */ ++struct qmp_phy_cfg { ++ /* phy-type - PCIE/UFS/USB */ ++ unsigned int type; ++ /* number of lanes provided by phy */ ++ int nlanes; ++ ++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ ++ const struct qmp_phy_init_tbl *serdes_tbl; ++ int serdes_tbl_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_sec; ++ int serdes_tbl_num_sec; ++ const struct qmp_phy_init_tbl *tx_tbl; ++ int tx_tbl_num; ++ const struct qmp_phy_init_tbl *tx_tbl_sec; ++ int tx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *rx_tbl; ++ int rx_tbl_num; ++ const struct qmp_phy_init_tbl *rx_tbl_sec; ++ int rx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_tbl; ++ int pcs_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_tbl_sec; ++ int pcs_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl; ++ int pcs_misc_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; ++ int pcs_misc_tbl_num_sec; ++ ++ /* Init sequence for DP PHY block link rates */ ++ const struct qmp_phy_init_tbl *serdes_tbl_rbr; ++ int serdes_tbl_rbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr; ++ int serdes_tbl_hbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2; ++ int serdes_tbl_hbr2_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3; ++ int serdes_tbl_hbr3_num; ++ ++ /* DP PHY callbacks */ ++ int (*configure_dp_phy)(struct qmp_phy *qphy); ++ void (*configure_dp_tx)(struct qmp_phy *qphy); ++ int (*calibrate_dp_phy)(struct qmp_phy *qphy); ++ void (*dp_aux_init)(struct qmp_phy *qphy); ++ ++ /* clock ids to be requested */ ++ const char * const *clk_list; ++ int num_clks; ++ /* resets to be requested */ ++ const char * const *reset_list; ++ int num_resets; ++ /* regulators to be requested */ ++ const char * const *vreg_list; ++ int num_vregs; ++ ++ /* array of registers with different offsets */ ++ const unsigned int *regs; ++ ++ unsigned int start_ctrl; ++ unsigned int pwrdn_ctrl; ++ unsigned int mask_com_pcs_ready; ++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ ++ unsigned int phy_status; ++ ++ /* true, if PHY has a separate PHY_COM control block */ ++ bool has_phy_com_ctrl; ++ /* true, if PHY has a reset for individual lanes */ ++ bool has_lane_rst; ++ /* true, if PHY needs delay after POWER_DOWN */ ++ bool has_pwrdn_delay; ++ /* power_down delay in usec */ ++ int pwrdn_delay_min; ++ int pwrdn_delay_max; ++ ++ /* true, if PHY has a separate DP_COM control block */ ++ bool has_phy_dp_com_ctrl; ++ /* true, if PHY has secondary tx/rx lanes to be configured */ ++ bool is_dual_lane_phy; ++ ++ /* true, if PCS block has no separate SW_RESET register */ ++ bool no_pcs_sw_reset; ++}; ++ ++struct qmp_phy_combo_cfg { ++ const struct qmp_phy_cfg *usb_cfg; ++ const struct qmp_phy_cfg *dp_cfg; ++}; ++ ++/** ++ * struct qmp_phy - per-lane phy descriptor ++ * ++ * @phy: generic phy ++ * @cfg: phy specific configuration ++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL) ++ * @tx: iomapped memory space for lane's tx ++ * @rx: iomapped memory space for lane's rx ++ * @pcs: iomapped memory space for lane's pcs ++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) ++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) ++ * @pcs_misc: iomapped memory space for lane's pcs_misc ++ * @pipe_clk: pipe clock ++ * @index: lane index ++ * @qmp: QMP phy to which this lane belongs ++ * @lane_rst: lane's reset controller ++ * @mode: current PHY mode ++ * @dp_aux_cfg: Display port aux config ++ * @dp_opts: Display port optional config ++ * @dp_clks: Display port clocks ++ */ ++struct qmp_phy { ++ struct phy *phy; ++ const struct qmp_phy_cfg *cfg; ++ void __iomem *serdes; ++ void __iomem *tx; ++ void __iomem *rx; ++ void __iomem *pcs; ++ void __iomem *tx2; ++ void __iomem *rx2; ++ void __iomem *pcs_misc; ++ struct clk *pipe_clk; ++ unsigned int index; ++ struct qcom_qmp *qmp; ++ struct reset_control *lane_rst; ++ enum phy_mode mode; ++ unsigned int dp_aux_cfg; ++ struct phy_configure_opts_dp dp_opts; ++ struct qmp_phy_dp_clks *dp_clks; ++}; ++ ++struct qmp_phy_dp_clks { ++ struct qmp_phy *qphy; ++ struct clk_hw dp_link_hw; ++ struct clk_hw dp_pixel_hw; ++}; ++ ++/** ++ * struct qcom_qmp - structure holding QMP phy block attributes ++ * ++ * @dev: device ++ * @dp_com: iomapped memory space for phy's dp_com control block ++ * ++ * @clks: array of clocks required by phy ++ * @resets: array of resets required by phy ++ * @vregs: regulator supplies bulk data ++ * ++ * @phys: array of per-lane phy descriptors ++ * @phy_mutex: mutex lock for PHY common block initialization ++ * @init_count: phy common block initialization count ++ * @ufs_reset: optional UFS PHY reset handle ++ */ ++struct qcom_qmp { ++ struct device *dev; ++ void __iomem *dp_com; ++ ++ struct clk_bulk_data *clks; ++ struct reset_control **resets; ++ struct regulator_bulk_data *vregs; ++ ++ struct qmp_phy **phys; ++ ++ struct mutex phy_mutex; ++ int init_count; ++ ++ struct reset_control *ufs_reset; ++}; ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg |= val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg &= ~val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++/* list of clocks required by phy */ ++static const char * const msm8996_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", ++}; ++ ++static const char * const msm8996_ufs_phy_clk_l[] = { ++ "ref", ++}; ++ ++static const char * const qmp_v3_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "com_aux", ++}; ++ ++static const char * const sdm845_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "refgen", ++}; ++ ++static const char * const qmp_v4_phy_clk_l[] = { ++ "aux", "ref_clk_src", "ref", "com_aux", ++}; ++ ++/* the primary usb3 phy on sm8250 doesn't have a ref clock */ ++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { ++ "aux", "ref_clk_src", "com_aux" ++}; ++ ++static const char * const sm8450_ufs_phy_clk_l[] = { ++ "qref", "ref", "ref_aux", ++}; ++ ++static const char * const sdm845_ufs_phy_clk_l[] = { ++ "ref", "ref_aux", ++}; ++ ++/* usb3 phy on sdx55 doesn't have com_aux clock */ ++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { ++ "aux", "cfg_ahb", "ref" ++}; ++ ++static const char * const qcm2290_usb3phy_clk_l[] = { ++ "cfg_ahb", "ref", "com_aux", ++}; ++ ++/* list of resets */ ++static const char * const msm8996_pciephy_reset_l[] = { ++ "phy", "common", "cfg", ++}; ++ ++static const char * const msm8996_usb3phy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const char * const sc7180_usb3phy_reset_l[] = { ++ "phy", ++}; ++ ++static const char * const qcm2290_usb3phy_reset_l[] = { ++ "phy_phy", "phy", ++}; ++ ++static const char * const sdm845_pciephy_reset_l[] = { ++ "phy", ++}; ++ ++/* list of regulators */ ++static const char * const qmp_phy_vreg_l[] = { ++ "vdda-phy", "vdda-pll", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = ipq8074_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), ++ .pcs_tbl = ipq8074_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 3, ++ ++ .serdes_tbl = msm8996_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), ++ .tx_tbl = msm8996_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), ++ .rx_tbl = msm8996_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), ++ .pcs_tbl = msm8996_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | PLL_READY_GATE_EN, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .mask_com_pcs_ready = PCS_READY, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = true, ++ .has_lane_rst = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg msm8996_ufs_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_ufs_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), ++ .tx_tbl = msm8996_ufs_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), ++ .rx_tbl = msm8996_ufs_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), ++ ++ .clk_list = msm8996_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), ++ ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ ++ .regs = msm8996_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = msm8996_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), ++ .pcs_tbl = msm8996_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const char * const ipq8074_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", ++}; ++/* list of resets */ ++static const char * const ipq8074_pciephy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), ++ .rx_tbl = ipq8074_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq6018_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), ++ .tx_tbl = ipq6018_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), ++ .rx_tbl = ipq6018_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), ++ .pcs_tbl = ipq6018_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = ipq_pciephy_gen3_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qmp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qhp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qhp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qhp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, ++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), ++ .tx_tbl = qmp_v3_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { ++ .usb_cfg = &sc7180_usb3phy_cfg, ++ .dp_cfg = &sc7180_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdm845_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), ++ .tx_tbl = sdm845_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), ++ .rx_tbl = sdm845_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), ++ .pcs_tbl = sdm845_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm6115_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), ++ .tx_tbl = sm6115_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), ++ .rx_tbl = sm6115_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), ++ .pcs_tbl = sm6115_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm6115_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ ++ .is_dual_lane_phy = false, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8998_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), ++ .tx_tbl = msm8998_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), ++ .rx_tbl = msm8998_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), ++ .pcs_tbl = msm8998_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), ++ .tx_tbl = msm8998_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), ++ .rx_tbl = msm8998_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), ++ .pcs_tbl = msm8998_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8150_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), ++ .tx_tbl = sm8150_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), ++ .rx_tbl = sm8150_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), ++ .pcs_tbl = sm8150_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8150_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), ++ .rx_tbl = sm8150_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), ++ .pcs_tbl = sm8150_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), ++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), ++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), ++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { ++ .usb_cfg = &sm8150_usb3phy_cfg, ++ .dp_cfg = &sc8180x_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8250_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), ++ .rx_tbl = sm8250_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), ++ .pcs_tbl = sm8250_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { ++ .usb_cfg = &sm8250_usb3phy_cfg, ++ .dp_cfg = &sm8250_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdx55_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), ++ .rx_tbl = sdx55_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8350_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), ++ .rx_tbl = sm8350_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), ++ .pcs_tbl = sm8350_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sm8450_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qcm2290_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), ++ .tx_tbl = qcm2290_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), ++ .rx_tbl = qcm2290_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), ++ .pcs_tbl = qcm2290_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), ++ .clk_list = qcm2290_usb3phy_clk_l, ++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), ++ .reset_list = qcm2290_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qcm2290_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static void qcom_qmp_phy_configure_lane(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num, ++ u8 lane_mask) ++{ ++ int i; ++ const struct qmp_phy_init_tbl *t = tbl; ++ ++ if (!t) ++ return; ++ ++ for (i = 0; i < num; i++, t++) { ++ if (!(t->lane_mask & lane_mask)) ++ continue; ++ ++ if (t->in_layout) ++ writel(t->val, base + regs[t->offset]); ++ else ++ writel(t->val, base + t->offset); ++ } ++} ++ ++static void qcom_qmp_phy_configure(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num) ++{ ++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++} ++ ++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; ++ int serdes_tbl_num = cfg->serdes_tbl_num; ++ int ret; ++ ++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ if (cfg->serdes_tbl_sec) ++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ cfg->serdes_tbl_num_sec); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ switch (dp_opts->link_rate) { ++ case 1620: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_rbr, ++ cfg->serdes_tbl_rbr_num); ++ break; ++ case 2700: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr, ++ cfg->serdes_tbl_hbr_num); ++ break; ++ case 5400: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr2, ++ cfg->serdes_tbl_hbr2_num); ++ break; ++ case 8100: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr3, ++ cfg->serdes_tbl_hbr3_num); ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ } ++ ++ ++ if (cfg->has_phy_com_ctrl) { ++ void __iomem *status; ++ unsigned int mask, val; ++ ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ ++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; ++ mask = cfg->mask_com_pcs_ready; ++ ++ ret = readl_poll_timeout(status, val, (val & mask), 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, ++ "phy common block init timed-out\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_LANE_0_1_PWRDN | ++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | ++ DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(QSERDES_V3_COM_BIAS_EN | ++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | ++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { ++ { 0x00, 0x0c, 0x15, 0x1a }, ++ { 0x02, 0x0e, 0x16, 0xff }, ++ { 0x02, 0x11, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { ++ { 0x02, 0x12, 0x16, 0x1a }, ++ { 0x09, 0x19, 0x1f, 0xff }, ++ { 0x10, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { ++ { 0x00, 0x0c, 0x14, 0x19 }, ++ { 0x00, 0x0b, 0x12, 0xff }, ++ { 0x00, 0x0b, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { ++ { 0x08, 0x0f, 0x16, 0x1f }, ++ { 0x11, 0x1e, 0x1f, 0xff }, ++ { 0x19, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, ++ unsigned int drv_lvl_reg, unsigned int emp_post_reg) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ unsigned int v_level = 0, p_level = 0; ++ u8 voltage_swing_cfg, pre_emphasis_cfg; ++ int i; ++ ++ for (i = 0; i < dp_opts->lanes; i++) { ++ v_level = max(v_level, dp_opts->voltage[i]); ++ p_level = max(p_level, dp_opts->pre[i]); ++ } ++ ++ if (dp_opts->link_rate <= 2700) { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; ++ } else { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; ++ } ++ ++ /* TODO: Move check to config check */ ++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) ++ return -EINVAL; ++ ++ /* Enable MUX to use Cursor values from these registers */ ++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; ++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; ++ ++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); ++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 bias_en, drvr_en; ++ ++ if (qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V3_TX_TX_DRV_LVL, ++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) ++ return; ++ ++ if (dp_opts->lanes == 1) { ++ bias_en = 0x3e; ++ drvr_en = 0x13; ++ } else { ++ bias_en = 0x3f; ++ drvr_en = 0x10; ++ } ++ ++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++} ++ ++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) ++{ ++ u32 val; ++ bool reverse = false; ++ ++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; ++ ++ /* ++ * TODO: Assume orientation is CC1 for now and two lanes, need to ++ * use type-c connector to understand orientation and lanes. ++ * ++ * Otherwise val changes to be like below if this code understood ++ * the orientation of the type-c cable. ++ * ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) ++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) ++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ * if (orientation == ORIENTATION_CC2) ++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); ++ */ ++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); ++ ++ return reverse; ++} ++ ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ ++ qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000); ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ /* Program default values before writing proper values */ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V4_TX_TX_DRV_LVL, ++ QSERDES_V4_TX_TX_EMP_POST1_LVL); ++} ++ ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en; ++ bool reverse; ++ ++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); ++ ++ reverse = qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ /* ++ * At least for 7nm DP PHY this has to be done after enabling link ++ * clock. ++ */ ++ ++ if (dp_opts->lanes == 1) { ++ bias0_en = reverse ? 0x3e : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3e; ++ drvr0_en = reverse ? 0x13 : 0x10; ++ drvr1_en = reverse ? 0x10 : 0x13; ++ } else if (dp_opts->lanes == 2) { ++ bias0_en = reverse ? 0x3f : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } else { ++ bias0_en = 0x3f; ++ bias1_en = 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } ++ ++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); ++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); ++ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ return 0; ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &opts->dp; ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); ++ if (qphy->dp_opts.set_voltages) { ++ cfg->configure_dp_tx(qphy); ++ qphy->dp_opts.set_voltages = 0; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_calibrate(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->calibrate_dp_phy) ++ return cfg->calibrate_dp_phy(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *dp_com = qmp->dp_com; ++ int ret, i; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (qmp->init_count++) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ /* turn on regulator supplies */ ++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); ++ if (ret) { ++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ++ goto err_unlock; ++ } ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ ret = reset_control_assert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset assert failed\n", ++ cfg->reset_list[i]); ++ goto err_disable_regulators; ++ } ++ } ++ ++ for (i = cfg->num_resets - 1; i >= 0; i--) { ++ ret = reset_control_deassert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset deassert failed\n", ++ qphy->cfg->reset_list[i]); ++ goto err_assert_reset; ++ } ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ goto err_assert_reset; ++ ++ if (cfg->has_phy_dp_com_ctrl) { ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, ++ SW_PWRDN); ++ /* override hardware control for reset of qmp phy */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ /* Default type-c orientation, i.e CC1 */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); ++ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, ++ USB3_MODE | DP_MODE); ++ ++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); ++ } ++ ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } else { ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) ++ qphy_setbits(pcs, ++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ else ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++ ++err_assert_reset: ++ while (++i < cfg->num_resets) ++ reset_control_assert(qmp->resets[i]); ++err_disable_regulators: ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++err_unlock: ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ int i = cfg->num_resets; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (--qmp->init_count) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ reset_control_assert(qmp->ufs_reset); ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], ++ SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } ++ ++ while (--i >= 0) ++ reset_control_assert(qmp->resets[i]); ++ ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_init(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret; ++ dev_vdbg(qmp->dev, "Initializing QMP phy\n"); ++ ++ if (cfg->no_pcs_sw_reset) { ++ /* ++ * Get UFS reset, which is delayed until now to avoid a ++ * circular dependency where UFS needs its PHY, but the PHY ++ * needs this UFS reset. ++ */ ++ if (!qmp->ufs_reset) { ++ qmp->ufs_reset = ++ devm_reset_control_get_exclusive(qmp->dev, ++ "ufsphy"); ++ ++ if (IS_ERR(qmp->ufs_reset)) { ++ ret = PTR_ERR(qmp->ufs_reset); ++ dev_err(qmp->dev, ++ "failed to get UFS reset: %d\n", ++ ret); ++ ++ qmp->ufs_reset = NULL; ++ return ret; ++ } ++ } ++ ++ ret = reset_control_assert(qmp->ufs_reset); ++ if (ret) ++ return ret; ++ } ++ ++ ret = qcom_qmp_phy_com_init(qphy); ++ if (ret) ++ return ret; ++ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->dp_aux_init(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_power_on(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *tx = qphy->tx; ++ void __iomem *rx = qphy->rx; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ void __iomem *status; ++ unsigned int mask, val, ready; ++ int ret; ++ ++ qcom_qmp_phy_serdes_init(qphy); ++ ++ if (cfg->has_lane_rst) { ++ ret = reset_control_deassert(qphy->lane_rst); ++ if (ret) { ++ dev_err(qmp->dev, "lane%d reset deassert failed\n", ++ qphy->index); ++ return ret; ++ } ++ } ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); ++ goto err_reset_lane; ++ } ++ ++ /* Tx, Rx, and PCS configurations */ ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 1); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 1); ++ ++ /* Configuration for other LANE for USB-DP combo PHY */ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 2); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 2); ++ } ++ ++ /* Configure special DP tx tunings */ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->configure_dp_tx(qphy); ++ ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 1); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); ++ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 2); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl_sec, ++ cfg->rx_tbl_num_sec, 2); ++ } ++ ++ /* Configure link rate, swing, etc. */ ++ if (cfg->type == PHY_TYPE_DP) { ++ cfg->configure_dp_phy(qphy); ++ } else { ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); ++ } ++ ++ ret = reset_control_deassert(qmp->ufs_reset); ++ if (ret) ++ goto err_disable_pipe_clk; ++ ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ cfg->pcs_misc_tbl_num); ++ if (cfg->pcs_misc_tbl_sec) ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ cfg->pcs_misc_tbl_num_sec); ++ ++ /* ++ * Pull out PHY from POWER DOWN state. ++ * This is active low enable signal to power-down PHY. ++ */ ++ if(cfg->type == PHY_TYPE_PCIE) ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); ++ ++ if (cfg->has_pwrdn_delay) ++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); ++ ++ if (cfg->type != PHY_TYPE_DP) { ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ if (cfg->type == PHY_TYPE_UFS) { ++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; ++ mask = PCS_READY; ++ ready = PCS_READY; ++ } else { ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ } ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; ++ } ++ } ++ return 0; ++ ++err_disable_pipe_clk: ++ clk_disable_unprepare(qphy->pipe_clk); ++err_reset_lane: ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_power_off(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ /* Assert DP PHY power down */ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ } else { ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_exit(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ qcom_qmp_phy_com_exit(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_enable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_init(phy); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_power_on(phy); ++ if (ret) ++ qcom_qmp_phy_exit(phy); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_disable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_power_off(phy); ++ if (ret) ++ return ret; ++ return qcom_qmp_phy_exit(phy); ++} ++ ++static int qcom_qmp_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ ++ qphy->mode = mode; ++ ++ return 0; ++} ++ ++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ u32 intr_mask; ++ ++ if (qphy->mode == PHY_MODE_USB_HOST_SS || ++ qphy->mode == PHY_MODE_USB_DEVICE_SS) ++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; ++ else ++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ++ ++ /* Clear any pending interrupts status */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); ++ ++ /* Enable required PHY autonomous mode interrupts */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); ++ ++ /* Enable i/o clamp_n for autonomous mode */ ++ if (pcs_misc) ++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++} ++ ++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ ++ /* Disable i/o clamp_n on resume for normal mode */ ++ if (pcs_misc) ++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); ++ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ qcom_qmp_phy_enable_autonomous_mode(qphy); ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret = 0; ++ ++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ return ret; ++ } ++ ++ qcom_qmp_phy_disable_autonomous_mode(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_vregs; ++ int i; ++ ++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); ++ if (!qmp->vregs) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->vregs[i].supply = cfg->vreg_list[i]; ++ ++ return devm_regulator_bulk_get(dev, num, qmp->vregs); ++} ++ ++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int i; ++ ++ qmp->resets = devm_kcalloc(dev, cfg->num_resets, ++ sizeof(*qmp->resets), GFP_KERNEL); ++ if (!qmp->resets) ++ return -ENOMEM; ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ struct reset_control *rst; ++ const char *name = cfg->reset_list[i]; ++ ++ rst = devm_reset_control_get_exclusive(dev, name); ++ if (IS_ERR(rst)) { ++ dev_err(dev, "failed to get %s reset\n", name); ++ return PTR_ERR(rst); ++ } ++ qmp->resets[i] = rst; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_clks; ++ int i; ++ ++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); ++ if (!qmp->clks) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->clks[i].id = cfg->clk_list[i]; ++ ++ return devm_clk_bulk_get(dev, num, qmp->clks); ++} ++ ++static void phy_clk_release_provider(void *res) ++{ ++ of_clk_del_provider(res); ++} ++ ++/* ++ * Register a fixed rate pipe clock. ++ * ++ * The _pipe_clksrc generated by PHY goes to the GCC that gate ++ * controls it. The _pipe_clk coming out of the GCC is requested ++ * by the PHY driver for its operations. ++ * We register the _pipe_clksrc here. The gcc driver takes care ++ * of assigning this _pipe_clksrc as parent to _pipe_clk. ++ * Below picture shows this relationship. ++ * ++ * +---------------+ ++ * | PHY block |<<---------------------------------------+ ++ * | | | ++ * | +-------+ | +-----+ | ++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ ++ * clk | +-------+ | +-----+ ++ * +---------------+ ++ */ ++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) ++{ ++ struct clk_fixed_rate *fixed; ++ struct clk_init_data init = { }; ++ int ret; ++ ++ ret = of_property_read_string(np, "clock-output-names", &init.name); ++ if (ret) { ++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); ++ return ret; ++ } ++ ++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); ++ if (!fixed) ++ return -ENOMEM; ++ ++ init.ops = &clk_fixed_rate_ops; ++ ++ /* controllers using QMP phys use 125MHz pipe clock interface */ ++ fixed->fixed_rate = 125000000; ++ fixed->hw.init = &init; ++ ++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++/* ++ * Display Port PLL driver block diagram for branch clocks ++ * ++ * +------------------------------+ ++ * | DP_VCO_CLK | ++ * | | ++ * | +-------------------+ | ++ * | | (DP PLL/VCO) | | ++ * | +---------+---------+ | ++ * | v | ++ * | +----------+-----------+ | ++ * | | hsclk_divsel_clk_src | | ++ * | +----------+-----------+ | ++ * +------------------------------+ ++ * | ++ * +---------<---------v------------>----------+ ++ * | | ++ * +--------v----------------+ | ++ * | dp_phy_pll_link_clk | | ++ * | link_clk | | ++ * +--------+----------------+ | ++ * | | ++ * | | ++ * v v ++ * Input to DISPCC block | ++ * for link clk, crypto clk | ++ * and interface clock | ++ * | ++ * | ++ * +--------<------------+-----------------+---<---+ ++ * | | | ++ * +----v---------+ +--------v-----+ +--------v------+ ++ * | vco_divided | | vco_divided | | vco_divided | ++ * | _clk_src | | _clk_src | | _clk_src | ++ * | | | | | | ++ * |divsel_six | | divsel_two | | divsel_four | ++ * +-------+------+ +-----+--------+ +--------+------+ ++ * | | | ++ * v---->----------v-------------<------v ++ * | ++ * +----------+-----------------+ ++ * | dp_phy_pll_vco_div_clk | ++ * +---------+------------------+ ++ * | ++ * v ++ * Input to DISPCC block ++ * for DP pixel clock ++ * ++ */ ++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 1620000000UL / 2: ++ case 2700000000UL / 2: ++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ return 1620000000UL / 2; ++ case 2700: ++ return 2700000000UL / 2; ++ case 5400: ++ return 5400000000UL / 4; ++ case 8100: ++ return 8100000000UL / 6; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { ++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, ++}; ++ ++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 162000000: ++ case 270000000: ++ case 540000000: ++ case 810000000: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ return dp_opts->link_rate * 100000; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_link_clk_ops = { ++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, ++}; ++ ++static struct clk_hw * ++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct qmp_phy_dp_clks *dp_clks = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx >= 2) { ++ pr_err("%s: invalid index %u\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (idx == 0) ++ return &dp_clks->dp_link_hw; ++ ++ return &dp_clks->dp_pixel_hw; ++} ++ ++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, ++ struct device_node *np) ++{ ++ struct clk_init_data init = { }; ++ struct qmp_phy_dp_clks *dp_clks; ++ char name[64]; ++ int ret; ++ ++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); ++ if (!dp_clks) ++ return -ENOMEM; ++ ++ dp_clks->qphy = qphy; ++ qphy->dp_clks = dp_clks; ++ ++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_link_clk_ops; ++ init.name = name; ++ dp_clks->dp_link_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); ++ if (ret) ++ return ret; ++ ++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_pixel_clk_ops; ++ init.name = name; ++ dp_clks->dp_pixel_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++static const struct phy_ops qcom_qmp_phy_gen_ops = { ++ .init = qcom_qmp_phy_enable, ++ .exit = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_phy_dp_ops = { ++ .init = qcom_qmp_phy_init, ++ .configure = qcom_qmp_dp_phy_configure, ++ .power_on = qcom_qmp_phy_power_on, ++ .calibrate = qcom_qmp_dp_phy_calibrate, ++ .power_off = qcom_qmp_phy_power_off, ++ .exit = qcom_qmp_phy_exit, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_pcie_ufs_ops = { ++ .power_on = qcom_qmp_phy_enable, ++ .power_off = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static void qcom_qmp_reset_control_put(void *data) ++{ ++ reset_control_put(data); ++} ++ ++static ++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++ void __iomem *serdes, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct phy *generic_phy; ++ struct qmp_phy *qphy; ++ const struct phy_ops *ops; ++ char prop_name[MAX_PROP_NAME]; ++ int ret; ++ ++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); ++ if (!qphy) ++ return -ENOMEM; ++ ++ qphy->cfg = cfg; ++ qphy->serdes = serdes; ++ /* ++ * Get memory resources for each phy lane: ++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. ++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 ++ * For single lane PHYs: pcs_misc (optional) -> 3. ++ */ ++ qphy->tx = of_iomap(np, 0); ++ if (!qphy->tx) ++ return -ENOMEM; ++ ++ qphy->rx = of_iomap(np, 1); ++ if (!qphy->rx) ++ return -ENOMEM; ++ ++ qphy->pcs = of_iomap(np, 2); ++ if (!qphy->pcs) ++ return -ENOMEM; ++ ++ /* ++ * If this is a dual-lane PHY, then there should be registers for the ++ * second lane. Some old device trees did not specify this, so fall ++ * back to old legacy behavior of assuming they can be reached at an ++ * offset from the first lane. ++ */ ++ if (cfg->is_dual_lane_phy) { ++ qphy->tx2 = of_iomap(np, 3); ++ qphy->rx2 = of_iomap(np, 4); ++ if (!qphy->tx2 || !qphy->rx2) { ++ dev_warn(dev, ++ "Underspecified device tree, falling back to legacy register regions\n"); ++ ++ /* In the old version, pcs_misc is at index 3. */ ++ qphy->pcs_misc = qphy->tx2; ++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; ++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 5); ++ } ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 3); ++ } ++ ++ if (!qphy->pcs_misc) ++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ ++ /* ++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 ++ * based phys, so they essentially have pipe clock. So, ++ * we return error in case phy is USB3 or PIPE type. ++ * Otherwise, we initialize pipe clock to NULL for ++ * all phys that don't need this. ++ */ ++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id); ++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); ++ if (IS_ERR(qphy->pipe_clk)) { ++ if (cfg->type == PHY_TYPE_PCIE || ++ cfg->type == PHY_TYPE_USB3) { ++ ret = PTR_ERR(qphy->pipe_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, ++ "failed to get lane%d pipe_clk, %d\n", ++ id, ret); ++ return ret; ++ } ++ qphy->pipe_clk = NULL; ++ } ++ ++ /* Get lane reset, if any */ ++ if (cfg->has_lane_rst) { ++ snprintf(prop_name, sizeof(prop_name), "lane%d", id); ++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); ++ if (IS_ERR(qphy->lane_rst)) { ++ dev_err(dev, "failed to get lane%d reset\n", id); ++ return PTR_ERR(qphy->lane_rst); ++ } ++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, ++ qphy->lane_rst); ++ if (ret) ++ return ret; ++ } ++ ++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ++ ops = &qcom_qmp_pcie_ufs_ops; ++ else if (cfg->type == PHY_TYPE_DP) ++ ops = &qcom_qmp_phy_dp_ops; ++ else ++ ops = &qcom_qmp_phy_gen_ops; ++ ++ generic_phy = devm_phy_create(dev, np, ops); ++ if (IS_ERR(generic_phy)) { ++ ret = PTR_ERR(generic_phy); ++ dev_err(dev, "failed to create qphy %d\n", ret); ++ return ret; ++ } ++ ++ qphy->phy = generic_phy; ++ qphy->index = id; ++ qphy->qmp = qmp; ++ qmp->phys[id] = qphy; ++ phy_set_drvdata(generic_phy, qphy); ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,ipq8074-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-pcie-phy", ++ .data = &msm8996_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-ufs-phy", ++ .data = &msm8996_ufs_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-usb3-phy", ++ .data = &msm8996_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-pcie-phy", ++ .data = &msm8998_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-phy", ++ .data = &ipq8074_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-pcie-phy", ++ .data = &ipq6018_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-phy", ++ .data = &sc7180_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sc8180x-qmp-pcie-phy", ++ .data = &sc8180x_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8280xp-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sdm845-qhp-pcie-phy", ++ .data = &sdm845_qhp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-pcie-phy", ++ .data = &sdm845_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-phy", ++ .data = &qmp_v3_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy", ++ .data = &qmp_v3_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-usb3-phy", ++ .data = &msm8998_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm6115-qmp-ufs-phy", ++ .data = &sm6115_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm6350-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy", ++ .data = &sm8150_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-phy", ++ .data = &sm8250_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy", ++ .data = &sm8250_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", ++ .data = &sm8250_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-pcie-phy", ++ .data = &sdx55_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy", ++ .data = &sdx55_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy", ++ .data = &sdx65_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy", ++ .data = &sm8350_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", ++ .data = &sm8450_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", ++ .data = &sm8450_qmp_gen4x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-ufs-phy", ++ .data = &sm8450_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,qcm2290-qmp-usb3-phy", ++ .data = &qcm2290_usb3phy_cfg, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++ ++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ .data = &sc7180_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ .data = &sm8250_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ .data = &sc8180x_usb3dpphy_cfg, ++ }, ++ { } ++}; ++ ++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, ++ qcom_qmp_phy_runtime_resume, NULL) ++}; ++ ++static int qcom_qmp_phy_probe(struct platform_device *pdev) ++{ ++ struct qcom_qmp *qmp; ++ struct device *dev = &pdev->dev; ++ struct device_node *child; ++ struct phy_provider *phy_provider; ++ void __iomem *serdes; ++ void __iomem *usb_serdes; ++ void __iomem *dp_serdes = NULL; ++ const struct qmp_phy_combo_cfg *combo_cfg = NULL; ++ const struct qmp_phy_cfg *cfg = NULL; ++ const struct qmp_phy_cfg *usb_cfg = NULL; ++ const struct qmp_phy_cfg *dp_cfg = NULL; ++ int num, id, expected_phys; ++ int ret; ++ ++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); ++ if (!qmp) ++ return -ENOMEM; ++ ++ qmp->dev = dev; ++ dev_set_drvdata(dev, qmp); ++ ++ /* Get the specific init parameters of QMP phy */ ++ cfg = of_device_get_match_data(dev); ++ if (!cfg) { ++ const struct of_device_id *match; ++ ++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); ++ if (!match) ++ return -EINVAL; ++ ++ combo_cfg = match->data; ++ if (!combo_cfg) ++ return -EINVAL; ++ ++ usb_cfg = combo_cfg->usb_cfg; ++ cfg = usb_cfg; /* Setup clks and regulators */ ++ } ++ ++ /* per PHY serdes; usually located at base address */ ++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(serdes)) ++ return PTR_ERR(serdes); ++ ++ /* per PHY dp_com; if PHY has dp_com control block */ ++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(qmp->dp_com)) ++ return PTR_ERR(qmp->dp_com); ++ } ++ ++ if (combo_cfg) { ++ /* Only two serdes for combo PHY */ ++ dp_serdes = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(dp_serdes)) ++ return PTR_ERR(dp_serdes); ++ ++ dp_cfg = combo_cfg->dp_cfg; ++ expected_phys = 2; ++ } else { ++ expected_phys = cfg->nlanes; ++ } ++ ++ mutex_init(&qmp->phy_mutex); ++ ++ ret = qcom_qmp_phy_clk_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_reset_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to get regulator supplies: %d\n", ++ ret); ++ return ret; ++ } ++ ++ num = of_get_available_child_count(dev->of_node); ++ /* do we have a rogue child node ? */ ++ if (num > expected_phys) ++ return -EINVAL; ++ ++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); ++ if (!qmp->phys) ++ return -ENOMEM; ++ ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ /* ++ * Prevent runtime pm from being ON by default. Users can enable ++ * it using power/control in sysfs. ++ */ ++ pm_runtime_forbid(dev); ++ ++ id = 0; ++ for_each_available_child_of_node(dev->of_node, child) { ++ if (of_node_name_eq(child, "dp-phy")) { ++ cfg = dp_cfg; ++ serdes = dp_serdes; ++ } else if (of_node_name_eq(child, "usb3-phy")) { ++ cfg = usb_cfg; ++ serdes = usb_serdes; ++ } ++ ++ /* Create per-lane phy */ ++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ if (ret) { ++ dev_err(dev, "failed to create lane%d phy, %d\n", ++ id, ret); ++ goto err_node_put; ++ } ++ ++ /* ++ * Register the pipe clock provided by phy. ++ * See function description to see details of this pipe clock. ++ */ ++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; ++ } ++ } else if (cfg->type == PHY_TYPE_DP) { ++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register DP clock source\n"); ++ goto err_node_put; ++ } ++ } ++ id++; ++ } ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (!IS_ERR(phy_provider)) ++ dev_info(dev, "Registered Qcom-QMP phy\n"); ++ else ++ pm_runtime_disable(dev); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++ ++err_node_put: ++ pm_runtime_disable(dev); ++ of_node_put(child); ++ return ret; ++} ++ ++static struct platform_driver qcom_qmp_phy_driver = { ++ .probe = qcom_qmp_phy_probe, ++ .driver = { ++ .name = "qcom-qmp-phy", ++ .pm = &qcom_qmp_phy_pm_ops, ++ .of_match_table = qcom_qmp_phy_of_match_table, ++ }, ++}; ++ ++module_platform_driver(qcom_qmp_phy_driver); ++ ++MODULE_AUTHOR("Vivek Gautam "); ++MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +new file mode 100644 +index 000000000000..c7309e981bfb +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +@@ -0,0 +1,6350 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-qcom-qmp.h" ++ ++/* QPHY_SW_RESET bit */ ++#define SW_RESET BIT(0) ++/* QPHY_POWER_DOWN_CONTROL */ ++#define SW_PWRDN BIT(0) ++#define REFCLK_DRV_DSBL BIT(1) ++/* QPHY_START_CONTROL bits */ ++#define SERDES_START BIT(0) ++#define PCS_START BIT(1) ++#define PLL_READY_GATE_EN BIT(3) ++/* QPHY_PCS_STATUS bit */ ++#define PHYSTATUS BIT(6) ++#define PHYSTATUS_4_20 BIT(7) ++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ ++#define PCS_READY BIT(0) ++ ++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ ++/* DP PHY soft reset */ ++#define SW_DPPHY_RESET BIT(0) ++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ ++#define SW_DPPHY_RESET_MUX BIT(1) ++/* USB3 PHY soft reset */ ++#define SW_USB3PHY_RESET BIT(2) ++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ ++#define SW_USB3PHY_RESET_MUX BIT(3) ++ ++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ ++#define USB3_MODE BIT(0) /* enables USB3 mode */ ++#define DP_MODE BIT(1) /* enables DP mode */ ++ ++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ ++#define ARCVR_DTCT_EN BIT(0) ++#define ALFPS_DTCT_EN BIT(1) ++#define ARCVR_DTCT_EVENT_SEL BIT(4) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ ++#define IRQ_CLEAR BIT(0) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ ++#define RCVR_DETECT BIT(0) ++ ++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ ++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ ++ ++#define PHY_INIT_COMPLETE_TIMEOUT 10000 ++#define POWER_DOWN_DELAY_US_MIN 10 ++#define POWER_DOWN_DELAY_US_MAX 11 ++ ++#define MAX_PROP_NAME 32 ++ ++/* Define the assumed distance between lanes for underspecified device trees. */ ++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 ++ ++struct qmp_phy_init_tbl { ++ unsigned int offset; ++ unsigned int val; ++ /* ++ * register part of layout ? ++ * if yes, then offset gives index in the reg-layout ++ */ ++ bool in_layout; ++ /* ++ * mask of lanes for which this register is written ++ * for cases when second lane needs different values ++ */ ++ u8 lane_mask; ++}; ++ ++#define QMP_PHY_INIT_CFG(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_L(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .in_layout = true, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = l, \ ++ } ++ ++/* set of registers with offsets different per-PHY */ ++enum qphy_reg_layout { ++ /* Common block control registers */ ++ QPHY_COM_SW_RESET, ++ QPHY_COM_POWER_DOWN_CONTROL, ++ QPHY_COM_START_CONTROL, ++ QPHY_COM_PCS_READY_STATUS, ++ /* PCS registers */ ++ QPHY_PLL_LOCK_CHK_DLY_TIME, ++ QPHY_FLL_CNTRL1, ++ QPHY_FLL_CNTRL2, ++ QPHY_FLL_CNT_VAL_L, ++ QPHY_FLL_CNT_VAL_H_TOL, ++ QPHY_FLL_MAN_CODE, ++ QPHY_SW_RESET, ++ QPHY_START_CTRL, ++ QPHY_PCS_READY_STATUS, ++ QPHY_PCS_STATUS, ++ QPHY_PCS_AUTONOMOUS_MODE_CTRL, ++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, ++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, ++ QPHY_PCS_POWER_DOWN_CONTROL, ++ /* PCS_MISC registers */ ++ QPHY_PCS_MISC_TYPEC_CTRL, ++ /* Keep last to ensure regs_layout arrays are properly initialized */ ++ QPHY_LAYOUT_SIZE ++}; ++ ++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_COM_SW_RESET] = 0x400, ++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, ++ [QPHY_COM_START_CONTROL] = 0x408, ++ [QPHY_COM_PCS_READY_STATUS] = 0x448, ++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, ++ [QPHY_FLL_CNTRL1] = 0xc4, ++ [QPHY_FLL_CNTRL2] = 0xc8, ++ [QPHY_FLL_CNT_VAL_L] = 0xcc, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, ++ [QPHY_FLL_MAN_CODE] = 0xd4, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_FLL_CNTRL1] = 0xc0, ++ [QPHY_FLL_CNTRL2] = 0xc4, ++ [QPHY_FLL_CNT_VAL_L] = 0xc8, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, ++ [QPHY_FLL_MAN_CODE] = 0xd0, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x17c, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, ++}; ++ ++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, ++}; ++ ++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x2ac, ++}; ++ ++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, ++}; ++ ++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, ++}; ++ ++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, ++}; ++ ++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, ++}; ++ ++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x160, ++}; ++ ++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, ++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, ++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), ++ ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), ++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), ++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), ++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), ++}; ++ ++/* Register names should be validated, they might be different for this PHY */ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), ++}; ++ ++struct qmp_phy; ++ ++/* struct qmp_phy_cfg - per-PHY initialization config */ ++struct qmp_phy_cfg { ++ /* phy-type - PCIE/UFS/USB */ ++ unsigned int type; ++ /* number of lanes provided by phy */ ++ int nlanes; ++ ++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ ++ const struct qmp_phy_init_tbl *serdes_tbl; ++ int serdes_tbl_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_sec; ++ int serdes_tbl_num_sec; ++ const struct qmp_phy_init_tbl *tx_tbl; ++ int tx_tbl_num; ++ const struct qmp_phy_init_tbl *tx_tbl_sec; ++ int tx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *rx_tbl; ++ int rx_tbl_num; ++ const struct qmp_phy_init_tbl *rx_tbl_sec; ++ int rx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_tbl; ++ int pcs_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_tbl_sec; ++ int pcs_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl; ++ int pcs_misc_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; ++ int pcs_misc_tbl_num_sec; ++ ++ /* Init sequence for DP PHY block link rates */ ++ const struct qmp_phy_init_tbl *serdes_tbl_rbr; ++ int serdes_tbl_rbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr; ++ int serdes_tbl_hbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2; ++ int serdes_tbl_hbr2_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3; ++ int serdes_tbl_hbr3_num; ++ ++ /* DP PHY callbacks */ ++ int (*configure_dp_phy)(struct qmp_phy *qphy); ++ void (*configure_dp_tx)(struct qmp_phy *qphy); ++ int (*calibrate_dp_phy)(struct qmp_phy *qphy); ++ void (*dp_aux_init)(struct qmp_phy *qphy); ++ ++ /* clock ids to be requested */ ++ const char * const *clk_list; ++ int num_clks; ++ /* resets to be requested */ ++ const char * const *reset_list; ++ int num_resets; ++ /* regulators to be requested */ ++ const char * const *vreg_list; ++ int num_vregs; ++ ++ /* array of registers with different offsets */ ++ const unsigned int *regs; ++ ++ unsigned int start_ctrl; ++ unsigned int pwrdn_ctrl; ++ unsigned int mask_com_pcs_ready; ++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ ++ unsigned int phy_status; ++ ++ /* true, if PHY has a separate PHY_COM control block */ ++ bool has_phy_com_ctrl; ++ /* true, if PHY has a reset for individual lanes */ ++ bool has_lane_rst; ++ /* true, if PHY needs delay after POWER_DOWN */ ++ bool has_pwrdn_delay; ++ /* power_down delay in usec */ ++ int pwrdn_delay_min; ++ int pwrdn_delay_max; ++ ++ /* true, if PHY has a separate DP_COM control block */ ++ bool has_phy_dp_com_ctrl; ++ /* true, if PHY has secondary tx/rx lanes to be configured */ ++ bool is_dual_lane_phy; ++ ++ /* true, if PCS block has no separate SW_RESET register */ ++ bool no_pcs_sw_reset; ++}; ++ ++struct qmp_phy_combo_cfg { ++ const struct qmp_phy_cfg *usb_cfg; ++ const struct qmp_phy_cfg *dp_cfg; ++}; ++ ++/** ++ * struct qmp_phy - per-lane phy descriptor ++ * ++ * @phy: generic phy ++ * @cfg: phy specific configuration ++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL) ++ * @tx: iomapped memory space for lane's tx ++ * @rx: iomapped memory space for lane's rx ++ * @pcs: iomapped memory space for lane's pcs ++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) ++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) ++ * @pcs_misc: iomapped memory space for lane's pcs_misc ++ * @pipe_clk: pipe clock ++ * @index: lane index ++ * @qmp: QMP phy to which this lane belongs ++ * @lane_rst: lane's reset controller ++ * @mode: current PHY mode ++ * @dp_aux_cfg: Display port aux config ++ * @dp_opts: Display port optional config ++ * @dp_clks: Display port clocks ++ */ ++struct qmp_phy { ++ struct phy *phy; ++ const struct qmp_phy_cfg *cfg; ++ void __iomem *serdes; ++ void __iomem *tx; ++ void __iomem *rx; ++ void __iomem *pcs; ++ void __iomem *tx2; ++ void __iomem *rx2; ++ void __iomem *pcs_misc; ++ struct clk *pipe_clk; ++ unsigned int index; ++ struct qcom_qmp *qmp; ++ struct reset_control *lane_rst; ++ enum phy_mode mode; ++ unsigned int dp_aux_cfg; ++ struct phy_configure_opts_dp dp_opts; ++ struct qmp_phy_dp_clks *dp_clks; ++}; ++ ++struct qmp_phy_dp_clks { ++ struct qmp_phy *qphy; ++ struct clk_hw dp_link_hw; ++ struct clk_hw dp_pixel_hw; ++}; ++ ++/** ++ * struct qcom_qmp - structure holding QMP phy block attributes ++ * ++ * @dev: device ++ * @dp_com: iomapped memory space for phy's dp_com control block ++ * ++ * @clks: array of clocks required by phy ++ * @resets: array of resets required by phy ++ * @vregs: regulator supplies bulk data ++ * ++ * @phys: array of per-lane phy descriptors ++ * @phy_mutex: mutex lock for PHY common block initialization ++ * @init_count: phy common block initialization count ++ * @ufs_reset: optional UFS PHY reset handle ++ */ ++struct qcom_qmp { ++ struct device *dev; ++ void __iomem *dp_com; ++ ++ struct clk_bulk_data *clks; ++ struct reset_control **resets; ++ struct regulator_bulk_data *vregs; ++ ++ struct qmp_phy **phys; ++ ++ struct mutex phy_mutex; ++ int init_count; ++ ++ struct reset_control *ufs_reset; ++}; ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg |= val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg &= ~val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++/* list of clocks required by phy */ ++static const char * const msm8996_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", ++}; ++ ++static const char * const msm8996_ufs_phy_clk_l[] = { ++ "ref", ++}; ++ ++static const char * const qmp_v3_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "com_aux", ++}; ++ ++static const char * const sdm845_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "refgen", ++}; ++ ++static const char * const qmp_v4_phy_clk_l[] = { ++ "aux", "ref_clk_src", "ref", "com_aux", ++}; ++ ++/* the primary usb3 phy on sm8250 doesn't have a ref clock */ ++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { ++ "aux", "ref_clk_src", "com_aux" ++}; ++ ++static const char * const sm8450_ufs_phy_clk_l[] = { ++ "qref", "ref", "ref_aux", ++}; ++ ++static const char * const sdm845_ufs_phy_clk_l[] = { ++ "ref", "ref_aux", ++}; ++ ++/* usb3 phy on sdx55 doesn't have com_aux clock */ ++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { ++ "aux", "cfg_ahb", "ref" ++}; ++ ++static const char * const qcm2290_usb3phy_clk_l[] = { ++ "cfg_ahb", "ref", "com_aux", ++}; ++ ++/* list of resets */ ++static const char * const msm8996_pciephy_reset_l[] = { ++ "phy", "common", "cfg", ++}; ++ ++static const char * const msm8996_usb3phy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const char * const sc7180_usb3phy_reset_l[] = { ++ "phy", ++}; ++ ++static const char * const qcm2290_usb3phy_reset_l[] = { ++ "phy_phy", "phy", ++}; ++ ++static const char * const sdm845_pciephy_reset_l[] = { ++ "phy", ++}; ++ ++/* list of regulators */ ++static const char * const qmp_phy_vreg_l[] = { ++ "vdda-phy", "vdda-pll", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = ipq8074_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), ++ .pcs_tbl = ipq8074_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 3, ++ ++ .serdes_tbl = msm8996_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), ++ .tx_tbl = msm8996_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), ++ .rx_tbl = msm8996_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), ++ .pcs_tbl = msm8996_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | PLL_READY_GATE_EN, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .mask_com_pcs_ready = PCS_READY, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = true, ++ .has_lane_rst = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg msm8996_ufs_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_ufs_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), ++ .tx_tbl = msm8996_ufs_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), ++ .rx_tbl = msm8996_ufs_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), ++ ++ .clk_list = msm8996_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), ++ ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ ++ .regs = msm8996_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = msm8996_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), ++ .pcs_tbl = msm8996_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const char * const ipq8074_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", ++}; ++/* list of resets */ ++static const char * const ipq8074_pciephy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), ++ .rx_tbl = ipq8074_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq6018_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), ++ .tx_tbl = ipq6018_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), ++ .rx_tbl = ipq6018_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), ++ .pcs_tbl = ipq6018_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = ipq_pciephy_gen3_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qmp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qhp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qhp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qhp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, ++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), ++ .tx_tbl = qmp_v3_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { ++ .usb_cfg = &sc7180_usb3phy_cfg, ++ .dp_cfg = &sc7180_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdm845_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), ++ .tx_tbl = sdm845_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), ++ .rx_tbl = sdm845_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), ++ .pcs_tbl = sdm845_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm6115_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), ++ .tx_tbl = sm6115_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), ++ .rx_tbl = sm6115_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), ++ .pcs_tbl = sm6115_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm6115_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ ++ .is_dual_lane_phy = false, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8998_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), ++ .tx_tbl = msm8998_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), ++ .rx_tbl = msm8998_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), ++ .pcs_tbl = msm8998_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), ++ .tx_tbl = msm8998_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), ++ .rx_tbl = msm8998_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), ++ .pcs_tbl = msm8998_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8150_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), ++ .tx_tbl = sm8150_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), ++ .rx_tbl = sm8150_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), ++ .pcs_tbl = sm8150_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8150_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), ++ .rx_tbl = sm8150_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), ++ .pcs_tbl = sm8150_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), ++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), ++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), ++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { ++ .usb_cfg = &sm8150_usb3phy_cfg, ++ .dp_cfg = &sc8180x_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8250_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), ++ .rx_tbl = sm8250_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), ++ .pcs_tbl = sm8250_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { ++ .usb_cfg = &sm8250_usb3phy_cfg, ++ .dp_cfg = &sm8250_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdx55_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), ++ .rx_tbl = sdx55_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8350_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), ++ .rx_tbl = sm8350_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), ++ .pcs_tbl = sm8350_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sm8450_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qcm2290_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), ++ .tx_tbl = qcm2290_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), ++ .rx_tbl = qcm2290_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), ++ .pcs_tbl = qcm2290_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), ++ .clk_list = qcm2290_usb3phy_clk_l, ++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), ++ .reset_list = qcm2290_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qcm2290_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static void qcom_qmp_phy_configure_lane(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num, ++ u8 lane_mask) ++{ ++ int i; ++ const struct qmp_phy_init_tbl *t = tbl; ++ ++ if (!t) ++ return; ++ ++ for (i = 0; i < num; i++, t++) { ++ if (!(t->lane_mask & lane_mask)) ++ continue; ++ ++ if (t->in_layout) ++ writel(t->val, base + regs[t->offset]); ++ else ++ writel(t->val, base + t->offset); ++ } ++} ++ ++static void qcom_qmp_phy_configure(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num) ++{ ++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++} ++ ++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; ++ int serdes_tbl_num = cfg->serdes_tbl_num; ++ int ret; ++ ++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ if (cfg->serdes_tbl_sec) ++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ cfg->serdes_tbl_num_sec); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ switch (dp_opts->link_rate) { ++ case 1620: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_rbr, ++ cfg->serdes_tbl_rbr_num); ++ break; ++ case 2700: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr, ++ cfg->serdes_tbl_hbr_num); ++ break; ++ case 5400: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr2, ++ cfg->serdes_tbl_hbr2_num); ++ break; ++ case 8100: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr3, ++ cfg->serdes_tbl_hbr3_num); ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ } ++ ++ ++ if (cfg->has_phy_com_ctrl) { ++ void __iomem *status; ++ unsigned int mask, val; ++ ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ ++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; ++ mask = cfg->mask_com_pcs_ready; ++ ++ ret = readl_poll_timeout(status, val, (val & mask), 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, ++ "phy common block init timed-out\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_LANE_0_1_PWRDN | ++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | ++ DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(QSERDES_V3_COM_BIAS_EN | ++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | ++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { ++ { 0x00, 0x0c, 0x15, 0x1a }, ++ { 0x02, 0x0e, 0x16, 0xff }, ++ { 0x02, 0x11, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { ++ { 0x02, 0x12, 0x16, 0x1a }, ++ { 0x09, 0x19, 0x1f, 0xff }, ++ { 0x10, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { ++ { 0x00, 0x0c, 0x14, 0x19 }, ++ { 0x00, 0x0b, 0x12, 0xff }, ++ { 0x00, 0x0b, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { ++ { 0x08, 0x0f, 0x16, 0x1f }, ++ { 0x11, 0x1e, 0x1f, 0xff }, ++ { 0x19, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, ++ unsigned int drv_lvl_reg, unsigned int emp_post_reg) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ unsigned int v_level = 0, p_level = 0; ++ u8 voltage_swing_cfg, pre_emphasis_cfg; ++ int i; ++ ++ for (i = 0; i < dp_opts->lanes; i++) { ++ v_level = max(v_level, dp_opts->voltage[i]); ++ p_level = max(p_level, dp_opts->pre[i]); ++ } ++ ++ if (dp_opts->link_rate <= 2700) { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; ++ } else { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; ++ } ++ ++ /* TODO: Move check to config check */ ++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) ++ return -EINVAL; ++ ++ /* Enable MUX to use Cursor values from these registers */ ++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; ++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; ++ ++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); ++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 bias_en, drvr_en; ++ ++ if (qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V3_TX_TX_DRV_LVL, ++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) ++ return; ++ ++ if (dp_opts->lanes == 1) { ++ bias_en = 0x3e; ++ drvr_en = 0x13; ++ } else { ++ bias_en = 0x3f; ++ drvr_en = 0x10; ++ } ++ ++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++} ++ ++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) ++{ ++ u32 val; ++ bool reverse = false; ++ ++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; ++ ++ /* ++ * TODO: Assume orientation is CC1 for now and two lanes, need to ++ * use type-c connector to understand orientation and lanes. ++ * ++ * Otherwise val changes to be like below if this code understood ++ * the orientation of the type-c cable. ++ * ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) ++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) ++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ * if (orientation == ORIENTATION_CC2) ++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); ++ */ ++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); ++ ++ return reverse; ++} ++ ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ ++ qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000); ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ /* Program default values before writing proper values */ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V4_TX_TX_DRV_LVL, ++ QSERDES_V4_TX_TX_EMP_POST1_LVL); ++} ++ ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en; ++ bool reverse; ++ ++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); ++ ++ reverse = qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ /* ++ * At least for 7nm DP PHY this has to be done after enabling link ++ * clock. ++ */ ++ ++ if (dp_opts->lanes == 1) { ++ bias0_en = reverse ? 0x3e : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3e; ++ drvr0_en = reverse ? 0x13 : 0x10; ++ drvr1_en = reverse ? 0x10 : 0x13; ++ } else if (dp_opts->lanes == 2) { ++ bias0_en = reverse ? 0x3f : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } else { ++ bias0_en = 0x3f; ++ bias1_en = 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } ++ ++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); ++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); ++ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ return 0; ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &opts->dp; ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); ++ if (qphy->dp_opts.set_voltages) { ++ cfg->configure_dp_tx(qphy); ++ qphy->dp_opts.set_voltages = 0; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_calibrate(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->calibrate_dp_phy) ++ return cfg->calibrate_dp_phy(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *dp_com = qmp->dp_com; ++ int ret, i; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (qmp->init_count++) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ /* turn on regulator supplies */ ++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); ++ if (ret) { ++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ++ goto err_unlock; ++ } ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ ret = reset_control_assert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset assert failed\n", ++ cfg->reset_list[i]); ++ goto err_disable_regulators; ++ } ++ } ++ ++ for (i = cfg->num_resets - 1; i >= 0; i--) { ++ ret = reset_control_deassert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset deassert failed\n", ++ qphy->cfg->reset_list[i]); ++ goto err_assert_reset; ++ } ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ goto err_assert_reset; ++ ++ if (cfg->has_phy_dp_com_ctrl) { ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, ++ SW_PWRDN); ++ /* override hardware control for reset of qmp phy */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ /* Default type-c orientation, i.e CC1 */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); ++ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, ++ USB3_MODE | DP_MODE); ++ ++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); ++ } ++ ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } else { ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) ++ qphy_setbits(pcs, ++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ else ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++ ++err_assert_reset: ++ while (++i < cfg->num_resets) ++ reset_control_assert(qmp->resets[i]); ++err_disable_regulators: ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++err_unlock: ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ int i = cfg->num_resets; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (--qmp->init_count) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ reset_control_assert(qmp->ufs_reset); ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], ++ SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } ++ ++ while (--i >= 0) ++ reset_control_assert(qmp->resets[i]); ++ ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_init(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret; ++ dev_vdbg(qmp->dev, "Initializing QMP phy\n"); ++ ++ if (cfg->no_pcs_sw_reset) { ++ /* ++ * Get UFS reset, which is delayed until now to avoid a ++ * circular dependency where UFS needs its PHY, but the PHY ++ * needs this UFS reset. ++ */ ++ if (!qmp->ufs_reset) { ++ qmp->ufs_reset = ++ devm_reset_control_get_exclusive(qmp->dev, ++ "ufsphy"); ++ ++ if (IS_ERR(qmp->ufs_reset)) { ++ ret = PTR_ERR(qmp->ufs_reset); ++ dev_err(qmp->dev, ++ "failed to get UFS reset: %d\n", ++ ret); ++ ++ qmp->ufs_reset = NULL; ++ return ret; ++ } ++ } ++ ++ ret = reset_control_assert(qmp->ufs_reset); ++ if (ret) ++ return ret; ++ } ++ ++ ret = qcom_qmp_phy_com_init(qphy); ++ if (ret) ++ return ret; ++ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->dp_aux_init(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_power_on(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *tx = qphy->tx; ++ void __iomem *rx = qphy->rx; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ void __iomem *status; ++ unsigned int mask, val, ready; ++ int ret; ++ ++ qcom_qmp_phy_serdes_init(qphy); ++ ++ if (cfg->has_lane_rst) { ++ ret = reset_control_deassert(qphy->lane_rst); ++ if (ret) { ++ dev_err(qmp->dev, "lane%d reset deassert failed\n", ++ qphy->index); ++ return ret; ++ } ++ } ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); ++ goto err_reset_lane; ++ } ++ ++ /* Tx, Rx, and PCS configurations */ ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 1); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 1); ++ ++ /* Configuration for other LANE for USB-DP combo PHY */ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 2); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 2); ++ } ++ ++ /* Configure special DP tx tunings */ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->configure_dp_tx(qphy); ++ ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 1); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); ++ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 2); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl_sec, ++ cfg->rx_tbl_num_sec, 2); ++ } ++ ++ /* Configure link rate, swing, etc. */ ++ if (cfg->type == PHY_TYPE_DP) { ++ cfg->configure_dp_phy(qphy); ++ } else { ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); ++ } ++ ++ ret = reset_control_deassert(qmp->ufs_reset); ++ if (ret) ++ goto err_disable_pipe_clk; ++ ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ cfg->pcs_misc_tbl_num); ++ if (cfg->pcs_misc_tbl_sec) ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ cfg->pcs_misc_tbl_num_sec); ++ ++ /* ++ * Pull out PHY from POWER DOWN state. ++ * This is active low enable signal to power-down PHY. ++ */ ++ if(cfg->type == PHY_TYPE_PCIE) ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); ++ ++ if (cfg->has_pwrdn_delay) ++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); ++ ++ if (cfg->type != PHY_TYPE_DP) { ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ if (cfg->type == PHY_TYPE_UFS) { ++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; ++ mask = PCS_READY; ++ ready = PCS_READY; ++ } else { ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ } ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; ++ } ++ } ++ return 0; ++ ++err_disable_pipe_clk: ++ clk_disable_unprepare(qphy->pipe_clk); ++err_reset_lane: ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_power_off(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ /* Assert DP PHY power down */ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ } else { ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_exit(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ qcom_qmp_phy_com_exit(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_enable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_init(phy); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_power_on(phy); ++ if (ret) ++ qcom_qmp_phy_exit(phy); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_disable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_power_off(phy); ++ if (ret) ++ return ret; ++ return qcom_qmp_phy_exit(phy); ++} ++ ++static int qcom_qmp_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ ++ qphy->mode = mode; ++ ++ return 0; ++} ++ ++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ u32 intr_mask; ++ ++ if (qphy->mode == PHY_MODE_USB_HOST_SS || ++ qphy->mode == PHY_MODE_USB_DEVICE_SS) ++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; ++ else ++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ++ ++ /* Clear any pending interrupts status */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); ++ ++ /* Enable required PHY autonomous mode interrupts */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); ++ ++ /* Enable i/o clamp_n for autonomous mode */ ++ if (pcs_misc) ++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++} ++ ++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ ++ /* Disable i/o clamp_n on resume for normal mode */ ++ if (pcs_misc) ++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); ++ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ qcom_qmp_phy_enable_autonomous_mode(qphy); ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret = 0; ++ ++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ return ret; ++ } ++ ++ qcom_qmp_phy_disable_autonomous_mode(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_vregs; ++ int i; ++ ++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); ++ if (!qmp->vregs) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->vregs[i].supply = cfg->vreg_list[i]; ++ ++ return devm_regulator_bulk_get(dev, num, qmp->vregs); ++} ++ ++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int i; ++ ++ qmp->resets = devm_kcalloc(dev, cfg->num_resets, ++ sizeof(*qmp->resets), GFP_KERNEL); ++ if (!qmp->resets) ++ return -ENOMEM; ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ struct reset_control *rst; ++ const char *name = cfg->reset_list[i]; ++ ++ rst = devm_reset_control_get_exclusive(dev, name); ++ if (IS_ERR(rst)) { ++ dev_err(dev, "failed to get %s reset\n", name); ++ return PTR_ERR(rst); ++ } ++ qmp->resets[i] = rst; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_clks; ++ int i; ++ ++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); ++ if (!qmp->clks) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->clks[i].id = cfg->clk_list[i]; ++ ++ return devm_clk_bulk_get(dev, num, qmp->clks); ++} ++ ++static void phy_clk_release_provider(void *res) ++{ ++ of_clk_del_provider(res); ++} ++ ++/* ++ * Register a fixed rate pipe clock. ++ * ++ * The _pipe_clksrc generated by PHY goes to the GCC that gate ++ * controls it. The _pipe_clk coming out of the GCC is requested ++ * by the PHY driver for its operations. ++ * We register the _pipe_clksrc here. The gcc driver takes care ++ * of assigning this _pipe_clksrc as parent to _pipe_clk. ++ * Below picture shows this relationship. ++ * ++ * +---------------+ ++ * | PHY block |<<---------------------------------------+ ++ * | | | ++ * | +-------+ | +-----+ | ++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ ++ * clk | +-------+ | +-----+ ++ * +---------------+ ++ */ ++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) ++{ ++ struct clk_fixed_rate *fixed; ++ struct clk_init_data init = { }; ++ int ret; ++ ++ ret = of_property_read_string(np, "clock-output-names", &init.name); ++ if (ret) { ++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); ++ return ret; ++ } ++ ++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); ++ if (!fixed) ++ return -ENOMEM; ++ ++ init.ops = &clk_fixed_rate_ops; ++ ++ /* controllers using QMP phys use 125MHz pipe clock interface */ ++ fixed->fixed_rate = 125000000; ++ fixed->hw.init = &init; ++ ++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++/* ++ * Display Port PLL driver block diagram for branch clocks ++ * ++ * +------------------------------+ ++ * | DP_VCO_CLK | ++ * | | ++ * | +-------------------+ | ++ * | | (DP PLL/VCO) | | ++ * | +---------+---------+ | ++ * | v | ++ * | +----------+-----------+ | ++ * | | hsclk_divsel_clk_src | | ++ * | +----------+-----------+ | ++ * +------------------------------+ ++ * | ++ * +---------<---------v------------>----------+ ++ * | | ++ * +--------v----------------+ | ++ * | dp_phy_pll_link_clk | | ++ * | link_clk | | ++ * +--------+----------------+ | ++ * | | ++ * | | ++ * v v ++ * Input to DISPCC block | ++ * for link clk, crypto clk | ++ * and interface clock | ++ * | ++ * | ++ * +--------<------------+-----------------+---<---+ ++ * | | | ++ * +----v---------+ +--------v-----+ +--------v------+ ++ * | vco_divided | | vco_divided | | vco_divided | ++ * | _clk_src | | _clk_src | | _clk_src | ++ * | | | | | | ++ * |divsel_six | | divsel_two | | divsel_four | ++ * +-------+------+ +-----+--------+ +--------+------+ ++ * | | | ++ * v---->----------v-------------<------v ++ * | ++ * +----------+-----------------+ ++ * | dp_phy_pll_vco_div_clk | ++ * +---------+------------------+ ++ * | ++ * v ++ * Input to DISPCC block ++ * for DP pixel clock ++ * ++ */ ++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 1620000000UL / 2: ++ case 2700000000UL / 2: ++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ return 1620000000UL / 2; ++ case 2700: ++ return 2700000000UL / 2; ++ case 5400: ++ return 5400000000UL / 4; ++ case 8100: ++ return 8100000000UL / 6; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { ++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, ++}; ++ ++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 162000000: ++ case 270000000: ++ case 540000000: ++ case 810000000: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ return dp_opts->link_rate * 100000; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_link_clk_ops = { ++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, ++}; ++ ++static struct clk_hw * ++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct qmp_phy_dp_clks *dp_clks = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx >= 2) { ++ pr_err("%s: invalid index %u\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (idx == 0) ++ return &dp_clks->dp_link_hw; ++ ++ return &dp_clks->dp_pixel_hw; ++} ++ ++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, ++ struct device_node *np) ++{ ++ struct clk_init_data init = { }; ++ struct qmp_phy_dp_clks *dp_clks; ++ char name[64]; ++ int ret; ++ ++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); ++ if (!dp_clks) ++ return -ENOMEM; ++ ++ dp_clks->qphy = qphy; ++ qphy->dp_clks = dp_clks; ++ ++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_link_clk_ops; ++ init.name = name; ++ dp_clks->dp_link_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); ++ if (ret) ++ return ret; ++ ++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_pixel_clk_ops; ++ init.name = name; ++ dp_clks->dp_pixel_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++static const struct phy_ops qcom_qmp_phy_gen_ops = { ++ .init = qcom_qmp_phy_enable, ++ .exit = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_phy_dp_ops = { ++ .init = qcom_qmp_phy_init, ++ .configure = qcom_qmp_dp_phy_configure, ++ .power_on = qcom_qmp_phy_power_on, ++ .calibrate = qcom_qmp_dp_phy_calibrate, ++ .power_off = qcom_qmp_phy_power_off, ++ .exit = qcom_qmp_phy_exit, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_pcie_ufs_ops = { ++ .power_on = qcom_qmp_phy_enable, ++ .power_off = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static void qcom_qmp_reset_control_put(void *data) ++{ ++ reset_control_put(data); ++} ++ ++static ++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++ void __iomem *serdes, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct phy *generic_phy; ++ struct qmp_phy *qphy; ++ const struct phy_ops *ops; ++ char prop_name[MAX_PROP_NAME]; ++ int ret; ++ ++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); ++ if (!qphy) ++ return -ENOMEM; ++ ++ qphy->cfg = cfg; ++ qphy->serdes = serdes; ++ /* ++ * Get memory resources for each phy lane: ++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. ++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 ++ * For single lane PHYs: pcs_misc (optional) -> 3. ++ */ ++ qphy->tx = of_iomap(np, 0); ++ if (!qphy->tx) ++ return -ENOMEM; ++ ++ qphy->rx = of_iomap(np, 1); ++ if (!qphy->rx) ++ return -ENOMEM; ++ ++ qphy->pcs = of_iomap(np, 2); ++ if (!qphy->pcs) ++ return -ENOMEM; ++ ++ /* ++ * If this is a dual-lane PHY, then there should be registers for the ++ * second lane. Some old device trees did not specify this, so fall ++ * back to old legacy behavior of assuming they can be reached at an ++ * offset from the first lane. ++ */ ++ if (cfg->is_dual_lane_phy) { ++ qphy->tx2 = of_iomap(np, 3); ++ qphy->rx2 = of_iomap(np, 4); ++ if (!qphy->tx2 || !qphy->rx2) { ++ dev_warn(dev, ++ "Underspecified device tree, falling back to legacy register regions\n"); ++ ++ /* In the old version, pcs_misc is at index 3. */ ++ qphy->pcs_misc = qphy->tx2; ++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; ++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 5); ++ } ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 3); ++ } ++ ++ if (!qphy->pcs_misc) ++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ ++ /* ++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 ++ * based phys, so they essentially have pipe clock. So, ++ * we return error in case phy is USB3 or PIPE type. ++ * Otherwise, we initialize pipe clock to NULL for ++ * all phys that don't need this. ++ */ ++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id); ++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); ++ if (IS_ERR(qphy->pipe_clk)) { ++ if (cfg->type == PHY_TYPE_PCIE || ++ cfg->type == PHY_TYPE_USB3) { ++ ret = PTR_ERR(qphy->pipe_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, ++ "failed to get lane%d pipe_clk, %d\n", ++ id, ret); ++ return ret; ++ } ++ qphy->pipe_clk = NULL; ++ } ++ ++ /* Get lane reset, if any */ ++ if (cfg->has_lane_rst) { ++ snprintf(prop_name, sizeof(prop_name), "lane%d", id); ++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); ++ if (IS_ERR(qphy->lane_rst)) { ++ dev_err(dev, "failed to get lane%d reset\n", id); ++ return PTR_ERR(qphy->lane_rst); ++ } ++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, ++ qphy->lane_rst); ++ if (ret) ++ return ret; ++ } ++ ++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ++ ops = &qcom_qmp_pcie_ufs_ops; ++ else if (cfg->type == PHY_TYPE_DP) ++ ops = &qcom_qmp_phy_dp_ops; ++ else ++ ops = &qcom_qmp_phy_gen_ops; ++ ++ generic_phy = devm_phy_create(dev, np, ops); ++ if (IS_ERR(generic_phy)) { ++ ret = PTR_ERR(generic_phy); ++ dev_err(dev, "failed to create qphy %d\n", ret); ++ return ret; ++ } ++ ++ qphy->phy = generic_phy; ++ qphy->index = id; ++ qphy->qmp = qmp; ++ qmp->phys[id] = qphy; ++ phy_set_drvdata(generic_phy, qphy); ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,ipq8074-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-pcie-phy", ++ .data = &msm8996_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-ufs-phy", ++ .data = &msm8996_ufs_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-usb3-phy", ++ .data = &msm8996_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-pcie-phy", ++ .data = &msm8998_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-phy", ++ .data = &ipq8074_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-pcie-phy", ++ .data = &ipq6018_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-phy", ++ .data = &sc7180_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sc8180x-qmp-pcie-phy", ++ .data = &sc8180x_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8280xp-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sdm845-qhp-pcie-phy", ++ .data = &sdm845_qhp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-pcie-phy", ++ .data = &sdm845_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-phy", ++ .data = &qmp_v3_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy", ++ .data = &qmp_v3_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-usb3-phy", ++ .data = &msm8998_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm6115-qmp-ufs-phy", ++ .data = &sm6115_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm6350-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy", ++ .data = &sm8150_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-phy", ++ .data = &sm8250_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy", ++ .data = &sm8250_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", ++ .data = &sm8250_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-pcie-phy", ++ .data = &sdx55_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy", ++ .data = &sdx55_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy", ++ .data = &sdx65_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy", ++ .data = &sm8350_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", ++ .data = &sm8450_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", ++ .data = &sm8450_qmp_gen4x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-ufs-phy", ++ .data = &sm8450_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,qcm2290-qmp-usb3-phy", ++ .data = &qcm2290_usb3phy_cfg, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++ ++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ .data = &sc7180_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ .data = &sm8250_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ .data = &sc8180x_usb3dpphy_cfg, ++ }, ++ { } ++}; ++ ++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, ++ qcom_qmp_phy_runtime_resume, NULL) ++}; ++ ++static int qcom_qmp_phy_probe(struct platform_device *pdev) ++{ ++ struct qcom_qmp *qmp; ++ struct device *dev = &pdev->dev; ++ struct device_node *child; ++ struct phy_provider *phy_provider; ++ void __iomem *serdes; ++ void __iomem *usb_serdes; ++ void __iomem *dp_serdes = NULL; ++ const struct qmp_phy_combo_cfg *combo_cfg = NULL; ++ const struct qmp_phy_cfg *cfg = NULL; ++ const struct qmp_phy_cfg *usb_cfg = NULL; ++ const struct qmp_phy_cfg *dp_cfg = NULL; ++ int num, id, expected_phys; ++ int ret; ++ ++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); ++ if (!qmp) ++ return -ENOMEM; ++ ++ qmp->dev = dev; ++ dev_set_drvdata(dev, qmp); ++ ++ /* Get the specific init parameters of QMP phy */ ++ cfg = of_device_get_match_data(dev); ++ if (!cfg) { ++ const struct of_device_id *match; ++ ++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); ++ if (!match) ++ return -EINVAL; ++ ++ combo_cfg = match->data; ++ if (!combo_cfg) ++ return -EINVAL; ++ ++ usb_cfg = combo_cfg->usb_cfg; ++ cfg = usb_cfg; /* Setup clks and regulators */ ++ } ++ ++ /* per PHY serdes; usually located at base address */ ++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(serdes)) ++ return PTR_ERR(serdes); ++ ++ /* per PHY dp_com; if PHY has dp_com control block */ ++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(qmp->dp_com)) ++ return PTR_ERR(qmp->dp_com); ++ } ++ ++ if (combo_cfg) { ++ /* Only two serdes for combo PHY */ ++ dp_serdes = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(dp_serdes)) ++ return PTR_ERR(dp_serdes); ++ ++ dp_cfg = combo_cfg->dp_cfg; ++ expected_phys = 2; ++ } else { ++ expected_phys = cfg->nlanes; ++ } ++ ++ mutex_init(&qmp->phy_mutex); ++ ++ ret = qcom_qmp_phy_clk_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_reset_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to get regulator supplies: %d\n", ++ ret); ++ return ret; ++ } ++ ++ num = of_get_available_child_count(dev->of_node); ++ /* do we have a rogue child node ? */ ++ if (num > expected_phys) ++ return -EINVAL; ++ ++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); ++ if (!qmp->phys) ++ return -ENOMEM; ++ ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ /* ++ * Prevent runtime pm from being ON by default. Users can enable ++ * it using power/control in sysfs. ++ */ ++ pm_runtime_forbid(dev); ++ ++ id = 0; ++ for_each_available_child_of_node(dev->of_node, child) { ++ if (of_node_name_eq(child, "dp-phy")) { ++ cfg = dp_cfg; ++ serdes = dp_serdes; ++ } else if (of_node_name_eq(child, "usb3-phy")) { ++ cfg = usb_cfg; ++ serdes = usb_serdes; ++ } ++ ++ /* Create per-lane phy */ ++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ if (ret) { ++ dev_err(dev, "failed to create lane%d phy, %d\n", ++ id, ret); ++ goto err_node_put; ++ } ++ ++ /* ++ * Register the pipe clock provided by phy. ++ * See function description to see details of this pipe clock. ++ */ ++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; ++ } ++ } else if (cfg->type == PHY_TYPE_DP) { ++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register DP clock source\n"); ++ goto err_node_put; ++ } ++ } ++ id++; ++ } ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (!IS_ERR(phy_provider)) ++ dev_info(dev, "Registered Qcom-QMP phy\n"); ++ else ++ pm_runtime_disable(dev); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++ ++err_node_put: ++ pm_runtime_disable(dev); ++ of_node_put(child); ++ return ret; ++} ++ ++static struct platform_driver qcom_qmp_phy_driver = { ++ .probe = qcom_qmp_phy_probe, ++ .driver = { ++ .name = "qcom-qmp-phy", ++ .pm = &qcom_qmp_phy_pm_ops, ++ .of_match_table = qcom_qmp_phy_of_match_table, ++ }, ++}; ++ ++module_platform_driver(qcom_qmp_phy_driver); ++ ++MODULE_AUTHOR("Vivek Gautam "); ++MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +new file mode 100644 +index 000000000000..c7309e981bfb +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +@@ -0,0 +1,6350 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-qcom-qmp.h" ++ ++/* QPHY_SW_RESET bit */ ++#define SW_RESET BIT(0) ++/* QPHY_POWER_DOWN_CONTROL */ ++#define SW_PWRDN BIT(0) ++#define REFCLK_DRV_DSBL BIT(1) ++/* QPHY_START_CONTROL bits */ ++#define SERDES_START BIT(0) ++#define PCS_START BIT(1) ++#define PLL_READY_GATE_EN BIT(3) ++/* QPHY_PCS_STATUS bit */ ++#define PHYSTATUS BIT(6) ++#define PHYSTATUS_4_20 BIT(7) ++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ ++#define PCS_READY BIT(0) ++ ++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ ++/* DP PHY soft reset */ ++#define SW_DPPHY_RESET BIT(0) ++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ ++#define SW_DPPHY_RESET_MUX BIT(1) ++/* USB3 PHY soft reset */ ++#define SW_USB3PHY_RESET BIT(2) ++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ ++#define SW_USB3PHY_RESET_MUX BIT(3) ++ ++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ ++#define USB3_MODE BIT(0) /* enables USB3 mode */ ++#define DP_MODE BIT(1) /* enables DP mode */ ++ ++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ ++#define ARCVR_DTCT_EN BIT(0) ++#define ALFPS_DTCT_EN BIT(1) ++#define ARCVR_DTCT_EVENT_SEL BIT(4) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ ++#define IRQ_CLEAR BIT(0) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ ++#define RCVR_DETECT BIT(0) ++ ++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ ++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ ++ ++#define PHY_INIT_COMPLETE_TIMEOUT 10000 ++#define POWER_DOWN_DELAY_US_MIN 10 ++#define POWER_DOWN_DELAY_US_MAX 11 ++ ++#define MAX_PROP_NAME 32 ++ ++/* Define the assumed distance between lanes for underspecified device trees. */ ++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 ++ ++struct qmp_phy_init_tbl { ++ unsigned int offset; ++ unsigned int val; ++ /* ++ * register part of layout ? ++ * if yes, then offset gives index in the reg-layout ++ */ ++ bool in_layout; ++ /* ++ * mask of lanes for which this register is written ++ * for cases when second lane needs different values ++ */ ++ u8 lane_mask; ++}; ++ ++#define QMP_PHY_INIT_CFG(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_L(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .in_layout = true, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = l, \ ++ } ++ ++/* set of registers with offsets different per-PHY */ ++enum qphy_reg_layout { ++ /* Common block control registers */ ++ QPHY_COM_SW_RESET, ++ QPHY_COM_POWER_DOWN_CONTROL, ++ QPHY_COM_START_CONTROL, ++ QPHY_COM_PCS_READY_STATUS, ++ /* PCS registers */ ++ QPHY_PLL_LOCK_CHK_DLY_TIME, ++ QPHY_FLL_CNTRL1, ++ QPHY_FLL_CNTRL2, ++ QPHY_FLL_CNT_VAL_L, ++ QPHY_FLL_CNT_VAL_H_TOL, ++ QPHY_FLL_MAN_CODE, ++ QPHY_SW_RESET, ++ QPHY_START_CTRL, ++ QPHY_PCS_READY_STATUS, ++ QPHY_PCS_STATUS, ++ QPHY_PCS_AUTONOMOUS_MODE_CTRL, ++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, ++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, ++ QPHY_PCS_POWER_DOWN_CONTROL, ++ /* PCS_MISC registers */ ++ QPHY_PCS_MISC_TYPEC_CTRL, ++ /* Keep last to ensure regs_layout arrays are properly initialized */ ++ QPHY_LAYOUT_SIZE ++}; ++ ++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_COM_SW_RESET] = 0x400, ++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, ++ [QPHY_COM_START_CONTROL] = 0x408, ++ [QPHY_COM_PCS_READY_STATUS] = 0x448, ++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, ++ [QPHY_FLL_CNTRL1] = 0xc4, ++ [QPHY_FLL_CNTRL2] = 0xc8, ++ [QPHY_FLL_CNT_VAL_L] = 0xcc, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, ++ [QPHY_FLL_MAN_CODE] = 0xd4, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_FLL_CNTRL1] = 0xc0, ++ [QPHY_FLL_CNTRL2] = 0xc4, ++ [QPHY_FLL_CNT_VAL_L] = 0xc8, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, ++ [QPHY_FLL_MAN_CODE] = 0xd0, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x17c, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, ++}; ++ ++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, ++}; ++ ++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x2ac, ++}; ++ ++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, ++}; ++ ++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, ++}; ++ ++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, ++}; ++ ++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, ++}; ++ ++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x160, ++}; ++ ++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, ++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, ++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), ++ ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), ++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), ++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), ++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), ++}; ++ ++/* Register names should be validated, they might be different for this PHY */ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), ++}; ++ ++struct qmp_phy; ++ ++/* struct qmp_phy_cfg - per-PHY initialization config */ ++struct qmp_phy_cfg { ++ /* phy-type - PCIE/UFS/USB */ ++ unsigned int type; ++ /* number of lanes provided by phy */ ++ int nlanes; ++ ++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ ++ const struct qmp_phy_init_tbl *serdes_tbl; ++ int serdes_tbl_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_sec; ++ int serdes_tbl_num_sec; ++ const struct qmp_phy_init_tbl *tx_tbl; ++ int tx_tbl_num; ++ const struct qmp_phy_init_tbl *tx_tbl_sec; ++ int tx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *rx_tbl; ++ int rx_tbl_num; ++ const struct qmp_phy_init_tbl *rx_tbl_sec; ++ int rx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_tbl; ++ int pcs_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_tbl_sec; ++ int pcs_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl; ++ int pcs_misc_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; ++ int pcs_misc_tbl_num_sec; ++ ++ /* Init sequence for DP PHY block link rates */ ++ const struct qmp_phy_init_tbl *serdes_tbl_rbr; ++ int serdes_tbl_rbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr; ++ int serdes_tbl_hbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2; ++ int serdes_tbl_hbr2_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3; ++ int serdes_tbl_hbr3_num; ++ ++ /* DP PHY callbacks */ ++ int (*configure_dp_phy)(struct qmp_phy *qphy); ++ void (*configure_dp_tx)(struct qmp_phy *qphy); ++ int (*calibrate_dp_phy)(struct qmp_phy *qphy); ++ void (*dp_aux_init)(struct qmp_phy *qphy); ++ ++ /* clock ids to be requested */ ++ const char * const *clk_list; ++ int num_clks; ++ /* resets to be requested */ ++ const char * const *reset_list; ++ int num_resets; ++ /* regulators to be requested */ ++ const char * const *vreg_list; ++ int num_vregs; ++ ++ /* array of registers with different offsets */ ++ const unsigned int *regs; ++ ++ unsigned int start_ctrl; ++ unsigned int pwrdn_ctrl; ++ unsigned int mask_com_pcs_ready; ++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ ++ unsigned int phy_status; ++ ++ /* true, if PHY has a separate PHY_COM control block */ ++ bool has_phy_com_ctrl; ++ /* true, if PHY has a reset for individual lanes */ ++ bool has_lane_rst; ++ /* true, if PHY needs delay after POWER_DOWN */ ++ bool has_pwrdn_delay; ++ /* power_down delay in usec */ ++ int pwrdn_delay_min; ++ int pwrdn_delay_max; ++ ++ /* true, if PHY has a separate DP_COM control block */ ++ bool has_phy_dp_com_ctrl; ++ /* true, if PHY has secondary tx/rx lanes to be configured */ ++ bool is_dual_lane_phy; ++ ++ /* true, if PCS block has no separate SW_RESET register */ ++ bool no_pcs_sw_reset; ++}; ++ ++struct qmp_phy_combo_cfg { ++ const struct qmp_phy_cfg *usb_cfg; ++ const struct qmp_phy_cfg *dp_cfg; ++}; ++ ++/** ++ * struct qmp_phy - per-lane phy descriptor ++ * ++ * @phy: generic phy ++ * @cfg: phy specific configuration ++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL) ++ * @tx: iomapped memory space for lane's tx ++ * @rx: iomapped memory space for lane's rx ++ * @pcs: iomapped memory space for lane's pcs ++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) ++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) ++ * @pcs_misc: iomapped memory space for lane's pcs_misc ++ * @pipe_clk: pipe clock ++ * @index: lane index ++ * @qmp: QMP phy to which this lane belongs ++ * @lane_rst: lane's reset controller ++ * @mode: current PHY mode ++ * @dp_aux_cfg: Display port aux config ++ * @dp_opts: Display port optional config ++ * @dp_clks: Display port clocks ++ */ ++struct qmp_phy { ++ struct phy *phy; ++ const struct qmp_phy_cfg *cfg; ++ void __iomem *serdes; ++ void __iomem *tx; ++ void __iomem *rx; ++ void __iomem *pcs; ++ void __iomem *tx2; ++ void __iomem *rx2; ++ void __iomem *pcs_misc; ++ struct clk *pipe_clk; ++ unsigned int index; ++ struct qcom_qmp *qmp; ++ struct reset_control *lane_rst; ++ enum phy_mode mode; ++ unsigned int dp_aux_cfg; ++ struct phy_configure_opts_dp dp_opts; ++ struct qmp_phy_dp_clks *dp_clks; ++}; ++ ++struct qmp_phy_dp_clks { ++ struct qmp_phy *qphy; ++ struct clk_hw dp_link_hw; ++ struct clk_hw dp_pixel_hw; ++}; ++ ++/** ++ * struct qcom_qmp - structure holding QMP phy block attributes ++ * ++ * @dev: device ++ * @dp_com: iomapped memory space for phy's dp_com control block ++ * ++ * @clks: array of clocks required by phy ++ * @resets: array of resets required by phy ++ * @vregs: regulator supplies bulk data ++ * ++ * @phys: array of per-lane phy descriptors ++ * @phy_mutex: mutex lock for PHY common block initialization ++ * @init_count: phy common block initialization count ++ * @ufs_reset: optional UFS PHY reset handle ++ */ ++struct qcom_qmp { ++ struct device *dev; ++ void __iomem *dp_com; ++ ++ struct clk_bulk_data *clks; ++ struct reset_control **resets; ++ struct regulator_bulk_data *vregs; ++ ++ struct qmp_phy **phys; ++ ++ struct mutex phy_mutex; ++ int init_count; ++ ++ struct reset_control *ufs_reset; ++}; ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg |= val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg &= ~val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++/* list of clocks required by phy */ ++static const char * const msm8996_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", ++}; ++ ++static const char * const msm8996_ufs_phy_clk_l[] = { ++ "ref", ++}; ++ ++static const char * const qmp_v3_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "com_aux", ++}; ++ ++static const char * const sdm845_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "refgen", ++}; ++ ++static const char * const qmp_v4_phy_clk_l[] = { ++ "aux", "ref_clk_src", "ref", "com_aux", ++}; ++ ++/* the primary usb3 phy on sm8250 doesn't have a ref clock */ ++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { ++ "aux", "ref_clk_src", "com_aux" ++}; ++ ++static const char * const sm8450_ufs_phy_clk_l[] = { ++ "qref", "ref", "ref_aux", ++}; ++ ++static const char * const sdm845_ufs_phy_clk_l[] = { ++ "ref", "ref_aux", ++}; ++ ++/* usb3 phy on sdx55 doesn't have com_aux clock */ ++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { ++ "aux", "cfg_ahb", "ref" ++}; ++ ++static const char * const qcm2290_usb3phy_clk_l[] = { ++ "cfg_ahb", "ref", "com_aux", ++}; ++ ++/* list of resets */ ++static const char * const msm8996_pciephy_reset_l[] = { ++ "phy", "common", "cfg", ++}; ++ ++static const char * const msm8996_usb3phy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const char * const sc7180_usb3phy_reset_l[] = { ++ "phy", ++}; ++ ++static const char * const qcm2290_usb3phy_reset_l[] = { ++ "phy_phy", "phy", ++}; ++ ++static const char * const sdm845_pciephy_reset_l[] = { ++ "phy", ++}; ++ ++/* list of regulators */ ++static const char * const qmp_phy_vreg_l[] = { ++ "vdda-phy", "vdda-pll", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = ipq8074_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), ++ .pcs_tbl = ipq8074_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 3, ++ ++ .serdes_tbl = msm8996_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), ++ .tx_tbl = msm8996_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), ++ .rx_tbl = msm8996_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), ++ .pcs_tbl = msm8996_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | PLL_READY_GATE_EN, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .mask_com_pcs_ready = PCS_READY, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = true, ++ .has_lane_rst = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg msm8996_ufs_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_ufs_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), ++ .tx_tbl = msm8996_ufs_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), ++ .rx_tbl = msm8996_ufs_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), ++ ++ .clk_list = msm8996_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), ++ ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ ++ .regs = msm8996_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = msm8996_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), ++ .pcs_tbl = msm8996_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const char * const ipq8074_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", ++}; ++/* list of resets */ ++static const char * const ipq8074_pciephy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), ++ .rx_tbl = ipq8074_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq6018_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), ++ .tx_tbl = ipq6018_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), ++ .rx_tbl = ipq6018_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), ++ .pcs_tbl = ipq6018_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = ipq_pciephy_gen3_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qmp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qhp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qhp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qhp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, ++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), ++ .tx_tbl = qmp_v3_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { ++ .usb_cfg = &sc7180_usb3phy_cfg, ++ .dp_cfg = &sc7180_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdm845_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), ++ .tx_tbl = sdm845_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), ++ .rx_tbl = sdm845_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), ++ .pcs_tbl = sdm845_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm6115_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), ++ .tx_tbl = sm6115_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), ++ .rx_tbl = sm6115_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), ++ .pcs_tbl = sm6115_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm6115_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ ++ .is_dual_lane_phy = false, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8998_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), ++ .tx_tbl = msm8998_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), ++ .rx_tbl = msm8998_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), ++ .pcs_tbl = msm8998_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), ++ .tx_tbl = msm8998_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), ++ .rx_tbl = msm8998_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), ++ .pcs_tbl = msm8998_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8150_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), ++ .tx_tbl = sm8150_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), ++ .rx_tbl = sm8150_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), ++ .pcs_tbl = sm8150_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8150_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), ++ .rx_tbl = sm8150_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), ++ .pcs_tbl = sm8150_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), ++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), ++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), ++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { ++ .usb_cfg = &sm8150_usb3phy_cfg, ++ .dp_cfg = &sc8180x_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8250_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), ++ .rx_tbl = sm8250_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), ++ .pcs_tbl = sm8250_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { ++ .usb_cfg = &sm8250_usb3phy_cfg, ++ .dp_cfg = &sm8250_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdx55_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), ++ .rx_tbl = sdx55_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8350_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), ++ .rx_tbl = sm8350_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), ++ .pcs_tbl = sm8350_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sm8450_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qcm2290_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), ++ .tx_tbl = qcm2290_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), ++ .rx_tbl = qcm2290_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), ++ .pcs_tbl = qcm2290_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), ++ .clk_list = qcm2290_usb3phy_clk_l, ++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), ++ .reset_list = qcm2290_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qcm2290_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static void qcom_qmp_phy_configure_lane(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num, ++ u8 lane_mask) ++{ ++ int i; ++ const struct qmp_phy_init_tbl *t = tbl; ++ ++ if (!t) ++ return; ++ ++ for (i = 0; i < num; i++, t++) { ++ if (!(t->lane_mask & lane_mask)) ++ continue; ++ ++ if (t->in_layout) ++ writel(t->val, base + regs[t->offset]); ++ else ++ writel(t->val, base + t->offset); ++ } ++} ++ ++static void qcom_qmp_phy_configure(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num) ++{ ++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++} ++ ++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; ++ int serdes_tbl_num = cfg->serdes_tbl_num; ++ int ret; ++ ++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ if (cfg->serdes_tbl_sec) ++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ cfg->serdes_tbl_num_sec); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ switch (dp_opts->link_rate) { ++ case 1620: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_rbr, ++ cfg->serdes_tbl_rbr_num); ++ break; ++ case 2700: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr, ++ cfg->serdes_tbl_hbr_num); ++ break; ++ case 5400: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr2, ++ cfg->serdes_tbl_hbr2_num); ++ break; ++ case 8100: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr3, ++ cfg->serdes_tbl_hbr3_num); ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ } ++ ++ ++ if (cfg->has_phy_com_ctrl) { ++ void __iomem *status; ++ unsigned int mask, val; ++ ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ ++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; ++ mask = cfg->mask_com_pcs_ready; ++ ++ ret = readl_poll_timeout(status, val, (val & mask), 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, ++ "phy common block init timed-out\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_LANE_0_1_PWRDN | ++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | ++ DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(QSERDES_V3_COM_BIAS_EN | ++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | ++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { ++ { 0x00, 0x0c, 0x15, 0x1a }, ++ { 0x02, 0x0e, 0x16, 0xff }, ++ { 0x02, 0x11, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { ++ { 0x02, 0x12, 0x16, 0x1a }, ++ { 0x09, 0x19, 0x1f, 0xff }, ++ { 0x10, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { ++ { 0x00, 0x0c, 0x14, 0x19 }, ++ { 0x00, 0x0b, 0x12, 0xff }, ++ { 0x00, 0x0b, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { ++ { 0x08, 0x0f, 0x16, 0x1f }, ++ { 0x11, 0x1e, 0x1f, 0xff }, ++ { 0x19, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, ++ unsigned int drv_lvl_reg, unsigned int emp_post_reg) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ unsigned int v_level = 0, p_level = 0; ++ u8 voltage_swing_cfg, pre_emphasis_cfg; ++ int i; ++ ++ for (i = 0; i < dp_opts->lanes; i++) { ++ v_level = max(v_level, dp_opts->voltage[i]); ++ p_level = max(p_level, dp_opts->pre[i]); ++ } ++ ++ if (dp_opts->link_rate <= 2700) { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; ++ } else { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; ++ } ++ ++ /* TODO: Move check to config check */ ++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) ++ return -EINVAL; ++ ++ /* Enable MUX to use Cursor values from these registers */ ++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; ++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; ++ ++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); ++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 bias_en, drvr_en; ++ ++ if (qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V3_TX_TX_DRV_LVL, ++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) ++ return; ++ ++ if (dp_opts->lanes == 1) { ++ bias_en = 0x3e; ++ drvr_en = 0x13; ++ } else { ++ bias_en = 0x3f; ++ drvr_en = 0x10; ++ } ++ ++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++} ++ ++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) ++{ ++ u32 val; ++ bool reverse = false; ++ ++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; ++ ++ /* ++ * TODO: Assume orientation is CC1 for now and two lanes, need to ++ * use type-c connector to understand orientation and lanes. ++ * ++ * Otherwise val changes to be like below if this code understood ++ * the orientation of the type-c cable. ++ * ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) ++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) ++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ * if (orientation == ORIENTATION_CC2) ++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); ++ */ ++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); ++ ++ return reverse; ++} ++ ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ ++ qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000); ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ /* Program default values before writing proper values */ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V4_TX_TX_DRV_LVL, ++ QSERDES_V4_TX_TX_EMP_POST1_LVL); ++} ++ ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en; ++ bool reverse; ++ ++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); ++ ++ reverse = qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ /* ++ * At least for 7nm DP PHY this has to be done after enabling link ++ * clock. ++ */ ++ ++ if (dp_opts->lanes == 1) { ++ bias0_en = reverse ? 0x3e : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3e; ++ drvr0_en = reverse ? 0x13 : 0x10; ++ drvr1_en = reverse ? 0x10 : 0x13; ++ } else if (dp_opts->lanes == 2) { ++ bias0_en = reverse ? 0x3f : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } else { ++ bias0_en = 0x3f; ++ bias1_en = 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } ++ ++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); ++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); ++ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ return 0; ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &opts->dp; ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); ++ if (qphy->dp_opts.set_voltages) { ++ cfg->configure_dp_tx(qphy); ++ qphy->dp_opts.set_voltages = 0; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_calibrate(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->calibrate_dp_phy) ++ return cfg->calibrate_dp_phy(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *dp_com = qmp->dp_com; ++ int ret, i; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (qmp->init_count++) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ /* turn on regulator supplies */ ++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); ++ if (ret) { ++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ++ goto err_unlock; ++ } ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ ret = reset_control_assert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset assert failed\n", ++ cfg->reset_list[i]); ++ goto err_disable_regulators; ++ } ++ } ++ ++ for (i = cfg->num_resets - 1; i >= 0; i--) { ++ ret = reset_control_deassert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset deassert failed\n", ++ qphy->cfg->reset_list[i]); ++ goto err_assert_reset; ++ } ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ goto err_assert_reset; ++ ++ if (cfg->has_phy_dp_com_ctrl) { ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, ++ SW_PWRDN); ++ /* override hardware control for reset of qmp phy */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ /* Default type-c orientation, i.e CC1 */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); ++ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, ++ USB3_MODE | DP_MODE); ++ ++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); ++ } ++ ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } else { ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) ++ qphy_setbits(pcs, ++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ else ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++ ++err_assert_reset: ++ while (++i < cfg->num_resets) ++ reset_control_assert(qmp->resets[i]); ++err_disable_regulators: ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++err_unlock: ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ int i = cfg->num_resets; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (--qmp->init_count) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ reset_control_assert(qmp->ufs_reset); ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], ++ SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } ++ ++ while (--i >= 0) ++ reset_control_assert(qmp->resets[i]); ++ ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_init(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret; ++ dev_vdbg(qmp->dev, "Initializing QMP phy\n"); ++ ++ if (cfg->no_pcs_sw_reset) { ++ /* ++ * Get UFS reset, which is delayed until now to avoid a ++ * circular dependency where UFS needs its PHY, but the PHY ++ * needs this UFS reset. ++ */ ++ if (!qmp->ufs_reset) { ++ qmp->ufs_reset = ++ devm_reset_control_get_exclusive(qmp->dev, ++ "ufsphy"); ++ ++ if (IS_ERR(qmp->ufs_reset)) { ++ ret = PTR_ERR(qmp->ufs_reset); ++ dev_err(qmp->dev, ++ "failed to get UFS reset: %d\n", ++ ret); ++ ++ qmp->ufs_reset = NULL; ++ return ret; ++ } ++ } ++ ++ ret = reset_control_assert(qmp->ufs_reset); ++ if (ret) ++ return ret; ++ } ++ ++ ret = qcom_qmp_phy_com_init(qphy); ++ if (ret) ++ return ret; ++ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->dp_aux_init(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_power_on(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *tx = qphy->tx; ++ void __iomem *rx = qphy->rx; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ void __iomem *status; ++ unsigned int mask, val, ready; ++ int ret; ++ ++ qcom_qmp_phy_serdes_init(qphy); ++ ++ if (cfg->has_lane_rst) { ++ ret = reset_control_deassert(qphy->lane_rst); ++ if (ret) { ++ dev_err(qmp->dev, "lane%d reset deassert failed\n", ++ qphy->index); ++ return ret; ++ } ++ } ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); ++ goto err_reset_lane; ++ } ++ ++ /* Tx, Rx, and PCS configurations */ ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 1); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 1); ++ ++ /* Configuration for other LANE for USB-DP combo PHY */ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 2); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 2); ++ } ++ ++ /* Configure special DP tx tunings */ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->configure_dp_tx(qphy); ++ ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 1); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); ++ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 2); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl_sec, ++ cfg->rx_tbl_num_sec, 2); ++ } ++ ++ /* Configure link rate, swing, etc. */ ++ if (cfg->type == PHY_TYPE_DP) { ++ cfg->configure_dp_phy(qphy); ++ } else { ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); ++ } ++ ++ ret = reset_control_deassert(qmp->ufs_reset); ++ if (ret) ++ goto err_disable_pipe_clk; ++ ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ cfg->pcs_misc_tbl_num); ++ if (cfg->pcs_misc_tbl_sec) ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ cfg->pcs_misc_tbl_num_sec); ++ ++ /* ++ * Pull out PHY from POWER DOWN state. ++ * This is active low enable signal to power-down PHY. ++ */ ++ if(cfg->type == PHY_TYPE_PCIE) ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); ++ ++ if (cfg->has_pwrdn_delay) ++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); ++ ++ if (cfg->type != PHY_TYPE_DP) { ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ if (cfg->type == PHY_TYPE_UFS) { ++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; ++ mask = PCS_READY; ++ ready = PCS_READY; ++ } else { ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ } ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; ++ } ++ } ++ return 0; ++ ++err_disable_pipe_clk: ++ clk_disable_unprepare(qphy->pipe_clk); ++err_reset_lane: ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_power_off(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ /* Assert DP PHY power down */ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ } else { ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_exit(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ qcom_qmp_phy_com_exit(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_enable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_init(phy); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_power_on(phy); ++ if (ret) ++ qcom_qmp_phy_exit(phy); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_disable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_power_off(phy); ++ if (ret) ++ return ret; ++ return qcom_qmp_phy_exit(phy); ++} ++ ++static int qcom_qmp_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ ++ qphy->mode = mode; ++ ++ return 0; ++} ++ ++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ u32 intr_mask; ++ ++ if (qphy->mode == PHY_MODE_USB_HOST_SS || ++ qphy->mode == PHY_MODE_USB_DEVICE_SS) ++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; ++ else ++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ++ ++ /* Clear any pending interrupts status */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); ++ ++ /* Enable required PHY autonomous mode interrupts */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); ++ ++ /* Enable i/o clamp_n for autonomous mode */ ++ if (pcs_misc) ++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++} ++ ++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ ++ /* Disable i/o clamp_n on resume for normal mode */ ++ if (pcs_misc) ++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); ++ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ qcom_qmp_phy_enable_autonomous_mode(qphy); ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret = 0; ++ ++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ return ret; ++ } ++ ++ qcom_qmp_phy_disable_autonomous_mode(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_vregs; ++ int i; ++ ++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); ++ if (!qmp->vregs) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->vregs[i].supply = cfg->vreg_list[i]; ++ ++ return devm_regulator_bulk_get(dev, num, qmp->vregs); ++} ++ ++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int i; ++ ++ qmp->resets = devm_kcalloc(dev, cfg->num_resets, ++ sizeof(*qmp->resets), GFP_KERNEL); ++ if (!qmp->resets) ++ return -ENOMEM; ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ struct reset_control *rst; ++ const char *name = cfg->reset_list[i]; ++ ++ rst = devm_reset_control_get_exclusive(dev, name); ++ if (IS_ERR(rst)) { ++ dev_err(dev, "failed to get %s reset\n", name); ++ return PTR_ERR(rst); ++ } ++ qmp->resets[i] = rst; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_clks; ++ int i; ++ ++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); ++ if (!qmp->clks) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->clks[i].id = cfg->clk_list[i]; ++ ++ return devm_clk_bulk_get(dev, num, qmp->clks); ++} ++ ++static void phy_clk_release_provider(void *res) ++{ ++ of_clk_del_provider(res); ++} ++ ++/* ++ * Register a fixed rate pipe clock. ++ * ++ * The _pipe_clksrc generated by PHY goes to the GCC that gate ++ * controls it. The _pipe_clk coming out of the GCC is requested ++ * by the PHY driver for its operations. ++ * We register the _pipe_clksrc here. The gcc driver takes care ++ * of assigning this _pipe_clksrc as parent to _pipe_clk. ++ * Below picture shows this relationship. ++ * ++ * +---------------+ ++ * | PHY block |<<---------------------------------------+ ++ * | | | ++ * | +-------+ | +-----+ | ++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ ++ * clk | +-------+ | +-----+ ++ * +---------------+ ++ */ ++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) ++{ ++ struct clk_fixed_rate *fixed; ++ struct clk_init_data init = { }; ++ int ret; ++ ++ ret = of_property_read_string(np, "clock-output-names", &init.name); ++ if (ret) { ++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); ++ return ret; ++ } ++ ++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); ++ if (!fixed) ++ return -ENOMEM; ++ ++ init.ops = &clk_fixed_rate_ops; ++ ++ /* controllers using QMP phys use 125MHz pipe clock interface */ ++ fixed->fixed_rate = 125000000; ++ fixed->hw.init = &init; ++ ++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++/* ++ * Display Port PLL driver block diagram for branch clocks ++ * ++ * +------------------------------+ ++ * | DP_VCO_CLK | ++ * | | ++ * | +-------------------+ | ++ * | | (DP PLL/VCO) | | ++ * | +---------+---------+ | ++ * | v | ++ * | +----------+-----------+ | ++ * | | hsclk_divsel_clk_src | | ++ * | +----------+-----------+ | ++ * +------------------------------+ ++ * | ++ * +---------<---------v------------>----------+ ++ * | | ++ * +--------v----------------+ | ++ * | dp_phy_pll_link_clk | | ++ * | link_clk | | ++ * +--------+----------------+ | ++ * | | ++ * | | ++ * v v ++ * Input to DISPCC block | ++ * for link clk, crypto clk | ++ * and interface clock | ++ * | ++ * | ++ * +--------<------------+-----------------+---<---+ ++ * | | | ++ * +----v---------+ +--------v-----+ +--------v------+ ++ * | vco_divided | | vco_divided | | vco_divided | ++ * | _clk_src | | _clk_src | | _clk_src | ++ * | | | | | | ++ * |divsel_six | | divsel_two | | divsel_four | ++ * +-------+------+ +-----+--------+ +--------+------+ ++ * | | | ++ * v---->----------v-------------<------v ++ * | ++ * +----------+-----------------+ ++ * | dp_phy_pll_vco_div_clk | ++ * +---------+------------------+ ++ * | ++ * v ++ * Input to DISPCC block ++ * for DP pixel clock ++ * ++ */ ++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 1620000000UL / 2: ++ case 2700000000UL / 2: ++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ return 1620000000UL / 2; ++ case 2700: ++ return 2700000000UL / 2; ++ case 5400: ++ return 5400000000UL / 4; ++ case 8100: ++ return 8100000000UL / 6; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { ++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, ++}; ++ ++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 162000000: ++ case 270000000: ++ case 540000000: ++ case 810000000: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ return dp_opts->link_rate * 100000; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_link_clk_ops = { ++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, ++}; ++ ++static struct clk_hw * ++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct qmp_phy_dp_clks *dp_clks = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx >= 2) { ++ pr_err("%s: invalid index %u\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (idx == 0) ++ return &dp_clks->dp_link_hw; ++ ++ return &dp_clks->dp_pixel_hw; ++} ++ ++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, ++ struct device_node *np) ++{ ++ struct clk_init_data init = { }; ++ struct qmp_phy_dp_clks *dp_clks; ++ char name[64]; ++ int ret; ++ ++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); ++ if (!dp_clks) ++ return -ENOMEM; ++ ++ dp_clks->qphy = qphy; ++ qphy->dp_clks = dp_clks; ++ ++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_link_clk_ops; ++ init.name = name; ++ dp_clks->dp_link_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); ++ if (ret) ++ return ret; ++ ++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_pixel_clk_ops; ++ init.name = name; ++ dp_clks->dp_pixel_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++static const struct phy_ops qcom_qmp_phy_gen_ops = { ++ .init = qcom_qmp_phy_enable, ++ .exit = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_phy_dp_ops = { ++ .init = qcom_qmp_phy_init, ++ .configure = qcom_qmp_dp_phy_configure, ++ .power_on = qcom_qmp_phy_power_on, ++ .calibrate = qcom_qmp_dp_phy_calibrate, ++ .power_off = qcom_qmp_phy_power_off, ++ .exit = qcom_qmp_phy_exit, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_pcie_ufs_ops = { ++ .power_on = qcom_qmp_phy_enable, ++ .power_off = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static void qcom_qmp_reset_control_put(void *data) ++{ ++ reset_control_put(data); ++} ++ ++static ++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++ void __iomem *serdes, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct phy *generic_phy; ++ struct qmp_phy *qphy; ++ const struct phy_ops *ops; ++ char prop_name[MAX_PROP_NAME]; ++ int ret; ++ ++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); ++ if (!qphy) ++ return -ENOMEM; ++ ++ qphy->cfg = cfg; ++ qphy->serdes = serdes; ++ /* ++ * Get memory resources for each phy lane: ++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. ++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 ++ * For single lane PHYs: pcs_misc (optional) -> 3. ++ */ ++ qphy->tx = of_iomap(np, 0); ++ if (!qphy->tx) ++ return -ENOMEM; ++ ++ qphy->rx = of_iomap(np, 1); ++ if (!qphy->rx) ++ return -ENOMEM; ++ ++ qphy->pcs = of_iomap(np, 2); ++ if (!qphy->pcs) ++ return -ENOMEM; ++ ++ /* ++ * If this is a dual-lane PHY, then there should be registers for the ++ * second lane. Some old device trees did not specify this, so fall ++ * back to old legacy behavior of assuming they can be reached at an ++ * offset from the first lane. ++ */ ++ if (cfg->is_dual_lane_phy) { ++ qphy->tx2 = of_iomap(np, 3); ++ qphy->rx2 = of_iomap(np, 4); ++ if (!qphy->tx2 || !qphy->rx2) { ++ dev_warn(dev, ++ "Underspecified device tree, falling back to legacy register regions\n"); ++ ++ /* In the old version, pcs_misc is at index 3. */ ++ qphy->pcs_misc = qphy->tx2; ++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; ++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 5); ++ } ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 3); ++ } ++ ++ if (!qphy->pcs_misc) ++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ ++ /* ++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 ++ * based phys, so they essentially have pipe clock. So, ++ * we return error in case phy is USB3 or PIPE type. ++ * Otherwise, we initialize pipe clock to NULL for ++ * all phys that don't need this. ++ */ ++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id); ++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); ++ if (IS_ERR(qphy->pipe_clk)) { ++ if (cfg->type == PHY_TYPE_PCIE || ++ cfg->type == PHY_TYPE_USB3) { ++ ret = PTR_ERR(qphy->pipe_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, ++ "failed to get lane%d pipe_clk, %d\n", ++ id, ret); ++ return ret; ++ } ++ qphy->pipe_clk = NULL; ++ } ++ ++ /* Get lane reset, if any */ ++ if (cfg->has_lane_rst) { ++ snprintf(prop_name, sizeof(prop_name), "lane%d", id); ++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); ++ if (IS_ERR(qphy->lane_rst)) { ++ dev_err(dev, "failed to get lane%d reset\n", id); ++ return PTR_ERR(qphy->lane_rst); ++ } ++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, ++ qphy->lane_rst); ++ if (ret) ++ return ret; ++ } ++ ++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ++ ops = &qcom_qmp_pcie_ufs_ops; ++ else if (cfg->type == PHY_TYPE_DP) ++ ops = &qcom_qmp_phy_dp_ops; ++ else ++ ops = &qcom_qmp_phy_gen_ops; ++ ++ generic_phy = devm_phy_create(dev, np, ops); ++ if (IS_ERR(generic_phy)) { ++ ret = PTR_ERR(generic_phy); ++ dev_err(dev, "failed to create qphy %d\n", ret); ++ return ret; ++ } ++ ++ qphy->phy = generic_phy; ++ qphy->index = id; ++ qphy->qmp = qmp; ++ qmp->phys[id] = qphy; ++ phy_set_drvdata(generic_phy, qphy); ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,ipq8074-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-pcie-phy", ++ .data = &msm8996_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-ufs-phy", ++ .data = &msm8996_ufs_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-usb3-phy", ++ .data = &msm8996_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-pcie-phy", ++ .data = &msm8998_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-phy", ++ .data = &ipq8074_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-pcie-phy", ++ .data = &ipq6018_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-phy", ++ .data = &sc7180_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sc8180x-qmp-pcie-phy", ++ .data = &sc8180x_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8280xp-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sdm845-qhp-pcie-phy", ++ .data = &sdm845_qhp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-pcie-phy", ++ .data = &sdm845_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-phy", ++ .data = &qmp_v3_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy", ++ .data = &qmp_v3_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-usb3-phy", ++ .data = &msm8998_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm6115-qmp-ufs-phy", ++ .data = &sm6115_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm6350-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy", ++ .data = &sm8150_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-phy", ++ .data = &sm8250_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy", ++ .data = &sm8250_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", ++ .data = &sm8250_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-pcie-phy", ++ .data = &sdx55_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy", ++ .data = &sdx55_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy", ++ .data = &sdx65_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy", ++ .data = &sm8350_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", ++ .data = &sm8450_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", ++ .data = &sm8450_qmp_gen4x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-ufs-phy", ++ .data = &sm8450_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,qcm2290-qmp-usb3-phy", ++ .data = &qcm2290_usb3phy_cfg, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++ ++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ .data = &sc7180_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ .data = &sm8250_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ .data = &sc8180x_usb3dpphy_cfg, ++ }, ++ { } ++}; ++ ++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, ++ qcom_qmp_phy_runtime_resume, NULL) ++}; ++ ++static int qcom_qmp_phy_probe(struct platform_device *pdev) ++{ ++ struct qcom_qmp *qmp; ++ struct device *dev = &pdev->dev; ++ struct device_node *child; ++ struct phy_provider *phy_provider; ++ void __iomem *serdes; ++ void __iomem *usb_serdes; ++ void __iomem *dp_serdes = NULL; ++ const struct qmp_phy_combo_cfg *combo_cfg = NULL; ++ const struct qmp_phy_cfg *cfg = NULL; ++ const struct qmp_phy_cfg *usb_cfg = NULL; ++ const struct qmp_phy_cfg *dp_cfg = NULL; ++ int num, id, expected_phys; ++ int ret; ++ ++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); ++ if (!qmp) ++ return -ENOMEM; ++ ++ qmp->dev = dev; ++ dev_set_drvdata(dev, qmp); ++ ++ /* Get the specific init parameters of QMP phy */ ++ cfg = of_device_get_match_data(dev); ++ if (!cfg) { ++ const struct of_device_id *match; ++ ++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); ++ if (!match) ++ return -EINVAL; ++ ++ combo_cfg = match->data; ++ if (!combo_cfg) ++ return -EINVAL; ++ ++ usb_cfg = combo_cfg->usb_cfg; ++ cfg = usb_cfg; /* Setup clks and regulators */ ++ } ++ ++ /* per PHY serdes; usually located at base address */ ++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(serdes)) ++ return PTR_ERR(serdes); ++ ++ /* per PHY dp_com; if PHY has dp_com control block */ ++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(qmp->dp_com)) ++ return PTR_ERR(qmp->dp_com); ++ } ++ ++ if (combo_cfg) { ++ /* Only two serdes for combo PHY */ ++ dp_serdes = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(dp_serdes)) ++ return PTR_ERR(dp_serdes); ++ ++ dp_cfg = combo_cfg->dp_cfg; ++ expected_phys = 2; ++ } else { ++ expected_phys = cfg->nlanes; ++ } ++ ++ mutex_init(&qmp->phy_mutex); ++ ++ ret = qcom_qmp_phy_clk_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_reset_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to get regulator supplies: %d\n", ++ ret); ++ return ret; ++ } ++ ++ num = of_get_available_child_count(dev->of_node); ++ /* do we have a rogue child node ? */ ++ if (num > expected_phys) ++ return -EINVAL; ++ ++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); ++ if (!qmp->phys) ++ return -ENOMEM; ++ ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ /* ++ * Prevent runtime pm from being ON by default. Users can enable ++ * it using power/control in sysfs. ++ */ ++ pm_runtime_forbid(dev); ++ ++ id = 0; ++ for_each_available_child_of_node(dev->of_node, child) { ++ if (of_node_name_eq(child, "dp-phy")) { ++ cfg = dp_cfg; ++ serdes = dp_serdes; ++ } else if (of_node_name_eq(child, "usb3-phy")) { ++ cfg = usb_cfg; ++ serdes = usb_serdes; ++ } ++ ++ /* Create per-lane phy */ ++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ if (ret) { ++ dev_err(dev, "failed to create lane%d phy, %d\n", ++ id, ret); ++ goto err_node_put; ++ } ++ ++ /* ++ * Register the pipe clock provided by phy. ++ * See function description to see details of this pipe clock. ++ */ ++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; ++ } ++ } else if (cfg->type == PHY_TYPE_DP) { ++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register DP clock source\n"); ++ goto err_node_put; ++ } ++ } ++ id++; ++ } ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (!IS_ERR(phy_provider)) ++ dev_info(dev, "Registered Qcom-QMP phy\n"); ++ else ++ pm_runtime_disable(dev); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++ ++err_node_put: ++ pm_runtime_disable(dev); ++ of_node_put(child); ++ return ret; ++} ++ ++static struct platform_driver qcom_qmp_phy_driver = { ++ .probe = qcom_qmp_phy_probe, ++ .driver = { ++ .name = "qcom-qmp-phy", ++ .pm = &qcom_qmp_phy_pm_ops, ++ .of_match_table = qcom_qmp_phy_of_match_table, ++ }, ++}; ++ ++module_platform_driver(qcom_qmp_phy_driver); ++ ++MODULE_AUTHOR("Vivek Gautam "); ++MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +new file mode 100644 +index 000000000000..c7309e981bfb +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +@@ -0,0 +1,6350 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-qcom-qmp.h" ++ ++/* QPHY_SW_RESET bit */ ++#define SW_RESET BIT(0) ++/* QPHY_POWER_DOWN_CONTROL */ ++#define SW_PWRDN BIT(0) ++#define REFCLK_DRV_DSBL BIT(1) ++/* QPHY_START_CONTROL bits */ ++#define SERDES_START BIT(0) ++#define PCS_START BIT(1) ++#define PLL_READY_GATE_EN BIT(3) ++/* QPHY_PCS_STATUS bit */ ++#define PHYSTATUS BIT(6) ++#define PHYSTATUS_4_20 BIT(7) ++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ ++#define PCS_READY BIT(0) ++ ++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ ++/* DP PHY soft reset */ ++#define SW_DPPHY_RESET BIT(0) ++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ ++#define SW_DPPHY_RESET_MUX BIT(1) ++/* USB3 PHY soft reset */ ++#define SW_USB3PHY_RESET BIT(2) ++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ ++#define SW_USB3PHY_RESET_MUX BIT(3) ++ ++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ ++#define USB3_MODE BIT(0) /* enables USB3 mode */ ++#define DP_MODE BIT(1) /* enables DP mode */ ++ ++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ ++#define ARCVR_DTCT_EN BIT(0) ++#define ALFPS_DTCT_EN BIT(1) ++#define ARCVR_DTCT_EVENT_SEL BIT(4) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ ++#define IRQ_CLEAR BIT(0) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ ++#define RCVR_DETECT BIT(0) ++ ++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ ++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ ++ ++#define PHY_INIT_COMPLETE_TIMEOUT 10000 ++#define POWER_DOWN_DELAY_US_MIN 10 ++#define POWER_DOWN_DELAY_US_MAX 11 ++ ++#define MAX_PROP_NAME 32 ++ ++/* Define the assumed distance between lanes for underspecified device trees. */ ++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 ++ ++struct qmp_phy_init_tbl { ++ unsigned int offset; ++ unsigned int val; ++ /* ++ * register part of layout ? ++ * if yes, then offset gives index in the reg-layout ++ */ ++ bool in_layout; ++ /* ++ * mask of lanes for which this register is written ++ * for cases when second lane needs different values ++ */ ++ u8 lane_mask; ++}; ++ ++#define QMP_PHY_INIT_CFG(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_L(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .in_layout = true, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = l, \ ++ } ++ ++/* set of registers with offsets different per-PHY */ ++enum qphy_reg_layout { ++ /* Common block control registers */ ++ QPHY_COM_SW_RESET, ++ QPHY_COM_POWER_DOWN_CONTROL, ++ QPHY_COM_START_CONTROL, ++ QPHY_COM_PCS_READY_STATUS, ++ /* PCS registers */ ++ QPHY_PLL_LOCK_CHK_DLY_TIME, ++ QPHY_FLL_CNTRL1, ++ QPHY_FLL_CNTRL2, ++ QPHY_FLL_CNT_VAL_L, ++ QPHY_FLL_CNT_VAL_H_TOL, ++ QPHY_FLL_MAN_CODE, ++ QPHY_SW_RESET, ++ QPHY_START_CTRL, ++ QPHY_PCS_READY_STATUS, ++ QPHY_PCS_STATUS, ++ QPHY_PCS_AUTONOMOUS_MODE_CTRL, ++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, ++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, ++ QPHY_PCS_POWER_DOWN_CONTROL, ++ /* PCS_MISC registers */ ++ QPHY_PCS_MISC_TYPEC_CTRL, ++ /* Keep last to ensure regs_layout arrays are properly initialized */ ++ QPHY_LAYOUT_SIZE ++}; ++ ++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_COM_SW_RESET] = 0x400, ++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, ++ [QPHY_COM_START_CONTROL] = 0x408, ++ [QPHY_COM_PCS_READY_STATUS] = 0x448, ++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, ++ [QPHY_FLL_CNTRL1] = 0xc4, ++ [QPHY_FLL_CNTRL2] = 0xc8, ++ [QPHY_FLL_CNT_VAL_L] = 0xcc, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, ++ [QPHY_FLL_MAN_CODE] = 0xd4, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_FLL_CNTRL1] = 0xc0, ++ [QPHY_FLL_CNTRL2] = 0xc4, ++ [QPHY_FLL_CNT_VAL_L] = 0xc8, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, ++ [QPHY_FLL_MAN_CODE] = 0xd0, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x17c, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, ++}; ++ ++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, ++}; ++ ++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x2ac, ++}; ++ ++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, ++}; ++ ++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, ++}; ++ ++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, ++}; ++ ++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, ++}; ++ ++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x160, ++}; ++ ++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, ++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, ++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), ++ ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), ++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), ++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), ++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), ++}; ++ ++/* Register names should be validated, they might be different for this PHY */ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), ++}; ++ ++struct qmp_phy; ++ ++/* struct qmp_phy_cfg - per-PHY initialization config */ ++struct qmp_phy_cfg { ++ /* phy-type - PCIE/UFS/USB */ ++ unsigned int type; ++ /* number of lanes provided by phy */ ++ int nlanes; ++ ++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ ++ const struct qmp_phy_init_tbl *serdes_tbl; ++ int serdes_tbl_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_sec; ++ int serdes_tbl_num_sec; ++ const struct qmp_phy_init_tbl *tx_tbl; ++ int tx_tbl_num; ++ const struct qmp_phy_init_tbl *tx_tbl_sec; ++ int tx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *rx_tbl; ++ int rx_tbl_num; ++ const struct qmp_phy_init_tbl *rx_tbl_sec; ++ int rx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_tbl; ++ int pcs_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_tbl_sec; ++ int pcs_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl; ++ int pcs_misc_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; ++ int pcs_misc_tbl_num_sec; ++ ++ /* Init sequence for DP PHY block link rates */ ++ const struct qmp_phy_init_tbl *serdes_tbl_rbr; ++ int serdes_tbl_rbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr; ++ int serdes_tbl_hbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2; ++ int serdes_tbl_hbr2_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3; ++ int serdes_tbl_hbr3_num; ++ ++ /* DP PHY callbacks */ ++ int (*configure_dp_phy)(struct qmp_phy *qphy); ++ void (*configure_dp_tx)(struct qmp_phy *qphy); ++ int (*calibrate_dp_phy)(struct qmp_phy *qphy); ++ void (*dp_aux_init)(struct qmp_phy *qphy); ++ ++ /* clock ids to be requested */ ++ const char * const *clk_list; ++ int num_clks; ++ /* resets to be requested */ ++ const char * const *reset_list; ++ int num_resets; ++ /* regulators to be requested */ ++ const char * const *vreg_list; ++ int num_vregs; ++ ++ /* array of registers with different offsets */ ++ const unsigned int *regs; ++ ++ unsigned int start_ctrl; ++ unsigned int pwrdn_ctrl; ++ unsigned int mask_com_pcs_ready; ++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ ++ unsigned int phy_status; ++ ++ /* true, if PHY has a separate PHY_COM control block */ ++ bool has_phy_com_ctrl; ++ /* true, if PHY has a reset for individual lanes */ ++ bool has_lane_rst; ++ /* true, if PHY needs delay after POWER_DOWN */ ++ bool has_pwrdn_delay; ++ /* power_down delay in usec */ ++ int pwrdn_delay_min; ++ int pwrdn_delay_max; ++ ++ /* true, if PHY has a separate DP_COM control block */ ++ bool has_phy_dp_com_ctrl; ++ /* true, if PHY has secondary tx/rx lanes to be configured */ ++ bool is_dual_lane_phy; ++ ++ /* true, if PCS block has no separate SW_RESET register */ ++ bool no_pcs_sw_reset; ++}; ++ ++struct qmp_phy_combo_cfg { ++ const struct qmp_phy_cfg *usb_cfg; ++ const struct qmp_phy_cfg *dp_cfg; ++}; ++ ++/** ++ * struct qmp_phy - per-lane phy descriptor ++ * ++ * @phy: generic phy ++ * @cfg: phy specific configuration ++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL) ++ * @tx: iomapped memory space for lane's tx ++ * @rx: iomapped memory space for lane's rx ++ * @pcs: iomapped memory space for lane's pcs ++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) ++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) ++ * @pcs_misc: iomapped memory space for lane's pcs_misc ++ * @pipe_clk: pipe clock ++ * @index: lane index ++ * @qmp: QMP phy to which this lane belongs ++ * @lane_rst: lane's reset controller ++ * @mode: current PHY mode ++ * @dp_aux_cfg: Display port aux config ++ * @dp_opts: Display port optional config ++ * @dp_clks: Display port clocks ++ */ ++struct qmp_phy { ++ struct phy *phy; ++ const struct qmp_phy_cfg *cfg; ++ void __iomem *serdes; ++ void __iomem *tx; ++ void __iomem *rx; ++ void __iomem *pcs; ++ void __iomem *tx2; ++ void __iomem *rx2; ++ void __iomem *pcs_misc; ++ struct clk *pipe_clk; ++ unsigned int index; ++ struct qcom_qmp *qmp; ++ struct reset_control *lane_rst; ++ enum phy_mode mode; ++ unsigned int dp_aux_cfg; ++ struct phy_configure_opts_dp dp_opts; ++ struct qmp_phy_dp_clks *dp_clks; ++}; ++ ++struct qmp_phy_dp_clks { ++ struct qmp_phy *qphy; ++ struct clk_hw dp_link_hw; ++ struct clk_hw dp_pixel_hw; ++}; ++ ++/** ++ * struct qcom_qmp - structure holding QMP phy block attributes ++ * ++ * @dev: device ++ * @dp_com: iomapped memory space for phy's dp_com control block ++ * ++ * @clks: array of clocks required by phy ++ * @resets: array of resets required by phy ++ * @vregs: regulator supplies bulk data ++ * ++ * @phys: array of per-lane phy descriptors ++ * @phy_mutex: mutex lock for PHY common block initialization ++ * @init_count: phy common block initialization count ++ * @ufs_reset: optional UFS PHY reset handle ++ */ ++struct qcom_qmp { ++ struct device *dev; ++ void __iomem *dp_com; ++ ++ struct clk_bulk_data *clks; ++ struct reset_control **resets; ++ struct regulator_bulk_data *vregs; ++ ++ struct qmp_phy **phys; ++ ++ struct mutex phy_mutex; ++ int init_count; ++ ++ struct reset_control *ufs_reset; ++}; ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg |= val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg &= ~val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++/* list of clocks required by phy */ ++static const char * const msm8996_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", ++}; ++ ++static const char * const msm8996_ufs_phy_clk_l[] = { ++ "ref", ++}; ++ ++static const char * const qmp_v3_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "com_aux", ++}; ++ ++static const char * const sdm845_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "refgen", ++}; ++ ++static const char * const qmp_v4_phy_clk_l[] = { ++ "aux", "ref_clk_src", "ref", "com_aux", ++}; ++ ++/* the primary usb3 phy on sm8250 doesn't have a ref clock */ ++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { ++ "aux", "ref_clk_src", "com_aux" ++}; ++ ++static const char * const sm8450_ufs_phy_clk_l[] = { ++ "qref", "ref", "ref_aux", ++}; ++ ++static const char * const sdm845_ufs_phy_clk_l[] = { ++ "ref", "ref_aux", ++}; ++ ++/* usb3 phy on sdx55 doesn't have com_aux clock */ ++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { ++ "aux", "cfg_ahb", "ref" ++}; ++ ++static const char * const qcm2290_usb3phy_clk_l[] = { ++ "cfg_ahb", "ref", "com_aux", ++}; ++ ++/* list of resets */ ++static const char * const msm8996_pciephy_reset_l[] = { ++ "phy", "common", "cfg", ++}; ++ ++static const char * const msm8996_usb3phy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const char * const sc7180_usb3phy_reset_l[] = { ++ "phy", ++}; ++ ++static const char * const qcm2290_usb3phy_reset_l[] = { ++ "phy_phy", "phy", ++}; ++ ++static const char * const sdm845_pciephy_reset_l[] = { ++ "phy", ++}; ++ ++/* list of regulators */ ++static const char * const qmp_phy_vreg_l[] = { ++ "vdda-phy", "vdda-pll", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = ipq8074_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), ++ .pcs_tbl = ipq8074_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 3, ++ ++ .serdes_tbl = msm8996_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), ++ .tx_tbl = msm8996_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), ++ .rx_tbl = msm8996_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), ++ .pcs_tbl = msm8996_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | PLL_READY_GATE_EN, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .mask_com_pcs_ready = PCS_READY, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = true, ++ .has_lane_rst = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg msm8996_ufs_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_ufs_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), ++ .tx_tbl = msm8996_ufs_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), ++ .rx_tbl = msm8996_ufs_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), ++ ++ .clk_list = msm8996_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), ++ ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ ++ .regs = msm8996_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = msm8996_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), ++ .pcs_tbl = msm8996_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const char * const ipq8074_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", ++}; ++/* list of resets */ ++static const char * const ipq8074_pciephy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), ++ .rx_tbl = ipq8074_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq6018_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), ++ .tx_tbl = ipq6018_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), ++ .rx_tbl = ipq6018_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), ++ .pcs_tbl = ipq6018_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = ipq_pciephy_gen3_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qmp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qhp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qhp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qhp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, ++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), ++ .tx_tbl = qmp_v3_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { ++ .usb_cfg = &sc7180_usb3phy_cfg, ++ .dp_cfg = &sc7180_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdm845_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), ++ .tx_tbl = sdm845_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), ++ .rx_tbl = sdm845_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), ++ .pcs_tbl = sdm845_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm6115_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), ++ .tx_tbl = sm6115_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), ++ .rx_tbl = sm6115_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), ++ .pcs_tbl = sm6115_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm6115_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ ++ .is_dual_lane_phy = false, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8998_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), ++ .tx_tbl = msm8998_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), ++ .rx_tbl = msm8998_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), ++ .pcs_tbl = msm8998_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), ++ .tx_tbl = msm8998_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), ++ .rx_tbl = msm8998_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), ++ .pcs_tbl = msm8998_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8150_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), ++ .tx_tbl = sm8150_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), ++ .rx_tbl = sm8150_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), ++ .pcs_tbl = sm8150_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8150_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), ++ .rx_tbl = sm8150_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), ++ .pcs_tbl = sm8150_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), ++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), ++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), ++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { ++ .usb_cfg = &sm8150_usb3phy_cfg, ++ .dp_cfg = &sc8180x_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8250_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), ++ .rx_tbl = sm8250_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), ++ .pcs_tbl = sm8250_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { ++ .usb_cfg = &sm8250_usb3phy_cfg, ++ .dp_cfg = &sm8250_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdx55_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), ++ .rx_tbl = sdx55_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8350_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), ++ .rx_tbl = sm8350_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), ++ .pcs_tbl = sm8350_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sm8450_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qcm2290_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), ++ .tx_tbl = qcm2290_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), ++ .rx_tbl = qcm2290_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), ++ .pcs_tbl = qcm2290_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), ++ .clk_list = qcm2290_usb3phy_clk_l, ++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), ++ .reset_list = qcm2290_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qcm2290_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static void qcom_qmp_phy_configure_lane(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num, ++ u8 lane_mask) ++{ ++ int i; ++ const struct qmp_phy_init_tbl *t = tbl; ++ ++ if (!t) ++ return; ++ ++ for (i = 0; i < num; i++, t++) { ++ if (!(t->lane_mask & lane_mask)) ++ continue; ++ ++ if (t->in_layout) ++ writel(t->val, base + regs[t->offset]); ++ else ++ writel(t->val, base + t->offset); ++ } ++} ++ ++static void qcom_qmp_phy_configure(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num) ++{ ++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++} ++ ++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; ++ int serdes_tbl_num = cfg->serdes_tbl_num; ++ int ret; ++ ++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ if (cfg->serdes_tbl_sec) ++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ cfg->serdes_tbl_num_sec); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ switch (dp_opts->link_rate) { ++ case 1620: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_rbr, ++ cfg->serdes_tbl_rbr_num); ++ break; ++ case 2700: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr, ++ cfg->serdes_tbl_hbr_num); ++ break; ++ case 5400: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr2, ++ cfg->serdes_tbl_hbr2_num); ++ break; ++ case 8100: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr3, ++ cfg->serdes_tbl_hbr3_num); ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ } ++ ++ ++ if (cfg->has_phy_com_ctrl) { ++ void __iomem *status; ++ unsigned int mask, val; ++ ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ ++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; ++ mask = cfg->mask_com_pcs_ready; ++ ++ ret = readl_poll_timeout(status, val, (val & mask), 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, ++ "phy common block init timed-out\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_LANE_0_1_PWRDN | ++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | ++ DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(QSERDES_V3_COM_BIAS_EN | ++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | ++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { ++ { 0x00, 0x0c, 0x15, 0x1a }, ++ { 0x02, 0x0e, 0x16, 0xff }, ++ { 0x02, 0x11, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { ++ { 0x02, 0x12, 0x16, 0x1a }, ++ { 0x09, 0x19, 0x1f, 0xff }, ++ { 0x10, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { ++ { 0x00, 0x0c, 0x14, 0x19 }, ++ { 0x00, 0x0b, 0x12, 0xff }, ++ { 0x00, 0x0b, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { ++ { 0x08, 0x0f, 0x16, 0x1f }, ++ { 0x11, 0x1e, 0x1f, 0xff }, ++ { 0x19, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, ++ unsigned int drv_lvl_reg, unsigned int emp_post_reg) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ unsigned int v_level = 0, p_level = 0; ++ u8 voltage_swing_cfg, pre_emphasis_cfg; ++ int i; ++ ++ for (i = 0; i < dp_opts->lanes; i++) { ++ v_level = max(v_level, dp_opts->voltage[i]); ++ p_level = max(p_level, dp_opts->pre[i]); ++ } ++ ++ if (dp_opts->link_rate <= 2700) { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; ++ } else { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; ++ } ++ ++ /* TODO: Move check to config check */ ++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) ++ return -EINVAL; ++ ++ /* Enable MUX to use Cursor values from these registers */ ++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; ++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; ++ ++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); ++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 bias_en, drvr_en; ++ ++ if (qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V3_TX_TX_DRV_LVL, ++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) ++ return; ++ ++ if (dp_opts->lanes == 1) { ++ bias_en = 0x3e; ++ drvr_en = 0x13; ++ } else { ++ bias_en = 0x3f; ++ drvr_en = 0x10; ++ } ++ ++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++} ++ ++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) ++{ ++ u32 val; ++ bool reverse = false; ++ ++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; ++ ++ /* ++ * TODO: Assume orientation is CC1 for now and two lanes, need to ++ * use type-c connector to understand orientation and lanes. ++ * ++ * Otherwise val changes to be like below if this code understood ++ * the orientation of the type-c cable. ++ * ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) ++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) ++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ * if (orientation == ORIENTATION_CC2) ++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); ++ */ ++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); ++ ++ return reverse; ++} ++ ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ ++ qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000); ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ /* Program default values before writing proper values */ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V4_TX_TX_DRV_LVL, ++ QSERDES_V4_TX_TX_EMP_POST1_LVL); ++} ++ ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en; ++ bool reverse; ++ ++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); ++ ++ reverse = qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ /* ++ * At least for 7nm DP PHY this has to be done after enabling link ++ * clock. ++ */ ++ ++ if (dp_opts->lanes == 1) { ++ bias0_en = reverse ? 0x3e : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3e; ++ drvr0_en = reverse ? 0x13 : 0x10; ++ drvr1_en = reverse ? 0x10 : 0x13; ++ } else if (dp_opts->lanes == 2) { ++ bias0_en = reverse ? 0x3f : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } else { ++ bias0_en = 0x3f; ++ bias1_en = 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } ++ ++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); ++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); ++ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ return 0; ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &opts->dp; ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); ++ if (qphy->dp_opts.set_voltages) { ++ cfg->configure_dp_tx(qphy); ++ qphy->dp_opts.set_voltages = 0; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_calibrate(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->calibrate_dp_phy) ++ return cfg->calibrate_dp_phy(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *dp_com = qmp->dp_com; ++ int ret, i; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (qmp->init_count++) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ /* turn on regulator supplies */ ++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); ++ if (ret) { ++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ++ goto err_unlock; ++ } ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ ret = reset_control_assert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset assert failed\n", ++ cfg->reset_list[i]); ++ goto err_disable_regulators; ++ } ++ } ++ ++ for (i = cfg->num_resets - 1; i >= 0; i--) { ++ ret = reset_control_deassert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset deassert failed\n", ++ qphy->cfg->reset_list[i]); ++ goto err_assert_reset; ++ } ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ goto err_assert_reset; ++ ++ if (cfg->has_phy_dp_com_ctrl) { ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, ++ SW_PWRDN); ++ /* override hardware control for reset of qmp phy */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ /* Default type-c orientation, i.e CC1 */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); ++ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, ++ USB3_MODE | DP_MODE); ++ ++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); ++ } ++ ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } else { ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) ++ qphy_setbits(pcs, ++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ else ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++ ++err_assert_reset: ++ while (++i < cfg->num_resets) ++ reset_control_assert(qmp->resets[i]); ++err_disable_regulators: ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++err_unlock: ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ int i = cfg->num_resets; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (--qmp->init_count) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ reset_control_assert(qmp->ufs_reset); ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], ++ SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } ++ ++ while (--i >= 0) ++ reset_control_assert(qmp->resets[i]); ++ ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_init(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret; ++ dev_vdbg(qmp->dev, "Initializing QMP phy\n"); ++ ++ if (cfg->no_pcs_sw_reset) { ++ /* ++ * Get UFS reset, which is delayed until now to avoid a ++ * circular dependency where UFS needs its PHY, but the PHY ++ * needs this UFS reset. ++ */ ++ if (!qmp->ufs_reset) { ++ qmp->ufs_reset = ++ devm_reset_control_get_exclusive(qmp->dev, ++ "ufsphy"); ++ ++ if (IS_ERR(qmp->ufs_reset)) { ++ ret = PTR_ERR(qmp->ufs_reset); ++ dev_err(qmp->dev, ++ "failed to get UFS reset: %d\n", ++ ret); ++ ++ qmp->ufs_reset = NULL; ++ return ret; ++ } ++ } ++ ++ ret = reset_control_assert(qmp->ufs_reset); ++ if (ret) ++ return ret; ++ } ++ ++ ret = qcom_qmp_phy_com_init(qphy); ++ if (ret) ++ return ret; ++ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->dp_aux_init(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_power_on(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *tx = qphy->tx; ++ void __iomem *rx = qphy->rx; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ void __iomem *status; ++ unsigned int mask, val, ready; ++ int ret; ++ ++ qcom_qmp_phy_serdes_init(qphy); ++ ++ if (cfg->has_lane_rst) { ++ ret = reset_control_deassert(qphy->lane_rst); ++ if (ret) { ++ dev_err(qmp->dev, "lane%d reset deassert failed\n", ++ qphy->index); ++ return ret; ++ } ++ } ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); ++ goto err_reset_lane; ++ } ++ ++ /* Tx, Rx, and PCS configurations */ ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 1); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 1); ++ ++ /* Configuration for other LANE for USB-DP combo PHY */ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 2); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 2); ++ } ++ ++ /* Configure special DP tx tunings */ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->configure_dp_tx(qphy); ++ ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 1); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); ++ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 2); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl_sec, ++ cfg->rx_tbl_num_sec, 2); ++ } ++ ++ /* Configure link rate, swing, etc. */ ++ if (cfg->type == PHY_TYPE_DP) { ++ cfg->configure_dp_phy(qphy); ++ } else { ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); ++ } ++ ++ ret = reset_control_deassert(qmp->ufs_reset); ++ if (ret) ++ goto err_disable_pipe_clk; ++ ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ cfg->pcs_misc_tbl_num); ++ if (cfg->pcs_misc_tbl_sec) ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ cfg->pcs_misc_tbl_num_sec); ++ ++ /* ++ * Pull out PHY from POWER DOWN state. ++ * This is active low enable signal to power-down PHY. ++ */ ++ if(cfg->type == PHY_TYPE_PCIE) ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); ++ ++ if (cfg->has_pwrdn_delay) ++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); ++ ++ if (cfg->type != PHY_TYPE_DP) { ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ if (cfg->type == PHY_TYPE_UFS) { ++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; ++ mask = PCS_READY; ++ ready = PCS_READY; ++ } else { ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ } ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; ++ } ++ } ++ return 0; ++ ++err_disable_pipe_clk: ++ clk_disable_unprepare(qphy->pipe_clk); ++err_reset_lane: ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_power_off(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ /* Assert DP PHY power down */ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ } else { ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_exit(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ qcom_qmp_phy_com_exit(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_enable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_init(phy); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_power_on(phy); ++ if (ret) ++ qcom_qmp_phy_exit(phy); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_disable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_power_off(phy); ++ if (ret) ++ return ret; ++ return qcom_qmp_phy_exit(phy); ++} ++ ++static int qcom_qmp_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ ++ qphy->mode = mode; ++ ++ return 0; ++} ++ ++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ u32 intr_mask; ++ ++ if (qphy->mode == PHY_MODE_USB_HOST_SS || ++ qphy->mode == PHY_MODE_USB_DEVICE_SS) ++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; ++ else ++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ++ ++ /* Clear any pending interrupts status */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); ++ ++ /* Enable required PHY autonomous mode interrupts */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); ++ ++ /* Enable i/o clamp_n for autonomous mode */ ++ if (pcs_misc) ++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++} ++ ++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ ++ /* Disable i/o clamp_n on resume for normal mode */ ++ if (pcs_misc) ++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); ++ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ qcom_qmp_phy_enable_autonomous_mode(qphy); ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret = 0; ++ ++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ return ret; ++ } ++ ++ qcom_qmp_phy_disable_autonomous_mode(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_vregs; ++ int i; ++ ++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); ++ if (!qmp->vregs) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->vregs[i].supply = cfg->vreg_list[i]; ++ ++ return devm_regulator_bulk_get(dev, num, qmp->vregs); ++} ++ ++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int i; ++ ++ qmp->resets = devm_kcalloc(dev, cfg->num_resets, ++ sizeof(*qmp->resets), GFP_KERNEL); ++ if (!qmp->resets) ++ return -ENOMEM; ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ struct reset_control *rst; ++ const char *name = cfg->reset_list[i]; ++ ++ rst = devm_reset_control_get_exclusive(dev, name); ++ if (IS_ERR(rst)) { ++ dev_err(dev, "failed to get %s reset\n", name); ++ return PTR_ERR(rst); ++ } ++ qmp->resets[i] = rst; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_clks; ++ int i; ++ ++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); ++ if (!qmp->clks) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->clks[i].id = cfg->clk_list[i]; ++ ++ return devm_clk_bulk_get(dev, num, qmp->clks); ++} ++ ++static void phy_clk_release_provider(void *res) ++{ ++ of_clk_del_provider(res); ++} ++ ++/* ++ * Register a fixed rate pipe clock. ++ * ++ * The _pipe_clksrc generated by PHY goes to the GCC that gate ++ * controls it. The _pipe_clk coming out of the GCC is requested ++ * by the PHY driver for its operations. ++ * We register the _pipe_clksrc here. The gcc driver takes care ++ * of assigning this _pipe_clksrc as parent to _pipe_clk. ++ * Below picture shows this relationship. ++ * ++ * +---------------+ ++ * | PHY block |<<---------------------------------------+ ++ * | | | ++ * | +-------+ | +-----+ | ++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ ++ * clk | +-------+ | +-----+ ++ * +---------------+ ++ */ ++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) ++{ ++ struct clk_fixed_rate *fixed; ++ struct clk_init_data init = { }; ++ int ret; ++ ++ ret = of_property_read_string(np, "clock-output-names", &init.name); ++ if (ret) { ++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); ++ return ret; ++ } ++ ++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); ++ if (!fixed) ++ return -ENOMEM; ++ ++ init.ops = &clk_fixed_rate_ops; ++ ++ /* controllers using QMP phys use 125MHz pipe clock interface */ ++ fixed->fixed_rate = 125000000; ++ fixed->hw.init = &init; ++ ++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++/* ++ * Display Port PLL driver block diagram for branch clocks ++ * ++ * +------------------------------+ ++ * | DP_VCO_CLK | ++ * | | ++ * | +-------------------+ | ++ * | | (DP PLL/VCO) | | ++ * | +---------+---------+ | ++ * | v | ++ * | +----------+-----------+ | ++ * | | hsclk_divsel_clk_src | | ++ * | +----------+-----------+ | ++ * +------------------------------+ ++ * | ++ * +---------<---------v------------>----------+ ++ * | | ++ * +--------v----------------+ | ++ * | dp_phy_pll_link_clk | | ++ * | link_clk | | ++ * +--------+----------------+ | ++ * | | ++ * | | ++ * v v ++ * Input to DISPCC block | ++ * for link clk, crypto clk | ++ * and interface clock | ++ * | ++ * | ++ * +--------<------------+-----------------+---<---+ ++ * | | | ++ * +----v---------+ +--------v-----+ +--------v------+ ++ * | vco_divided | | vco_divided | | vco_divided | ++ * | _clk_src | | _clk_src | | _clk_src | ++ * | | | | | | ++ * |divsel_six | | divsel_two | | divsel_four | ++ * +-------+------+ +-----+--------+ +--------+------+ ++ * | | | ++ * v---->----------v-------------<------v ++ * | ++ * +----------+-----------------+ ++ * | dp_phy_pll_vco_div_clk | ++ * +---------+------------------+ ++ * | ++ * v ++ * Input to DISPCC block ++ * for DP pixel clock ++ * ++ */ ++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 1620000000UL / 2: ++ case 2700000000UL / 2: ++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ return 1620000000UL / 2; ++ case 2700: ++ return 2700000000UL / 2; ++ case 5400: ++ return 5400000000UL / 4; ++ case 8100: ++ return 8100000000UL / 6; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { ++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, ++}; ++ ++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 162000000: ++ case 270000000: ++ case 540000000: ++ case 810000000: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ return dp_opts->link_rate * 100000; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_link_clk_ops = { ++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, ++}; ++ ++static struct clk_hw * ++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct qmp_phy_dp_clks *dp_clks = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx >= 2) { ++ pr_err("%s: invalid index %u\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (idx == 0) ++ return &dp_clks->dp_link_hw; ++ ++ return &dp_clks->dp_pixel_hw; ++} ++ ++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, ++ struct device_node *np) ++{ ++ struct clk_init_data init = { }; ++ struct qmp_phy_dp_clks *dp_clks; ++ char name[64]; ++ int ret; ++ ++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); ++ if (!dp_clks) ++ return -ENOMEM; ++ ++ dp_clks->qphy = qphy; ++ qphy->dp_clks = dp_clks; ++ ++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_link_clk_ops; ++ init.name = name; ++ dp_clks->dp_link_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); ++ if (ret) ++ return ret; ++ ++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_pixel_clk_ops; ++ init.name = name; ++ dp_clks->dp_pixel_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++static const struct phy_ops qcom_qmp_phy_gen_ops = { ++ .init = qcom_qmp_phy_enable, ++ .exit = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_phy_dp_ops = { ++ .init = qcom_qmp_phy_init, ++ .configure = qcom_qmp_dp_phy_configure, ++ .power_on = qcom_qmp_phy_power_on, ++ .calibrate = qcom_qmp_dp_phy_calibrate, ++ .power_off = qcom_qmp_phy_power_off, ++ .exit = qcom_qmp_phy_exit, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_pcie_ufs_ops = { ++ .power_on = qcom_qmp_phy_enable, ++ .power_off = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static void qcom_qmp_reset_control_put(void *data) ++{ ++ reset_control_put(data); ++} ++ ++static ++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++ void __iomem *serdes, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct phy *generic_phy; ++ struct qmp_phy *qphy; ++ const struct phy_ops *ops; ++ char prop_name[MAX_PROP_NAME]; ++ int ret; ++ ++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); ++ if (!qphy) ++ return -ENOMEM; ++ ++ qphy->cfg = cfg; ++ qphy->serdes = serdes; ++ /* ++ * Get memory resources for each phy lane: ++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. ++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 ++ * For single lane PHYs: pcs_misc (optional) -> 3. ++ */ ++ qphy->tx = of_iomap(np, 0); ++ if (!qphy->tx) ++ return -ENOMEM; ++ ++ qphy->rx = of_iomap(np, 1); ++ if (!qphy->rx) ++ return -ENOMEM; ++ ++ qphy->pcs = of_iomap(np, 2); ++ if (!qphy->pcs) ++ return -ENOMEM; ++ ++ /* ++ * If this is a dual-lane PHY, then there should be registers for the ++ * second lane. Some old device trees did not specify this, so fall ++ * back to old legacy behavior of assuming they can be reached at an ++ * offset from the first lane. ++ */ ++ if (cfg->is_dual_lane_phy) { ++ qphy->tx2 = of_iomap(np, 3); ++ qphy->rx2 = of_iomap(np, 4); ++ if (!qphy->tx2 || !qphy->rx2) { ++ dev_warn(dev, ++ "Underspecified device tree, falling back to legacy register regions\n"); ++ ++ /* In the old version, pcs_misc is at index 3. */ ++ qphy->pcs_misc = qphy->tx2; ++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; ++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 5); ++ } ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 3); ++ } ++ ++ if (!qphy->pcs_misc) ++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ ++ /* ++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 ++ * based phys, so they essentially have pipe clock. So, ++ * we return error in case phy is USB3 or PIPE type. ++ * Otherwise, we initialize pipe clock to NULL for ++ * all phys that don't need this. ++ */ ++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id); ++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); ++ if (IS_ERR(qphy->pipe_clk)) { ++ if (cfg->type == PHY_TYPE_PCIE || ++ cfg->type == PHY_TYPE_USB3) { ++ ret = PTR_ERR(qphy->pipe_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, ++ "failed to get lane%d pipe_clk, %d\n", ++ id, ret); ++ return ret; ++ } ++ qphy->pipe_clk = NULL; ++ } ++ ++ /* Get lane reset, if any */ ++ if (cfg->has_lane_rst) { ++ snprintf(prop_name, sizeof(prop_name), "lane%d", id); ++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); ++ if (IS_ERR(qphy->lane_rst)) { ++ dev_err(dev, "failed to get lane%d reset\n", id); ++ return PTR_ERR(qphy->lane_rst); ++ } ++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, ++ qphy->lane_rst); ++ if (ret) ++ return ret; ++ } ++ ++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ++ ops = &qcom_qmp_pcie_ufs_ops; ++ else if (cfg->type == PHY_TYPE_DP) ++ ops = &qcom_qmp_phy_dp_ops; ++ else ++ ops = &qcom_qmp_phy_gen_ops; ++ ++ generic_phy = devm_phy_create(dev, np, ops); ++ if (IS_ERR(generic_phy)) { ++ ret = PTR_ERR(generic_phy); ++ dev_err(dev, "failed to create qphy %d\n", ret); ++ return ret; ++ } ++ ++ qphy->phy = generic_phy; ++ qphy->index = id; ++ qphy->qmp = qmp; ++ qmp->phys[id] = qphy; ++ phy_set_drvdata(generic_phy, qphy); ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,ipq8074-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-pcie-phy", ++ .data = &msm8996_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-ufs-phy", ++ .data = &msm8996_ufs_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-usb3-phy", ++ .data = &msm8996_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-pcie-phy", ++ .data = &msm8998_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-phy", ++ .data = &ipq8074_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-pcie-phy", ++ .data = &ipq6018_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-phy", ++ .data = &sc7180_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sc8180x-qmp-pcie-phy", ++ .data = &sc8180x_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8280xp-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sdm845-qhp-pcie-phy", ++ .data = &sdm845_qhp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-pcie-phy", ++ .data = &sdm845_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-phy", ++ .data = &qmp_v3_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy", ++ .data = &qmp_v3_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-usb3-phy", ++ .data = &msm8998_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm6115-qmp-ufs-phy", ++ .data = &sm6115_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm6350-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy", ++ .data = &sm8150_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-phy", ++ .data = &sm8250_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy", ++ .data = &sm8250_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", ++ .data = &sm8250_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-pcie-phy", ++ .data = &sdx55_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy", ++ .data = &sdx55_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy", ++ .data = &sdx65_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy", ++ .data = &sm8350_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", ++ .data = &sm8450_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", ++ .data = &sm8450_qmp_gen4x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-ufs-phy", ++ .data = &sm8450_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,qcm2290-qmp-usb3-phy", ++ .data = &qcm2290_usb3phy_cfg, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++ ++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ .data = &sc7180_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ .data = &sm8250_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ .data = &sc8180x_usb3dpphy_cfg, ++ }, ++ { } ++}; ++ ++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, ++ qcom_qmp_phy_runtime_resume, NULL) ++}; ++ ++static int qcom_qmp_phy_probe(struct platform_device *pdev) ++{ ++ struct qcom_qmp *qmp; ++ struct device *dev = &pdev->dev; ++ struct device_node *child; ++ struct phy_provider *phy_provider; ++ void __iomem *serdes; ++ void __iomem *usb_serdes; ++ void __iomem *dp_serdes = NULL; ++ const struct qmp_phy_combo_cfg *combo_cfg = NULL; ++ const struct qmp_phy_cfg *cfg = NULL; ++ const struct qmp_phy_cfg *usb_cfg = NULL; ++ const struct qmp_phy_cfg *dp_cfg = NULL; ++ int num, id, expected_phys; ++ int ret; ++ ++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); ++ if (!qmp) ++ return -ENOMEM; ++ ++ qmp->dev = dev; ++ dev_set_drvdata(dev, qmp); ++ ++ /* Get the specific init parameters of QMP phy */ ++ cfg = of_device_get_match_data(dev); ++ if (!cfg) { ++ const struct of_device_id *match; ++ ++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); ++ if (!match) ++ return -EINVAL; ++ ++ combo_cfg = match->data; ++ if (!combo_cfg) ++ return -EINVAL; ++ ++ usb_cfg = combo_cfg->usb_cfg; ++ cfg = usb_cfg; /* Setup clks and regulators */ ++ } ++ ++ /* per PHY serdes; usually located at base address */ ++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(serdes)) ++ return PTR_ERR(serdes); ++ ++ /* per PHY dp_com; if PHY has dp_com control block */ ++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(qmp->dp_com)) ++ return PTR_ERR(qmp->dp_com); ++ } ++ ++ if (combo_cfg) { ++ /* Only two serdes for combo PHY */ ++ dp_serdes = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(dp_serdes)) ++ return PTR_ERR(dp_serdes); ++ ++ dp_cfg = combo_cfg->dp_cfg; ++ expected_phys = 2; ++ } else { ++ expected_phys = cfg->nlanes; ++ } ++ ++ mutex_init(&qmp->phy_mutex); ++ ++ ret = qcom_qmp_phy_clk_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_reset_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to get regulator supplies: %d\n", ++ ret); ++ return ret; ++ } ++ ++ num = of_get_available_child_count(dev->of_node); ++ /* do we have a rogue child node ? */ ++ if (num > expected_phys) ++ return -EINVAL; ++ ++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); ++ if (!qmp->phys) ++ return -ENOMEM; ++ ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ /* ++ * Prevent runtime pm from being ON by default. Users can enable ++ * it using power/control in sysfs. ++ */ ++ pm_runtime_forbid(dev); ++ ++ id = 0; ++ for_each_available_child_of_node(dev->of_node, child) { ++ if (of_node_name_eq(child, "dp-phy")) { ++ cfg = dp_cfg; ++ serdes = dp_serdes; ++ } else if (of_node_name_eq(child, "usb3-phy")) { ++ cfg = usb_cfg; ++ serdes = usb_serdes; ++ } ++ ++ /* Create per-lane phy */ ++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ if (ret) { ++ dev_err(dev, "failed to create lane%d phy, %d\n", ++ id, ret); ++ goto err_node_put; ++ } ++ ++ /* ++ * Register the pipe clock provided by phy. ++ * See function description to see details of this pipe clock. ++ */ ++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; ++ } ++ } else if (cfg->type == PHY_TYPE_DP) { ++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register DP clock source\n"); ++ goto err_node_put; ++ } ++ } ++ id++; ++ } ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (!IS_ERR(phy_provider)) ++ dev_info(dev, "Registered Qcom-QMP phy\n"); ++ else ++ pm_runtime_disable(dev); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++ ++err_node_put: ++ pm_runtime_disable(dev); ++ of_node_put(child); ++ return ret; ++} ++ ++static struct platform_driver qcom_qmp_phy_driver = { ++ .probe = qcom_qmp_phy_probe, ++ .driver = { ++ .name = "qcom-qmp-phy", ++ .pm = &qcom_qmp_phy_pm_ops, ++ .of_match_table = qcom_qmp_phy_of_match_table, ++ }, ++}; ++ ++module_platform_driver(qcom_qmp_phy_driver); ++ ++MODULE_AUTHOR("Vivek Gautam "); ++MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +new file mode 100644 +index 000000000000..c7309e981bfb +--- /dev/null ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -0,0 +1,6350 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2017, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-qcom-qmp.h" ++ ++/* QPHY_SW_RESET bit */ ++#define SW_RESET BIT(0) ++/* QPHY_POWER_DOWN_CONTROL */ ++#define SW_PWRDN BIT(0) ++#define REFCLK_DRV_DSBL BIT(1) ++/* QPHY_START_CONTROL bits */ ++#define SERDES_START BIT(0) ++#define PCS_START BIT(1) ++#define PLL_READY_GATE_EN BIT(3) ++/* QPHY_PCS_STATUS bit */ ++#define PHYSTATUS BIT(6) ++#define PHYSTATUS_4_20 BIT(7) ++/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ ++#define PCS_READY BIT(0) ++ ++/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ ++/* DP PHY soft reset */ ++#define SW_DPPHY_RESET BIT(0) ++/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ ++#define SW_DPPHY_RESET_MUX BIT(1) ++/* USB3 PHY soft reset */ ++#define SW_USB3PHY_RESET BIT(2) ++/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ ++#define SW_USB3PHY_RESET_MUX BIT(3) ++ ++/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ ++#define USB3_MODE BIT(0) /* enables USB3 mode */ ++#define DP_MODE BIT(1) /* enables DP mode */ ++ ++/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ ++#define ARCVR_DTCT_EN BIT(0) ++#define ALFPS_DTCT_EN BIT(1) ++#define ARCVR_DTCT_EVENT_SEL BIT(4) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ ++#define IRQ_CLEAR BIT(0) ++ ++/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ ++#define RCVR_DETECT BIT(0) ++ ++/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ ++#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ ++ ++#define PHY_INIT_COMPLETE_TIMEOUT 10000 ++#define POWER_DOWN_DELAY_US_MIN 10 ++#define POWER_DOWN_DELAY_US_MAX 11 ++ ++#define MAX_PROP_NAME 32 ++ ++/* Define the assumed distance between lanes for underspecified device trees. */ ++#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 ++ ++struct qmp_phy_init_tbl { ++ unsigned int offset; ++ unsigned int val; ++ /* ++ * register part of layout ? ++ * if yes, then offset gives index in the reg-layout ++ */ ++ bool in_layout; ++ /* ++ * mask of lanes for which this register is written ++ * for cases when second lane needs different values ++ */ ++ u8 lane_mask; ++}; ++ ++#define QMP_PHY_INIT_CFG(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_L(o, v) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .in_layout = true, \ ++ .lane_mask = 0xff, \ ++ } ++ ++#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ ++ { \ ++ .offset = o, \ ++ .val = v, \ ++ .lane_mask = l, \ ++ } ++ ++/* set of registers with offsets different per-PHY */ ++enum qphy_reg_layout { ++ /* Common block control registers */ ++ QPHY_COM_SW_RESET, ++ QPHY_COM_POWER_DOWN_CONTROL, ++ QPHY_COM_START_CONTROL, ++ QPHY_COM_PCS_READY_STATUS, ++ /* PCS registers */ ++ QPHY_PLL_LOCK_CHK_DLY_TIME, ++ QPHY_FLL_CNTRL1, ++ QPHY_FLL_CNTRL2, ++ QPHY_FLL_CNT_VAL_L, ++ QPHY_FLL_CNT_VAL_H_TOL, ++ QPHY_FLL_MAN_CODE, ++ QPHY_SW_RESET, ++ QPHY_START_CTRL, ++ QPHY_PCS_READY_STATUS, ++ QPHY_PCS_STATUS, ++ QPHY_PCS_AUTONOMOUS_MODE_CTRL, ++ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, ++ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, ++ QPHY_PCS_POWER_DOWN_CONTROL, ++ /* PCS_MISC registers */ ++ QPHY_PCS_MISC_TYPEC_CTRL, ++ /* Keep last to ensure regs_layout arrays are properly initialized */ ++ QPHY_LAYOUT_SIZE ++}; ++ ++static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_COM_SW_RESET] = 0x400, ++ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, ++ [QPHY_COM_START_CONTROL] = 0x408, ++ [QPHY_COM_PCS_READY_STATUS] = 0x448, ++ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, ++ [QPHY_FLL_CNTRL1] = 0xc4, ++ [QPHY_FLL_CNTRL2] = 0xc8, ++ [QPHY_FLL_CNT_VAL_L] = 0xcc, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, ++ [QPHY_FLL_MAN_CODE] = 0xd4, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_FLL_CNTRL1] = 0xc0, ++ [QPHY_FLL_CNTRL2] = 0xc4, ++ [QPHY_FLL_CNT_VAL_L] = 0xc8, ++ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, ++ [QPHY_FLL_MAN_CODE] = 0xd0, ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x17c, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, ++}; ++ ++static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, ++}; ++ ++static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x174, ++}; ++ ++static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_STATUS] = 0x2ac, ++}; ++ ++static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, ++}; ++ ++static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, ++}; ++ ++static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, ++}; ++ ++static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, ++ [QPHY_START_CTRL] = 0x08, ++ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, ++ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, ++ [QPHY_PCS_STATUS] = 0x174, ++ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, ++}; ++ ++static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x160, ++}; ++ ++static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = 0x00, ++ [QPHY_PCS_READY_STATUS] = 0x168, ++}; ++ ++static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_SW_RESET] = 0x00, ++ [QPHY_START_CTRL] = 0x44, ++ [QPHY_PCS_STATUS] = 0x14, ++ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, ++}; ++ ++static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ++ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, ++ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, ++ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), ++ ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), ++ /* PLL and Loop filter settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ /* SSC settings */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++}; ++ ++static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), ++ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), ++ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), ++}; ++ ++static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), ++ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), ++ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), ++ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), ++ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), ++ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), ++ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { ++ /* FLL settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), ++ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), ++ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), ++}; ++ ++static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), ++ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), ++}; ++ ++static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), ++ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { ++ /* Lock Det settings */ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), ++}; ++ ++static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), ++ ++ /* Rate B */ ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), ++ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), ++}; ++ ++static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), ++ ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), ++}; ++ ++/* Register names should be validated, they might be different for this PHY */ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), ++}; ++ ++static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), ++ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), ++}; ++ ++struct qmp_phy; ++ ++/* struct qmp_phy_cfg - per-PHY initialization config */ ++struct qmp_phy_cfg { ++ /* phy-type - PCIE/UFS/USB */ ++ unsigned int type; ++ /* number of lanes provided by phy */ ++ int nlanes; ++ ++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ ++ const struct qmp_phy_init_tbl *serdes_tbl; ++ int serdes_tbl_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_sec; ++ int serdes_tbl_num_sec; ++ const struct qmp_phy_init_tbl *tx_tbl; ++ int tx_tbl_num; ++ const struct qmp_phy_init_tbl *tx_tbl_sec; ++ int tx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *rx_tbl; ++ int rx_tbl_num; ++ const struct qmp_phy_init_tbl *rx_tbl_sec; ++ int rx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_tbl; ++ int pcs_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_tbl_sec; ++ int pcs_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl; ++ int pcs_misc_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; ++ int pcs_misc_tbl_num_sec; ++ ++ /* Init sequence for DP PHY block link rates */ ++ const struct qmp_phy_init_tbl *serdes_tbl_rbr; ++ int serdes_tbl_rbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr; ++ int serdes_tbl_hbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2; ++ int serdes_tbl_hbr2_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3; ++ int serdes_tbl_hbr3_num; ++ ++ /* DP PHY callbacks */ ++ int (*configure_dp_phy)(struct qmp_phy *qphy); ++ void (*configure_dp_tx)(struct qmp_phy *qphy); ++ int (*calibrate_dp_phy)(struct qmp_phy *qphy); ++ void (*dp_aux_init)(struct qmp_phy *qphy); ++ ++ /* clock ids to be requested */ ++ const char * const *clk_list; ++ int num_clks; ++ /* resets to be requested */ ++ const char * const *reset_list; ++ int num_resets; ++ /* regulators to be requested */ ++ const char * const *vreg_list; ++ int num_vregs; ++ ++ /* array of registers with different offsets */ ++ const unsigned int *regs; ++ ++ unsigned int start_ctrl; ++ unsigned int pwrdn_ctrl; ++ unsigned int mask_com_pcs_ready; ++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ ++ unsigned int phy_status; ++ ++ /* true, if PHY has a separate PHY_COM control block */ ++ bool has_phy_com_ctrl; ++ /* true, if PHY has a reset for individual lanes */ ++ bool has_lane_rst; ++ /* true, if PHY needs delay after POWER_DOWN */ ++ bool has_pwrdn_delay; ++ /* power_down delay in usec */ ++ int pwrdn_delay_min; ++ int pwrdn_delay_max; ++ ++ /* true, if PHY has a separate DP_COM control block */ ++ bool has_phy_dp_com_ctrl; ++ /* true, if PHY has secondary tx/rx lanes to be configured */ ++ bool is_dual_lane_phy; ++ ++ /* true, if PCS block has no separate SW_RESET register */ ++ bool no_pcs_sw_reset; ++}; ++ ++struct qmp_phy_combo_cfg { ++ const struct qmp_phy_cfg *usb_cfg; ++ const struct qmp_phy_cfg *dp_cfg; ++}; ++ ++/** ++ * struct qmp_phy - per-lane phy descriptor ++ * ++ * @phy: generic phy ++ * @cfg: phy specific configuration ++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL) ++ * @tx: iomapped memory space for lane's tx ++ * @rx: iomapped memory space for lane's rx ++ * @pcs: iomapped memory space for lane's pcs ++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) ++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) ++ * @pcs_misc: iomapped memory space for lane's pcs_misc ++ * @pipe_clk: pipe clock ++ * @index: lane index ++ * @qmp: QMP phy to which this lane belongs ++ * @lane_rst: lane's reset controller ++ * @mode: current PHY mode ++ * @dp_aux_cfg: Display port aux config ++ * @dp_opts: Display port optional config ++ * @dp_clks: Display port clocks ++ */ ++struct qmp_phy { ++ struct phy *phy; ++ const struct qmp_phy_cfg *cfg; ++ void __iomem *serdes; ++ void __iomem *tx; ++ void __iomem *rx; ++ void __iomem *pcs; ++ void __iomem *tx2; ++ void __iomem *rx2; ++ void __iomem *pcs_misc; ++ struct clk *pipe_clk; ++ unsigned int index; ++ struct qcom_qmp *qmp; ++ struct reset_control *lane_rst; ++ enum phy_mode mode; ++ unsigned int dp_aux_cfg; ++ struct phy_configure_opts_dp dp_opts; ++ struct qmp_phy_dp_clks *dp_clks; ++}; ++ ++struct qmp_phy_dp_clks { ++ struct qmp_phy *qphy; ++ struct clk_hw dp_link_hw; ++ struct clk_hw dp_pixel_hw; ++}; ++ ++/** ++ * struct qcom_qmp - structure holding QMP phy block attributes ++ * ++ * @dev: device ++ * @dp_com: iomapped memory space for phy's dp_com control block ++ * ++ * @clks: array of clocks required by phy ++ * @resets: array of resets required by phy ++ * @vregs: regulator supplies bulk data ++ * ++ * @phys: array of per-lane phy descriptors ++ * @phy_mutex: mutex lock for PHY common block initialization ++ * @init_count: phy common block initialization count ++ * @ufs_reset: optional UFS PHY reset handle ++ */ ++struct qcom_qmp { ++ struct device *dev; ++ void __iomem *dp_com; ++ ++ struct clk_bulk_data *clks; ++ struct reset_control **resets; ++ struct regulator_bulk_data *vregs; ++ ++ struct qmp_phy **phys; ++ ++ struct mutex phy_mutex; ++ int init_count; ++ ++ struct reset_control *ufs_reset; ++}; ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); ++ ++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg |= val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; ++ ++ reg = readl(base + offset); ++ reg &= ~val; ++ writel(reg, base + offset); ++ ++ /* ensure that above write is through */ ++ readl(base + offset); ++} ++ ++/* list of clocks required by phy */ ++static const char * const msm8996_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", ++}; ++ ++static const char * const msm8996_ufs_phy_clk_l[] = { ++ "ref", ++}; ++ ++static const char * const qmp_v3_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "com_aux", ++}; ++ ++static const char * const sdm845_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", "refgen", ++}; ++ ++static const char * const qmp_v4_phy_clk_l[] = { ++ "aux", "ref_clk_src", "ref", "com_aux", ++}; ++ ++/* the primary usb3 phy on sm8250 doesn't have a ref clock */ ++static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { ++ "aux", "ref_clk_src", "com_aux" ++}; ++ ++static const char * const sm8450_ufs_phy_clk_l[] = { ++ "qref", "ref", "ref_aux", ++}; ++ ++static const char * const sdm845_ufs_phy_clk_l[] = { ++ "ref", "ref_aux", ++}; ++ ++/* usb3 phy on sdx55 doesn't have com_aux clock */ ++static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { ++ "aux", "cfg_ahb", "ref" ++}; ++ ++static const char * const qcm2290_usb3phy_clk_l[] = { ++ "cfg_ahb", "ref", "com_aux", ++}; ++ ++/* list of resets */ ++static const char * const msm8996_pciephy_reset_l[] = { ++ "phy", "common", "cfg", ++}; ++ ++static const char * const msm8996_usb3phy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const char * const sc7180_usb3phy_reset_l[] = { ++ "phy", ++}; ++ ++static const char * const qcm2290_usb3phy_reset_l[] = { ++ "phy_phy", "phy", ++}; ++ ++static const char * const sdm845_pciephy_reset_l[] = { ++ "phy", ++}; ++ ++/* list of regulators */ ++static const char * const qmp_phy_vreg_l[] = { ++ "vdda-phy", "vdda-pll", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = ipq8074_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), ++ .pcs_tbl = ipq8074_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 3, ++ ++ .serdes_tbl = msm8996_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), ++ .tx_tbl = msm8996_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), ++ .rx_tbl = msm8996_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), ++ .pcs_tbl = msm8996_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | PLL_READY_GATE_EN, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .mask_com_pcs_ready = PCS_READY, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = true, ++ .has_lane_rst = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg msm8996_ufs_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_ufs_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), ++ .tx_tbl = msm8996_ufs_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), ++ .rx_tbl = msm8996_ufs_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), ++ ++ .clk_list = msm8996_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), ++ ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ ++ .regs = msm8996_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8996_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), ++ .tx_tbl = msm8996_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), ++ .rx_tbl = msm8996_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), ++ .pcs_tbl = msm8996_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const char * const ipq8074_pciephy_clk_l[] = { ++ "aux", "cfg_ahb", ++}; ++/* list of resets */ ++static const char * const ipq8074_pciephy_reset_l[] = { ++ "phy", "common", ++}; ++ ++static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq8074_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), ++ .tx_tbl = ipq8074_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), ++ .rx_tbl = ipq8074_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), ++ .pcs_tbl = ipq8074_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = ipq6018_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), ++ .tx_tbl = ipq6018_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), ++ .rx_tbl = ipq6018_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), ++ .pcs_tbl = ipq6018_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), ++ .clk_list = ipq8074_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = ipq_pciephy_gen3_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_phy_com_ctrl = false, ++ .has_lane_rst = false, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qmp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), ++ .tx_tbl = sdm845_qhp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), ++ .rx_tbl = sdm845_qhp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), ++ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_qhp_pciephy_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), ++ .tx_tbl = sm8250_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), ++ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, ++ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), ++ .rx_tbl = sm8250_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), ++ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, ++ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), ++ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), ++ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, ++ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), ++ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc7180_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), ++ .tx_tbl = qmp_v3_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { ++ .usb_cfg = &sc7180_usb3phy_cfg, ++ .dp_cfg = &sc7180_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), ++ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), ++ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), ++ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdm845_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), ++ .tx_tbl = sdm845_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), ++ .rx_tbl = sdm845_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), ++ .pcs_tbl = sdm845_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sdm845_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm6115_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), ++ .tx_tbl = sm6115_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), ++ .rx_tbl = sm6115_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), ++ .pcs_tbl = sm6115_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm6115_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ ++ .is_dual_lane_phy = false, ++ .no_pcs_sw_reset = true, ++}; ++ ++static const struct qmp_phy_cfg msm8998_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), ++ .tx_tbl = msm8998_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), ++ .rx_tbl = msm8998_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), ++ .pcs_tbl = msm8998_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = pciephy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++}; ++ ++static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = msm8998_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), ++ .tx_tbl = msm8998_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), ++ .rx_tbl = msm8998_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), ++ .pcs_tbl = msm8998_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8150_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), ++ .tx_tbl = sm8150_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), ++ .rx_tbl = sm8150_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), ++ .pcs_tbl = sm8150_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8150_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), ++ .rx_tbl = sm8150_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), ++ .pcs_tbl = sm8150_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), ++ .tx_tbl = sc8180x_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), ++ .rx_tbl = sc8180x_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), ++ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v3_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), ++ .reset_list = sc7180_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v3_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { ++ .usb_cfg = &sm8150_usb3phy_cfg, ++ .dp_cfg = &sc8180x_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8150_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8150_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8250_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), ++ .rx_tbl = sm8250_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), ++ .pcs_tbl = sm8250_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8250_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8250_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8250_dpphy_cfg = { ++ .type = PHY_TYPE_DP, ++ .nlanes = 1, ++ ++ .serdes_tbl = qmp_v4_dp_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), ++ .tx_tbl = qmp_v4_dp_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), ++ ++ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, ++ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ++ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, ++ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), ++ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, ++ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), ++ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, ++ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), ++ ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++ ++ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, ++ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, ++ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, ++ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, ++}; ++ ++static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { ++ .usb_cfg = &sm8250_usb3phy_cfg, ++ .dp_cfg = &sm8250_dpphy_cfg, ++}; ++ ++static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx55_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx55_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), ++ .tx_tbl = sdx55_qmp_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), ++ .rx_tbl = sdx55_qmp_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), ++ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), ++ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = PCS_START | SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sdx65_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), ++ .rx_tbl = sdx65_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_sdx55_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sdm845_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), ++ .tx_tbl = sm8350_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), ++ .rx_tbl = sm8350_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), ++ .pcs_tbl = sm8350_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), ++ .clk_list = qmp_v4_sm8250_usbphy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qmp_v4_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ ++ .has_phy_dp_com_ctrl = true, ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), ++ .tx_tbl = sm8350_usb3_uniphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), ++ .rx_tbl = sm8350_usb3_uniphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), ++ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), ++ .clk_list = qmp_v4_phy_clk_l, ++ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), ++ .reset_list = msm8996_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8350_usb3_uniphy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++}; ++ ++static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { ++ .type = PHY_TYPE_UFS, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8350_ufsphy_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), ++ .tx_tbl = sm8350_ufsphy_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), ++ .rx_tbl = sm8350_ufsphy_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), ++ .pcs_tbl = sm8350_ufsphy_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), ++ .clk_list = sm8450_ufs_phy_clk_l, ++ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8150_ufsphy_regs_layout, ++ ++ .start_ctrl = SERDES_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 1, ++ ++ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 2, ++ ++ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), ++ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), ++ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), ++ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), ++ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, ++ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), ++ .clk_list = sdm845_pciephy_clk_l, ++ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), ++ .reset_list = sdm845_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = sm8250_pcie_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS_4_20, ++ ++ .is_dual_lane_phy = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = 995, /* us */ ++ .pwrdn_delay_max = 1005, /* us */ ++}; ++ ++static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ++ .type = PHY_TYPE_USB3, ++ .nlanes = 1, ++ ++ .serdes_tbl = qcm2290_usb3_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), ++ .tx_tbl = qcm2290_usb3_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), ++ .rx_tbl = qcm2290_usb3_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), ++ .pcs_tbl = qcm2290_usb3_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), ++ .clk_list = qcm2290_usb3phy_clk_l, ++ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), ++ .reset_list = qcm2290_usb3phy_reset_l, ++ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), ++ .vreg_list = qmp_phy_vreg_l, ++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), ++ .regs = qcm2290_usb3phy_regs_layout, ++ ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, ++ .phy_status = PHYSTATUS, ++ ++ .is_dual_lane_phy = true, ++}; ++ ++static void qcom_qmp_phy_configure_lane(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num, ++ u8 lane_mask) ++{ ++ int i; ++ const struct qmp_phy_init_tbl *t = tbl; ++ ++ if (!t) ++ return; ++ ++ for (i = 0; i < num; i++, t++) { ++ if (!(t->lane_mask & lane_mask)) ++ continue; ++ ++ if (t->in_layout) ++ writel(t->val, base + regs[t->offset]); ++ else ++ writel(t->val, base + t->offset); ++ } ++} ++ ++static void qcom_qmp_phy_configure(void __iomem *base, ++ const unsigned int *regs, ++ const struct qmp_phy_init_tbl tbl[], ++ int num) ++{ ++ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++} ++ ++static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; ++ int serdes_tbl_num = cfg->serdes_tbl_num; ++ int ret; ++ ++ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ if (cfg->serdes_tbl_sec) ++ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ cfg->serdes_tbl_num_sec); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ switch (dp_opts->link_rate) { ++ case 1620: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_rbr, ++ cfg->serdes_tbl_rbr_num); ++ break; ++ case 2700: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr, ++ cfg->serdes_tbl_hbr_num); ++ break; ++ case 5400: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr2, ++ cfg->serdes_tbl_hbr2_num); ++ break; ++ case 8100: ++ qcom_qmp_phy_configure(serdes, cfg->regs, ++ cfg->serdes_tbl_hbr3, ++ cfg->serdes_tbl_hbr3_num); ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ } ++ ++ ++ if (cfg->has_phy_com_ctrl) { ++ void __iomem *status; ++ unsigned int mask, val; ++ ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ ++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; ++ mask = cfg->mask_com_pcs_ready; ++ ++ ret = readl_poll_timeout(status, val, (val & mask), 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, ++ "phy common block init timed-out\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_LANE_0_1_PWRDN | ++ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | ++ DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(QSERDES_V3_COM_BIAS_EN | ++ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | ++ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | ++ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, ++ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { ++ { 0x00, 0x0c, 0x15, 0x1a }, ++ { 0x02, 0x0e, 0x16, 0xff }, ++ { 0x02, 0x11, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { ++ { 0x02, 0x12, 0x16, 0x1a }, ++ { 0x09, 0x19, 0x1f, 0xff }, ++ { 0x10, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { ++ { 0x00, 0x0c, 0x14, 0x19 }, ++ { 0x00, 0x0b, 0x12, 0xff }, ++ { 0x00, 0x0b, 0xff, 0xff }, ++ { 0x04, 0xff, 0xff, 0xff } ++}; ++ ++static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { ++ { 0x08, 0x0f, 0x16, 0x1f }, ++ { 0x11, 0x1e, 0x1f, 0xff }, ++ { 0x19, 0x1f, 0xff, 0xff }, ++ { 0x1f, 0xff, 0xff, 0xff } ++}; ++ ++static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, ++ unsigned int drv_lvl_reg, unsigned int emp_post_reg) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ unsigned int v_level = 0, p_level = 0; ++ u8 voltage_swing_cfg, pre_emphasis_cfg; ++ int i; ++ ++ for (i = 0; i < dp_opts->lanes; i++) { ++ v_level = max(v_level, dp_opts->voltage[i]); ++ p_level = max(p_level, dp_opts->pre[i]); ++ } ++ ++ if (dp_opts->link_rate <= 2700) { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; ++ } else { ++ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; ++ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; ++ } ++ ++ /* TODO: Move check to config check */ ++ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) ++ return -EINVAL; ++ ++ /* Enable MUX to use Cursor values from these registers */ ++ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; ++ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; ++ ++ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); ++ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); ++ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 bias_en, drvr_en; ++ ++ if (qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V3_TX_TX_DRV_LVL, ++ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) ++ return; ++ ++ if (dp_opts->lanes == 1) { ++ bias_en = 0x3e; ++ drvr_en = 0x13; ++ } else { ++ bias_en = 0x3f; ++ drvr_en = 0x10; ++ } ++ ++ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); ++ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); ++} ++ ++static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) ++{ ++ u32 val; ++ bool reverse = false; ++ ++ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; ++ ++ /* ++ * TODO: Assume orientation is CC1 for now and two lanes, need to ++ * use type-c connector to understand orientation and lanes. ++ * ++ * Otherwise val changes to be like below if this code understood ++ * the orientation of the type-c cable. ++ * ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) ++ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; ++ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) ++ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ * if (orientation == ORIENTATION_CC2) ++ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); ++ */ ++ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; ++ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); ++ ++ return reverse; ++} ++ ++static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ ++ qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000); ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) ++{ ++ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | ++ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ++ qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ ++ /* Turn on BIAS current for PHY/PLL */ ++ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); ++ ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); ++ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); ++ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); ++ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); ++ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); ++ qphy->dp_aux_cfg = 0; ++ ++ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | ++ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ++ PHY_AUX_REQ_ERR_MASK, ++ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); ++} ++ ++static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) ++{ ++ /* Program default values before writing proper values */ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ qcom_qmp_phy_configure_dp_swing(qphy, ++ QSERDES_V4_TX_TX_DRV_LVL, ++ QSERDES_V4_TX_TX_EMP_POST1_LVL); ++} ++ ++static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; ++ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; ++ u32 phy_vco_div, status; ++ unsigned long pixel_freq; ++ u32 bias0_en, drvr0_en, bias1_en, drvr1_en; ++ bool reverse; ++ ++ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); ++ ++ reverse = qcom_qmp_phy_configure_dp_mode(qphy); ++ ++ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); ++ ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); ++ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ phy_vco_div = 0x1; ++ pixel_freq = 1620000000UL / 2; ++ break; ++ case 2700: ++ phy_vco_div = 0x1; ++ pixel_freq = 2700000000UL / 2; ++ break; ++ case 5400: ++ phy_vco_div = 0x2; ++ pixel_freq = 5400000000UL / 4; ++ break; ++ case 8100: ++ phy_vco_div = 0x0; ++ pixel_freq = 8100000000UL / 6; ++ break; ++ default: ++ /* Other link rates aren't supported */ ++ return -EINVAL; ++ } ++ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); ++ ++ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); ++ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); ++ ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); ++ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(0)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ /* ++ * At least for 7nm DP PHY this has to be done after enabling link ++ * clock. ++ */ ++ ++ if (dp_opts->lanes == 1) { ++ bias0_en = reverse ? 0x3e : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3e; ++ drvr0_en = reverse ? 0x13 : 0x10; ++ drvr1_en = reverse ? 0x10 : 0x13; ++ } else if (dp_opts->lanes == 2) { ++ bias0_en = reverse ? 0x3f : 0x15; ++ bias1_en = reverse ? 0x15 : 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } else { ++ bias0_en = 0x3f; ++ bias1_en = 0x3f; ++ drvr0_en = 0x10; ++ drvr1_en = 0x10; ++ } ++ ++ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); ++ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); ++ ++ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); ++ udelay(2000); ++ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); ++ ++ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, ++ status, ++ ((status & BIT(1)) > 0), ++ 500, ++ 10000)) ++ return -ETIMEDOUT; ++ ++ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); ++ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); ++ ++ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); ++ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); ++ ++ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); ++ ++ return 0; ++} ++ ++/* ++ * We need to calibrate the aux setting here as many times ++ * as the caller tries ++ */ ++static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) ++{ ++ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; ++ u8 val; ++ ++ qphy->dp_aux_cfg++; ++ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); ++ val = cfg1_settings[qphy->dp_aux_cfg]; ++ ++ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) ++{ ++ const struct phy_configure_opts_dp *dp_opts = &opts->dp; ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); ++ if (qphy->dp_opts.set_voltages) { ++ cfg->configure_dp_tx(qphy); ++ qphy->dp_opts.set_voltages = 0; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_dp_phy_calibrate(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->calibrate_dp_phy) ++ return cfg->calibrate_dp_phy(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *dp_com = qmp->dp_com; ++ int ret, i; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (qmp->init_count++) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ /* turn on regulator supplies */ ++ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); ++ if (ret) { ++ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ++ goto err_unlock; ++ } ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ ret = reset_control_assert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset assert failed\n", ++ cfg->reset_list[i]); ++ goto err_disable_regulators; ++ } ++ } ++ ++ for (i = cfg->num_resets - 1; i >= 0; i--) { ++ ret = reset_control_deassert(qmp->resets[i]); ++ if (ret) { ++ dev_err(qmp->dev, "%s reset deassert failed\n", ++ qphy->cfg->reset_list[i]); ++ goto err_assert_reset; ++ } ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ goto err_assert_reset; ++ ++ if (cfg->has_phy_dp_com_ctrl) { ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, ++ SW_PWRDN); ++ /* override hardware control for reset of qmp phy */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ /* Default type-c orientation, i.e CC1 */ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); ++ ++ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, ++ USB3_MODE | DP_MODE); ++ ++ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, ++ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | ++ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); ++ ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); ++ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); ++ } ++ ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } else { ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) ++ qphy_setbits(pcs, ++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ else ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++ ++err_assert_reset: ++ while (++i < cfg->num_resets) ++ reset_control_assert(qmp->resets[i]); ++err_disable_regulators: ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++err_unlock: ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++{ ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *serdes = qphy->serdes; ++ int i = cfg->num_resets; ++ ++ mutex_lock(&qmp->phy_mutex); ++ if (--qmp->init_count) { ++ mutex_unlock(&qmp->phy_mutex); ++ return 0; ++ } ++ ++ reset_control_assert(qmp->ufs_reset); ++ if (cfg->has_phy_com_ctrl) { ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], ++ SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); ++ } ++ ++ while (--i >= 0) ++ reset_control_assert(qmp->resets[i]); ++ ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ regulator_bulk_disable(cfg->num_vregs, qmp->vregs); ++ ++ mutex_unlock(&qmp->phy_mutex); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_init(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret; ++ dev_vdbg(qmp->dev, "Initializing QMP phy\n"); ++ ++ if (cfg->no_pcs_sw_reset) { ++ /* ++ * Get UFS reset, which is delayed until now to avoid a ++ * circular dependency where UFS needs its PHY, but the PHY ++ * needs this UFS reset. ++ */ ++ if (!qmp->ufs_reset) { ++ qmp->ufs_reset = ++ devm_reset_control_get_exclusive(qmp->dev, ++ "ufsphy"); ++ ++ if (IS_ERR(qmp->ufs_reset)) { ++ ret = PTR_ERR(qmp->ufs_reset); ++ dev_err(qmp->dev, ++ "failed to get UFS reset: %d\n", ++ ret); ++ ++ qmp->ufs_reset = NULL; ++ return ret; ++ } ++ } ++ ++ ret = reset_control_assert(qmp->ufs_reset); ++ if (ret) ++ return ret; ++ } ++ ++ ret = qcom_qmp_phy_com_init(qphy); ++ if (ret) ++ return ret; ++ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->dp_aux_init(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_power_on(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ struct qcom_qmp *qmp = qphy->qmp; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *tx = qphy->tx; ++ void __iomem *rx = qphy->rx; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ void __iomem *status; ++ unsigned int mask, val, ready; ++ int ret; ++ ++ qcom_qmp_phy_serdes_init(qphy); ++ ++ if (cfg->has_lane_rst) { ++ ret = reset_control_deassert(qphy->lane_rst); ++ if (ret) { ++ dev_err(qmp->dev, "lane%d reset deassert failed\n", ++ qphy->index); ++ return ret; ++ } ++ } ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); ++ goto err_reset_lane; ++ } ++ ++ /* Tx, Rx, and PCS configurations */ ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 1); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 1); ++ ++ /* Configuration for other LANE for USB-DP combo PHY */ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl, cfg->tx_tbl_num, 2); ++ if (cfg->tx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ cfg->tx_tbl_sec, ++ cfg->tx_tbl_num_sec, 2); ++ } ++ ++ /* Configure special DP tx tunings */ ++ if (cfg->type == PHY_TYPE_DP) ++ cfg->configure_dp_tx(qphy); ++ ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 1); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); ++ ++ if (cfg->is_dual_lane_phy) { ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl, cfg->rx_tbl_num, 2); ++ if (cfg->rx_tbl_sec) ++ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ cfg->rx_tbl_sec, ++ cfg->rx_tbl_num_sec, 2); ++ } ++ ++ /* Configure link rate, swing, etc. */ ++ if (cfg->type == PHY_TYPE_DP) { ++ cfg->configure_dp_phy(qphy); ++ } else { ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); ++ } ++ ++ ret = reset_control_deassert(qmp->ufs_reset); ++ if (ret) ++ goto err_disable_pipe_clk; ++ ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ cfg->pcs_misc_tbl_num); ++ if (cfg->pcs_misc_tbl_sec) ++ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ cfg->pcs_misc_tbl_num_sec); ++ ++ /* ++ * Pull out PHY from POWER DOWN state. ++ * This is active low enable signal to power-down PHY. ++ */ ++ if(cfg->type == PHY_TYPE_PCIE) ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); ++ ++ if (cfg->has_pwrdn_delay) ++ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); ++ ++ if (cfg->type != PHY_TYPE_DP) { ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ if (cfg->type == PHY_TYPE_UFS) { ++ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; ++ mask = PCS_READY; ++ ready = PCS_READY; ++ } else { ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ } ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; ++ } ++ } ++ return 0; ++ ++err_disable_pipe_clk: ++ clk_disable_unprepare(qphy->pipe_clk); ++err_reset_lane: ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_power_off(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ ++ if (cfg->type == PHY_TYPE_DP) { ++ /* Assert DP PHY power down */ ++ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); ++ } else { ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_exit(struct phy *phy) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ if (cfg->has_lane_rst) ++ reset_control_assert(qphy->lane_rst); ++ ++ qcom_qmp_phy_com_exit(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_enable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_init(phy); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_power_on(phy); ++ if (ret) ++ qcom_qmp_phy_exit(phy); ++ ++ return ret; ++} ++ ++static int qcom_qmp_phy_disable(struct phy *phy) ++{ ++ int ret; ++ ++ ret = qcom_qmp_phy_power_off(phy); ++ if (ret) ++ return ret; ++ return qcom_qmp_phy_exit(phy); ++} ++ ++static int qcom_qmp_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct qmp_phy *qphy = phy_get_drvdata(phy); ++ ++ qphy->mode = mode; ++ ++ return 0; ++} ++ ++static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ u32 intr_mask; ++ ++ if (qphy->mode == PHY_MODE_USB_HOST_SS || ++ qphy->mode == PHY_MODE_USB_DEVICE_SS) ++ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; ++ else ++ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ++ ++ /* Clear any pending interrupts status */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); ++ ++ /* Enable required PHY autonomous mode interrupts */ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); ++ ++ /* Enable i/o clamp_n for autonomous mode */ ++ if (pcs_misc) ++ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++} ++ ++static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++{ ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ void __iomem *pcs = qphy->pcs; ++ void __iomem *pcs_misc = qphy->pcs_misc; ++ ++ /* Disable i/o clamp_n on resume for normal mode */ ++ if (pcs_misc) ++ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); ++ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ++ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); ++ ++ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++ /* Writing 1 followed by 0 clears the interrupt */ ++ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ ++ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ qcom_qmp_phy_enable_autonomous_mode(qphy); ++ ++ clk_disable_unprepare(qphy->pipe_clk); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct qmp_phy *qphy = qmp->phys[0]; ++ const struct qmp_phy_cfg *cfg = qphy->cfg; ++ int ret = 0; ++ ++ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); ++ ++ /* Supported only for USB3 PHY and luckily USB3 is the first phy */ ++ if (cfg->type != PHY_TYPE_USB3) ++ return 0; ++ ++ if (!qmp->init_count) { ++ dev_vdbg(dev, "PHY not initialized, bailing out\n"); ++ return 0; ++ } ++ ++ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(qphy->pipe_clk); ++ if (ret) { ++ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); ++ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); ++ return ret; ++ } ++ ++ qcom_qmp_phy_disable_autonomous_mode(qphy); ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_vregs; ++ int i; ++ ++ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); ++ if (!qmp->vregs) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->vregs[i].supply = cfg->vreg_list[i]; ++ ++ return devm_regulator_bulk_get(dev, num, qmp->vregs); ++} ++ ++static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int i; ++ ++ qmp->resets = devm_kcalloc(dev, cfg->num_resets, ++ sizeof(*qmp->resets), GFP_KERNEL); ++ if (!qmp->resets) ++ return -ENOMEM; ++ ++ for (i = 0; i < cfg->num_resets; i++) { ++ struct reset_control *rst; ++ const char *name = cfg->reset_list[i]; ++ ++ rst = devm_reset_control_get_exclusive(dev, name); ++ if (IS_ERR(rst)) { ++ dev_err(dev, "failed to get %s reset\n", name); ++ return PTR_ERR(rst); ++ } ++ qmp->resets[i] = rst; ++ } ++ ++ return 0; ++} ++ ++static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ int num = cfg->num_clks; ++ int i; ++ ++ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); ++ if (!qmp->clks) ++ return -ENOMEM; ++ ++ for (i = 0; i < num; i++) ++ qmp->clks[i].id = cfg->clk_list[i]; ++ ++ return devm_clk_bulk_get(dev, num, qmp->clks); ++} ++ ++static void phy_clk_release_provider(void *res) ++{ ++ of_clk_del_provider(res); ++} ++ ++/* ++ * Register a fixed rate pipe clock. ++ * ++ * The _pipe_clksrc generated by PHY goes to the GCC that gate ++ * controls it. The _pipe_clk coming out of the GCC is requested ++ * by the PHY driver for its operations. ++ * We register the _pipe_clksrc here. The gcc driver takes care ++ * of assigning this _pipe_clksrc as parent to _pipe_clk. ++ * Below picture shows this relationship. ++ * ++ * +---------------+ ++ * | PHY block |<<---------------------------------------+ ++ * | | | ++ * | +-------+ | +-----+ | ++ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ ++ * clk | +-------+ | +-----+ ++ * +---------------+ ++ */ ++static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) ++{ ++ struct clk_fixed_rate *fixed; ++ struct clk_init_data init = { }; ++ int ret; ++ ++ ret = of_property_read_string(np, "clock-output-names", &init.name); ++ if (ret) { ++ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); ++ return ret; ++ } ++ ++ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); ++ if (!fixed) ++ return -ENOMEM; ++ ++ init.ops = &clk_fixed_rate_ops; ++ ++ /* controllers using QMP phys use 125MHz pipe clock interface */ ++ fixed->fixed_rate = 125000000; ++ fixed->hw.init = &init; ++ ++ ret = devm_clk_hw_register(qmp->dev, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++/* ++ * Display Port PLL driver block diagram for branch clocks ++ * ++ * +------------------------------+ ++ * | DP_VCO_CLK | ++ * | | ++ * | +-------------------+ | ++ * | | (DP PLL/VCO) | | ++ * | +---------+---------+ | ++ * | v | ++ * | +----------+-----------+ | ++ * | | hsclk_divsel_clk_src | | ++ * | +----------+-----------+ | ++ * +------------------------------+ ++ * | ++ * +---------<---------v------------>----------+ ++ * | | ++ * +--------v----------------+ | ++ * | dp_phy_pll_link_clk | | ++ * | link_clk | | ++ * +--------+----------------+ | ++ * | | ++ * | | ++ * v v ++ * Input to DISPCC block | ++ * for link clk, crypto clk | ++ * and interface clock | ++ * | ++ * | ++ * +--------<------------+-----------------+---<---+ ++ * | | | ++ * +----v---------+ +--------v-----+ +--------v------+ ++ * | vco_divided | | vco_divided | | vco_divided | ++ * | _clk_src | | _clk_src | | _clk_src | ++ * | | | | | | ++ * |divsel_six | | divsel_two | | divsel_four | ++ * +-------+------+ +-----+--------+ +--------+------+ ++ * | | | ++ * v---->----------v-------------<------v ++ * | ++ * +----------+-----------------+ ++ * | dp_phy_pll_vco_div_clk | ++ * +---------+------------------+ ++ * | ++ * v ++ * Input to DISPCC block ++ * for DP pixel clock ++ * ++ */ ++static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 1620000000UL / 2: ++ case 2700000000UL / 2: ++ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ return 1620000000UL / 2; ++ case 2700: ++ return 2700000000UL / 2; ++ case 5400: ++ return 5400000000UL / 4; ++ case 8100: ++ return 8100000000UL / 6; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { ++ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, ++}; ++ ++static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ switch (req->rate) { ++ case 162000000: ++ case 270000000: ++ case 540000000: ++ case 810000000: ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static unsigned long ++qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ const struct qmp_phy_dp_clks *dp_clks; ++ const struct qmp_phy *qphy; ++ const struct phy_configure_opts_dp *dp_opts; ++ ++ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); ++ qphy = dp_clks->qphy; ++ dp_opts = &qphy->dp_opts; ++ ++ switch (dp_opts->link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ return dp_opts->link_rate * 100000; ++ default: ++ return 0; ++ } ++} ++ ++static const struct clk_ops qcom_qmp_dp_link_clk_ops = { ++ .determine_rate = qcom_qmp_dp_link_clk_determine_rate, ++ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, ++}; ++ ++static struct clk_hw * ++qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct qmp_phy_dp_clks *dp_clks = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx >= 2) { ++ pr_err("%s: invalid index %u\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (idx == 0) ++ return &dp_clks->dp_link_hw; ++ ++ return &dp_clks->dp_pixel_hw; ++} ++ ++static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, ++ struct device_node *np) ++{ ++ struct clk_init_data init = { }; ++ struct qmp_phy_dp_clks *dp_clks; ++ char name[64]; ++ int ret; ++ ++ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); ++ if (!dp_clks) ++ return -ENOMEM; ++ ++ dp_clks->qphy = qphy; ++ qphy->dp_clks = dp_clks; ++ ++ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_link_clk_ops; ++ init.name = name; ++ dp_clks->dp_link_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); ++ if (ret) ++ return ret; ++ ++ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); ++ init.ops = &qcom_qmp_dp_pixel_clk_ops; ++ init.name = name; ++ dp_clks->dp_pixel_hw.init = &init; ++ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); ++ if (ret) ++ return ret; ++ ++ /* ++ * Roll a devm action because the clock provider is the child node, but ++ * the child node is not actually a device. ++ */ ++ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); ++} ++ ++static const struct phy_ops qcom_qmp_phy_gen_ops = { ++ .init = qcom_qmp_phy_enable, ++ .exit = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_phy_dp_ops = { ++ .init = qcom_qmp_phy_init, ++ .configure = qcom_qmp_dp_phy_configure, ++ .power_on = qcom_qmp_phy_power_on, ++ .calibrate = qcom_qmp_dp_phy_calibrate, ++ .power_off = qcom_qmp_phy_power_off, ++ .exit = qcom_qmp_phy_exit, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops qcom_qmp_pcie_ufs_ops = { ++ .power_on = qcom_qmp_phy_enable, ++ .power_off = qcom_qmp_phy_disable, ++ .set_mode = qcom_qmp_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static void qcom_qmp_reset_control_put(void *data) ++{ ++ reset_control_put(data); ++} ++ ++static ++int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++ void __iomem *serdes, const struct qmp_phy_cfg *cfg) ++{ ++ struct qcom_qmp *qmp = dev_get_drvdata(dev); ++ struct phy *generic_phy; ++ struct qmp_phy *qphy; ++ const struct phy_ops *ops; ++ char prop_name[MAX_PROP_NAME]; ++ int ret; ++ ++ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); ++ if (!qphy) ++ return -ENOMEM; ++ ++ qphy->cfg = cfg; ++ qphy->serdes = serdes; ++ /* ++ * Get memory resources for each phy lane: ++ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. ++ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 ++ * For single lane PHYs: pcs_misc (optional) -> 3. ++ */ ++ qphy->tx = of_iomap(np, 0); ++ if (!qphy->tx) ++ return -ENOMEM; ++ ++ qphy->rx = of_iomap(np, 1); ++ if (!qphy->rx) ++ return -ENOMEM; ++ ++ qphy->pcs = of_iomap(np, 2); ++ if (!qphy->pcs) ++ return -ENOMEM; ++ ++ /* ++ * If this is a dual-lane PHY, then there should be registers for the ++ * second lane. Some old device trees did not specify this, so fall ++ * back to old legacy behavior of assuming they can be reached at an ++ * offset from the first lane. ++ */ ++ if (cfg->is_dual_lane_phy) { ++ qphy->tx2 = of_iomap(np, 3); ++ qphy->rx2 = of_iomap(np, 4); ++ if (!qphy->tx2 || !qphy->rx2) { ++ dev_warn(dev, ++ "Underspecified device tree, falling back to legacy register regions\n"); ++ ++ /* In the old version, pcs_misc is at index 3. */ ++ qphy->pcs_misc = qphy->tx2; ++ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; ++ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 5); ++ } ++ ++ } else { ++ qphy->pcs_misc = of_iomap(np, 3); ++ } ++ ++ if (!qphy->pcs_misc) ++ dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ ++ /* ++ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 ++ * based phys, so they essentially have pipe clock. So, ++ * we return error in case phy is USB3 or PIPE type. ++ * Otherwise, we initialize pipe clock to NULL for ++ * all phys that don't need this. ++ */ ++ snprintf(prop_name, sizeof(prop_name), "pipe%d", id); ++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); ++ if (IS_ERR(qphy->pipe_clk)) { ++ if (cfg->type == PHY_TYPE_PCIE || ++ cfg->type == PHY_TYPE_USB3) { ++ ret = PTR_ERR(qphy->pipe_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, ++ "failed to get lane%d pipe_clk, %d\n", ++ id, ret); ++ return ret; ++ } ++ qphy->pipe_clk = NULL; ++ } ++ ++ /* Get lane reset, if any */ ++ if (cfg->has_lane_rst) { ++ snprintf(prop_name, sizeof(prop_name), "lane%d", id); ++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); ++ if (IS_ERR(qphy->lane_rst)) { ++ dev_err(dev, "failed to get lane%d reset\n", id); ++ return PTR_ERR(qphy->lane_rst); ++ } ++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, ++ qphy->lane_rst); ++ if (ret) ++ return ret; ++ } ++ ++ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ++ ops = &qcom_qmp_pcie_ufs_ops; ++ else if (cfg->type == PHY_TYPE_DP) ++ ops = &qcom_qmp_phy_dp_ops; ++ else ++ ops = &qcom_qmp_phy_gen_ops; ++ ++ generic_phy = devm_phy_create(dev, np, ops); ++ if (IS_ERR(generic_phy)) { ++ ret = PTR_ERR(generic_phy); ++ dev_err(dev, "failed to create qphy %d\n", ret); ++ return ret; ++ } ++ ++ qphy->phy = generic_phy; ++ qphy->index = id; ++ qphy->qmp = qmp; ++ qmp->phys[id] = qphy; ++ phy_set_drvdata(generic_phy, qphy); ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,ipq8074-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-pcie-phy", ++ .data = &msm8996_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-ufs-phy", ++ .data = &msm8996_ufs_cfg, ++ }, { ++ .compatible = "qcom,msm8996-qmp-usb3-phy", ++ .data = &msm8996_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-pcie-phy", ++ .data = &msm8998_pciephy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,ipq8074-qmp-pcie-phy", ++ .data = &ipq8074_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-pcie-phy", ++ .data = &ipq6018_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq6018-qmp-usb3-phy", ++ .data = &ipq8074_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-phy", ++ .data = &sc7180_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sc8180x-qmp-pcie-phy", ++ .data = &sc8180x_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8280xp-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sdm845-qhp-pcie-phy", ++ .data = &sdm845_qhp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-pcie-phy", ++ .data = &sdm845_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-phy", ++ .data = &qmp_v3_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-usb3-uni-phy", ++ .data = &qmp_v3_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdm845-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,msm8998-qmp-usb3-phy", ++ .data = &msm8998_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm6115-qmp-ufs-phy", ++ .data = &sm6115_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm6350-qmp-ufs-phy", ++ .data = &sdm845_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-ufs-phy", ++ .data = &sm8150_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-phy", ++ .data = &sm8150_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8150-qmp-usb3-uni-phy", ++ .data = &sm8150_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-phy", ++ .data = &sm8250_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ /* It's a combo phy */ ++ }, { ++ .compatible = "qcom,sm8250-qmp-usb3-uni-phy", ++ .data = &sm8250_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", ++ .data = &sm8250_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-ufs-phy", ++ .data = &sm8350_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8250-qmp-modem-pcie-phy", ++ .data = &sm8250_qmp_gen3x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-pcie-phy", ++ .data = &sdx55_qmp_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sdx55-qmp-usb3-uni-phy", ++ .data = &sdx55_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sdx65-qmp-usb3-uni-phy", ++ .data = &sdx65_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,sm8350-qmp-usb3-uni-phy", ++ .data = &sm8350_usb3_uniphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", ++ .data = &sm8450_qmp_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", ++ .data = &sm8450_qmp_gen4x2_pciephy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-ufs-phy", ++ .data = &sm8450_ufsphy_cfg, ++ }, { ++ .compatible = "qcom,sm8450-qmp-usb3-phy", ++ .data = &sm8350_usb3phy_cfg, ++ }, { ++ .compatible = "qcom,qcm2290-qmp-usb3-phy", ++ .data = &qcm2290_usb3phy_cfg, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++ ++static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { ++ { ++ .compatible = "qcom,sc7180-qmp-usb3-dp-phy", ++ .data = &sc7180_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sm8250-qmp-usb3-dp-phy", ++ .data = &sm8250_usb3dpphy_cfg, ++ }, ++ { ++ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", ++ .data = &sc8180x_usb3dpphy_cfg, ++ }, ++ { } ++}; ++ ++static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, ++ qcom_qmp_phy_runtime_resume, NULL) ++}; ++ ++static int qcom_qmp_phy_probe(struct platform_device *pdev) ++{ ++ struct qcom_qmp *qmp; ++ struct device *dev = &pdev->dev; ++ struct device_node *child; ++ struct phy_provider *phy_provider; ++ void __iomem *serdes; ++ void __iomem *usb_serdes; ++ void __iomem *dp_serdes = NULL; ++ const struct qmp_phy_combo_cfg *combo_cfg = NULL; ++ const struct qmp_phy_cfg *cfg = NULL; ++ const struct qmp_phy_cfg *usb_cfg = NULL; ++ const struct qmp_phy_cfg *dp_cfg = NULL; ++ int num, id, expected_phys; ++ int ret; ++ ++ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); ++ if (!qmp) ++ return -ENOMEM; ++ ++ qmp->dev = dev; ++ dev_set_drvdata(dev, qmp); ++ ++ /* Get the specific init parameters of QMP phy */ ++ cfg = of_device_get_match_data(dev); ++ if (!cfg) { ++ const struct of_device_id *match; ++ ++ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); ++ if (!match) ++ return -EINVAL; ++ ++ combo_cfg = match->data; ++ if (!combo_cfg) ++ return -EINVAL; ++ ++ usb_cfg = combo_cfg->usb_cfg; ++ cfg = usb_cfg; /* Setup clks and regulators */ ++ } ++ ++ /* per PHY serdes; usually located at base address */ ++ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(serdes)) ++ return PTR_ERR(serdes); ++ ++ /* per PHY dp_com; if PHY has dp_com control block */ ++ if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(qmp->dp_com)) ++ return PTR_ERR(qmp->dp_com); ++ } ++ ++ if (combo_cfg) { ++ /* Only two serdes for combo PHY */ ++ dp_serdes = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(dp_serdes)) ++ return PTR_ERR(dp_serdes); ++ ++ dp_cfg = combo_cfg->dp_cfg; ++ expected_phys = 2; ++ } else { ++ expected_phys = cfg->nlanes; ++ } ++ ++ mutex_init(&qmp->phy_mutex); ++ ++ ret = qcom_qmp_phy_clk_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_reset_init(dev, cfg); ++ if (ret) ++ return ret; ++ ++ ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to get regulator supplies: %d\n", ++ ret); ++ return ret; ++ } ++ ++ num = of_get_available_child_count(dev->of_node); ++ /* do we have a rogue child node ? */ ++ if (num > expected_phys) ++ return -EINVAL; ++ ++ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); ++ if (!qmp->phys) ++ return -ENOMEM; ++ ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ /* ++ * Prevent runtime pm from being ON by default. Users can enable ++ * it using power/control in sysfs. ++ */ ++ pm_runtime_forbid(dev); ++ ++ id = 0; ++ for_each_available_child_of_node(dev->of_node, child) { ++ if (of_node_name_eq(child, "dp-phy")) { ++ cfg = dp_cfg; ++ serdes = dp_serdes; ++ } else if (of_node_name_eq(child, "usb3-phy")) { ++ cfg = usb_cfg; ++ serdes = usb_serdes; ++ } ++ ++ /* Create per-lane phy */ ++ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ if (ret) { ++ dev_err(dev, "failed to create lane%d phy, %d\n", ++ id, ret); ++ goto err_node_put; ++ } ++ ++ /* ++ * Register the pipe clock provided by phy. ++ * See function description to see details of this pipe clock. ++ */ ++ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; ++ } ++ } else if (cfg->type == PHY_TYPE_DP) { ++ ret = phy_dp_clks_register(qmp, qmp->phys[id], child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register DP clock source\n"); ++ goto err_node_put; ++ } ++ } ++ id++; ++ } ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (!IS_ERR(phy_provider)) ++ dev_info(dev, "Registered Qcom-QMP phy\n"); ++ else ++ pm_runtime_disable(dev); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++ ++err_node_put: ++ pm_runtime_disable(dev); ++ of_node_put(child); ++ return ret; ++} ++ ++static struct platform_driver qcom_qmp_phy_driver = { ++ .probe = qcom_qmp_phy_probe, ++ .driver = { ++ .name = "qcom-qmp-phy", ++ .pm = &qcom_qmp_phy_pm_ops, ++ .of_match_table = qcom_qmp_phy_of_match_table, ++ }, ++}; ++ ++module_platform_driver(qcom_qmp_phy_driver); ++ ++MODULE_AUTHOR("Vivek Gautam "); ++MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-pcie-change-symbol-prefix-to-qcom_qmp_p.patch b/queue-5.10/phy-qcom-qmp-pcie-change-symbol-prefix-to-qcom_qmp_p.patch new file mode 100644 index 00000000000..6c4d15db9a8 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-pcie-change-symbol-prefix-to-qcom_qmp_p.patch @@ -0,0 +1,503 @@ +From 199a9ad13bbfb271b3658b858314eab44445fa13 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:42 +0300 +Subject: phy: qcom-qmp-pcie: change symbol prefix to qcom_qmp_phy_pcie_msm8996 + +From: Dmitry Baryshkov + +[ Upstream commit 2abf0c8e61a900a77f2262f54596973db572cabb ] + +Change all symbol names to start with qcom_qmp_phy_pcie_msm8996_ rather +than old qcom_qmp_phy_. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-10-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 158 +++++++++--------- + 1 file changed, 79 insertions(+), 79 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +index 260e534b5607..1741a5675f9a 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +@@ -474,7 +474,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + +-static void qcom_qmp_phy_configure_lane(void __iomem *base, ++static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, +@@ -497,15 +497,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base, + } + } + +-static void qcom_qmp_phy_configure(void __iomem *base, ++static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) + { +- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++ qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); + } + +-static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -515,30 +515,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) + int serdes_tbl_num = cfg->serdes_tbl_num; + int ret; + +- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (cfg->serdes_tbl_sec) +- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + + if (cfg->type == PHY_TYPE_DP) { + switch (dp_opts->link_rate) { + case 1620: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, + cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + case 8100: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr3, + cfg->serdes_tbl_hbr3_num); + break; +@@ -602,7 +602,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy) + return 0; + } + +-static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -697,7 +697,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) + return ret; + } + +-static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -732,7 +732,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) + return 0; + } + +-static int qcom_qmp_phy_init(struct phy *phy) ++static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; +@@ -767,7 +767,7 @@ static int qcom_qmp_phy_init(struct phy *phy) + return ret; + } + +- ret = qcom_qmp_phy_com_init(qphy); ++ ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); + if (ret) + return ret; + +@@ -777,7 +777,7 @@ static int qcom_qmp_phy_init(struct phy *phy) + return 0; + } + +-static int qcom_qmp_phy_power_on(struct phy *phy) ++static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; +@@ -790,7 +790,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + unsigned int mask, val, ready; + int ret; + +- qcom_qmp_phy_serdes_init(qphy); ++ qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); + + if (cfg->has_lane_rst) { + ret = reset_control_deassert(qphy->lane_rst); +@@ -808,18 +808,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + } + + /* Tx, Rx, and PCS configurations */ +- qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + if (cfg->tx_tbl_sec) +- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { +- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); + if (cfg->tx_tbl_sec) +- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 2); + } +@@ -828,17 +828,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + if (cfg->type == PHY_TYPE_DP) + cfg->configure_dp_tx(qphy); + +- qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) +- qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + + if (cfg->is_dual_lane_phy) { +- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); + if (cfg->rx_tbl_sec) +- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl_sec, + cfg->rx_tbl_num_sec, 2); + } +@@ -847,9 +847,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + if (cfg->type == PHY_TYPE_DP) { + cfg->configure_dp_phy(qphy); + } else { +- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) +- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); + } + +@@ -857,10 +857,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + if (ret) + goto err_disable_pipe_clk; + +- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + cfg->pcs_misc_tbl_num); + if (cfg->pcs_misc_tbl_sec) +- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + cfg->pcs_misc_tbl_num_sec); + + /* +@@ -908,7 +908,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + return ret; + } + +-static int qcom_qmp_phy_power_off(struct phy *phy) ++static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -939,7 +939,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) + return 0; + } + +-static int qcom_qmp_phy_exit(struct phy *phy) ++static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -947,37 +947,37 @@ static int qcom_qmp_phy_exit(struct phy *phy) + if (cfg->has_lane_rst) + reset_control_assert(qphy->lane_rst); + +- qcom_qmp_phy_com_exit(qphy); ++ qcom_qmp_phy_pcie_msm8996_com_exit(qphy); + + return 0; + } + +-static int qcom_qmp_phy_enable(struct phy *phy) ++static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy) + { + int ret; + +- ret = qcom_qmp_phy_init(phy); ++ ret = qcom_qmp_phy_pcie_msm8996_init(phy); + if (ret) + return ret; + +- ret = qcom_qmp_phy_power_on(phy); ++ ret = qcom_qmp_phy_pcie_msm8996_power_on(phy); + if (ret) +- qcom_qmp_phy_exit(phy); ++ qcom_qmp_phy_pcie_msm8996_exit(phy); + + return ret; + } + +-static int qcom_qmp_phy_disable(struct phy *phy) ++static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy) + { + int ret; + +- ret = qcom_qmp_phy_power_off(phy); ++ ret = qcom_qmp_phy_pcie_msm8996_power_off(phy); + if (ret) + return ret; +- return qcom_qmp_phy_exit(phy); ++ return qcom_qmp_phy_pcie_msm8996_exit(phy); + } + +-static int qcom_qmp_phy_set_mode(struct phy *phy, ++static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy, + enum phy_mode mode, int submode) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); +@@ -987,7 +987,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, + return 0; + } + +-static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy) + { + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; +@@ -1016,7 +1016,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); + } + +-static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy) + { + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; +@@ -1034,7 +1034,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + } + +-static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; +@@ -1051,7 +1051,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) + return 0; + } + +- qcom_qmp_phy_enable_autonomous_mode(qphy); ++ qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy); + + clk_disable_unprepare(qphy->pipe_clk); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); +@@ -1059,7 +1059,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) + return 0; + } + +-static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; +@@ -1088,12 +1088,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) + return ret; + } + +- qcom_qmp_phy_disable_autonomous_mode(qphy); ++ qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy); + + return 0; + } + +-static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; +@@ -1109,7 +1109,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg * + return devm_regulator_bulk_get(dev, num, qmp->vregs); + } + +-static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int i; +@@ -1134,7 +1134,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg + return 0; + } + +-static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; +@@ -1402,28 +1402,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + } + +-static const struct phy_ops qcom_qmp_phy_gen_ops = { +- .init = qcom_qmp_phy_enable, +- .exit = qcom_qmp_phy_disable, +- .set_mode = qcom_qmp_phy_set_mode, ++static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = { ++ .init = qcom_qmp_phy_pcie_msm8996_enable, ++ .exit = qcom_qmp_phy_pcie_msm8996_disable, ++ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, + .owner = THIS_MODULE, + }; + +-static const struct phy_ops qcom_qmp_phy_dp_ops = { +- .init = qcom_qmp_phy_init, ++static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = { ++ .init = qcom_qmp_phy_pcie_msm8996_init, + .configure = qcom_qmp_dp_phy_configure, +- .power_on = qcom_qmp_phy_power_on, ++ .power_on = qcom_qmp_phy_pcie_msm8996_power_on, + .calibrate = qcom_qmp_dp_phy_calibrate, +- .power_off = qcom_qmp_phy_power_off, +- .exit = qcom_qmp_phy_exit, +- .set_mode = qcom_qmp_phy_set_mode, ++ .power_off = qcom_qmp_phy_pcie_msm8996_power_off, ++ .exit = qcom_qmp_phy_pcie_msm8996_exit, ++ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, + .owner = THIS_MODULE, + }; + + static const struct phy_ops qcom_qmp_pcie_ufs_ops = { +- .power_on = qcom_qmp_phy_enable, +- .power_off = qcom_qmp_phy_disable, +- .set_mode = qcom_qmp_phy_set_mode, ++ .power_on = qcom_qmp_phy_pcie_msm8996_enable, ++ .power_off = qcom_qmp_phy_pcie_msm8996_disable, ++ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, + .owner = THIS_MODULE, + }; + +@@ -1433,7 +1433,7 @@ static void qcom_qmp_reset_control_put(void *data) + } + + static +-int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); +@@ -1535,9 +1535,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) + ops = &qcom_qmp_pcie_ufs_ops; + else if (cfg->type == PHY_TYPE_DP) +- ops = &qcom_qmp_phy_dp_ops; ++ ops = &qcom_qmp_phy_pcie_msm8996_dp_ops; + else +- ops = &qcom_qmp_phy_gen_ops; ++ ops = &qcom_qmp_phy_pcie_msm8996_gen_ops; + + generic_phy = devm_phy_create(dev, np, ops); + if (IS_ERR(generic_phy)) { +@@ -1555,21 +1555,21 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + return 0; + } + +-static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = { + { + .compatible = "qcom,msm8996-qmp-pcie-phy", + .data = &msm8996_pciephy_cfg, + }, + { }, + }; +-MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table); + +-static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { +- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, +- qcom_qmp_phy_runtime_resume, NULL) ++static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend, ++ qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL) + }; + +-static int qcom_qmp_phy_probe(struct platform_device *pdev) ++static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + { + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; +@@ -1623,15 +1623,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + + mutex_init(&qmp->phy_mutex); + +- ret = qcom_qmp_phy_clk_init(dev, cfg); ++ ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg); + if (ret) + return ret; + +- ret = qcom_qmp_phy_reset_init(dev, cfg); ++ ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg); + if (ret) + return ret; + +- ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", +@@ -1667,7 +1667,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + } + + /* Create per-lane phy */ +- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); +@@ -1710,16 +1710,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + return ret; + } + +-static struct platform_driver qcom_qmp_phy_driver = { +- .probe = qcom_qmp_phy_probe, ++static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = { ++ .probe = qcom_qmp_phy_pcie_msm8996_probe, + .driver = { + .name = "qcom-qmp-msm8996-pcie-phy", +- .pm = &qcom_qmp_phy_pm_ops, +- .of_match_table = qcom_qmp_phy_of_match_table, ++ .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops, ++ .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table, + }, + }; + +-module_platform_driver(qcom_qmp_phy_driver); ++module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver); + + MODULE_AUTHOR("Vivek Gautam "); + MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-pcie-msm8996-cleanup-the-driver.patch b/queue-5.10/phy-qcom-qmp-pcie-msm8996-cleanup-the-driver.patch new file mode 100644 index 00000000000..9bb304a437f --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-pcie-msm8996-cleanup-the-driver.patch @@ -0,0 +1,498 @@ +From 299192ee58f58e9f9b5f0cf204cf6eabf2ae7908 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:54 +0300 +Subject: phy: qcom-qmp-pcie-msm8996: cleanup the driver + +From: Dmitry Baryshkov + +[ Upstream commit 4856865b0dec88570edfbdf3e9c3b551923c0768 ] + +Remove the conditionals and options that are not used by the MSM8996 +PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is +the case for this PHY. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-22-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 268 +++--------------- + 1 file changed, 41 insertions(+), 227 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +index 02e5ae7fa213..51da3a3a199e 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +@@ -266,22 +266,6 @@ struct qmp_phy_cfg { + const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; + int pcs_misc_tbl_num_sec; + +- /* Init sequence for DP PHY block link rates */ +- const struct qmp_phy_init_tbl *serdes_tbl_rbr; +- int serdes_tbl_rbr_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr; +- int serdes_tbl_hbr_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr2; +- int serdes_tbl_hbr2_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr3; +- int serdes_tbl_hbr3_num; +- +- /* DP PHY callbacks */ +- int (*configure_dp_phy)(struct qmp_phy *qphy); +- void (*configure_dp_tx)(struct qmp_phy *qphy); +- int (*calibrate_dp_phy)(struct qmp_phy *qphy); +- void (*dp_aux_init)(struct qmp_phy *qphy); +- + /* clock ids to be requested */ + const char * const *clk_list; + int num_clks; +@@ -301,28 +285,11 @@ struct qmp_phy_cfg { + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + +- /* true, if PHY has a separate PHY_COM control block */ +- bool has_phy_com_ctrl; +- /* true, if PHY has a reset for individual lanes */ +- bool has_lane_rst; + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; + /* power_down delay in usec */ + int pwrdn_delay_min; + int pwrdn_delay_max; +- +- /* true, if PHY has a separate DP_COM control block */ +- bool has_phy_dp_com_ctrl; +- /* true, if PHY has secondary tx/rx lanes to be configured */ +- bool is_dual_lane_phy; +- +- /* true, if PCS block has no separate SW_RESET register */ +- bool no_pcs_sw_reset; +-}; +- +-struct qmp_phy_combo_cfg { +- const struct qmp_phy_cfg *usb_cfg; +- const struct qmp_phy_cfg *dp_cfg; + }; + + /** +@@ -334,17 +301,12 @@ struct qmp_phy_combo_cfg { + * @tx: iomapped memory space for lane's tx + * @rx: iomapped memory space for lane's rx + * @pcs: iomapped memory space for lane's pcs +- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) +- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) + * @pcs_misc: iomapped memory space for lane's pcs_misc + * @pipe_clk: pipe clock + * @index: lane index + * @qmp: QMP phy to which this lane belongs + * @lane_rst: lane's reset controller + * @mode: current PHY mode +- * @dp_aux_cfg: Display port aux config +- * @dp_opts: Display port optional config +- * @dp_clks: Display port clocks + */ + struct qmp_phy { + struct phy *phy; +@@ -353,30 +315,18 @@ struct qmp_phy { + void __iomem *tx; + void __iomem *rx; + void __iomem *pcs; +- void __iomem *tx2; +- void __iomem *rx2; + void __iomem *pcs_misc; + struct clk *pipe_clk; + unsigned int index; + struct qcom_qmp *qmp; + struct reset_control *lane_rst; + enum phy_mode mode; +- unsigned int dp_aux_cfg; +- struct phy_configure_opts_dp dp_opts; +- struct qmp_phy_dp_clks *dp_clks; +-}; +- +-struct qmp_phy_dp_clks { +- struct qmp_phy *qphy; +- struct clk_hw dp_link_hw; +- struct clk_hw dp_pixel_hw; + }; + + /** + * struct qcom_qmp - structure holding QMP phy block attributes + * + * @dev: device +- * @dp_com: iomapped memory space for phy's dp_com control block + * + * @clks: array of clocks required by phy + * @resets: array of resets required by phy +@@ -385,11 +335,9 @@ struct qmp_phy_dp_clks { + * @phys: array of per-lane phy descriptors + * @phy_mutex: mutex lock for PHY common block initialization + * @init_count: phy common block initialization count +- * @ufs_reset: optional UFS PHY reset handle + */ + struct qcom_qmp { + struct device *dev; +- void __iomem *dp_com; + + struct clk_bulk_data *clks; + struct reset_control **resets; +@@ -399,8 +347,6 @@ struct qcom_qmp { + + struct mutex phy_mutex; + int init_count; +- +- struct reset_control *ufs_reset; + }; + + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +@@ -467,8 +413,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { + .mask_com_pcs_ready = PCS_READY, + .phy_status = PHYSTATUS, + +- .has_phy_com_ctrl = true, +- .has_lane_rst = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +@@ -512,6 +456,8 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) + void __iomem *serdes = qphy->serdes; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; ++ void __iomem *status; ++ unsigned int mask, val; + int ret; + + qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); +@@ -519,24 +465,20 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) + qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + +- if (cfg->has_phy_com_ctrl) { +- void __iomem *status; +- unsigned int mask, val; + +- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); +- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], +- SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); + +- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; +- mask = cfg->mask_com_pcs_ready; ++ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; ++ mask = cfg->mask_com_pcs_ready; + +- ret = readl_poll_timeout(status, val, (val & mask), 10, +- PHY_INIT_COMPLETE_TIMEOUT); +- if (ret) { +- dev_err(qmp->dev, +- "phy common block init timed-out\n"); +- return ret; +- } ++ ret = readl_poll_timeout(status, val, (val & mask), 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, ++ "phy common block init timed-out\n"); ++ return ret; + } + + return 0; +@@ -547,8 +489,6 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; +- void __iomem *pcs = qphy->pcs; +- void __iomem *dp_com = qmp->dp_com; + int ret, i; + + mutex_lock(&qmp->phy_mutex); +@@ -586,41 +526,8 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) + if (ret) + goto err_assert_reset; + +- if (cfg->has_phy_dp_com_ctrl) { +- qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, +- SW_PWRDN); +- /* override hardware control for reset of qmp phy */ +- qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, +- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | +- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); +- +- /* Default type-c orientation, i.e CC1 */ +- qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); +- +- qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, +- USB3_MODE | DP_MODE); +- +- /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ +- qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, +- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | +- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); +- +- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); +- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); +- } +- +- if (cfg->has_phy_com_ctrl) { +- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], +- SW_PWRDN); +- } else { +- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) +- qphy_setbits(pcs, +- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], +- cfg->pwrdn_ctrl); +- else +- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, +- cfg->pwrdn_ctrl); +- } ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); + + mutex_unlock(&qmp->phy_mutex); + +@@ -650,15 +557,12 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) + return 0; + } + +- reset_control_assert(qmp->ufs_reset); +- if (cfg->has_phy_com_ctrl) { +- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], +- SERDES_START | PCS_START); +- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], +- SW_RESET); +- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], +- SW_PWRDN); +- } ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], ++ SERDES_START | PCS_START); ++ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], ++ SW_RESET); ++ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], ++ SW_PWRDN); + + while (--i >= 0) + reset_control_assert(qmp->resets[i]); +@@ -676,37 +580,9 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; +- const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + +- if (cfg->no_pcs_sw_reset) { +- /* +- * Get UFS reset, which is delayed until now to avoid a +- * circular dependency where UFS needs its PHY, but the PHY +- * needs this UFS reset. +- */ +- if (!qmp->ufs_reset) { +- qmp->ufs_reset = +- devm_reset_control_get_exclusive(qmp->dev, +- "ufsphy"); +- +- if (IS_ERR(qmp->ufs_reset)) { +- ret = PTR_ERR(qmp->ufs_reset); +- dev_err(qmp->dev, +- "failed to get UFS reset: %d\n", +- ret); +- +- qmp->ufs_reset = NULL; +- return ret; +- } +- } +- +- ret = reset_control_assert(qmp->ufs_reset); +- if (ret) +- return ret; +- } +- + ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); + if (ret) + return ret; +@@ -729,13 +605,11 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + + qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); + +- if (cfg->has_lane_rst) { +- ret = reset_control_deassert(qphy->lane_rst); +- if (ret) { +- dev_err(qmp->dev, "lane%d reset deassert failed\n", +- qphy->index); +- return ret; +- } ++ ret = reset_control_deassert(qphy->lane_rst); ++ if (ret) { ++ dev_err(qmp->dev, "lane%d reset deassert failed\n", ++ qphy->index); ++ return ret; + } + + ret = clk_prepare_enable(qphy->pipe_clk); +@@ -751,40 +625,17 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 1); + +- /* Configuration for other LANE for USB-DP combo PHY */ +- if (cfg->is_dual_lane_phy) { +- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, +- cfg->tx_tbl, cfg->tx_tbl_num, 2); +- if (cfg->tx_tbl_sec) +- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, +- cfg->tx_tbl_sec, +- cfg->tx_tbl_num_sec, 2); +- } +- + qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + +- if (cfg->is_dual_lane_phy) { +- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, +- cfg->rx_tbl, cfg->rx_tbl_num, 2); +- if (cfg->rx_tbl_sec) +- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, +- cfg->rx_tbl_sec, +- cfg->rx_tbl_num_sec, 2); +- } +- + qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); + +- ret = reset_control_deassert(qmp->ufs_reset); +- if (ret) +- goto err_disable_pipe_clk; +- + qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + cfg->pcs_misc_tbl_num); + if (cfg->pcs_misc_tbl_sec) +@@ -801,8 +652,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + + /* Pull PHY out of reset state */ +- if (!cfg->no_pcs_sw_reset) +- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + +@@ -822,8 +673,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + err_disable_pipe_clk: + clk_disable_unprepare(qphy->pipe_clk); + err_reset_lane: +- if (cfg->has_lane_rst) +- reset_control_assert(qphy->lane_rst); ++ reset_control_assert(qphy->lane_rst); + + return ret; + } +@@ -836,8 +686,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) + clk_disable_unprepare(qphy->pipe_clk); + + /* PHY reset */ +- if (!cfg->no_pcs_sw_reset) +- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); +@@ -857,10 +706,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) + static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); +- const struct qmp_phy_cfg *cfg = qphy->cfg; + +- if (cfg->has_lane_rst) +- reset_control_assert(qphy->lane_rst); ++ reset_control_assert(qphy->lane_rst); + + qcom_qmp_phy_pcie_msm8996_com_exit(qphy); + +@@ -1065,31 +912,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, + if (!qphy->pcs) + return -ENOMEM; + +- /* +- * If this is a dual-lane PHY, then there should be registers for the +- * second lane. Some old device trees did not specify this, so fall +- * back to old legacy behavior of assuming they can be reached at an +- * offset from the first lane. +- */ +- if (cfg->is_dual_lane_phy) { +- qphy->tx2 = of_iomap(np, 3); +- qphy->rx2 = of_iomap(np, 4); +- if (!qphy->tx2 || !qphy->rx2) { +- dev_warn(dev, +- "Underspecified device tree, falling back to legacy register regions\n"); +- +- /* In the old version, pcs_misc is at index 3. */ +- qphy->pcs_misc = qphy->tx2; +- qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; +- qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; +- +- } else { +- qphy->pcs_misc = of_iomap(np, 5); +- } +- +- } else { +- qphy->pcs_misc = of_iomap(np, 3); +- } ++ qphy->pcs_misc = of_iomap(np, 3); + + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); +@@ -1117,18 +940,16 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, + } + + /* Get lane reset, if any */ +- if (cfg->has_lane_rst) { +- snprintf(prop_name, sizeof(prop_name), "lane%d", id); +- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); +- if (IS_ERR(qphy->lane_rst)) { +- dev_err(dev, "failed to get lane%d reset\n", id); +- return PTR_ERR(qphy->lane_rst); +- } +- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, +- qphy->lane_rst); +- if (ret) +- return ret; ++ snprintf(prop_name, sizeof(prop_name), "lane%d", id); ++ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); ++ if (IS_ERR(qphy->lane_rst)) { ++ dev_err(dev, "failed to get lane%d reset\n", id); ++ return PTR_ERR(qphy->lane_rst); + } ++ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, ++ qphy->lane_rst); ++ if (ret) ++ return ret; + + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); + if (IS_ERR(generic_phy)) { +@@ -1183,13 +1004,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + +- /* per PHY dp_com; if PHY has dp_com control block */ +- if (cfg->has_phy_dp_com_ctrl) { +- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); +- if (IS_ERR(qmp->dp_com)) +- return PTR_ERR(qmp->dp_com); +- } +- + expected_phys = cfg->nlanes; + + mutex_init(&qmp->phy_mutex); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-pcie-msm8996-drop-all-compatibles-excep.patch b/queue-5.10/phy-qcom-qmp-pcie-msm8996-drop-all-compatibles-excep.patch new file mode 100644 index 00000000000..042be0b554f --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-pcie-msm8996-drop-all-compatibles-excep.patch @@ -0,0 +1,5162 @@ +From 7e8f57ac63c3b62c0ba9f7bf131aefa566be1b96 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:36 +0300 +Subject: phy: qcom-qmp-pcie-msm8996: drop all compatibles except + msm8996-pcie-phy + +From: Dmitry Baryshkov + +[ Upstream commit 9fc8fa59ef1038714a9b86259f515373a7380169 ] + +Drop support for all compatibles from the new qmp-pcie driver except the +qcom,msm8996-qmp-pcie-phy. This PHY differs from the rest of PCIe PHYs, +so it warrants a separate device driver. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-4-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5024 +---------------- + 1 file changed, 200 insertions(+), 4824 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +index c7309e981bfb..260e534b5607 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +@@ -141,18 +141,6 @@ enum qphy_reg_layout { + QPHY_LAYOUT_SIZE + }; + +-static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = 0x00, +- [QPHY_PCS_READY_STATUS] = 0x168, +-}; +- +-static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +-}; +- + static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_COM_SW_RESET] = 0x400, + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, +@@ -169,176 +157,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_PCS_STATUS] = 0x174, + }; + +-static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_FLL_CNTRL1] = 0xc0, +- [QPHY_FLL_CNTRL2] = 0xc4, +- [QPHY_FLL_CNT_VAL_L] = 0xc8, +- [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, +- [QPHY_FLL_MAN_CODE] = 0xd0, +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x17c, +- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, +- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, +- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, +-}; +- +-static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x174, +- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, +- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, +- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, +-}; +- +-static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x174, +-}; +- +-static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x2ac, +-}; +- +-static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, +- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, +-}; +- +-static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, +- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, +-}; +- +-static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, +- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, +-}; +- +-static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, +- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, +- [QPHY_PCS_STATUS] = 0x174, +- [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, +-}; +- +-static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = 0x00, +- [QPHY_PCS_READY_STATUS] = 0x160, +-}; +- +-static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = 0x00, +- [QPHY_PCS_READY_STATUS] = 0x168, +-}; +- +-static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +-}; +- +-static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, +- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, +- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), +- /* PLL and Loop filter settings */ +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- /* SSC settings */ +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), +-}; +- + static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), +@@ -417,4078 +235,243 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), + }; + +-static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), +- /* PLL and Loop filter settings */ +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- /* SSC settings */ +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { +- /* FLL settings */ +- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), +- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), +- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), +- QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), +- +- /* Lock Det settings */ +- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), +- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), +- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), +- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), +- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), +- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), +- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), +- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), +- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), +- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), +- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), +- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), +- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), +- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), +- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), +- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), +- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), +- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), +- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), +- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), +- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), +- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), +- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), +- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), +- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), +- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), +- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), +- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), ++struct qmp_phy; + +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++/* struct qmp_phy_cfg - per-PHY initialization config */ ++struct qmp_phy_cfg { ++ /* phy-type - PCIE/UFS/USB */ ++ unsigned int type; ++ /* number of lanes provided by phy */ ++ int nlanes; + +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), +-}; ++ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ ++ const struct qmp_phy_init_tbl *serdes_tbl; ++ int serdes_tbl_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_sec; ++ int serdes_tbl_num_sec; ++ const struct qmp_phy_init_tbl *tx_tbl; ++ int tx_tbl_num; ++ const struct qmp_phy_init_tbl *tx_tbl_sec; ++ int tx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *rx_tbl; ++ int rx_tbl_num; ++ const struct qmp_phy_init_tbl *rx_tbl_sec; ++ int rx_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_tbl; ++ int pcs_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_tbl_sec; ++ int pcs_tbl_num_sec; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl; ++ int pcs_misc_tbl_num; ++ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; ++ int pcs_misc_tbl_num_sec; + +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +-}; ++ /* Init sequence for DP PHY block link rates */ ++ const struct qmp_phy_init_tbl *serdes_tbl_rbr; ++ int serdes_tbl_rbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr; ++ int serdes_tbl_hbr_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr2; ++ int serdes_tbl_hbr2_num; ++ const struct qmp_phy_init_tbl *serdes_tbl_hbr3; ++ int serdes_tbl_hbr3_num; + +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), +-}; ++ /* DP PHY callbacks */ ++ int (*configure_dp_phy)(struct qmp_phy *qphy); ++ void (*configure_dp_tx)(struct qmp_phy *qphy); ++ int (*calibrate_dp_phy)(struct qmp_phy *qphy); ++ void (*dp_aux_init)(struct qmp_phy *qphy); + +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), +-}; ++ /* clock ids to be requested */ ++ const char * const *clk_list; ++ int num_clks; ++ /* resets to be requested */ ++ const char * const *reset_list; ++ int num_resets; ++ /* regulators to be requested */ ++ const char * const *vreg_list; ++ int num_vregs; + +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { +-}; ++ /* array of registers with different offsets */ ++ const unsigned int *regs; + +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), +-}; ++ unsigned int start_ctrl; ++ unsigned int pwrdn_ctrl; ++ unsigned int mask_com_pcs_ready; ++ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ ++ unsigned int phy_status; + +-static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +-}; ++ /* true, if PHY has a separate PHY_COM control block */ ++ bool has_phy_com_ctrl; ++ /* true, if PHY has a reset for individual lanes */ ++ bool has_lane_rst; ++ /* true, if PHY needs delay after POWER_DOWN */ ++ bool has_pwrdn_delay; ++ /* power_down delay in usec */ ++ int pwrdn_delay_min; ++ int pwrdn_delay_max; + +-static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +-}; ++ /* true, if PHY has a separate DP_COM control block */ ++ bool has_phy_dp_com_ctrl; ++ /* true, if PHY has secondary tx/rx lanes to be configured */ ++ bool is_dual_lane_phy; + +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), ++ /* true, if PCS block has no separate SW_RESET register */ ++ bool no_pcs_sw_reset; + }; + +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), ++struct qmp_phy_combo_cfg { ++ const struct qmp_phy_cfg *usb_cfg; ++ const struct qmp_phy_cfg *dp_cfg; + }; + +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { +- /* FLL settings */ +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- +- /* Lock Det settings */ +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { +- /* FLL settings */ +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- +- /* Lock Det settings */ +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), +- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), +- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), +- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), +- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), +- +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { +- /* Lock Det settings */ +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), +-}; +- +-static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), +- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +-}; +- +-static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), +-}; +- +-static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), +-}; +- +-/* Register names should be validated, they might be different for this PHY */ +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), +-}; +- +-struct qmp_phy; +- +-/* struct qmp_phy_cfg - per-PHY initialization config */ +-struct qmp_phy_cfg { +- /* phy-type - PCIE/UFS/USB */ +- unsigned int type; +- /* number of lanes provided by phy */ +- int nlanes; +- +- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ +- const struct qmp_phy_init_tbl *serdes_tbl; +- int serdes_tbl_num; +- const struct qmp_phy_init_tbl *serdes_tbl_sec; +- int serdes_tbl_num_sec; +- const struct qmp_phy_init_tbl *tx_tbl; +- int tx_tbl_num; +- const struct qmp_phy_init_tbl *tx_tbl_sec; +- int tx_tbl_num_sec; +- const struct qmp_phy_init_tbl *rx_tbl; +- int rx_tbl_num; +- const struct qmp_phy_init_tbl *rx_tbl_sec; +- int rx_tbl_num_sec; +- const struct qmp_phy_init_tbl *pcs_tbl; +- int pcs_tbl_num; +- const struct qmp_phy_init_tbl *pcs_tbl_sec; +- int pcs_tbl_num_sec; +- const struct qmp_phy_init_tbl *pcs_misc_tbl; +- int pcs_misc_tbl_num; +- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; +- int pcs_misc_tbl_num_sec; +- +- /* Init sequence for DP PHY block link rates */ +- const struct qmp_phy_init_tbl *serdes_tbl_rbr; +- int serdes_tbl_rbr_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr; +- int serdes_tbl_hbr_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr2; +- int serdes_tbl_hbr2_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr3; +- int serdes_tbl_hbr3_num; +- +- /* DP PHY callbacks */ +- int (*configure_dp_phy)(struct qmp_phy *qphy); +- void (*configure_dp_tx)(struct qmp_phy *qphy); +- int (*calibrate_dp_phy)(struct qmp_phy *qphy); +- void (*dp_aux_init)(struct qmp_phy *qphy); +- +- /* clock ids to be requested */ +- const char * const *clk_list; +- int num_clks; +- /* resets to be requested */ +- const char * const *reset_list; +- int num_resets; +- /* regulators to be requested */ +- const char * const *vreg_list; +- int num_vregs; +- +- /* array of registers with different offsets */ +- const unsigned int *regs; +- +- unsigned int start_ctrl; +- unsigned int pwrdn_ctrl; +- unsigned int mask_com_pcs_ready; +- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ +- unsigned int phy_status; +- +- /* true, if PHY has a separate PHY_COM control block */ +- bool has_phy_com_ctrl; +- /* true, if PHY has a reset for individual lanes */ +- bool has_lane_rst; +- /* true, if PHY needs delay after POWER_DOWN */ +- bool has_pwrdn_delay; +- /* power_down delay in usec */ +- int pwrdn_delay_min; +- int pwrdn_delay_max; +- +- /* true, if PHY has a separate DP_COM control block */ +- bool has_phy_dp_com_ctrl; +- /* true, if PHY has secondary tx/rx lanes to be configured */ +- bool is_dual_lane_phy; +- +- /* true, if PCS block has no separate SW_RESET register */ +- bool no_pcs_sw_reset; +-}; +- +-struct qmp_phy_combo_cfg { +- const struct qmp_phy_cfg *usb_cfg; +- const struct qmp_phy_cfg *dp_cfg; +-}; +- +-/** +- * struct qmp_phy - per-lane phy descriptor +- * +- * @phy: generic phy +- * @cfg: phy specific configuration +- * @serdes: iomapped memory space for phy's serdes (i.e. PLL) +- * @tx: iomapped memory space for lane's tx +- * @rx: iomapped memory space for lane's rx +- * @pcs: iomapped memory space for lane's pcs +- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) +- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) +- * @pcs_misc: iomapped memory space for lane's pcs_misc +- * @pipe_clk: pipe clock +- * @index: lane index +- * @qmp: QMP phy to which this lane belongs +- * @lane_rst: lane's reset controller +- * @mode: current PHY mode +- * @dp_aux_cfg: Display port aux config +- * @dp_opts: Display port optional config +- * @dp_clks: Display port clocks +- */ +-struct qmp_phy { +- struct phy *phy; +- const struct qmp_phy_cfg *cfg; +- void __iomem *serdes; +- void __iomem *tx; +- void __iomem *rx; +- void __iomem *pcs; +- void __iomem *tx2; +- void __iomem *rx2; +- void __iomem *pcs_misc; +- struct clk *pipe_clk; +- unsigned int index; +- struct qcom_qmp *qmp; +- struct reset_control *lane_rst; +- enum phy_mode mode; +- unsigned int dp_aux_cfg; +- struct phy_configure_opts_dp dp_opts; +- struct qmp_phy_dp_clks *dp_clks; +-}; +- +-struct qmp_phy_dp_clks { +- struct qmp_phy *qphy; +- struct clk_hw dp_link_hw; +- struct clk_hw dp_pixel_hw; +-}; +- +-/** +- * struct qcom_qmp - structure holding QMP phy block attributes +- * +- * @dev: device +- * @dp_com: iomapped memory space for phy's dp_com control block +- * +- * @clks: array of clocks required by phy +- * @resets: array of resets required by phy +- * @vregs: regulator supplies bulk data +- * +- * @phys: array of per-lane phy descriptors +- * @phy_mutex: mutex lock for PHY common block initialization +- * @init_count: phy common block initialization count +- * @ufs_reset: optional UFS PHY reset handle +- */ +-struct qcom_qmp { +- struct device *dev; +- void __iomem *dp_com; +- +- struct clk_bulk_data *clks; +- struct reset_control **resets; +- struct regulator_bulk_data *vregs; +- +- struct qmp_phy **phys; +- +- struct mutex phy_mutex; +- int init_count; +- +- struct reset_control *ufs_reset; +-}; +- +-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); +-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); +-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); +-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); +- +-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); +-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); +-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); +-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); +- +-static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +-{ +- u32 reg; +- +- reg = readl(base + offset); +- reg |= val; +- writel(reg, base + offset); +- +- /* ensure that above write is through */ +- readl(base + offset); +-} +- +-static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +-{ +- u32 reg; +- +- reg = readl(base + offset); +- reg &= ~val; +- writel(reg, base + offset); +- +- /* ensure that above write is through */ +- readl(base + offset); +-} +- +-/* list of clocks required by phy */ +-static const char * const msm8996_phy_clk_l[] = { +- "aux", "cfg_ahb", "ref", +-}; +- +-static const char * const msm8996_ufs_phy_clk_l[] = { +- "ref", +-}; +- +-static const char * const qmp_v3_phy_clk_l[] = { +- "aux", "cfg_ahb", "ref", "com_aux", +-}; +- +-static const char * const sdm845_pciephy_clk_l[] = { +- "aux", "cfg_ahb", "ref", "refgen", +-}; +- +-static const char * const qmp_v4_phy_clk_l[] = { +- "aux", "ref_clk_src", "ref", "com_aux", +-}; +- +-/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +-static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { +- "aux", "ref_clk_src", "com_aux" +-}; +- +-static const char * const sm8450_ufs_phy_clk_l[] = { +- "qref", "ref", "ref_aux", +-}; +- +-static const char * const sdm845_ufs_phy_clk_l[] = { +- "ref", "ref_aux", +-}; +- +-/* usb3 phy on sdx55 doesn't have com_aux clock */ +-static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { +- "aux", "cfg_ahb", "ref" +-}; +- +-static const char * const qcm2290_usb3phy_clk_l[] = { +- "cfg_ahb", "ref", "com_aux", +-}; +- +-/* list of resets */ +-static const char * const msm8996_pciephy_reset_l[] = { +- "phy", "common", "cfg", +-}; +- +-static const char * const msm8996_usb3phy_reset_l[] = { +- "phy", "common", +-}; +- +-static const char * const sc7180_usb3phy_reset_l[] = { +- "phy", +-}; +- +-static const char * const qcm2290_usb3phy_reset_l[] = { +- "phy_phy", "phy", +-}; +- +-static const char * const sdm845_pciephy_reset_l[] = { +- "phy", +-}; +- +-/* list of regulators */ +-static const char * const qmp_phy_vreg_l[] = { +- "vdda-phy", "vdda-pll", +-}; +- +-static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = ipq8074_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), +- .tx_tbl = msm8996_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), +- .rx_tbl = ipq8074_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), +- .pcs_tbl = ipq8074_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +-}; +- +-static const struct qmp_phy_cfg msm8996_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 3, +- +- .serdes_tbl = msm8996_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), +- .tx_tbl = msm8996_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), +- .rx_tbl = msm8996_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), +- .pcs_tbl = msm8996_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = msm8996_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = pciephy_regs_layout, +- +- .start_ctrl = PCS_START | PLL_READY_GATE_EN, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .mask_com_pcs_ready = PCS_READY, +- .phy_status = PHYSTATUS, +- +- .has_phy_com_ctrl = true, +- .has_lane_rst = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; +- +-static const struct qmp_phy_cfg msm8996_ufs_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 1, +- +- .serdes_tbl = msm8996_ufs_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), +- .tx_tbl = msm8996_ufs_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), +- .rx_tbl = msm8996_ufs_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), +- +- .clk_list = msm8996_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), +- +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- +- .regs = msm8996_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .no_pcs_sw_reset = true, +-}; +- +-static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = msm8996_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), +- .tx_tbl = msm8996_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), +- .rx_tbl = msm8996_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), +- .pcs_tbl = msm8996_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +-}; +- +-static const char * const ipq8074_pciephy_clk_l[] = { +- "aux", "cfg_ahb", +-}; +-/* list of resets */ +-static const char * const ipq8074_pciephy_reset_l[] = { +- "phy", "common", +-}; +- +-static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = ipq8074_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), +- .tx_tbl = ipq8074_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), +- .rx_tbl = ipq8074_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), +- .pcs_tbl = ipq8074_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), +- .clk_list = ipq8074_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), +- .reset_list = ipq8074_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), +- .vreg_list = NULL, +- .num_vregs = 0, +- .regs = pciephy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_phy_com_ctrl = false, +- .has_lane_rst = false, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = ipq6018_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), +- .tx_tbl = ipq6018_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), +- .rx_tbl = ipq6018_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), +- .pcs_tbl = ipq6018_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), +- .clk_list = ipq8074_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), +- .reset_list = ipq8074_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), +- .vreg_list = NULL, +- .num_vregs = 0, +- .regs = ipq_pciephy_gen3_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- +- .has_phy_com_ctrl = false, +- .has_lane_rst = false, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), +- .tx_tbl = sdm845_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), +- .rx_tbl = sdm845_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), +- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), +- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sdm845_qmp_pciephy_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), +- .tx_tbl = sdm845_qhp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), +- .rx_tbl = sdm845_qhp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), +- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sdm845_qhp_pciephy_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), +- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, +- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), +- .tx_tbl = sm8250_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), +- .rx_tbl = sm8250_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), +- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, +- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), +- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), +- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, +- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), +- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 2, +- +- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), +- .tx_tbl = sm8250_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), +- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, +- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), +- .rx_tbl = sm8250_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), +- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, +- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), +- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), +- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, +- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), +- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v3_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), +- .tx_tbl = qmp_v3_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), +- .rx_tbl = qmp_v3_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), +- .pcs_tbl = qmp_v3_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v3_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), +- .tx_tbl = qmp_v3_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), +- .rx_tbl = qmp_v3_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), +- .pcs_tbl = qmp_v3_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = sc7180_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sc7180_dpphy_cfg = { +- .type = PHY_TYPE_DP, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v3_dp_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), +- .tx_tbl = qmp_v3_dp_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), +- +- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, +- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), +- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, +- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), +- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, +- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), +- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, +- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), +- +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = sc7180_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +- +- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, +- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, +- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, +- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, +-}; +- +-static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { +- .usb_cfg = &sc7180_usb3phy_cfg, +- .dp_cfg = &sc7180_dpphy_cfg, +-}; +- +-static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), +- .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), +- .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), +- .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; +- +-static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sdm845_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), +- .tx_tbl = sdm845_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), +- .rx_tbl = sdm845_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), +- .pcs_tbl = sdm845_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sdm845_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +- .no_pcs_sw_reset = true, +-}; +- +-static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 1, +- +- .serdes_tbl = sm6115_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), +- .tx_tbl = sm6115_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), +- .rx_tbl = sm6115_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), +- .pcs_tbl = sm6115_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm6115_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- +- .is_dual_lane_phy = false, +- .no_pcs_sw_reset = true, +-}; +- +-static const struct qmp_phy_cfg msm8998_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = msm8998_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), +- .tx_tbl = msm8998_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), +- .rx_tbl = msm8998_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), +- .pcs_tbl = msm8998_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = ipq8074_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = pciephy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +-}; +- +-static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = msm8998_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), +- .tx_tbl = msm8998_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), +- .rx_tbl = msm8998_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), +- .pcs_tbl = msm8998_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sm8150_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), +- .tx_tbl = sm8150_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), +- .rx_tbl = sm8150_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), +- .pcs_tbl = sm8150_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8150_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), +- .tx_tbl = sm8150_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), +- .rx_tbl = sm8150_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), +- .pcs_tbl = sm8150_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), +- .clk_list = qmp_v4_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), +- .tx_tbl = sc8180x_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), +- .rx_tbl = sc8180x_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), +- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), +- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { +- .type = PHY_TYPE_DP, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v4_dp_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), +- .tx_tbl = qmp_v4_dp_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), +- +- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, +- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), +- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, +- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), +- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, +- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), +- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, +- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), +- +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = sc7180_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +- +- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, +- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, +- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, +- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +-}; +- +-static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { +- .usb_cfg = &sm8150_usb3phy_cfg, +- .dp_cfg = &sc8180x_dpphy_cfg, +-}; +- +-static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), +- .tx_tbl = sm8150_usb3_uniphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), +- .rx_tbl = sm8150_usb3_uniphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), +- .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), +- .clk_list = qmp_v4_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3_uniphy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; +- +-static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), +- .tx_tbl = sm8250_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), +- .rx_tbl = sm8250_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), +- .pcs_tbl = sm8250_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), +- .clk_list = qmp_v4_sm8250_usbphy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), +- .tx_tbl = sm8250_usb3_uniphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), +- .rx_tbl = sm8250_usb3_uniphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), +- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), +- .clk_list = qmp_v4_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3_uniphy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; +- +-static const struct qmp_phy_cfg sm8250_dpphy_cfg = { +- .type = PHY_TYPE_DP, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v4_dp_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), +- .tx_tbl = qmp_v4_dp_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), +- +- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, +- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), +- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, +- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), +- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, +- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), +- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, +- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), +- +- .clk_list = qmp_v4_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3phy_regs_layout, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +- +- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, +- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, +- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, +- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +-}; +- +-static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { +- .usb_cfg = &sm8250_usb3phy_cfg, +- .dp_cfg = &sm8250_dpphy_cfg, +-}; +- +-static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), +- .tx_tbl = sdx55_usb3_uniphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), +- .rx_tbl = sdx55_usb3_uniphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), +- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), +- .clk_list = qmp_v4_sdx55_usbphy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3_uniphy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; +- +-static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 2, +- +- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), +- .tx_tbl = sdx55_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), +- .rx_tbl = sdx55_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), +- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), +- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS_4_20, +- +- .is_dual_lane_phy = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ ++/** ++ * struct qmp_phy - per-lane phy descriptor ++ * ++ * @phy: generic phy ++ * @cfg: phy specific configuration ++ * @serdes: iomapped memory space for phy's serdes (i.e. PLL) ++ * @tx: iomapped memory space for lane's tx ++ * @rx: iomapped memory space for lane's rx ++ * @pcs: iomapped memory space for lane's pcs ++ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) ++ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) ++ * @pcs_misc: iomapped memory space for lane's pcs_misc ++ * @pipe_clk: pipe clock ++ * @index: lane index ++ * @qmp: QMP phy to which this lane belongs ++ * @lane_rst: lane's reset controller ++ * @mode: current PHY mode ++ * @dp_aux_cfg: Display port aux config ++ * @dp_opts: Display port optional config ++ * @dp_clks: Display port clocks ++ */ ++struct qmp_phy { ++ struct phy *phy; ++ const struct qmp_phy_cfg *cfg; ++ void __iomem *serdes; ++ void __iomem *tx; ++ void __iomem *rx; ++ void __iomem *pcs; ++ void __iomem *tx2; ++ void __iomem *rx2; ++ void __iomem *pcs_misc; ++ struct clk *pipe_clk; ++ unsigned int index; ++ struct qcom_qmp *qmp; ++ struct reset_control *lane_rst; ++ enum phy_mode mode; ++ unsigned int dp_aux_cfg; ++ struct phy_configure_opts_dp dp_opts; ++ struct qmp_phy_dp_clks *dp_clks; + }; + +-static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), +- .tx_tbl = sdx65_usb3_uniphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), +- .rx_tbl = sdx65_usb3_uniphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), +- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), +- .clk_list = qmp_v4_sdx55_usbphy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8350_usb3_uniphy_regs_layout, ++struct qmp_phy_dp_clks { ++ struct qmp_phy *qphy; ++ struct clk_hw dp_link_hw; ++ struct clk_hw dp_pixel_hw; ++}; + +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, ++/** ++ * struct qcom_qmp - structure holding QMP phy block attributes ++ * ++ * @dev: device ++ * @dp_com: iomapped memory space for phy's dp_com control block ++ * ++ * @clks: array of clocks required by phy ++ * @resets: array of resets required by phy ++ * @vregs: regulator supplies bulk data ++ * ++ * @phys: array of per-lane phy descriptors ++ * @phy_mutex: mutex lock for PHY common block initialization ++ * @init_count: phy common block initialization count ++ * @ufs_reset: optional UFS PHY reset handle ++ */ ++struct qcom_qmp { ++ struct device *dev; ++ void __iomem *dp_com; + +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; ++ struct clk_bulk_data *clks; ++ struct reset_control **resets; ++ struct regulator_bulk_data *vregs; + +-static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sm8350_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), +- .tx_tbl = sm8350_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), +- .rx_tbl = sm8350_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), +- .pcs_tbl = sm8350_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8150_ufsphy_regs_layout, ++ struct qmp_phy **phys; + +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, ++ struct mutex phy_mutex; ++ int init_count; + +- .is_dual_lane_phy = true, ++ struct reset_control *ufs_reset; + }; + +-static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), +- .tx_tbl = sm8350_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), +- .rx_tbl = sm8350_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), +- .pcs_tbl = sm8350_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), +- .clk_list = qmp_v4_sm8250_usbphy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3phy_regs_layout, ++static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; + +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, ++ reg = readl(base + offset); ++ reg |= val; ++ writel(reg, base + offset); + +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++ /* ensure that above write is through */ ++ readl(base + offset); ++} + +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +-}; ++static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) ++{ ++ u32 reg; + +-static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), +- .tx_tbl = sm8350_usb3_uniphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), +- .rx_tbl = sm8350_usb3_uniphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), +- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), +- .clk_list = qmp_v4_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8350_usb3_uniphy_regs_layout, ++ reg = readl(base + offset); ++ reg &= ~val; ++ writel(reg, base + offset); + +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, ++ /* ensure that above write is through */ ++ readl(base + offset); ++} + +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ++/* list of clocks required by phy */ ++static const char * const msm8996_phy_clk_l[] = { ++ "aux", "cfg_ahb", "ref", + }; + +-static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sm8350_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), +- .tx_tbl = sm8350_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), +- .rx_tbl = sm8350_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), +- .pcs_tbl = sm8350_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), +- .clk_list = sm8450_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8150_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, ++/* list of resets */ ++static const char * const msm8996_pciephy_reset_l[] = { ++ "phy", "common", "cfg", + }; + +-static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), +- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), +- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), +- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ ++/* list of regulators */ ++static const char * const qmp_phy_vreg_l[] = { ++ "vdda-phy", "vdda-pll", + }; + +-static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 2, +- +- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), +- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), +- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), +- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS_4_20, +- +- .is_dual_lane_phy = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; ++static const struct qmp_phy_cfg msm8996_pciephy_cfg = { ++ .type = PHY_TYPE_PCIE, ++ .nlanes = 3, + +-static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { +- .type = PHY_TYPE_USB3, +- .nlanes = 1, +- +- .serdes_tbl = qcm2290_usb3_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), +- .tx_tbl = qcm2290_usb3_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), +- .rx_tbl = qcm2290_usb3_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), +- .pcs_tbl = qcm2290_usb3_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), +- .clk_list = qcm2290_usb3phy_clk_l, +- .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), +- .reset_list = qcm2290_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), ++ .serdes_tbl = msm8996_pcie_serdes_tbl, ++ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), ++ .tx_tbl = msm8996_pcie_tx_tbl, ++ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), ++ .rx_tbl = msm8996_pcie_rx_tbl, ++ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), ++ .pcs_tbl = msm8996_pcie_pcs_tbl, ++ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), ++ .clk_list = msm8996_phy_clk_l, ++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), ++ .reset_list = msm8996_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qcm2290_usb3phy_regs_layout, ++ .regs = pciephy_regs_layout, + +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, ++ .start_ctrl = PCS_START | PLL_READY_GATE_EN, ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .mask_com_pcs_ready = PCS_READY, + .phy_status = PHYSTATUS, + +- .is_dual_lane_phy = true, ++ .has_phy_com_ctrl = true, ++ .has_lane_rst = true, ++ .has_pwrdn_delay = true, ++ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, ++ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + + static void qcom_qmp_phy_configure_lane(void __iomem *base, +@@ -4589,457 +572,10 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) + return 0; + } + +-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) +-{ +- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, +- qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- /* Turn on BIAS current for PHY/PLL */ +- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | +- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, +- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); +- +- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_LANE_0_1_PWRDN | +- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | +- DP_PHY_PD_CTL_DP_CLAMP_EN, +- qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- writel(QSERDES_V3_COM_BIAS_EN | +- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | +- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | +- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, +- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); +- +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); +- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); +- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); +- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); +- qphy->dp_aux_cfg = 0; +- +- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | +- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | +- PHY_AUX_REQ_ERR_MASK, +- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +-} +- +-static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { +- { 0x00, 0x0c, 0x15, 0x1a }, +- { 0x02, 0x0e, 0x16, 0xff }, +- { 0x02, 0x11, 0xff, 0xff }, +- { 0x04, 0xff, 0xff, 0xff } +-}; +- +-static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { +- { 0x02, 0x12, 0x16, 0x1a }, +- { 0x09, 0x19, 0x1f, 0xff }, +- { 0x10, 0x1f, 0xff, 0xff }, +- { 0x1f, 0xff, 0xff, 0xff } +-}; +- +-static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { +- { 0x00, 0x0c, 0x14, 0x19 }, +- { 0x00, 0x0b, 0x12, 0xff }, +- { 0x00, 0x0b, 0xff, 0xff }, +- { 0x04, 0xff, 0xff, 0xff } +-}; +- +-static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { +- { 0x08, 0x0f, 0x16, 0x1f }, +- { 0x11, 0x1e, 0x1f, 0xff }, +- { 0x19, 0x1f, 0xff, 0xff }, +- { 0x1f, 0xff, 0xff, 0xff } +-}; +- +-static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, +- unsigned int drv_lvl_reg, unsigned int emp_post_reg) +-{ +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- unsigned int v_level = 0, p_level = 0; +- u8 voltage_swing_cfg, pre_emphasis_cfg; +- int i; +- +- for (i = 0; i < dp_opts->lanes; i++) { +- v_level = max(v_level, dp_opts->voltage[i]); +- p_level = max(p_level, dp_opts->pre[i]); +- } +- +- if (dp_opts->link_rate <= 2700) { +- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; +- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; +- } else { +- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; +- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; +- } +- +- /* TODO: Move check to config check */ +- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) +- return -EINVAL; +- +- /* Enable MUX to use Cursor values from these registers */ +- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; +- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; +- +- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); +- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); +- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); +- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); +- +- return 0; +-} +- +-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) +-{ +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- u32 bias_en, drvr_en; +- +- if (qcom_qmp_phy_configure_dp_swing(qphy, +- QSERDES_V3_TX_TX_DRV_LVL, +- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) +- return; +- +- if (dp_opts->lanes == 1) { +- bias_en = 0x3e; +- drvr_en = 0x13; +- } else { +- bias_en = 0x3f; +- drvr_en = 0x10; +- } +- +- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); +- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); +- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +-} +- +-static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) +-{ +- u32 val; +- bool reverse = false; +- +- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; +- +- /* +- * TODO: Assume orientation is CC1 for now and two lanes, need to +- * use type-c connector to understand orientation and lanes. +- * +- * Otherwise val changes to be like below if this code understood +- * the orientation of the type-c cable. +- * +- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) +- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; +- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) +- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; +- * if (orientation == ORIENTATION_CC2) +- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); +- */ +- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; +- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); +- +- return reverse; +-} +- +-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) +-{ +- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- u32 phy_vco_div, status; +- unsigned long pixel_freq; +- +- qcom_qmp_phy_configure_dp_mode(qphy); +- +- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); +- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); +- +- switch (dp_opts->link_rate) { +- case 1620: +- phy_vco_div = 0x1; +- pixel_freq = 1620000000UL / 2; +- break; +- case 2700: +- phy_vco_div = 0x1; +- pixel_freq = 2700000000UL / 2; +- break; +- case 5400: +- phy_vco_div = 0x2; +- pixel_freq = 5400000000UL / 4; +- break; +- case 8100: +- phy_vco_div = 0x0; +- pixel_freq = 8100000000UL / 6; +- break; +- default: +- /* Other link rates aren't supported */ +- return -EINVAL; +- } +- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); +- +- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); +- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); +- +- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); +- udelay(2000); +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000); +-} +- +-/* +- * We need to calibrate the aux setting here as many times +- * as the caller tries +- */ +-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) +-{ +- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; +- u8 val; +- +- qphy->dp_aux_cfg++; +- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); +- val = cfg1_settings[qphy->dp_aux_cfg]; +- +- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- +- return 0; +-} +- +-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) +-{ +- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, +- qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- /* Turn on BIAS current for PHY/PLL */ +- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); +- +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); +- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); +- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); +- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); +- qphy->dp_aux_cfg = 0; +- +- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | +- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | +- PHY_AUX_REQ_ERR_MASK, +- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); +-} +- +-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) +-{ +- /* Program default values before writing proper values */ +- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); +- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); +- +- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- +- qcom_qmp_phy_configure_dp_swing(qphy, +- QSERDES_V4_TX_TX_DRV_LVL, +- QSERDES_V4_TX_TX_EMP_POST1_LVL); +-} +- +-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) +-{ +- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- u32 phy_vco_div, status; +- unsigned long pixel_freq; +- u32 bias0_en, drvr0_en, bias1_en, drvr1_en; +- bool reverse; +- +- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); +- +- reverse = qcom_qmp_phy_configure_dp_mode(qphy); +- +- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- +- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); +- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); +- +- switch (dp_opts->link_rate) { +- case 1620: +- phy_vco_div = 0x1; +- pixel_freq = 1620000000UL / 2; +- break; +- case 2700: +- phy_vco_div = 0x1; +- pixel_freq = 2700000000UL / 2; +- break; +- case 5400: +- phy_vco_div = 0x2; +- pixel_freq = 5400000000UL / 4; +- break; +- case 8100: +- phy_vco_div = 0x0; +- pixel_freq = 8100000000UL / 6; +- break; +- default: +- /* Other link rates aren't supported */ +- return -EINVAL; +- } +- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); +- +- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); +- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); +- +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- /* +- * At least for 7nm DP PHY this has to be done after enabling link +- * clock. +- */ +- +- if (dp_opts->lanes == 1) { +- bias0_en = reverse ? 0x3e : 0x15; +- bias1_en = reverse ? 0x15 : 0x3e; +- drvr0_en = reverse ? 0x13 : 0x10; +- drvr1_en = reverse ? 0x10 : 0x13; +- } else if (dp_opts->lanes == 2) { +- bias0_en = reverse ? 0x3f : 0x15; +- bias1_en = reverse ? 0x15 : 0x3f; +- drvr0_en = 0x10; +- drvr1_en = 0x10; +- } else { +- bias0_en = 0x3f; +- bias1_en = 0x3f; +- drvr0_en = 0x10; +- drvr1_en = 0x10; +- } +- +- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); +- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); +- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); +- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); +- +- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); +- udelay(2000); +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); +- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); +- +- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); +- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); +- +- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- +- return 0; +-} +- + /* + * We need to calibrate the aux setting here as many times + * as the caller tries + */ +-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) +-{ +- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; +- u8 val; +- +- qphy->dp_aux_cfg++; +- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); +- val = cfg1_settings[qphy->dp_aux_cfg]; +- +- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- +- return 0; +-} +- + static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) + { + const struct phy_configure_opts_dp *dp_opts = &opts->dp; +@@ -6021,161 +1557,13 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + + static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + { +- .compatible = "qcom,ipq8074-qmp-usb3-phy", +- .data = &ipq8074_usb3phy_cfg, +- }, { + .compatible = "qcom,msm8996-qmp-pcie-phy", + .data = &msm8996_pciephy_cfg, +- }, { +- .compatible = "qcom,msm8996-qmp-ufs-phy", +- .data = &msm8996_ufs_cfg, +- }, { +- .compatible = "qcom,msm8996-qmp-usb3-phy", +- .data = &msm8996_usb3phy_cfg, +- }, { +- .compatible = "qcom,msm8998-qmp-pcie-phy", +- .data = &msm8998_pciephy_cfg, +- }, { +- .compatible = "qcom,msm8998-qmp-ufs-phy", +- .data = &sdm845_ufsphy_cfg, +- }, { +- .compatible = "qcom,ipq8074-qmp-pcie-phy", +- .data = &ipq8074_pciephy_cfg, +- }, { +- .compatible = "qcom,ipq6018-qmp-pcie-phy", +- .data = &ipq6018_pciephy_cfg, +- }, { +- .compatible = "qcom,ipq6018-qmp-usb3-phy", +- .data = &ipq8074_usb3phy_cfg, +- }, { +- .compatible = "qcom,sc7180-qmp-usb3-phy", +- .data = &sc7180_usb3phy_cfg, +- }, { +- .compatible = "qcom,sc7180-qmp-usb3-dp-phy", +- /* It's a combo phy */ +- }, { +- .compatible = "qcom,sc8180x-qmp-pcie-phy", +- .data = &sc8180x_pciephy_cfg, +- }, { +- .compatible = "qcom,sc8180x-qmp-ufs-phy", +- .data = &sm8150_ufsphy_cfg, +- }, { +- .compatible = "qcom,sc8280xp-qmp-ufs-phy", +- .data = &sm8350_ufsphy_cfg, +- }, { +- .compatible = "qcom,sc8180x-qmp-usb3-phy", +- .data = &sm8150_usb3phy_cfg, +- }, { +- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", +- /* It's a combo phy */ +- }, { +- .compatible = "qcom,sdm845-qhp-pcie-phy", +- .data = &sdm845_qhp_pciephy_cfg, +- }, { +- .compatible = "qcom,sdm845-qmp-pcie-phy", +- .data = &sdm845_qmp_pciephy_cfg, +- }, { +- .compatible = "qcom,sdm845-qmp-usb3-phy", +- .data = &qmp_v3_usb3phy_cfg, +- }, { +- .compatible = "qcom,sdm845-qmp-usb3-uni-phy", +- .data = &qmp_v3_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sdm845-qmp-ufs-phy", +- .data = &sdm845_ufsphy_cfg, +- }, { +- .compatible = "qcom,msm8998-qmp-usb3-phy", +- .data = &msm8998_usb3phy_cfg, +- }, { +- .compatible = "qcom,sm6115-qmp-ufs-phy", +- .data = &sm6115_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm6350-qmp-ufs-phy", +- .data = &sdm845_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8150-qmp-ufs-phy", +- .data = &sm8150_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-ufs-phy", +- .data = &sm8150_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8150-qmp-usb3-phy", +- .data = &sm8150_usb3phy_cfg, +- }, { +- .compatible = "qcom,sm8150-qmp-usb3-uni-phy", +- .data = &sm8150_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-usb3-phy", +- .data = &sm8250_usb3phy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-usb3-dp-phy", +- /* It's a combo phy */ +- }, { +- .compatible = "qcom,sm8250-qmp-usb3-uni-phy", +- .data = &sm8250_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", +- .data = &sm8250_qmp_gen3x1_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", +- .data = &sm8250_qmp_gen3x2_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8350-qmp-ufs-phy", +- .data = &sm8350_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-modem-pcie-phy", +- .data = &sm8250_qmp_gen3x2_pciephy_cfg, +- }, { +- .compatible = "qcom,sdx55-qmp-pcie-phy", +- .data = &sdx55_qmp_pciephy_cfg, +- }, { +- .compatible = "qcom,sdx55-qmp-usb3-uni-phy", +- .data = &sdx55_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sdx65-qmp-usb3-uni-phy", +- .data = &sdx65_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sm8350-qmp-usb3-phy", +- .data = &sm8350_usb3phy_cfg, +- }, { +- .compatible = "qcom,sm8350-qmp-usb3-uni-phy", +- .data = &sm8350_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", +- .data = &sm8450_qmp_gen3x1_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", +- .data = &sm8450_qmp_gen4x2_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-ufs-phy", +- .data = &sm8450_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-usb3-phy", +- .data = &sm8350_usb3phy_cfg, +- }, { +- .compatible = "qcom,qcm2290-qmp-usb3-phy", +- .data = &qcm2290_usb3phy_cfg, + }, + { }, + }; + MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); + +-static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { +- { +- .compatible = "qcom,sc7180-qmp-usb3-dp-phy", +- .data = &sc7180_usb3dpphy_cfg, +- }, +- { +- .compatible = "qcom,sm8250-qmp-usb3-dp-phy", +- .data = &sm8250_usb3dpphy_cfg, +- }, +- { +- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", +- .data = &sc8180x_usb3dpphy_cfg, +- }, +- { } +-}; +- + static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, + qcom_qmp_phy_runtime_resume, NULL) +@@ -6206,20 +1594,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + + /* Get the specific init parameters of QMP phy */ + cfg = of_device_get_match_data(dev); +- if (!cfg) { +- const struct of_device_id *match; +- +- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); +- if (!match) +- return -EINVAL; +- +- combo_cfg = match->data; +- if (!combo_cfg) +- return -EINVAL; +- +- usb_cfg = combo_cfg->usb_cfg; +- cfg = usb_cfg; /* Setup clks and regulators */ +- } ++ if (!cfg) ++ return -EINVAL; + + /* per PHY serdes; usually located at base address */ + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); +@@ -6337,7 +1713,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + static struct platform_driver qcom_qmp_phy_driver = { + .probe = qcom_qmp_phy_probe, + .driver = { +- .name = "qcom-qmp-phy", ++ .name = "qcom-qmp-msm8996-pcie-phy", + .pm = &qcom_qmp_phy_pm_ops, + .of_match_table = qcom_qmp_phy_of_match_table, + }, +@@ -6346,5 +1722,5 @@ static struct platform_driver qcom_qmp_phy_driver = { + module_platform_driver(qcom_qmp_phy_driver); + + MODULE_AUTHOR("Vivek Gautam "); +-MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver"); + MODULE_LICENSE("GPL v2"); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-pcie-msm8996-drop-support-for-non-pcie-.patch b/queue-5.10/phy-qcom-qmp-pcie-msm8996-drop-support-for-non-pcie-.patch new file mode 100644 index 00000000000..0b6c93fc30b --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-pcie-msm8996-drop-support-for-non-pcie-.patch @@ -0,0 +1,712 @@ +From a417a6ed8d18b2f57eb322f8470fc9268b3cf36e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:49 +0300 +Subject: phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types + +From: Dmitry Baryshkov + +[ Upstream commit f575ac2d64e7cedb2d70acd5baa359da216cf718 ] + +Drop remaining support for PHY types other than PCIe. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-17-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 532 ++---------------- + 1 file changed, 43 insertions(+), 489 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +index 1741a5675f9a..02e5ae7fa213 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +@@ -510,7 +510,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + int ret; +@@ -520,35 +519,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) + qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + +- if (cfg->type == PHY_TYPE_DP) { +- switch (dp_opts->link_rate) { +- case 1620: +- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, +- cfg->serdes_tbl_rbr, +- cfg->serdes_tbl_rbr_num); +- break; +- case 2700: +- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, +- cfg->serdes_tbl_hbr, +- cfg->serdes_tbl_hbr_num); +- break; +- case 5400: +- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, +- cfg->serdes_tbl_hbr2, +- cfg->serdes_tbl_hbr2_num); +- break; +- case 8100: +- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, +- cfg->serdes_tbl_hbr3, +- cfg->serdes_tbl_hbr3_num); +- break; +- default: +- /* Other link rates aren't supported */ +- return -EINVAL; +- } +- } +- +- + if (cfg->has_phy_com_ctrl) { + void __iomem *status; + unsigned int mask, val; +@@ -572,36 +542,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) + return 0; + } + +-/* +- * We need to calibrate the aux setting here as many times +- * as the caller tries +- */ +-static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +-{ +- const struct phy_configure_opts_dp *dp_opts = &opts->dp; +- struct qmp_phy *qphy = phy_get_drvdata(phy); +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- +- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); +- if (qphy->dp_opts.set_voltages) { +- cfg->configure_dp_tx(qphy); +- qphy->dp_opts.set_voltages = 0; +- } +- +- return 0; +-} +- +-static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +-{ +- struct qmp_phy *qphy = phy_get_drvdata(phy); +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- +- if (cfg->calibrate_dp_phy) +- return cfg->calibrate_dp_phy(qphy); +- +- return 0; +-} +- + static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; +@@ -771,9 +711,6 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) + if (ret) + return ret; + +- if (cfg->type == PHY_TYPE_DP) +- cfg->dp_aux_init(qphy); +- + return 0; + } + +@@ -824,10 +761,6 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + cfg->tx_tbl_num_sec, 2); + } + +- /* Configure special DP tx tunings */ +- if (cfg->type == PHY_TYPE_DP) +- cfg->configure_dp_tx(qphy); +- + qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) +@@ -843,15 +776,10 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + cfg->rx_tbl_num_sec, 2); + } + +- /* Configure link rate, swing, etc. */ +- if (cfg->type == PHY_TYPE_DP) { +- cfg->configure_dp_phy(qphy); +- } else { +- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); +- if (cfg->pcs_tbl_sec) +- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, +- cfg->pcs_tbl_num_sec); +- } ++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); + + ret = reset_control_deassert(qmp->ufs_reset); + if (ret) +@@ -867,36 +795,28 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) + * Pull out PHY from POWER DOWN state. + * This is active low enable signal to power-down PHY. + */ +- if(cfg->type == PHY_TYPE_PCIE) +- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + +- if (cfg->type != PHY_TYPE_DP) { +- /* Pull PHY out of reset state */ +- if (!cfg->no_pcs_sw_reset) +- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); +- /* start SerDes and Phy-Coding-Sublayer */ +- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); +- +- if (cfg->type == PHY_TYPE_UFS) { +- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; +- mask = PCS_READY; +- ready = PCS_READY; +- } else { +- status = pcs + cfg->regs[QPHY_PCS_STATUS]; +- mask = cfg->phy_status; +- ready = 0; +- } ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + +- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, +- PHY_INIT_COMPLETE_TIMEOUT); +- if (ret) { +- dev_err(qmp->dev, "phy initialization timed-out\n"); +- goto err_disable_pipe_clk; +- } ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; + } ++ + return 0; + + err_disable_pipe_clk: +@@ -915,25 +835,20 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) + + clk_disable_unprepare(qphy->pipe_clk); + +- if (cfg->type == PHY_TYPE_DP) { +- /* Assert DP PHY power down */ +- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- } else { +- /* PHY reset */ +- if (!cfg->no_pcs_sw_reset) +- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + +- /* stop SerDes and Phy-Coding-Sublayer */ +- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + +- /* Put PHY into POWER DOWN state: active low */ +- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { +- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], +- cfg->pwrdn_ctrl); +- } else { +- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, +- cfg->pwrdn_ctrl); +- } ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); + } + + return 0; +@@ -987,112 +902,6 @@ static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy, + return 0; + } + +-static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy) +-{ +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- void __iomem *pcs = qphy->pcs; +- void __iomem *pcs_misc = qphy->pcs_misc; +- u32 intr_mask; +- +- if (qphy->mode == PHY_MODE_USB_HOST_SS || +- qphy->mode == PHY_MODE_USB_DEVICE_SS) +- intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; +- else +- intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; +- +- /* Clear any pending interrupts status */ +- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +- /* Writing 1 followed by 0 clears the interrupt */ +- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +- +- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], +- ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); +- +- /* Enable required PHY autonomous mode interrupts */ +- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); +- +- /* Enable i/o clamp_n for autonomous mode */ +- if (pcs_misc) +- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); +-} +- +-static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy) +-{ +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- void __iomem *pcs = qphy->pcs; +- void __iomem *pcs_misc = qphy->pcs_misc; +- +- /* Disable i/o clamp_n on resume for normal mode */ +- if (pcs_misc) +- qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); +- +- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], +- ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); +- +- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +- /* Writing 1 followed by 0 clears the interrupt */ +- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); +-} +- +-static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev) +-{ +- struct qcom_qmp *qmp = dev_get_drvdata(dev); +- struct qmp_phy *qphy = qmp->phys[0]; +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- +- dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); +- +- /* Supported only for USB3 PHY and luckily USB3 is the first phy */ +- if (cfg->type != PHY_TYPE_USB3) +- return 0; +- +- if (!qmp->init_count) { +- dev_vdbg(dev, "PHY not initialized, bailing out\n"); +- return 0; +- } +- +- qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy); +- +- clk_disable_unprepare(qphy->pipe_clk); +- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); +- +- return 0; +-} +- +-static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev) +-{ +- struct qcom_qmp *qmp = dev_get_drvdata(dev); +- struct qmp_phy *qphy = qmp->phys[0]; +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- int ret = 0; +- +- dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); +- +- /* Supported only for USB3 PHY and luckily USB3 is the first phy */ +- if (cfg->type != PHY_TYPE_USB3) +- return 0; +- +- if (!qmp->init_count) { +- dev_vdbg(dev, "PHY not initialized, bailing out\n"); +- return 0; +- } +- +- ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); +- if (ret) +- return ret; +- +- ret = clk_prepare_enable(qphy->pipe_clk); +- if (ret) { +- dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); +- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); +- return ret; +- } +- +- qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy); +- +- return 0; +-} +- + static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); +@@ -1210,223 +1019,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + } + +-/* +- * Display Port PLL driver block diagram for branch clocks +- * +- * +------------------------------+ +- * | DP_VCO_CLK | +- * | | +- * | +-------------------+ | +- * | | (DP PLL/VCO) | | +- * | +---------+---------+ | +- * | v | +- * | +----------+-----------+ | +- * | | hsclk_divsel_clk_src | | +- * | +----------+-----------+ | +- * +------------------------------+ +- * | +- * +---------<---------v------------>----------+ +- * | | +- * +--------v----------------+ | +- * | dp_phy_pll_link_clk | | +- * | link_clk | | +- * +--------+----------------+ | +- * | | +- * | | +- * v v +- * Input to DISPCC block | +- * for link clk, crypto clk | +- * and interface clock | +- * | +- * | +- * +--------<------------+-----------------+---<---+ +- * | | | +- * +----v---------+ +--------v-----+ +--------v------+ +- * | vco_divided | | vco_divided | | vco_divided | +- * | _clk_src | | _clk_src | | _clk_src | +- * | | | | | | +- * |divsel_six | | divsel_two | | divsel_four | +- * +-------+------+ +-----+--------+ +--------+------+ +- * | | | +- * v---->----------v-------------<------v +- * | +- * +----------+-----------------+ +- * | dp_phy_pll_vco_div_clk | +- * +---------+------------------+ +- * | +- * v +- * Input to DISPCC block +- * for DP pixel clock +- * +- */ +-static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- switch (req->rate) { +- case 1620000000UL / 2: +- case 2700000000UL / 2: +- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ +- return 0; +- default: +- return -EINVAL; +- } +-} +- +-static unsigned long +-qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +-{ +- const struct qmp_phy_dp_clks *dp_clks; +- const struct qmp_phy *qphy; +- const struct phy_configure_opts_dp *dp_opts; +- +- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); +- qphy = dp_clks->qphy; +- dp_opts = &qphy->dp_opts; +- +- switch (dp_opts->link_rate) { +- case 1620: +- return 1620000000UL / 2; +- case 2700: +- return 2700000000UL / 2; +- case 5400: +- return 5400000000UL / 4; +- case 8100: +- return 8100000000UL / 6; +- default: +- return 0; +- } +-} +- +-static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { +- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, +- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, +-}; +- +-static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- switch (req->rate) { +- case 162000000: +- case 270000000: +- case 540000000: +- case 810000000: +- return 0; +- default: +- return -EINVAL; +- } +-} +- +-static unsigned long +-qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +-{ +- const struct qmp_phy_dp_clks *dp_clks; +- const struct qmp_phy *qphy; +- const struct phy_configure_opts_dp *dp_opts; +- +- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); +- qphy = dp_clks->qphy; +- dp_opts = &qphy->dp_opts; +- +- switch (dp_opts->link_rate) { +- case 1620: +- case 2700: +- case 5400: +- case 8100: +- return dp_opts->link_rate * 100000; +- default: +- return 0; +- } +-} +- +-static const struct clk_ops qcom_qmp_dp_link_clk_ops = { +- .determine_rate = qcom_qmp_dp_link_clk_determine_rate, +- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, +-}; +- +-static struct clk_hw * +-qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) +-{ +- struct qmp_phy_dp_clks *dp_clks = data; +- unsigned int idx = clkspec->args[0]; +- +- if (idx >= 2) { +- pr_err("%s: invalid index %u\n", __func__, idx); +- return ERR_PTR(-EINVAL); +- } +- +- if (idx == 0) +- return &dp_clks->dp_link_hw; +- +- return &dp_clks->dp_pixel_hw; +-} +- +-static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, +- struct device_node *np) +-{ +- struct clk_init_data init = { }; +- struct qmp_phy_dp_clks *dp_clks; +- char name[64]; +- int ret; +- +- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); +- if (!dp_clks) +- return -ENOMEM; +- +- dp_clks->qphy = qphy; +- qphy->dp_clks = dp_clks; +- +- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); +- init.ops = &qcom_qmp_dp_link_clk_ops; +- init.name = name; +- dp_clks->dp_link_hw.init = &init; +- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); +- if (ret) +- return ret; +- +- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); +- init.ops = &qcom_qmp_dp_pixel_clk_ops; +- init.name = name; +- dp_clks->dp_pixel_hw.init = &init; +- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); +- if (ret) +- return ret; +- +- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); +- if (ret) +- return ret; +- +- /* +- * Roll a devm action because the clock provider is the child node, but +- * the child node is not actually a device. +- */ +- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +-} +- +-static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = { ++static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = { + .init = qcom_qmp_phy_pcie_msm8996_enable, + .exit = qcom_qmp_phy_pcie_msm8996_disable, + .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, + .owner = THIS_MODULE, + }; + +-static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = { +- .init = qcom_qmp_phy_pcie_msm8996_init, +- .configure = qcom_qmp_dp_phy_configure, +- .power_on = qcom_qmp_phy_pcie_msm8996_power_on, +- .calibrate = qcom_qmp_dp_phy_calibrate, +- .power_off = qcom_qmp_phy_pcie_msm8996_power_off, +- .exit = qcom_qmp_phy_pcie_msm8996_exit, +- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, +- .owner = THIS_MODULE, +-}; +- +-static const struct phy_ops qcom_qmp_pcie_ufs_ops = { +- .power_on = qcom_qmp_phy_pcie_msm8996_enable, +- .power_off = qcom_qmp_phy_pcie_msm8996_disable, +- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, +- .owner = THIS_MODULE, +-}; +- + static void qcom_qmp_reset_control_put(void *data) + { + reset_control_put(data); +@@ -1439,7 +1038,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; +- const struct phy_ops *ops; + char prop_name[MAX_PROP_NAME]; + int ret; + +@@ -1532,14 +1130,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, + return ret; + } + +- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) +- ops = &qcom_qmp_pcie_ufs_ops; +- else if (cfg->type == PHY_TYPE_DP) +- ops = &qcom_qmp_phy_pcie_msm8996_dp_ops; +- else +- ops = &qcom_qmp_phy_pcie_msm8996_gen_ops; +- +- generic_phy = devm_phy_create(dev, np, ops); ++ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); +@@ -1564,11 +1155,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = { + }; + MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table); + +-static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = { +- SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend, +- qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL) +-}; +- + static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + { + struct qcom_qmp *qmp; +@@ -1576,12 +1162,7 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; +- void __iomem *usb_serdes; +- void __iomem *dp_serdes = NULL; +- const struct qmp_phy_combo_cfg *combo_cfg = NULL; + const struct qmp_phy_cfg *cfg = NULL; +- const struct qmp_phy_cfg *usb_cfg = NULL; +- const struct qmp_phy_cfg *dp_cfg = NULL; + int num, id, expected_phys; + int ret; + +@@ -1598,28 +1179,18 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + return -EINVAL; + + /* per PHY serdes; usually located at base address */ +- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + /* per PHY dp_com; if PHY has dp_com control block */ +- if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ if (cfg->has_phy_dp_com_ctrl) { + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->dp_com)) + return PTR_ERR(qmp->dp_com); + } + +- if (combo_cfg) { +- /* Only two serdes for combo PHY */ +- dp_serdes = devm_platform_ioremap_resource(pdev, 2); +- if (IS_ERR(dp_serdes)) +- return PTR_ERR(dp_serdes); +- +- dp_cfg = combo_cfg->dp_cfg; +- expected_phys = 2; +- } else { +- expected_phys = cfg->nlanes; +- } ++ expected_phys = cfg->nlanes; + + mutex_init(&qmp->phy_mutex); + +@@ -1658,14 +1229,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { +- if (of_node_name_eq(child, "dp-phy")) { +- cfg = dp_cfg; +- serdes = dp_serdes; +- } else if (of_node_name_eq(child, "usb3-phy")) { +- cfg = usb_cfg; +- serdes = usb_serdes; +- } +- + /* Create per-lane phy */ + ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg); + if (ret) { +@@ -1678,21 +1241,13 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) + * Register the pipe clock provided by phy. + * See function description to see details of this pipe clock. + */ +- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { +- ret = phy_pipe_clk_register(qmp, child); +- if (ret) { +- dev_err(qmp->dev, +- "failed to register pipe clock source\n"); +- goto err_node_put; +- } +- } else if (cfg->type == PHY_TYPE_DP) { +- ret = phy_dp_clks_register(qmp, qmp->phys[id], child); +- if (ret) { +- dev_err(qmp->dev, +- "failed to register DP clock source\n"); +- goto err_node_put; +- } ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; + } ++ + id++; + } + +@@ -1714,7 +1269,6 @@ static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = { + .probe = qcom_qmp_phy_pcie_msm8996_probe, + .driver = { + .name = "qcom-qmp-msm8996-pcie-phy", +- .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops, + .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table, + }, + }; +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-pcie-msm8996-fix-memleak-on-probe-defer.patch b/queue-5.10/phy-qcom-qmp-pcie-msm8996-fix-memleak-on-probe-defer.patch new file mode 100644 index 00000000000..1b1dca09e66 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-pcie-msm8996-fix-memleak-on-probe-defer.patch @@ -0,0 +1,64 @@ +From 2abab4c77f81b7098c3b63174aa789eed360a53e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 12:23:32 +0200 +Subject: phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral + +From: Johan Hovold + +[ Upstream commit 1f69ededf8e80c42352e7f1c165a003614de9cc2 ] + +Switch to using the device-managed of_iomap helper to avoid leaking +memory on probe deferral and driver unbind. + +Note that this helper checks for already reserved regions and may fail +if there are multiple devices claiming the same memory. + +Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20220916102340.11520-4-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 23 +++++++++---------- + 1 file changed, 11 insertions(+), 12 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +index 51da3a3a199e..9caad14aacde 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +@@ -900,21 +900,20 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ +- qphy->tx = of_iomap(np, 0); +- if (!qphy->tx) +- return -ENOMEM; +- +- qphy->rx = of_iomap(np, 1); +- if (!qphy->rx) +- return -ENOMEM; ++ qphy->tx = devm_of_iomap(dev, np, 0, NULL); ++ if (IS_ERR(qphy->tx)) ++ return PTR_ERR(qphy->tx); + +- qphy->pcs = of_iomap(np, 2); +- if (!qphy->pcs) +- return -ENOMEM; ++ qphy->rx = devm_of_iomap(dev, np, 1, NULL); ++ if (IS_ERR(qphy->rx)) ++ return PTR_ERR(qphy->rx); + +- qphy->pcs_misc = of_iomap(np, 3); ++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL); ++ if (IS_ERR(qphy->pcs)) ++ return PTR_ERR(qphy->pcs); + +- if (!qphy->pcs_misc) ++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); ++ if (IS_ERR(qphy->pcs_misc)) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + /* +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-ufs-fix-memleak-on-probe-deferral.patch b/queue-5.10/phy-qcom-qmp-ufs-fix-memleak-on-probe-deferral.patch new file mode 100644 index 00000000000..7675caf1562 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-ufs-fix-memleak-on-probe-deferral.patch @@ -0,0 +1,89 @@ +From 08209657389b42d4b5366c98a03fa6c4ba80e035 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 12:23:34 +0200 +Subject: phy: qcom-qmp-ufs: fix memleak on probe deferral + +From: Johan Hovold + +[ Upstream commit ef74a97f0df8758efe4476b4645961286aa86f0d ] + +Switch to using the device-managed of_iomap helper to avoid leaking +memory on probe deferral and driver unbind. + +Note that this helper checks for already reserved regions and may fail +if there are multiple devices claiming the same memory. + +Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20220916102340.11520-6-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 30 ++++++++++++------------- + 1 file changed, 15 insertions(+), 15 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +index c7309e981bfb..66a89fbacb33 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +@@ -5919,17 +5919,17 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ +- qphy->tx = of_iomap(np, 0); +- if (!qphy->tx) +- return -ENOMEM; ++ qphy->tx = devm_of_iomap(dev, np, 0, NULL); ++ if (IS_ERR(qphy->tx)) ++ return PTR_ERR(qphy->tx); + +- qphy->rx = of_iomap(np, 1); +- if (!qphy->rx) +- return -ENOMEM; ++ qphy->rx = devm_of_iomap(dev, np, 1, NULL); ++ if (IS_ERR(qphy->rx)) ++ return PTR_ERR(qphy->rx); + +- qphy->pcs = of_iomap(np, 2); +- if (!qphy->pcs) +- return -ENOMEM; ++ qphy->pcs = devm_of_iomap(dev, np, 2, NULL); ++ if (IS_ERR(qphy->pcs)) ++ return PTR_ERR(qphy->pcs); + + /* + * If this is a dual-lane PHY, then there should be registers for the +@@ -5938,9 +5938,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { +- qphy->tx2 = of_iomap(np, 3); +- qphy->rx2 = of_iomap(np, 4); +- if (!qphy->tx2 || !qphy->rx2) { ++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); ++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); ++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + +@@ -5950,14 +5950,14 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { +- qphy->pcs_misc = of_iomap(np, 5); ++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); + } + + } else { +- qphy->pcs_misc = of_iomap(np, 3); ++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); + } + +- if (!qphy->pcs_misc) ++ if (IS_ERR(qphy->pcs_misc)) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + + /* +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-change-symbol-prefix-to-qcom_qmp_ph.patch b/queue-5.10/phy-qcom-qmp-usb-change-symbol-prefix-to-qcom_qmp_ph.patch new file mode 100644 index 00000000000..dc2055568e7 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-change-symbol-prefix-to-qcom_qmp_ph.patch @@ -0,0 +1,504 @@ +From 75a813b667769bc3b67572376483a5d1a4c5f6f3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:44 +0300 +Subject: phy: qcom-qmp-usb: change symbol prefix to qcom_qmp_phy_usb + +From: Dmitry Baryshkov + +[ Upstream commit 09b492a379402395f646c6db2e16cdac1fc2229d ] + +Change all symbol names to start with qcom_qmp_phy_usb_ rather than old +qcom_qmp_phy_ + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-12-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 158 ++++++++++++------------ + 1 file changed, 79 insertions(+), 79 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index e147182afea7..2ae13b4485b6 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -2023,7 +2023,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { + .is_dual_lane_phy = true, + }; + +-static void qcom_qmp_phy_configure_lane(void __iomem *base, ++static void qcom_qmp_phy_usb_configure_lane(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num, +@@ -2046,15 +2046,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base, + } + } + +-static void qcom_qmp_phy_configure(void __iomem *base, ++static void qcom_qmp_phy_usb_configure(void __iomem *base, + const unsigned int *regs, + const struct qmp_phy_init_tbl tbl[], + int num) + { +- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); ++ qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff); + } + +-static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) ++static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -2064,30 +2064,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) + int serdes_tbl_num = cfg->serdes_tbl_num; + int ret; + +- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (cfg->serdes_tbl_sec) +- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, ++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + + if (cfg->type == PHY_TYPE_DP) { + switch (dp_opts->link_rate) { + case 1620: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, + cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + case 8100: +- qcom_qmp_phy_configure(serdes, cfg->regs, ++ qcom_qmp_phy_usb_configure(serdes, cfg->regs, + cfg->serdes_tbl_hbr3, + cfg->serdes_tbl_hbr3_num); + break; +@@ -2147,7 +2147,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy) + return 0; + } + +-static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) ++static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -2242,7 +2242,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) + return ret; + } + +-static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) ++static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -2277,7 +2277,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) + return 0; + } + +-static int qcom_qmp_phy_init(struct phy *phy) ++static int qcom_qmp_phy_usb_init(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; +@@ -2312,7 +2312,7 @@ static int qcom_qmp_phy_init(struct phy *phy) + return ret; + } + +- ret = qcom_qmp_phy_com_init(qphy); ++ ret = qcom_qmp_phy_usb_com_init(qphy); + if (ret) + return ret; + +@@ -2322,7 +2322,7 @@ static int qcom_qmp_phy_init(struct phy *phy) + return 0; + } + +-static int qcom_qmp_phy_power_on(struct phy *phy) ++static int qcom_qmp_phy_usb_power_on(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; +@@ -2335,7 +2335,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + unsigned int mask, val, ready; + int ret; + +- qcom_qmp_phy_serdes_init(qphy); ++ qcom_qmp_phy_usb_serdes_init(qphy); + + if (cfg->has_lane_rst) { + ret = reset_control_deassert(qphy->lane_rst); +@@ -2353,18 +2353,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + } + + /* Tx, Rx, and PCS configurations */ +- qcom_qmp_phy_configure_lane(tx, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); + if (cfg->tx_tbl_sec) +- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, ++ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { +- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); + if (cfg->tx_tbl_sec) +- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl_sec, + cfg->tx_tbl_num_sec, 2); + } +@@ -2373,17 +2373,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + if (cfg->type == PHY_TYPE_DP) + cfg->configure_dp_tx(qphy); + +- qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) +- qcom_qmp_phy_configure_lane(rx, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, + cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + + if (cfg->is_dual_lane_phy) { +- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); + if (cfg->rx_tbl_sec) +- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, ++ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl_sec, + cfg->rx_tbl_num_sec, 2); + } +@@ -2392,9 +2392,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + if (cfg->type == PHY_TYPE_DP) { + cfg->configure_dp_phy(qphy); + } else { +- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) +- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); + } + +@@ -2402,10 +2402,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + if (ret) + goto err_disable_pipe_clk; + +- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, ++ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + cfg->pcs_misc_tbl_num); + if (cfg->pcs_misc_tbl_sec) +- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, ++ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + cfg->pcs_misc_tbl_num_sec); + + /* +@@ -2453,7 +2453,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) + return ret; + } + +-static int qcom_qmp_phy_power_off(struct phy *phy) ++static int qcom_qmp_phy_usb_power_off(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -2484,7 +2484,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) + return 0; + } + +-static int qcom_qmp_phy_exit(struct phy *phy) ++static int qcom_qmp_phy_usb_exit(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qphy->cfg; +@@ -2492,37 +2492,37 @@ static int qcom_qmp_phy_exit(struct phy *phy) + if (cfg->has_lane_rst) + reset_control_assert(qphy->lane_rst); + +- qcom_qmp_phy_com_exit(qphy); ++ qcom_qmp_phy_usb_com_exit(qphy); + + return 0; + } + +-static int qcom_qmp_phy_enable(struct phy *phy) ++static int qcom_qmp_phy_usb_enable(struct phy *phy) + { + int ret; + +- ret = qcom_qmp_phy_init(phy); ++ ret = qcom_qmp_phy_usb_init(phy); + if (ret) + return ret; + +- ret = qcom_qmp_phy_power_on(phy); ++ ret = qcom_qmp_phy_usb_power_on(phy); + if (ret) +- qcom_qmp_phy_exit(phy); ++ qcom_qmp_phy_usb_exit(phy); + + return ret; + } + +-static int qcom_qmp_phy_disable(struct phy *phy) ++static int qcom_qmp_phy_usb_disable(struct phy *phy) + { + int ret; + +- ret = qcom_qmp_phy_power_off(phy); ++ ret = qcom_qmp_phy_usb_power_off(phy); + if (ret) + return ret; +- return qcom_qmp_phy_exit(phy); ++ return qcom_qmp_phy_usb_exit(phy); + } + +-static int qcom_qmp_phy_set_mode(struct phy *phy, ++static int qcom_qmp_phy_usb_set_mode(struct phy *phy, + enum phy_mode mode, int submode) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); +@@ -2532,7 +2532,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, + return 0; + } + +-static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) ++static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy) + { + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; +@@ -2561,7 +2561,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) + qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); + } + +-static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) ++static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy) + { + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; +@@ -2579,7 +2579,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) + qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); + } + +-static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) ++static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; +@@ -2596,7 +2596,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) + return 0; + } + +- qcom_qmp_phy_enable_autonomous_mode(qphy); ++ qcom_qmp_phy_usb_enable_autonomous_mode(qphy); + + clk_disable_unprepare(qphy->pipe_clk); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); +@@ -2604,7 +2604,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) + return 0; + } + +-static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) ++static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_phy *qphy = qmp->phys[0]; +@@ -2633,12 +2633,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) + return ret; + } + +- qcom_qmp_phy_disable_autonomous_mode(qphy); ++ qcom_qmp_phy_usb_disable_autonomous_mode(qphy); + + return 0; + } + +-static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_vregs; +@@ -2654,7 +2654,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg * + return devm_regulator_bulk_get(dev, num, qmp->vregs); + } + +-static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int i; +@@ -2679,7 +2679,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg + return 0; + } + +-static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) ++static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); + int num = cfg->num_clks; +@@ -2947,28 +2947,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + } + +-static const struct phy_ops qcom_qmp_phy_gen_ops = { +- .init = qcom_qmp_phy_enable, +- .exit = qcom_qmp_phy_disable, +- .set_mode = qcom_qmp_phy_set_mode, ++static const struct phy_ops qcom_qmp_phy_usb_gen_ops = { ++ .init = qcom_qmp_phy_usb_enable, ++ .exit = qcom_qmp_phy_usb_disable, ++ .set_mode = qcom_qmp_phy_usb_set_mode, + .owner = THIS_MODULE, + }; + +-static const struct phy_ops qcom_qmp_phy_dp_ops = { +- .init = qcom_qmp_phy_init, ++static const struct phy_ops qcom_qmp_phy_usb_dp_ops = { ++ .init = qcom_qmp_phy_usb_init, + .configure = qcom_qmp_dp_phy_configure, +- .power_on = qcom_qmp_phy_power_on, ++ .power_on = qcom_qmp_phy_usb_power_on, + .calibrate = qcom_qmp_dp_phy_calibrate, +- .power_off = qcom_qmp_phy_power_off, +- .exit = qcom_qmp_phy_exit, +- .set_mode = qcom_qmp_phy_set_mode, ++ .power_off = qcom_qmp_phy_usb_power_off, ++ .exit = qcom_qmp_phy_usb_exit, ++ .set_mode = qcom_qmp_phy_usb_set_mode, + .owner = THIS_MODULE, + }; + + static const struct phy_ops qcom_qmp_pcie_ufs_ops = { +- .power_on = qcom_qmp_phy_enable, +- .power_off = qcom_qmp_phy_disable, +- .set_mode = qcom_qmp_phy_set_mode, ++ .power_on = qcom_qmp_phy_usb_enable, ++ .power_off = qcom_qmp_phy_usb_disable, ++ .set_mode = qcom_qmp_phy_usb_set_mode, + .owner = THIS_MODULE, + }; + +@@ -2978,7 +2978,7 @@ static void qcom_qmp_reset_control_put(void *data) + } + + static +-int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, ++int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) + { + struct qcom_qmp *qmp = dev_get_drvdata(dev); +@@ -3080,9 +3080,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) + ops = &qcom_qmp_pcie_ufs_ops; + else if (cfg->type == PHY_TYPE_DP) +- ops = &qcom_qmp_phy_dp_ops; ++ ops = &qcom_qmp_phy_usb_dp_ops; + else +- ops = &qcom_qmp_phy_gen_ops; ++ ops = &qcom_qmp_phy_usb_gen_ops; + + generic_phy = devm_phy_create(dev, np, ops); + if (IS_ERR(generic_phy)) { +@@ -3100,7 +3100,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, + return 0; + } + +-static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ++static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = { + { + .compatible = "qcom,ipq8074-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, +@@ -3158,14 +3158,14 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + }, + { }, + }; +-MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); ++MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table); + +-static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { +- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, +- qcom_qmp_phy_runtime_resume, NULL) ++static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = { ++ SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend, ++ qcom_qmp_phy_usb_runtime_resume, NULL) + }; + +-static int qcom_qmp_phy_probe(struct platform_device *pdev) ++static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) + { + struct qcom_qmp *qmp; + struct device *dev = &pdev->dev; +@@ -3219,15 +3219,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + + mutex_init(&qmp->phy_mutex); + +- ret = qcom_qmp_phy_clk_init(dev, cfg); ++ ret = qcom_qmp_phy_usb_clk_init(dev, cfg); + if (ret) + return ret; + +- ret = qcom_qmp_phy_reset_init(dev, cfg); ++ ret = qcom_qmp_phy_usb_reset_init(dev, cfg); + if (ret) + return ret; + +- ret = qcom_qmp_phy_vreg_init(dev, cfg); ++ ret = qcom_qmp_phy_usb_vreg_init(dev, cfg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get regulator supplies: %d\n", +@@ -3265,7 +3265,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + } + + /* Create per-lane phy */ +- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); ++ ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg); + if (ret) { + dev_err(dev, "failed to create lane%d phy, %d\n", + id, ret); +@@ -3305,16 +3305,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + return ret; + } + +-static struct platform_driver qcom_qmp_phy_driver = { +- .probe = qcom_qmp_phy_probe, ++static struct platform_driver qcom_qmp_phy_usb_driver = { ++ .probe = qcom_qmp_phy_usb_probe, + .driver = { + .name = "qcom-qmp-usb-phy", +- .pm = &qcom_qmp_phy_pm_ops, +- .of_match_table = qcom_qmp_phy_of_match_table, ++ .pm = &qcom_qmp_phy_usb_pm_ops, ++ .of_match_table = qcom_qmp_phy_usb_of_match_table, + }, + }; + +-module_platform_driver(qcom_qmp_phy_driver); ++module_platform_driver(qcom_qmp_phy_usb_driver); + + MODULE_AUTHOR("Vivek Gautam "); + MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-clean-up-pipe-clock-handling.patch b/queue-5.10/phy-qcom-qmp-usb-clean-up-pipe-clock-handling.patch new file mode 100644 index 00000000000..ef0c2431aa3 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-clean-up-pipe-clock-handling.patch @@ -0,0 +1,55 @@ +From f0c162b04114d3867eff506ace5c3c27feb1ac9e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 Jun 2022 13:33:14 +0200 +Subject: phy: qcom-qmp-usb: clean up pipe clock handling + +From: Johan Hovold + +[ Upstream commit 5d5b7d509ff85675779caeafcffa8086d7094339 ] + +Clean up the pipe clock handling by using dev_err_probe() to handle +probe deferral and dropping the obsolete comment that claimed that the +pipe clock was optional for some other PHY types. + +Signed-off-by: Johan Hovold +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220623113314.29761-4-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 15 ++------------- + 1 file changed, 2 insertions(+), 13 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index 9e752fce638d..687f1a534837 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -2566,22 +2566,11 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + +- /* +- * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 +- * based phys, so they essentially have pipe clock. So, +- * we return error in case phy is USB3 or PIPE type. +- * Otherwise, we initialize pipe clock to NULL for +- * all phys that don't need this. +- */ + snprintf(prop_name, sizeof(prop_name), "pipe%d", id); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + if (IS_ERR(qphy->pipe_clk)) { +- ret = PTR_ERR(qphy->pipe_clk); +- if (ret != -EPROBE_DEFER) +- dev_err(dev, +- "failed to get lane%d pipe_clk, %d\n", +- id, ret); +- return ret; ++ return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), ++ "failed to get lane%d pipe clock\n", id); + } + + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-cleanup-the-driver.patch b/queue-5.10/phy-qcom-qmp-usb-cleanup-the-driver.patch new file mode 100644 index 00000000000..5e15eb0fd5e --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-cleanup-the-driver.patch @@ -0,0 +1,433 @@ +From 6b00b876de5cecb111ab9cc5b29c888ffada6368 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:56 +0300 +Subject: phy: qcom-qmp-usb: cleanup the driver + +From: Dmitry Baryshkov + +[ Upstream commit faf83af5d59498509eb84015453073fd5e85231e ] + +Remove the conditionals and options that are not used by any of USB PHY +devices. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-24-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 214 ++---------------------- + 1 file changed, 11 insertions(+), 203 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index 55785dcd47e0..9e752fce638d 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -1359,40 +1359,12 @@ struct qmp_phy_cfg { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; +- const struct qmp_phy_init_tbl *serdes_tbl_sec; +- int serdes_tbl_num_sec; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; +- const struct qmp_phy_init_tbl *tx_tbl_sec; +- int tx_tbl_num_sec; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; +- const struct qmp_phy_init_tbl *rx_tbl_sec; +- int rx_tbl_num_sec; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; +- const struct qmp_phy_init_tbl *pcs_tbl_sec; +- int pcs_tbl_num_sec; +- const struct qmp_phy_init_tbl *pcs_misc_tbl; +- int pcs_misc_tbl_num; +- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; +- int pcs_misc_tbl_num_sec; +- +- /* Init sequence for DP PHY block link rates */ +- const struct qmp_phy_init_tbl *serdes_tbl_rbr; +- int serdes_tbl_rbr_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr; +- int serdes_tbl_hbr_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr2; +- int serdes_tbl_hbr2_num; +- const struct qmp_phy_init_tbl *serdes_tbl_hbr3; +- int serdes_tbl_hbr3_num; +- +- /* DP PHY callbacks */ +- int (*configure_dp_phy)(struct qmp_phy *qphy); +- void (*configure_dp_tx)(struct qmp_phy *qphy); +- int (*calibrate_dp_phy)(struct qmp_phy *qphy); +- void (*dp_aux_init)(struct qmp_phy *qphy); + + /* clock ids to be requested */ + const char * const *clk_list; +@@ -1409,14 +1381,9 @@ struct qmp_phy_cfg { + + unsigned int start_ctrl; + unsigned int pwrdn_ctrl; +- unsigned int mask_com_pcs_ready; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + +- /* true, if PHY has a separate PHY_COM control block */ +- bool has_phy_com_ctrl; +- /* true, if PHY has a reset for individual lanes */ +- bool has_lane_rst; + /* true, if PHY needs delay after POWER_DOWN */ + bool has_pwrdn_delay; + /* power_down delay in usec */ +@@ -1427,14 +1394,6 @@ struct qmp_phy_cfg { + bool has_phy_dp_com_ctrl; + /* true, if PHY has secondary tx/rx lanes to be configured */ + bool is_dual_lane_phy; +- +- /* true, if PCS block has no separate SW_RESET register */ +- bool no_pcs_sw_reset; +-}; +- +-struct qmp_phy_combo_cfg { +- const struct qmp_phy_cfg *usb_cfg; +- const struct qmp_phy_cfg *dp_cfg; + }; + + /** +@@ -1452,11 +1411,7 @@ struct qmp_phy_combo_cfg { + * @pipe_clk: pipe clock + * @index: lane index + * @qmp: QMP phy to which this lane belongs +- * @lane_rst: lane's reset controller + * @mode: current PHY mode +- * @dp_aux_cfg: Display port aux config +- * @dp_opts: Display port optional config +- * @dp_clks: Display port clocks + */ + struct qmp_phy { + struct phy *phy; +@@ -1471,17 +1426,7 @@ struct qmp_phy { + struct clk *pipe_clk; + unsigned int index; + struct qcom_qmp *qmp; +- struct reset_control *lane_rst; + enum phy_mode mode; +- unsigned int dp_aux_cfg; +- struct phy_configure_opts_dp dp_opts; +- struct qmp_phy_dp_clks *dp_clks; +-}; +- +-struct qmp_phy_dp_clks { +- struct qmp_phy *qphy; +- struct clk_hw dp_link_hw; +- struct clk_hw dp_pixel_hw; + }; + + /** +@@ -1497,7 +1442,6 @@ struct qmp_phy_dp_clks { + * @phys: array of per-lane phy descriptors + * @phy_mutex: mutex lock for PHY common block initialization + * @init_count: phy common block initialization count +- * @ufs_reset: optional UFS PHY reset handle + */ + struct qcom_qmp { + struct device *dev; +@@ -1511,8 +1455,6 @@ struct qcom_qmp { + + struct mutex phy_mutex; + int init_count; +- +- struct reset_control *ufs_reset; + }; + + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +@@ -2056,37 +1998,12 @@ static void qcom_qmp_phy_usb_configure(void __iomem *base, + + static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) + { +- struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; +- int ret; + + qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); +- if (cfg->serdes_tbl_sec) +- qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, +- cfg->serdes_tbl_num_sec); +- +- if (cfg->has_phy_com_ctrl) { +- void __iomem *status; +- unsigned int mask, val; +- +- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); +- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], +- SERDES_START | PCS_START); +- +- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; +- mask = cfg->mask_com_pcs_ready; +- +- ret = readl_poll_timeout(status, val, (val & mask), 10, +- PHY_INIT_COMPLETE_TIMEOUT); +- if (ret) { +- dev_err(qmp->dev, +- "phy common block init timed-out\n"); +- return ret; +- } +- } + + return 0; + } +@@ -2095,7 +2012,6 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +- void __iomem *serdes = qphy->serdes; + void __iomem *pcs = qphy->pcs; + void __iomem *dp_com = qmp->dp_com; + int ret, i; +@@ -2158,18 +2074,13 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) + qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); + } + +- if (cfg->has_phy_com_ctrl) { +- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], +- SW_PWRDN); +- } else { +- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) +- qphy_setbits(pcs, +- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], +- cfg->pwrdn_ctrl); +- else +- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, +- cfg->pwrdn_ctrl); +- } ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) ++ qphy_setbits(pcs, ++ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ else ++ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); + + mutex_unlock(&qmp->phy_mutex); + +@@ -2190,7 +2101,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; +- void __iomem *serdes = qphy->serdes; + int i = cfg->num_resets; + + mutex_lock(&qmp->phy_mutex); +@@ -2199,16 +2109,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) + return 0; + } + +- reset_control_assert(qmp->ufs_reset); +- if (cfg->has_phy_com_ctrl) { +- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], +- SERDES_START | PCS_START); +- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], +- SW_RESET); +- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], +- SW_PWRDN); +- } +- + while (--i >= 0) + reset_control_assert(qmp->resets[i]); + +@@ -2225,37 +2125,9 @@ static int qcom_qmp_phy_usb_init(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; +- const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret; + dev_vdbg(qmp->dev, "Initializing QMP phy\n"); + +- if (cfg->no_pcs_sw_reset) { +- /* +- * Get UFS reset, which is delayed until now to avoid a +- * circular dependency where UFS needs its PHY, but the PHY +- * needs this UFS reset. +- */ +- if (!qmp->ufs_reset) { +- qmp->ufs_reset = +- devm_reset_control_get_exclusive(qmp->dev, +- "ufsphy"); +- +- if (IS_ERR(qmp->ufs_reset)) { +- ret = PTR_ERR(qmp->ufs_reset); +- dev_err(qmp->dev, +- "failed to get UFS reset: %d\n", +- ret); +- +- qmp->ufs_reset = NULL; +- return ret; +- } +- } +- +- ret = reset_control_assert(qmp->ufs_reset); +- if (ret) +- return ret; +- } +- + ret = qcom_qmp_phy_usb_com_init(qphy); + if (ret) + return ret; +@@ -2271,82 +2143,45 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + void __iomem *pcs = qphy->pcs; +- void __iomem *pcs_misc = qphy->pcs_misc; + void __iomem *status; + unsigned int mask, val, ready; + int ret; + + qcom_qmp_phy_usb_serdes_init(qphy); + +- if (cfg->has_lane_rst) { +- ret = reset_control_deassert(qphy->lane_rst); +- if (ret) { +- dev_err(qmp->dev, "lane%d reset deassert failed\n", +- qphy->index); +- return ret; +- } +- } +- + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); +- goto err_reset_lane; ++ return ret; + } + + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 1); +- if (cfg->tx_tbl_sec) +- qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, +- cfg->tx_tbl_num_sec, 1); + + /* Configuration for other LANE for USB-DP combo PHY */ + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, + cfg->tx_tbl, cfg->tx_tbl_num, 2); +- if (cfg->tx_tbl_sec) +- qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, +- cfg->tx_tbl_sec, +- cfg->tx_tbl_num_sec, 2); + } + + qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); +- if (cfg->rx_tbl_sec) +- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, +- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); + + if (cfg->is_dual_lane_phy) { + qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 2); +- if (cfg->rx_tbl_sec) +- qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, +- cfg->rx_tbl_sec, +- cfg->rx_tbl_num_sec, 2); + } + + /* Configure link rate, swing, etc. */ + qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); +- if (cfg->pcs_tbl_sec) +- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, +- cfg->pcs_tbl_num_sec); +- +- ret = reset_control_deassert(qmp->ufs_reset); +- if (ret) +- goto err_disable_pipe_clk; +- +- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, +- cfg->pcs_misc_tbl_num); +- if (cfg->pcs_misc_tbl_sec) +- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, +- cfg->pcs_misc_tbl_num_sec); + + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + + /* Pull PHY out of reset state */ +- if (!cfg->no_pcs_sw_reset) +- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + +@@ -2365,9 +2200,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) + + err_disable_pipe_clk: + clk_disable_unprepare(qphy->pipe_clk); +-err_reset_lane: +- if (cfg->has_lane_rst) +- reset_control_assert(qphy->lane_rst); + + return ret; + } +@@ -2380,8 +2212,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy) + clk_disable_unprepare(qphy->pipe_clk); + + /* PHY reset */ +- if (!cfg->no_pcs_sw_reset) +- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); +@@ -2401,10 +2232,6 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy) + static int qcom_qmp_phy_usb_exit(struct phy *phy) + { + struct qmp_phy *qphy = phy_get_drvdata(phy); +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- +- if (cfg->has_lane_rst) +- reset_control_assert(qphy->lane_rst); + + qcom_qmp_phy_usb_com_exit(qphy); + +@@ -2676,11 +2503,6 @@ static const struct phy_ops qcom_qmp_phy_usb_ops = { + .owner = THIS_MODULE, + }; + +-static void qcom_qmp_reset_control_put(void *data) +-{ +- reset_control_put(data); +-} +- + static + int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +@@ -2762,20 +2584,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + return ret; + } + +- /* Get lane reset, if any */ +- if (cfg->has_lane_rst) { +- snprintf(prop_name, sizeof(prop_name), "lane%d", id); +- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); +- if (IS_ERR(qphy->lane_rst)) { +- dev_err(dev, "failed to get lane%d reset\n", id); +- return PTR_ERR(qphy->lane_rst); +- } +- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, +- qphy->lane_rst); +- if (ret) +- return ret; +- } +- + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-disable-runtime-pm-on-unbind.patch b/queue-5.10/phy-qcom-qmp-usb-disable-runtime-pm-on-unbind.patch new file mode 100644 index 00000000000..1d9c55c030d --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-disable-runtime-pm-on-unbind.patch @@ -0,0 +1,53 @@ +From e054c8a8f4fa42be0dc61fc951088435fe56b64a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 13:07:21 +0200 +Subject: phy: qcom-qmp-usb: disable runtime PM on unbind + +From: Johan Hovold + +[ Upstream commit e57655e66806750785f9121c98a962404d02395b ] + +Make sure to disable runtime PM also on driver unbind. + +Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM"). +Signed-off-by: Johan Hovold +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220907110728.19092-10-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index c7309e981bfb..dcf8a8764e17 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -6273,7 +6273,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + return -ENOMEM; + + pm_runtime_set_active(dev); +- pm_runtime_enable(dev); ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ return ret; + /* + * Prevent runtime pm from being ON by default. Users can enable + * it using power/control in sysfs. +@@ -6323,13 +6325,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (!IS_ERR(phy_provider)) + dev_info(dev, "Registered Qcom-QMP phy\n"); +- else +- pm_runtime_disable(dev); + + return PTR_ERR_OR_ZERO(phy_provider); + + err_node_put: +- pm_runtime_disable(dev); + of_node_put(child); + return ret; + } +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-drop-all-non-usb-compatibles-suppor.patch b/queue-5.10/phy-qcom-qmp-usb-drop-all-non-usb-compatibles-suppor.patch new file mode 100644 index 00000000000..d4c1b79baf6 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-drop-all-non-usb-compatibles-suppor.patch @@ -0,0 +1,3417 @@ +From 052d5010c0d652291b70fdaa48dc81ca5203317d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:38 +0300 +Subject: phy: qcom-qmp-usb: drop all non-USB compatibles support + +From: Dmitry Baryshkov + +[ Upstream commit 8c924330ebe3e5c6f41bad0e5118875848843864 ] + +Drop support for all non-USB compatibles from the new qmp-usb driver. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-6-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3108 +---------------------- + 1 file changed, 40 insertions(+), 3068 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index dcf8a8764e17..e147182afea7 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -141,34 +141,6 @@ enum qphy_reg_layout { + QPHY_LAYOUT_SIZE + }; + +-static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = 0x00, +- [QPHY_PCS_READY_STATUS] = 0x168, +-}; +- +-static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +-}; +- +-static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_COM_SW_RESET] = 0x400, +- [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, +- [QPHY_COM_START_CONTROL] = 0x408, +- [QPHY_COM_PCS_READY_STATUS] = 0x448, +- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, +- [QPHY_FLL_CNTRL1] = 0xc4, +- [QPHY_FLL_CNTRL2] = 0xc8, +- [QPHY_FLL_CNT_VAL_L] = 0xcc, +- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, +- [QPHY_FLL_MAN_CODE] = 0xd4, +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x174, +-}; +- + static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_FLL_CNTRL1] = 0xc0, + [QPHY_FLL_CNTRL2] = 0xc4, +@@ -192,18 +164,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, + }; + +-static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x174, +-}; +- +-static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x08, +- [QPHY_PCS_STATUS] = 0x2ac, +-}; +- + static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = 0x00, + [QPHY_START_CTRL] = 0x44, +@@ -241,29 +201,6 @@ static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, + }; + +-static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = 0x00, +- [QPHY_PCS_READY_STATUS] = 0x160, +-}; +- +-static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = 0x00, +- [QPHY_PCS_READY_STATUS] = 0x168, +-}; +- +-static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_SW_RESET] = 0x00, +- [QPHY_START_CTRL] = 0x44, +- [QPHY_PCS_STATUS] = 0x14, +- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, +-}; +- +-static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, +- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, +- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, +-}; +- + static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +@@ -339,235 +276,6 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), + }; + +-static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), +- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), +- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), +- +- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), +- +- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), +- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), +- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), +- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), +-}; +- +-static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), +-}; +- + static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +@@ -639,414 +347,6 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), + }; + +-static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), +- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), +- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), +-}; +- +-static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), +- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), +- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), +- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), +- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), +- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), +- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), +- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), +- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), +- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), +- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), +- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), +-}; +- +-static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), +- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), +- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), +- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), +- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), +- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), +- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), +- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), +- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), +- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), +- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), +- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), +- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), +- +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { +-}; +- +-static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), +- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), +-}; +- + static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), +@@ -1094,88 +394,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), + }; + +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +-}; +- + static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +@@ -1346,175 +564,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), + }; + +-static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), +- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), +- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), +-}; +- +-static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15), +- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d), +- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), +- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12), +- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), +-}; +- +-static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a), +- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), +-}; +- + static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), +@@ -1624,93 +673,6 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + }; + +-static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), +- +-}; +- +-static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +-}; +- + static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +@@ -2023,374 +985,44 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), +-}; +- +-static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), +-}; +- +-static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + }; + +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), +-}; +- +-static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), +- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + }; + + static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { +@@ -2440,101 +1072,6 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), + }; + +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), +-}; +- +-static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), +-}; +- + static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), +@@ -2579,106 +1116,6 @@ static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), + }; + +-static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +- +- /* Rate B */ +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +-}; +- + static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), +@@ -2910,215 +1347,6 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), + }; + +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), +- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), +- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), +- +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), +- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), +-}; +- +-/* Register names should be validated, they might be different for this PHY */ +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), +- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), +-}; +- +-static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), +- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), +-}; +- + struct qmp_phy; + + /* struct qmp_phy_cfg - per-PHY initialization config */ +@@ -3287,16 +1515,6 @@ struct qcom_qmp { + struct reset_control *ufs_reset; + }; + +-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); +-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); +-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); +-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); +- +-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); +-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); +-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); +-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); +- + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) + { + u32 reg; +@@ -3326,18 +1544,10 @@ static const char * const msm8996_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", + }; + +-static const char * const msm8996_ufs_phy_clk_l[] = { +- "ref", +-}; +- + static const char * const qmp_v3_phy_clk_l[] = { + "aux", "cfg_ahb", "ref", "com_aux", + }; + +-static const char * const sdm845_pciephy_clk_l[] = { +- "aux", "cfg_ahb", "ref", "refgen", +-}; +- + static const char * const qmp_v4_phy_clk_l[] = { + "aux", "ref_clk_src", "ref", "com_aux", + }; +@@ -3347,14 +1557,6 @@ static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { + "aux", "ref_clk_src", "com_aux" + }; + +-static const char * const sm8450_ufs_phy_clk_l[] = { +- "qref", "ref", "ref_aux", +-}; +- +-static const char * const sdm845_ufs_phy_clk_l[] = { +- "ref", "ref_aux", +-}; +- + /* usb3 phy on sdx55 doesn't have com_aux clock */ + static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { + "aux", "cfg_ahb", "ref" +@@ -3365,10 +1567,6 @@ static const char * const qcm2290_usb3phy_clk_l[] = { + }; + + /* list of resets */ +-static const char * const msm8996_pciephy_reset_l[] = { +- "phy", "common", "cfg", +-}; +- + static const char * const msm8996_usb3phy_reset_l[] = { + "phy", "common", + }; +@@ -3381,10 +1579,6 @@ static const char * const qcm2290_usb3phy_reset_l[] = { + "phy_phy", "phy", + }; + +-static const char * const sdm845_pciephy_reset_l[] = { +- "phy", +-}; +- + /* list of regulators */ + static const char * const qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", +@@ -3415,64 +1609,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { + .phy_status = PHYSTATUS, + }; + +-static const struct qmp_phy_cfg msm8996_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 3, +- +- .serdes_tbl = msm8996_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), +- .tx_tbl = msm8996_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), +- .rx_tbl = msm8996_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), +- .pcs_tbl = msm8996_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = msm8996_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = pciephy_regs_layout, +- +- .start_ctrl = PCS_START | PLL_READY_GATE_EN, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .mask_com_pcs_ready = PCS_READY, +- .phy_status = PHYSTATUS, +- +- .has_phy_com_ctrl = true, +- .has_lane_rst = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, +- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, +-}; +- +-static const struct qmp_phy_cfg msm8996_ufs_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 1, +- +- .serdes_tbl = msm8996_ufs_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), +- .tx_tbl = msm8996_ufs_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), +- .rx_tbl = msm8996_ufs_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), +- +- .clk_list = msm8996_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), +- +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- +- .regs = msm8996_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .no_pcs_sw_reset = true, +-}; +- + static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -3498,214 +1634,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { + .phy_status = PHYSTATUS, + }; + +-static const char * const ipq8074_pciephy_clk_l[] = { +- "aux", "cfg_ahb", +-}; +-/* list of resets */ +-static const char * const ipq8074_pciephy_reset_l[] = { +- "phy", "common", +-}; +- +-static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = ipq8074_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), +- .tx_tbl = ipq8074_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), +- .rx_tbl = ipq8074_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), +- .pcs_tbl = ipq8074_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), +- .clk_list = ipq8074_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), +- .reset_list = ipq8074_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), +- .vreg_list = NULL, +- .num_vregs = 0, +- .regs = pciephy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_phy_com_ctrl = false, +- .has_lane_rst = false, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = ipq6018_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), +- .tx_tbl = ipq6018_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), +- .rx_tbl = ipq6018_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), +- .pcs_tbl = ipq6018_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), +- .clk_list = ipq8074_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), +- .reset_list = ipq8074_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), +- .vreg_list = NULL, +- .num_vregs = 0, +- .regs = ipq_pciephy_gen3_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- +- .has_phy_com_ctrl = false, +- .has_lane_rst = false, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), +- .tx_tbl = sdm845_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), +- .rx_tbl = sdm845_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), +- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), +- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sdm845_qmp_pciephy_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), +- .tx_tbl = sdm845_qhp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), +- .rx_tbl = sdm845_qhp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), +- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sdm845_qhp_pciephy_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), +- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, +- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), +- .tx_tbl = sm8250_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), +- .rx_tbl = sm8250_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), +- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, +- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), +- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), +- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, +- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), +- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 2, +- +- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), +- .tx_tbl = sm8250_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), +- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, +- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), +- .rx_tbl = sm8250_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), +- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, +- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), +- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), +- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, +- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), +- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- + static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -3770,46 +1698,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { + .is_dual_lane_phy = true, + }; + +-static const struct qmp_phy_cfg sc7180_dpphy_cfg = { +- .type = PHY_TYPE_DP, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v3_dp_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), +- .tx_tbl = qmp_v3_dp_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), +- +- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, +- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), +- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, +- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), +- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, +- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), +- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, +- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), +- +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = sc7180_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +- +- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, +- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, +- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, +- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, +-}; +- +-static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { +- .usb_cfg = &sc7180_usb3phy_cfg, +- .dp_cfg = &sc7180_dpphy_cfg, +-}; +- + static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -3839,82 +1727,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + +-static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sdm845_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), +- .tx_tbl = sdm845_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), +- .rx_tbl = sdm845_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), +- .pcs_tbl = sdm845_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sdm845_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +- .no_pcs_sw_reset = true, +-}; +- +-static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 1, +- +- .serdes_tbl = sm6115_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), +- .tx_tbl = sm6115_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), +- .rx_tbl = sm6115_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), +- .pcs_tbl = sm6115_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm6115_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- +- .is_dual_lane_phy = false, +- .no_pcs_sw_reset = true, +-}; +- +-static const struct qmp_phy_cfg msm8998_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = msm8998_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), +- .tx_tbl = msm8998_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), +- .rx_tbl = msm8998_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), +- .pcs_tbl = msm8998_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), +- .clk_list = msm8996_phy_clk_l, +- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), +- .reset_list = ipq8074_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = pciephy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +-}; +- + static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -3933,38 +1745,13 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sm8150_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), +- .tx_tbl = sm8150_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), +- .rx_tbl = sm8150_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), +- .pcs_tbl = sm8150_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8150_ufsphy_regs_layout, ++ .regs = qmp_v3_usb3phy_regs_layout, + +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, ++ .start_ctrl = SERDES_START | PCS_START, ++ .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + +- .is_dual_lane_phy = true, ++ .is_dual_lane_phy = true, + }; + + static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { +@@ -4000,76 +1787,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { + .is_dual_lane_phy = true, + }; + +-static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), +- .tx_tbl = sc8180x_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), +- .rx_tbl = sc8180x_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), +- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), +- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { +- .type = PHY_TYPE_DP, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v4_dp_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), +- .tx_tbl = qmp_v4_dp_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), +- +- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, +- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), +- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, +- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), +- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, +- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), +- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, +- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), +- +- .clk_list = qmp_v3_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), +- .reset_list = sc7180_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v3_usb3phy_regs_layout, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +- +- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, +- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, +- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, +- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +-}; +- +-static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { +- .usb_cfg = &sm8150_usb3phy_cfg, +- .dp_cfg = &sc8180x_dpphy_cfg, +-}; +- + static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -4160,46 +1877,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + +-static const struct qmp_phy_cfg sm8250_dpphy_cfg = { +- .type = PHY_TYPE_DP, +- .nlanes = 1, +- +- .serdes_tbl = qmp_v4_dp_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), +- .tx_tbl = qmp_v4_dp_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), +- +- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, +- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), +- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, +- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), +- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, +- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), +- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, +- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), +- +- .clk_list = qmp_v4_phy_clk_l, +- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), +- .reset_list = msm8996_usb3phy_reset_l, +- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = qmp_v4_usb3phy_regs_layout, +- +- .has_phy_dp_com_ctrl = true, +- .is_dual_lane_phy = true, +- +- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, +- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, +- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, +- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, +-}; +- +-static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { +- .usb_cfg = &sm8250_usb3phy_cfg, +- .dp_cfg = &sm8250_dpphy_cfg, +-}; +- + static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -4229,38 +1906,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + +-static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 2, +- +- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), +- .tx_tbl = sdx55_qmp_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), +- .rx_tbl = sdx55_qmp_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), +- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), +- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = PCS_START | SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS_4_20, +- +- .is_dual_lane_phy = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- + static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -4290,31 +1935,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + +-static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sm8350_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), +- .tx_tbl = sm8350_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), +- .rx_tbl = sm8350_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), +- .pcs_tbl = sm8350_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), +- .clk_list = sdm845_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8150_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +-}; +- + static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -4376,94 +1996,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { + .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, + }; + +-static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { +- .type = PHY_TYPE_UFS, +- .nlanes = 2, +- +- .serdes_tbl = sm8350_ufsphy_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), +- .tx_tbl = sm8350_ufsphy_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), +- .rx_tbl = sm8350_ufsphy_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), +- .pcs_tbl = sm8350_ufsphy_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), +- .clk_list = sm8450_ufs_phy_clk_l, +- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8150_ufsphy_regs_layout, +- +- .start_ctrl = SERDES_START, +- .pwrdn_ctrl = SW_PWRDN, +- .phy_status = PHYSTATUS, +- +- .is_dual_lane_phy = true, +-}; +- +-static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 1, +- +- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), +- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), +- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), +- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS, +- +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- +-static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { +- .type = PHY_TYPE_PCIE, +- .nlanes = 2, +- +- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, +- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), +- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, +- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), +- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, +- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), +- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, +- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), +- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, +- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), +- .clk_list = sdm845_pciephy_clk_l, +- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), +- .reset_list = sdm845_pciephy_reset_l, +- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), +- .vreg_list = qmp_phy_vreg_l, +- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), +- .regs = sm8250_pcie_regs_layout, +- +- .start_ctrl = SERDES_START | PCS_START, +- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, +- .phy_status = PHYSTATUS_4_20, +- +- .is_dual_lane_phy = true, +- .has_pwrdn_delay = true, +- .pwrdn_delay_min = 995, /* us */ +- .pwrdn_delay_max = 1005, /* us */ +-}; +- + static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { + .type = PHY_TYPE_USB3, + .nlanes = 1, +@@ -4589,457 +2121,6 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) + return 0; + } + +-static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) +-{ +- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, +- qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- /* Turn on BIAS current for PHY/PLL */ +- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | +- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, +- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); +- +- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_LANE_0_1_PWRDN | +- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | +- DP_PHY_PD_CTL_DP_CLAMP_EN, +- qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- writel(QSERDES_V3_COM_BIAS_EN | +- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | +- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | +- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, +- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); +- +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); +- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); +- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); +- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); +- qphy->dp_aux_cfg = 0; +- +- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | +- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | +- PHY_AUX_REQ_ERR_MASK, +- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +-} +- +-static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { +- { 0x00, 0x0c, 0x15, 0x1a }, +- { 0x02, 0x0e, 0x16, 0xff }, +- { 0x02, 0x11, 0xff, 0xff }, +- { 0x04, 0xff, 0xff, 0xff } +-}; +- +-static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { +- { 0x02, 0x12, 0x16, 0x1a }, +- { 0x09, 0x19, 0x1f, 0xff }, +- { 0x10, 0x1f, 0xff, 0xff }, +- { 0x1f, 0xff, 0xff, 0xff } +-}; +- +-static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { +- { 0x00, 0x0c, 0x14, 0x19 }, +- { 0x00, 0x0b, 0x12, 0xff }, +- { 0x00, 0x0b, 0xff, 0xff }, +- { 0x04, 0xff, 0xff, 0xff } +-}; +- +-static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { +- { 0x08, 0x0f, 0x16, 0x1f }, +- { 0x11, 0x1e, 0x1f, 0xff }, +- { 0x19, 0x1f, 0xff, 0xff }, +- { 0x1f, 0xff, 0xff, 0xff } +-}; +- +-static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, +- unsigned int drv_lvl_reg, unsigned int emp_post_reg) +-{ +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- unsigned int v_level = 0, p_level = 0; +- u8 voltage_swing_cfg, pre_emphasis_cfg; +- int i; +- +- for (i = 0; i < dp_opts->lanes; i++) { +- v_level = max(v_level, dp_opts->voltage[i]); +- p_level = max(p_level, dp_opts->pre[i]); +- } +- +- if (dp_opts->link_rate <= 2700) { +- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; +- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; +- } else { +- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; +- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; +- } +- +- /* TODO: Move check to config check */ +- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) +- return -EINVAL; +- +- /* Enable MUX to use Cursor values from these registers */ +- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; +- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; +- +- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); +- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); +- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); +- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); +- +- return 0; +-} +- +-static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) +-{ +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- u32 bias_en, drvr_en; +- +- if (qcom_qmp_phy_configure_dp_swing(qphy, +- QSERDES_V3_TX_TX_DRV_LVL, +- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) +- return; +- +- if (dp_opts->lanes == 1) { +- bias_en = 0x3e; +- drvr_en = 0x13; +- } else { +- bias_en = 0x3f; +- drvr_en = 0x10; +- } +- +- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); +- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); +- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); +-} +- +-static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy) +-{ +- u32 val; +- bool reverse = false; +- +- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; +- +- /* +- * TODO: Assume orientation is CC1 for now and two lanes, need to +- * use type-c connector to understand orientation and lanes. +- * +- * Otherwise val changes to be like below if this code understood +- * the orientation of the type-c cable. +- * +- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) +- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; +- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) +- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; +- * if (orientation == ORIENTATION_CC2) +- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); +- */ +- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; +- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); +- +- return reverse; +-} +- +-static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) +-{ +- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- u32 phy_vco_div, status; +- unsigned long pixel_freq; +- +- qcom_qmp_phy_configure_dp_mode(qphy); +- +- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); +- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); +- +- switch (dp_opts->link_rate) { +- case 1620: +- phy_vco_div = 0x1; +- pixel_freq = 1620000000UL / 2; +- break; +- case 2700: +- phy_vco_div = 0x1; +- pixel_freq = 2700000000UL / 2; +- break; +- case 5400: +- phy_vco_div = 0x2; +- pixel_freq = 5400000000UL / 4; +- break; +- case 8100: +- phy_vco_div = 0x0; +- pixel_freq = 8100000000UL / 6; +- break; +- default: +- /* Other link rates aren't supported */ +- return -EINVAL; +- } +- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); +- +- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); +- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); +- +- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); +- udelay(2000); +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000); +-} +- +-/* +- * We need to calibrate the aux setting here as many times +- * as the caller tries +- */ +-static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) +-{ +- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; +- u8 val; +- +- qphy->dp_aux_cfg++; +- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); +- val = cfg1_settings[qphy->dp_aux_cfg]; +- +- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- +- return 0; +-} +- +-static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) +-{ +- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | +- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, +- qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- +- /* Turn on BIAS current for PHY/PLL */ +- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); +- +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); +- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); +- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); +- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); +- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); +- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); +- qphy->dp_aux_cfg = 0; +- +- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | +- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | +- PHY_AUX_REQ_ERR_MASK, +- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); +-} +- +-static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) +-{ +- /* Program default values before writing proper values */ +- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); +- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); +- +- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- +- qcom_qmp_phy_configure_dp_swing(qphy, +- QSERDES_V4_TX_TX_DRV_LVL, +- QSERDES_V4_TX_TX_EMP_POST1_LVL); +-} +- +-static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) +-{ +- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; +- u32 phy_vco_div, status; +- unsigned long pixel_freq; +- u32 bias0_en, drvr0_en, bias1_en, drvr1_en; +- bool reverse; +- +- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); +- +- reverse = qcom_qmp_phy_configure_dp_mode(qphy); +- +- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); +- +- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); +- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); +- +- switch (dp_opts->link_rate) { +- case 1620: +- phy_vco_div = 0x1; +- pixel_freq = 1620000000UL / 2; +- break; +- case 2700: +- phy_vco_div = 0x1; +- pixel_freq = 2700000000UL / 2; +- break; +- case 5400: +- phy_vco_div = 0x2; +- pixel_freq = 5400000000UL / 4; +- break; +- case 8100: +- phy_vco_div = 0x0; +- pixel_freq = 8100000000UL / 6; +- break; +- default: +- /* Other link rates aren't supported */ +- return -EINVAL; +- } +- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); +- +- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); +- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); +- +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); +- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, +- status, +- ((status & BIT(0)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- /* +- * At least for 7nm DP PHY this has to be done after enabling link +- * clock. +- */ +- +- if (dp_opts->lanes == 1) { +- bias0_en = reverse ? 0x3e : 0x15; +- bias1_en = reverse ? 0x15 : 0x3e; +- drvr0_en = reverse ? 0x13 : 0x10; +- drvr1_en = reverse ? 0x10 : 0x13; +- } else if (dp_opts->lanes == 2) { +- bias0_en = reverse ? 0x3f : 0x15; +- bias1_en = reverse ? 0x15 : 0x3f; +- drvr0_en = 0x10; +- drvr1_en = 0x10; +- } else { +- bias0_en = 0x3f; +- bias1_en = 0x3f; +- drvr0_en = 0x10; +- drvr1_en = 0x10; +- } +- +- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); +- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); +- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); +- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); +- +- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); +- udelay(2000); +- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); +- +- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, +- status, +- ((status & BIT(1)) > 0), +- 500, +- 10000)) +- return -ETIMEDOUT; +- +- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); +- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); +- +- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); +- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); +- +- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); +- +- return 0; +-} +- +-/* +- * We need to calibrate the aux setting here as many times +- * as the caller tries +- */ +-static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) +-{ +- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; +- u8 val; +- +- qphy->dp_aux_cfg++; +- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); +- val = cfg1_settings[qphy->dp_aux_cfg]; +- +- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); +- +- return 0; +-} +- + static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) + { + const struct phy_configure_opts_dp *dp_opts = &opts->dp; +@@ -6023,81 +3104,27 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + { + .compatible = "qcom,ipq8074-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, +- }, { +- .compatible = "qcom,msm8996-qmp-pcie-phy", +- .data = &msm8996_pciephy_cfg, +- }, { +- .compatible = "qcom,msm8996-qmp-ufs-phy", +- .data = &msm8996_ufs_cfg, + }, { + .compatible = "qcom,msm8996-qmp-usb3-phy", + .data = &msm8996_usb3phy_cfg, +- }, { +- .compatible = "qcom,msm8998-qmp-pcie-phy", +- .data = &msm8998_pciephy_cfg, +- }, { +- .compatible = "qcom,msm8998-qmp-ufs-phy", +- .data = &sdm845_ufsphy_cfg, +- }, { +- .compatible = "qcom,ipq8074-qmp-pcie-phy", +- .data = &ipq8074_pciephy_cfg, +- }, { +- .compatible = "qcom,ipq6018-qmp-pcie-phy", +- .data = &ipq6018_pciephy_cfg, + }, { + .compatible = "qcom,ipq6018-qmp-usb3-phy", + .data = &ipq8074_usb3phy_cfg, + }, { + .compatible = "qcom,sc7180-qmp-usb3-phy", + .data = &sc7180_usb3phy_cfg, +- }, { +- .compatible = "qcom,sc7180-qmp-usb3-dp-phy", +- /* It's a combo phy */ +- }, { +- .compatible = "qcom,sc8180x-qmp-pcie-phy", +- .data = &sc8180x_pciephy_cfg, +- }, { +- .compatible = "qcom,sc8180x-qmp-ufs-phy", +- .data = &sm8150_ufsphy_cfg, +- }, { +- .compatible = "qcom,sc8280xp-qmp-ufs-phy", +- .data = &sm8350_ufsphy_cfg, + }, { + .compatible = "qcom,sc8180x-qmp-usb3-phy", + .data = &sm8150_usb3phy_cfg, +- }, { +- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", +- /* It's a combo phy */ +- }, { +- .compatible = "qcom,sdm845-qhp-pcie-phy", +- .data = &sdm845_qhp_pciephy_cfg, +- }, { +- .compatible = "qcom,sdm845-qmp-pcie-phy", +- .data = &sdm845_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-usb3-phy", + .data = &qmp_v3_usb3phy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-usb3-uni-phy", + .data = &qmp_v3_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sdm845-qmp-ufs-phy", +- .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,msm8998-qmp-usb3-phy", + .data = &msm8998_usb3phy_cfg, +- }, { +- .compatible = "qcom,sm6115-qmp-ufs-phy", +- .data = &sm6115_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm6350-qmp-ufs-phy", +- .data = &sdm845_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8150-qmp-ufs-phy", +- .data = &sm8150_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-ufs-phy", +- .data = &sm8150_ufsphy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-usb3-phy", + .data = &sm8150_usb3phy_cfg, +@@ -6107,27 +3134,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + }, { + .compatible = "qcom,sm8250-qmp-usb3-phy", + .data = &sm8250_usb3phy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-usb3-dp-phy", +- /* It's a combo phy */ + }, { + .compatible = "qcom,sm8250-qmp-usb3-uni-phy", + .data = &sm8250_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", +- .data = &sm8250_qmp_gen3x1_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", +- .data = &sm8250_qmp_gen3x2_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8350-qmp-ufs-phy", +- .data = &sm8350_ufsphy_cfg, +- }, { +- .compatible = "qcom,sm8250-qmp-modem-pcie-phy", +- .data = &sm8250_qmp_gen3x2_pciephy_cfg, +- }, { +- .compatible = "qcom,sdx55-qmp-pcie-phy", +- .data = &sdx55_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sdx55-qmp-usb3-uni-phy", + .data = &sdx55_usb3_uniphy_cfg, +@@ -6140,15 +3149,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + }, { + .compatible = "qcom,sm8350-qmp-usb3-uni-phy", + .data = &sm8350_usb3_uniphy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", +- .data = &sm8450_qmp_gen3x1_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", +- .data = &sm8450_qmp_gen4x2_pciephy_cfg, +- }, { +- .compatible = "qcom,sm8450-qmp-ufs-phy", +- .data = &sm8450_ufsphy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-usb3-phy", + .data = &sm8350_usb3phy_cfg, +@@ -6160,22 +3160,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { + }; + MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); + +-static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { +- { +- .compatible = "qcom,sc7180-qmp-usb3-dp-phy", +- .data = &sc7180_usb3dpphy_cfg, +- }, +- { +- .compatible = "qcom,sm8250-qmp-usb3-dp-phy", +- .data = &sm8250_usb3dpphy_cfg, +- }, +- { +- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", +- .data = &sc8180x_usb3dpphy_cfg, +- }, +- { } +-}; +- + static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, + qcom_qmp_phy_runtime_resume, NULL) +@@ -6206,20 +3190,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + + /* Get the specific init parameters of QMP phy */ + cfg = of_device_get_match_data(dev); +- if (!cfg) { +- const struct of_device_id *match; +- +- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev); +- if (!match) +- return -EINVAL; +- +- combo_cfg = match->data; +- if (!combo_cfg) +- return -EINVAL; +- +- usb_cfg = combo_cfg->usb_cfg; +- cfg = usb_cfg; /* Setup clks and regulators */ +- } ++ if (!cfg) ++ return -EINVAL; + + /* per PHY serdes; usually located at base address */ + usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); +@@ -6336,7 +3308,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) + static struct platform_driver qcom_qmp_phy_driver = { + .probe = qcom_qmp_phy_probe, + .driver = { +- .name = "qcom-qmp-phy", ++ .name = "qcom-qmp-usb-phy", + .pm = &qcom_qmp_phy_pm_ops, + .of_match_table = qcom_qmp_phy_of_match_table, + }, +@@ -6345,5 +3317,5 @@ static struct platform_driver qcom_qmp_phy_driver = { + module_platform_driver(qcom_qmp_phy_driver); + + MODULE_AUTHOR("Vivek Gautam "); +-MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); ++MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); + MODULE_LICENSE("GPL v2"); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-drop-pipe-clock-lane-suffix.patch b/queue-5.10/phy-qcom-qmp-usb-drop-pipe-clock-lane-suffix.patch new file mode 100644 index 00000000000..f70e3b16386 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-drop-pipe-clock-lane-suffix.patch @@ -0,0 +1,51 @@ +From 5bfef756238ed6300056dbf5152f2a2be054b52e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 13:29:23 +0200 +Subject: phy: qcom-qmp-usb: drop pipe clock lane suffix + +From: Johan Hovold + +[ Upstream commit c8c5d5e89ac52a462f48264863a7a32f0c76fa1d ] + +The pipe clock is defined in the "lane" node so there's no need to keep +adding a redundant lane-number suffix to the clock name. + +Update driver to support the new binding where the pipe clock name has +been deprecated by instead requesting the clock by index. + +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20220830112923.3725-31-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index 687f1a534837..116f60ef0649 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -2510,7 +2510,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; +- char prop_name[MAX_PROP_NAME]; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); +@@ -2566,8 +2565,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + if (!qphy->pcs_misc) + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); + +- snprintf(prop_name, sizeof(prop_name), "pipe%d", id); +- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); ++ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); + if (IS_ERR(qphy->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), + "failed to get lane%d pipe clock\n", id); +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-drop-support-for-non-usb-phy-types.patch b/queue-5.10/phy-qcom-qmp-usb-drop-support-for-non-usb-phy-types.patch new file mode 100644 index 00000000000..643babbaa80 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-drop-support-for-non-usb-phy-types.patch @@ -0,0 +1,600 @@ +From 8ec1d7a1d7cdbf41bd0641e91b68d1b2b6938792 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 00:31:51 +0300 +Subject: phy: qcom-qmp-usb: drop support for non-USB PHY types + +From: Dmitry Baryshkov + +[ Upstream commit 86f5ddddcd9c4755e3d1d1ca4be01df5a4ed5d96 ] + +Drop remaining support for PHY types other than USB. + +Acked-by: Bjorn Andersson +Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X +Signed-off-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20220607213203.2819885-19-dmitry.baryshkov@linaro.org +Signed-off-by: Vinod Koul +Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral") +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 435 +++--------------------- + 1 file changed, 48 insertions(+), 387 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index 2ae13b4485b6..55785dcd47e0 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -2059,7 +2059,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *serdes = qphy->serdes; +- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; + const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; + int serdes_tbl_num = cfg->serdes_tbl_num; + int ret; +@@ -2069,35 +2068,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) + qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + cfg->serdes_tbl_num_sec); + +- if (cfg->type == PHY_TYPE_DP) { +- switch (dp_opts->link_rate) { +- case 1620: +- qcom_qmp_phy_usb_configure(serdes, cfg->regs, +- cfg->serdes_tbl_rbr, +- cfg->serdes_tbl_rbr_num); +- break; +- case 2700: +- qcom_qmp_phy_usb_configure(serdes, cfg->regs, +- cfg->serdes_tbl_hbr, +- cfg->serdes_tbl_hbr_num); +- break; +- case 5400: +- qcom_qmp_phy_usb_configure(serdes, cfg->regs, +- cfg->serdes_tbl_hbr2, +- cfg->serdes_tbl_hbr2_num); +- break; +- case 8100: +- qcom_qmp_phy_usb_configure(serdes, cfg->regs, +- cfg->serdes_tbl_hbr3, +- cfg->serdes_tbl_hbr3_num); +- break; +- default: +- /* Other link rates aren't supported */ +- return -EINVAL; +- } +- } +- +- + if (cfg->has_phy_com_ctrl) { + void __iomem *status; + unsigned int mask, val; +@@ -2121,32 +2091,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) + return 0; + } + +-static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) +-{ +- const struct phy_configure_opts_dp *dp_opts = &opts->dp; +- struct qmp_phy *qphy = phy_get_drvdata(phy); +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- +- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); +- if (qphy->dp_opts.set_voltages) { +- cfg->configure_dp_tx(qphy); +- qphy->dp_opts.set_voltages = 0; +- } +- +- return 0; +-} +- +-static int qcom_qmp_dp_phy_calibrate(struct phy *phy) +-{ +- struct qmp_phy *qphy = phy_get_drvdata(phy); +- const struct qmp_phy_cfg *cfg = qphy->cfg; +- +- if (cfg->calibrate_dp_phy) +- return cfg->calibrate_dp_phy(qphy); +- +- return 0; +-} +- + static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) + { + struct qcom_qmp *qmp = qphy->qmp; +@@ -2316,9 +2260,6 @@ static int qcom_qmp_phy_usb_init(struct phy *phy) + if (ret) + return ret; + +- if (cfg->type == PHY_TYPE_DP) +- cfg->dp_aux_init(qphy); +- + return 0; + } + +@@ -2369,10 +2310,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) + cfg->tx_tbl_num_sec, 2); + } + +- /* Configure special DP tx tunings */ +- if (cfg->type == PHY_TYPE_DP) +- cfg->configure_dp_tx(qphy); +- + qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, + cfg->rx_tbl, cfg->rx_tbl_num, 1); + if (cfg->rx_tbl_sec) +@@ -2389,14 +2326,10 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) + } + + /* Configure link rate, swing, etc. */ +- if (cfg->type == PHY_TYPE_DP) { +- cfg->configure_dp_phy(qphy); +- } else { +- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); +- if (cfg->pcs_tbl_sec) +- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, +- cfg->pcs_tbl_num_sec); +- } ++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); ++ if (cfg->pcs_tbl_sec) ++ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, ++ cfg->pcs_tbl_num_sec); + + ret = reset_control_deassert(qmp->ufs_reset); + if (ret) +@@ -2408,40 +2341,26 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy) + qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + cfg->pcs_misc_tbl_num_sec); + +- /* +- * Pull out PHY from POWER DOWN state. +- * This is active low enable signal to power-down PHY. +- */ +- if(cfg->type == PHY_TYPE_PCIE) +- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); +- + if (cfg->has_pwrdn_delay) + usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + +- if (cfg->type != PHY_TYPE_DP) { +- /* Pull PHY out of reset state */ +- if (!cfg->no_pcs_sw_reset) +- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); +- /* start SerDes and Phy-Coding-Sublayer */ +- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); +- +- if (cfg->type == PHY_TYPE_UFS) { +- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; +- mask = PCS_READY; +- ready = PCS_READY; +- } else { +- status = pcs + cfg->regs[QPHY_PCS_STATUS]; +- mask = cfg->phy_status; +- ready = 0; +- } ++ /* Pull PHY out of reset state */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* start SerDes and Phy-Coding-Sublayer */ ++ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + +- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, +- PHY_INIT_COMPLETE_TIMEOUT); +- if (ret) { +- dev_err(qmp->dev, "phy initialization timed-out\n"); +- goto err_disable_pipe_clk; +- } ++ status = pcs + cfg->regs[QPHY_PCS_STATUS]; ++ mask = cfg->phy_status; ++ ready = 0; ++ ++ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, ++ PHY_INIT_COMPLETE_TIMEOUT); ++ if (ret) { ++ dev_err(qmp->dev, "phy initialization timed-out\n"); ++ goto err_disable_pipe_clk; + } ++ + return 0; + + err_disable_pipe_clk: +@@ -2460,25 +2379,20 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy) + + clk_disable_unprepare(qphy->pipe_clk); + +- if (cfg->type == PHY_TYPE_DP) { +- /* Assert DP PHY power down */ +- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); +- } else { +- /* PHY reset */ +- if (!cfg->no_pcs_sw_reset) +- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ++ /* PHY reset */ ++ if (!cfg->no_pcs_sw_reset) ++ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + +- /* stop SerDes and Phy-Coding-Sublayer */ +- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ++ /* stop SerDes and Phy-Coding-Sublayer */ ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + +- /* Put PHY into POWER DOWN state: active low */ +- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { +- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], +- cfg->pwrdn_ctrl); +- } else { +- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, +- cfg->pwrdn_ctrl); +- } ++ /* Put PHY into POWER DOWN state: active low */ ++ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { ++ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], ++ cfg->pwrdn_ctrl); ++ } else { ++ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, ++ cfg->pwrdn_ctrl); + } + + return 0; +@@ -2755,223 +2669,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + } + +-/* +- * Display Port PLL driver block diagram for branch clocks +- * +- * +------------------------------+ +- * | DP_VCO_CLK | +- * | | +- * | +-------------------+ | +- * | | (DP PLL/VCO) | | +- * | +---------+---------+ | +- * | v | +- * | +----------+-----------+ | +- * | | hsclk_divsel_clk_src | | +- * | +----------+-----------+ | +- * +------------------------------+ +- * | +- * +---------<---------v------------>----------+ +- * | | +- * +--------v----------------+ | +- * | dp_phy_pll_link_clk | | +- * | link_clk | | +- * +--------+----------------+ | +- * | | +- * | | +- * v v +- * Input to DISPCC block | +- * for link clk, crypto clk | +- * and interface clock | +- * | +- * | +- * +--------<------------+-----------------+---<---+ +- * | | | +- * +----v---------+ +--------v-----+ +--------v------+ +- * | vco_divided | | vco_divided | | vco_divided | +- * | _clk_src | | _clk_src | | _clk_src | +- * | | | | | | +- * |divsel_six | | divsel_two | | divsel_four | +- * +-------+------+ +-----+--------+ +--------+------+ +- * | | | +- * v---->----------v-------------<------v +- * | +- * +----------+-----------------+ +- * | dp_phy_pll_vco_div_clk | +- * +---------+------------------+ +- * | +- * v +- * Input to DISPCC block +- * for DP pixel clock +- * +- */ +-static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- switch (req->rate) { +- case 1620000000UL / 2: +- case 2700000000UL / 2: +- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ +- return 0; +- default: +- return -EINVAL; +- } +-} +- +-static unsigned long +-qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +-{ +- const struct qmp_phy_dp_clks *dp_clks; +- const struct qmp_phy *qphy; +- const struct phy_configure_opts_dp *dp_opts; +- +- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); +- qphy = dp_clks->qphy; +- dp_opts = &qphy->dp_opts; +- +- switch (dp_opts->link_rate) { +- case 1620: +- return 1620000000UL / 2; +- case 2700: +- return 2700000000UL / 2; +- case 5400: +- return 5400000000UL / 4; +- case 8100: +- return 8100000000UL / 6; +- default: +- return 0; +- } +-} +- +-static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { +- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, +- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, +-}; +- +-static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- switch (req->rate) { +- case 162000000: +- case 270000000: +- case 540000000: +- case 810000000: +- return 0; +- default: +- return -EINVAL; +- } +-} +- +-static unsigned long +-qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +-{ +- const struct qmp_phy_dp_clks *dp_clks; +- const struct qmp_phy *qphy; +- const struct phy_configure_opts_dp *dp_opts; +- +- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); +- qphy = dp_clks->qphy; +- dp_opts = &qphy->dp_opts; +- +- switch (dp_opts->link_rate) { +- case 1620: +- case 2700: +- case 5400: +- case 8100: +- return dp_opts->link_rate * 100000; +- default: +- return 0; +- } +-} +- +-static const struct clk_ops qcom_qmp_dp_link_clk_ops = { +- .determine_rate = qcom_qmp_dp_link_clk_determine_rate, +- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, +-}; +- +-static struct clk_hw * +-qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) +-{ +- struct qmp_phy_dp_clks *dp_clks = data; +- unsigned int idx = clkspec->args[0]; +- +- if (idx >= 2) { +- pr_err("%s: invalid index %u\n", __func__, idx); +- return ERR_PTR(-EINVAL); +- } +- +- if (idx == 0) +- return &dp_clks->dp_link_hw; +- +- return &dp_clks->dp_pixel_hw; +-} +- +-static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, +- struct device_node *np) +-{ +- struct clk_init_data init = { }; +- struct qmp_phy_dp_clks *dp_clks; +- char name[64]; +- int ret; +- +- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); +- if (!dp_clks) +- return -ENOMEM; +- +- dp_clks->qphy = qphy; +- qphy->dp_clks = dp_clks; +- +- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); +- init.ops = &qcom_qmp_dp_link_clk_ops; +- init.name = name; +- dp_clks->dp_link_hw.init = &init; +- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); +- if (ret) +- return ret; +- +- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); +- init.ops = &qcom_qmp_dp_pixel_clk_ops; +- init.name = name; +- dp_clks->dp_pixel_hw.init = &init; +- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); +- if (ret) +- return ret; +- +- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); +- if (ret) +- return ret; +- +- /* +- * Roll a devm action because the clock provider is the child node, but +- * the child node is not actually a device. +- */ +- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); +-} +- +-static const struct phy_ops qcom_qmp_phy_usb_gen_ops = { ++static const struct phy_ops qcom_qmp_phy_usb_ops = { + .init = qcom_qmp_phy_usb_enable, + .exit = qcom_qmp_phy_usb_disable, + .set_mode = qcom_qmp_phy_usb_set_mode, + .owner = THIS_MODULE, + }; + +-static const struct phy_ops qcom_qmp_phy_usb_dp_ops = { +- .init = qcom_qmp_phy_usb_init, +- .configure = qcom_qmp_dp_phy_configure, +- .power_on = qcom_qmp_phy_usb_power_on, +- .calibrate = qcom_qmp_dp_phy_calibrate, +- .power_off = qcom_qmp_phy_usb_power_off, +- .exit = qcom_qmp_phy_usb_exit, +- .set_mode = qcom_qmp_phy_usb_set_mode, +- .owner = THIS_MODULE, +-}; +- +-static const struct phy_ops qcom_qmp_pcie_ufs_ops = { +- .power_on = qcom_qmp_phy_usb_enable, +- .power_off = qcom_qmp_phy_usb_disable, +- .set_mode = qcom_qmp_phy_usb_set_mode, +- .owner = THIS_MODULE, +-}; +- + static void qcom_qmp_reset_control_put(void *data) + { + reset_control_put(data); +@@ -2984,7 +2688,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; +- const struct phy_ops *ops; + char prop_name[MAX_PROP_NAME]; + int ret; + +@@ -3051,16 +2754,12 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + snprintf(prop_name, sizeof(prop_name), "pipe%d", id); + qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); + if (IS_ERR(qphy->pipe_clk)) { +- if (cfg->type == PHY_TYPE_PCIE || +- cfg->type == PHY_TYPE_USB3) { +- ret = PTR_ERR(qphy->pipe_clk); +- if (ret != -EPROBE_DEFER) +- dev_err(dev, +- "failed to get lane%d pipe_clk, %d\n", +- id, ret); +- return ret; +- } +- qphy->pipe_clk = NULL; ++ ret = PTR_ERR(qphy->pipe_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, ++ "failed to get lane%d pipe_clk, %d\n", ++ id, ret); ++ return ret; + } + + /* Get lane reset, if any */ +@@ -3077,14 +2776,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + return ret; + } + +- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) +- ops = &qcom_qmp_pcie_ufs_ops; +- else if (cfg->type == PHY_TYPE_DP) +- ops = &qcom_qmp_phy_usb_dp_ops; +- else +- ops = &qcom_qmp_phy_usb_gen_ops; +- +- generic_phy = devm_phy_create(dev, np, ops); ++ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); + if (IS_ERR(generic_phy)) { + ret = PTR_ERR(generic_phy); + dev_err(dev, "failed to create qphy %d\n", ret); +@@ -3172,12 +2864,7 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) + struct device_node *child; + struct phy_provider *phy_provider; + void __iomem *serdes; +- void __iomem *usb_serdes; +- void __iomem *dp_serdes = NULL; +- const struct qmp_phy_combo_cfg *combo_cfg = NULL; + const struct qmp_phy_cfg *cfg = NULL; +- const struct qmp_phy_cfg *usb_cfg = NULL; +- const struct qmp_phy_cfg *dp_cfg = NULL; + int num, id, expected_phys; + int ret; + +@@ -3194,28 +2881,18 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) + return -EINVAL; + + /* per PHY serdes; usually located at base address */ +- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); ++ serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(serdes)) + return PTR_ERR(serdes); + + /* per PHY dp_com; if PHY has dp_com control block */ +- if (combo_cfg || cfg->has_phy_dp_com_ctrl) { ++ if (cfg->has_phy_dp_com_ctrl) { + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->dp_com)) + return PTR_ERR(qmp->dp_com); + } + +- if (combo_cfg) { +- /* Only two serdes for combo PHY */ +- dp_serdes = devm_platform_ioremap_resource(pdev, 2); +- if (IS_ERR(dp_serdes)) +- return PTR_ERR(dp_serdes); +- +- dp_cfg = combo_cfg->dp_cfg; +- expected_phys = 2; +- } else { +- expected_phys = cfg->nlanes; +- } ++ expected_phys = cfg->nlanes; + + mutex_init(&qmp->phy_mutex); + +@@ -3256,14 +2933,6 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) + + id = 0; + for_each_available_child_of_node(dev->of_node, child) { +- if (of_node_name_eq(child, "dp-phy")) { +- cfg = dp_cfg; +- serdes = dp_serdes; +- } else if (of_node_name_eq(child, "usb3-phy")) { +- cfg = usb_cfg; +- serdes = usb_serdes; +- } +- + /* Create per-lane phy */ + ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg); + if (ret) { +@@ -3276,21 +2945,13 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) + * Register the pipe clock provided by phy. + * See function description to see details of this pipe clock. + */ +- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { +- ret = phy_pipe_clk_register(qmp, child); +- if (ret) { +- dev_err(qmp->dev, +- "failed to register pipe clock source\n"); +- goto err_node_put; +- } +- } else if (cfg->type == PHY_TYPE_DP) { +- ret = phy_dp_clks_register(qmp, qmp->phys[id], child); +- if (ret) { +- dev_err(qmp->dev, +- "failed to register DP clock source\n"); +- goto err_node_put; +- } ++ ret = phy_pipe_clk_register(qmp, child); ++ if (ret) { ++ dev_err(qmp->dev, ++ "failed to register pipe clock source\n"); ++ goto err_node_put; + } ++ + id++; + } + +-- +2.35.1 + diff --git a/queue-5.10/phy-qcom-qmp-usb-fix-memleak-on-probe-deferral.patch b/queue-5.10/phy-qcom-qmp-usb-fix-memleak-on-probe-deferral.patch new file mode 100644 index 00000000000..e124d0d6918 --- /dev/null +++ b/queue-5.10/phy-qcom-qmp-usb-fix-memleak-on-probe-deferral.patch @@ -0,0 +1,136 @@ +From e0632f4b76cb0969d02f3a521cc9e879d9c6d412 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 12:23:35 +0200 +Subject: phy: qcom-qmp-usb: fix memleak on probe deferral + +From: Johan Hovold + +[ Upstream commit a5d6b1ac56cbd6b5850a3a54e35f1cb71e8e8cdd ] + +Switch to using the device-managed of_iomap helper to avoid leaking +memory on probe deferral and driver unbind. + +Note that this helper checks for already reserved regions and may fail +if there are multiple devices claiming the same memory. + +Two bindings currently rely on overlapping mappings for the PCS region +so fallback to non-exclusive mappings for those for now. + +Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20220916102340.11520-7-johan+linaro@kernel.org +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 57 ++++++++++++++++++------- + 1 file changed, 42 insertions(+), 15 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +index 116f60ef0649..b727dcf4f906 100644 +--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +@@ -2503,6 +2503,21 @@ static const struct phy_ops qcom_qmp_phy_usb_ops = { + .owner = THIS_MODULE, + }; + ++static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, ++ int index, bool exclusive) ++{ ++ struct resource res; ++ ++ if (!exclusive) { ++ if (of_address_to_resource(np, index, &res)) ++ return IOMEM_ERR_PTR(-EINVAL); ++ ++ return devm_ioremap(dev, res.start, resource_size(&res)); ++ } ++ ++ return devm_of_iomap(dev, np, index, NULL); ++} ++ + static + int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + void __iomem *serdes, const struct qmp_phy_cfg *cfg) +@@ -2510,8 +2525,18 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct phy *generic_phy; + struct qmp_phy *qphy; ++ bool exclusive = true; + int ret; + ++ /* ++ * FIXME: These bindings should be fixed to not rely on overlapping ++ * mappings for PCS. ++ */ ++ if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) ++ exclusive = false; ++ if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) ++ exclusive = false; ++ + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; +@@ -2524,17 +2549,17 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. + */ +- qphy->tx = of_iomap(np, 0); +- if (!qphy->tx) +- return -ENOMEM; ++ qphy->tx = devm_of_iomap(dev, np, 0, NULL); ++ if (IS_ERR(qphy->tx)) ++ return PTR_ERR(qphy->tx); + +- qphy->rx = of_iomap(np, 1); +- if (!qphy->rx) +- return -ENOMEM; ++ qphy->rx = devm_of_iomap(dev, np, 1, NULL); ++ if (IS_ERR(qphy->rx)) ++ return PTR_ERR(qphy->rx); + +- qphy->pcs = of_iomap(np, 2); +- if (!qphy->pcs) +- return -ENOMEM; ++ qphy->pcs = qmp_usb_iomap(dev, np, 2, exclusive); ++ if (IS_ERR(qphy->pcs)) ++ return PTR_ERR(qphy->pcs); + + /* + * If this is a dual-lane PHY, then there should be registers for the +@@ -2543,9 +2568,9 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + * offset from the first lane. + */ + if (cfg->is_dual_lane_phy) { +- qphy->tx2 = of_iomap(np, 3); +- qphy->rx2 = of_iomap(np, 4); +- if (!qphy->tx2 || !qphy->rx2) { ++ qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); ++ qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); ++ if (IS_ERR(qphy->tx2) || IS_ERR(qphy->rx2)) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + +@@ -2555,15 +2580,17 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { +- qphy->pcs_misc = of_iomap(np, 5); ++ qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); + } + + } else { +- qphy->pcs_misc = of_iomap(np, 3); ++ qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); + } + +- if (!qphy->pcs_misc) ++ if (IS_ERR(qphy->pcs_misc)) { + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ++ qphy->pcs_misc = NULL; ++ } + + qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); + if (IS_ERR(qphy->pipe_clk)) { +-- +2.35.1 + diff --git a/queue-5.10/phy-qualcomm-call-clk_disable_unprepare-in-the-error.patch b/queue-5.10/phy-qualcomm-call-clk_disable_unprepare-in-the-error.patch new file mode 100644 index 00000000000..487bb3aed11 --- /dev/null +++ b/queue-5.10/phy-qualcomm-call-clk_disable_unprepare-in-the-error.patch @@ -0,0 +1,53 @@ +From a332aa46f377d0344fd09742a168959c1ab6b4ef Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 14 Sep 2022 13:13:33 +0800 +Subject: phy: qualcomm: call clk_disable_unprepare in the error handling + +From: Dongliang Mu + +[ Upstream commit c3966ced8eb8dc53b6c8d7f97d32cc8a2107d83e ] + +Smatch reports the following error: + +drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on() +warn: 'uphy->cal_clk' from clk_prepare_enable() not released on lines: +58. +drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on() +warn: 'uphy->cal_sleep_clk' from clk_prepare_enable() not released on +lines: 58. +drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on() +warn: 'uphy->phy_clk' from clk_prepare_enable() not released on lines: +58. + +Fix this by calling proper clk_disable_unprepare calls. + +Fixes: 0b56e9a7e835 ("phy: Group vendor specific phy drivers") +Signed-off-by: Dongliang Mu +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20220914051334.69282-1-dzm91@hust.edu.cn +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c +index 04d18d52f700..d4741c2dbbb5 100644 +--- a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c ++++ b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c +@@ -54,8 +54,10 @@ static int qcom_usb_hsic_phy_power_on(struct phy *phy) + + /* Configure pins for HSIC functionality */ + pins_default = pinctrl_lookup_state(uphy->pctl, PINCTRL_STATE_DEFAULT); +- if (IS_ERR(pins_default)) +- return PTR_ERR(pins_default); ++ if (IS_ERR(pins_default)) { ++ ret = PTR_ERR(pins_default); ++ goto err_ulpi; ++ } + + ret = pinctrl_select_state(uphy->pctl, pins_default); + if (ret) +-- +2.35.1 + diff --git a/queue-5.10/platform-chrome-cros_ec-notify-the-pm-of-wake-events.patch b/queue-5.10/platform-chrome-cros_ec-notify-the-pm-of-wake-events.patch new file mode 100644 index 00000000000..65181ad81f6 --- /dev/null +++ b/queue-5.10/platform-chrome-cros_ec-notify-the-pm-of-wake-events.patch @@ -0,0 +1,55 @@ +From e8f551b40ae6daa42ce99166e9f65bcb5e8f2f1b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 20:49:54 +0000 +Subject: platform/chrome: cros_ec: Notify the PM of wake events during resume + +From: Jameson Thies + +[ Upstream commit 8edd2752b0aa498b3a61f3caee8f79f7e0567fad ] + +cros_ec_handle_event in the cros_ec driver can notify the PM of wake +events. When a device is suspended, cros_ec_handle_event will not check +MKBP events. Instead, received MKBP events are checked during resume by +cros_ec_report_events_during_suspend. But +cros_ec_report_events_during_suspend cannot notify the PM if received +events are wake events, causing wake events to not be reported if +received while the device is suspended. + +Update cros_ec_report_events_during_suspend to notify the PM of wake +events during resume by calling pm_wakeup_event. + +Signed-off-by: Jameson Thies +Reviewed-by: Prashant Malani +Reviewed-by: Benson Leung +Signed-off-by: Tzung-Bi Shih +Link: https://lore.kernel.org/r/20220913204954.2931042-1-jthies@google.com +Signed-off-by: Sasha Levin +--- + drivers/platform/chrome/cros_ec.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cros_ec.c +index c4de8c4db193..5a622666a075 100644 +--- a/drivers/platform/chrome/cros_ec.c ++++ b/drivers/platform/chrome/cros_ec.c +@@ -332,10 +332,16 @@ EXPORT_SYMBOL(cros_ec_suspend); + + static void cros_ec_report_events_during_suspend(struct cros_ec_device *ec_dev) + { ++ bool wake_event; ++ + while (ec_dev->mkbp_event_supported && +- cros_ec_get_next_event(ec_dev, NULL, NULL) > 0) ++ cros_ec_get_next_event(ec_dev, &wake_event, NULL) > 0) { + blocking_notifier_call_chain(&ec_dev->event_notifier, + 1, ec_dev); ++ ++ if (wake_event && device_may_wakeup(ec_dev->dev)) ++ pm_wakeup_event(ec_dev->dev, 0); ++ } + } + + /** +-- +2.35.1 + diff --git a/queue-5.10/platform-chrome-fix-double-free-in-chromeos_laptop_p.patch b/queue-5.10/platform-chrome-fix-double-free-in-chromeos_laptop_p.patch new file mode 100644 index 00000000000..e284fcfea09 --- /dev/null +++ b/queue-5.10/platform-chrome-fix-double-free-in-chromeos_laptop_p.patch @@ -0,0 +1,88 @@ +From 49b2857f75b477575e20b3da873e75cdfc4d13a3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 14 Aug 2022 01:08:43 +0300 +Subject: platform/chrome: fix double-free in chromeos_laptop_prepare() + +From: Rustam Subkhankulov + +[ Upstream commit 6ad4194d6a1e1d11b285989cd648ef695b4a93c0 ] + +If chromeos_laptop_prepare_i2c_peripherals() fails after allocating memory +for 'cros_laptop->i2c_peripherals', this memory is freed at 'err_out' label +and nonzero value is returned. Then chromeos_laptop_destroy() is called, +resulting in double-free error. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Signed-off-by: Rustam Subkhankulov +Fixes: 5020cd29d8bf ("platform/chrome: chromeos_laptop - supply properties for ACPI devices") +Reviewed-by: Dmitry Torokhov +Signed-off-by: Tzung-Bi Shih +Link: https://lore.kernel.org/r/20220813220843.2373004-1-subkhankulov@ispras.ru +Signed-off-by: Sasha Levin +--- + drivers/platform/chrome/chromeos_laptop.c | 24 ++++++++++++----------- + 1 file changed, 13 insertions(+), 11 deletions(-) + +diff --git a/drivers/platform/chrome/chromeos_laptop.c b/drivers/platform/chrome/chromeos_laptop.c +index 472a03daa869..109c191d35cf 100644 +--- a/drivers/platform/chrome/chromeos_laptop.c ++++ b/drivers/platform/chrome/chromeos_laptop.c +@@ -718,6 +718,7 @@ static int __init + chromeos_laptop_prepare_i2c_peripherals(struct chromeos_laptop *cros_laptop, + const struct chromeos_laptop *src) + { ++ struct i2c_peripheral *i2c_peripherals; + struct i2c_peripheral *i2c_dev; + struct i2c_board_info *info; + int i; +@@ -726,17 +727,15 @@ chromeos_laptop_prepare_i2c_peripherals(struct chromeos_laptop *cros_laptop, + if (!src->num_i2c_peripherals) + return 0; + +- cros_laptop->i2c_peripherals = kmemdup(src->i2c_peripherals, +- src->num_i2c_peripherals * +- sizeof(*src->i2c_peripherals), +- GFP_KERNEL); +- if (!cros_laptop->i2c_peripherals) ++ i2c_peripherals = kmemdup(src->i2c_peripherals, ++ src->num_i2c_peripherals * ++ sizeof(*src->i2c_peripherals), ++ GFP_KERNEL); ++ if (!i2c_peripherals) + return -ENOMEM; + +- cros_laptop->num_i2c_peripherals = src->num_i2c_peripherals; +- +- for (i = 0; i < cros_laptop->num_i2c_peripherals; i++) { +- i2c_dev = &cros_laptop->i2c_peripherals[i]; ++ for (i = 0; i < src->num_i2c_peripherals; i++) { ++ i2c_dev = &i2c_peripherals[i]; + info = &i2c_dev->board_info; + + error = chromeos_laptop_setup_irq(i2c_dev); +@@ -754,16 +753,19 @@ chromeos_laptop_prepare_i2c_peripherals(struct chromeos_laptop *cros_laptop, + } + } + ++ cros_laptop->i2c_peripherals = i2c_peripherals; ++ cros_laptop->num_i2c_peripherals = src->num_i2c_peripherals; ++ + return 0; + + err_out: + while (--i >= 0) { +- i2c_dev = &cros_laptop->i2c_peripherals[i]; ++ i2c_dev = &i2c_peripherals[i]; + info = &i2c_dev->board_info; + if (info->properties) + property_entries_free(info->properties); + } +- kfree(cros_laptop->i2c_peripherals); ++ kfree(i2c_peripherals); + return error; + } + +-- +2.35.1 + diff --git a/queue-5.10/platform-chrome-fix-memory-corruption-in-ioctl.patch b/queue-5.10/platform-chrome-fix-memory-corruption-in-ioctl.patch new file mode 100644 index 00000000000..ad3adb6f867 --- /dev/null +++ b/queue-5.10/platform-chrome-fix-memory-corruption-in-ioctl.patch @@ -0,0 +1,39 @@ +From bf9e77248fe40fc34e9ef24c624832f82a12d273 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 08:20:36 +0300 +Subject: platform/chrome: fix memory corruption in ioctl + +From: Dan Carpenter + +[ Upstream commit 8a07b45fd3c2dda24fad43639be5335a4595196a ] + +If "s_mem.bytes" is larger than the buffer size it leads to memory +corruption. + +Fixes: eda2e30c6684 ("mfd / platform: cros_ec: Miscellaneous character device to talk with the EC") +Signed-off-by: Dan Carpenter +Reviewed-by: Guenter Roeck +Signed-off-by: Tzung-Bi Shih +Link: https://lore.kernel.org/r/Yv8dpCFZJdbUT5ye@kili +Signed-off-by: Sasha Levin +--- + drivers/platform/chrome/cros_ec_chardev.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/platform/chrome/cros_ec_chardev.c b/drivers/platform/chrome/cros_ec_chardev.c +index fd33de546aee..0de7c255254e 100644 +--- a/drivers/platform/chrome/cros_ec_chardev.c ++++ b/drivers/platform/chrome/cros_ec_chardev.c +@@ -327,6 +327,9 @@ static long cros_ec_chardev_ioctl_readmem(struct cros_ec_dev *ec, + if (copy_from_user(&s_mem, arg, sizeof(s_mem))) + return -EFAULT; + ++ if (s_mem.bytes > sizeof(s_mem.buffer)) ++ return -EINVAL; ++ + num = ec_dev->cmd_readmem(ec_dev, s_mem.offset, s_mem.bytes, + s_mem.buffer); + if (num <= 0) +-- +2.35.1 + diff --git a/queue-5.10/platform-x86-msi-laptop-change-dmi-match-alias-strin.patch b/queue-5.10/platform-x86-msi-laptop-change-dmi-match-alias-strin.patch new file mode 100644 index 00000000000..297afce2924 --- /dev/null +++ b/queue-5.10/platform-x86-msi-laptop-change-dmi-match-alias-strin.patch @@ -0,0 +1,58 @@ +From 0e524b58fe1e7dc99948588f662c27e6fecabc83 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 17 Sep 2022 23:04:07 +0200 +Subject: platform/x86: msi-laptop: Change DMI match / alias strings to fix + module autoloading + +From: Hans de Goede + +[ Upstream commit 2a2565272a3628e45d61625e36ef17af7af4e3de ] + +On a MSI S270 with Fedora 37 x86_64 / systemd-251.4 the module does not +properly autoload. + +This is likely caused by issues with how systemd-udevd handles the single +quote char (') which is part of the sys_vendor / chassis_vendor strings +on this laptop. As a workaround remove the single quote char + everything +behind it from the sys_vendor + chassis_vendor matches. This fixes +the module not autoloading. + +Link: https://github.com/systemd/systemd/issues/24715 +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20220917210407.647432-1-hdegoede@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/platform/x86/msi-laptop.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c +index 3e935303b143..0e804b6c2d24 100644 +--- a/drivers/platform/x86/msi-laptop.c ++++ b/drivers/platform/x86/msi-laptop.c +@@ -596,11 +596,10 @@ static const struct dmi_system_id msi_dmi_table[] __initconst = { + { + .ident = "MSI S270", + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "MICRO-STAR INT'L CO.,LTD"), ++ DMI_MATCH(DMI_SYS_VENDOR, "MICRO-STAR INT"), + DMI_MATCH(DMI_PRODUCT_NAME, "MS-1013"), + DMI_MATCH(DMI_PRODUCT_VERSION, "0131"), +- DMI_MATCH(DMI_CHASSIS_VENDOR, +- "MICRO-STAR INT'L CO.,LTD") ++ DMI_MATCH(DMI_CHASSIS_VENDOR, "MICRO-STAR INT") + }, + .driver_data = &quirk_old_ec_model, + .callback = dmi_check_cb +@@ -633,8 +632,7 @@ static const struct dmi_system_id msi_dmi_table[] __initconst = { + DMI_MATCH(DMI_SYS_VENDOR, "NOTEBOOK"), + DMI_MATCH(DMI_PRODUCT_NAME, "SAM2000"), + DMI_MATCH(DMI_PRODUCT_VERSION, "0131"), +- DMI_MATCH(DMI_CHASSIS_VENDOR, +- "MICRO-STAR INT'L CO.,LTD") ++ DMI_MATCH(DMI_CHASSIS_VENDOR, "MICRO-STAR INT") + }, + .driver_data = &quirk_old_ec_model, + .callback = dmi_check_cb +-- +2.35.1 + diff --git a/queue-5.10/platform-x86-msi-laptop-fix-old-ec-check-for-backlig.patch b/queue-5.10/platform-x86-msi-laptop-fix-old-ec-check-for-backlig.patch new file mode 100644 index 00000000000..0f1b833e317 --- /dev/null +++ b/queue-5.10/platform-x86-msi-laptop-fix-old-ec-check-for-backlig.patch @@ -0,0 +1,58 @@ +From 9a1c0ec7ec3a3dc3d9ed1b5defb76367e526a682 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 16:13:34 +0200 +Subject: platform/x86: msi-laptop: Fix old-ec check for backlight registering + +From: Hans de Goede + +[ Upstream commit 83ac7a1c2ed5f17caa07cbbc84bad3c05dc3bf22 ] + +Commit 2cc6c717799f ("msi-laptop: Port to new backlight interface +selection API") replaced this check: + + if (!quirks->old_ec_model || acpi_video_backlight_support()) + pr_info("Brightness ignored, ..."); + else + do_register(); + +With: + + if (quirks->old_ec_model || + acpi_video_get_backlight_type() == acpi_backlight_vendor) + do_register(); + +But since the do_register() part was part of the else branch, the entire +condition should be inverted. So not only the 2 statements on either +side of the || should be inverted, but the || itself should be replaced +with a &&. + +In practice this has likely not been an issue because the new-ec models +(old_ec_model==false) likely all support ACPI video backlight control, +making acpi_video_get_backlight_type() return acpi_backlight_video +turning the second part of the || also false when old_ec_model == false. + +Fixes: 2cc6c717799f ("msi-laptop: Port to new backlight interface selection API") +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20220825141336.208597-1-hdegoede@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/platform/x86/msi-laptop.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c +index 24ffc8e2d2d1..0960205ee49f 100644 +--- a/drivers/platform/x86/msi-laptop.c ++++ b/drivers/platform/x86/msi-laptop.c +@@ -1048,8 +1048,7 @@ static int __init msi_init(void) + return -EINVAL; + + /* Register backlight stuff */ +- +- if (quirks->old_ec_model || ++ if (quirks->old_ec_model && + acpi_video_get_backlight_type() == acpi_backlight_vendor) { + struct backlight_properties props; + memset(&props, 0, sizeof(struct backlight_properties)); +-- +2.35.1 + diff --git a/queue-5.10/platform-x86-msi-laptop-fix-resource-cleanup.patch b/queue-5.10/platform-x86-msi-laptop-fix-resource-cleanup.patch new file mode 100644 index 00000000000..eb800fdb848 --- /dev/null +++ b/queue-5.10/platform-x86-msi-laptop-fix-resource-cleanup.patch @@ -0,0 +1,45 @@ +From 45a721cf2300bfdb44419c1e7fd805aa5741ae1c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 16:13:36 +0200 +Subject: platform/x86: msi-laptop: Fix resource cleanup + +From: Hans de Goede + +[ Upstream commit 5523632aa10f906dfe2eb714ee748590dc7fc6b1 ] + +Fix the input-device not getting free-ed on probe-errors and +fix the msi_touchpad_dwork not getting cancelled on neither +probe-errors nor on remove. + +Fixes: 143a4c0284dc ("msi-laptop: send out touchpad on/off key") +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20220825141336.208597-3-hdegoede@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/platform/x86/msi-laptop.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c +index 0960205ee49f..3e935303b143 100644 +--- a/drivers/platform/x86/msi-laptop.c ++++ b/drivers/platform/x86/msi-laptop.c +@@ -1116,6 +1116,8 @@ static int __init msi_init(void) + fail_create_group: + if (quirks->load_scm_model) { + i8042_remove_filter(msi_laptop_i8042_filter); ++ cancel_delayed_work_sync(&msi_touchpad_dwork); ++ input_unregister_device(msi_laptop_input_dev); + cancel_delayed_work_sync(&msi_rfkill_dwork); + cancel_work_sync(&msi_rfkill_work); + rfkill_cleanup(); +@@ -1136,6 +1138,7 @@ static void __exit msi_cleanup(void) + { + if (quirks->load_scm_model) { + i8042_remove_filter(msi_laptop_i8042_filter); ++ cancel_delayed_work_sync(&msi_touchpad_dwork); + input_unregister_device(msi_laptop_input_dev); + cancel_delayed_work_sync(&msi_rfkill_dwork); + cancel_work_sync(&msi_rfkill_work); +-- +2.35.1 + diff --git a/queue-5.10/power-supply-adp5061-fix-out-of-bounds-read-in-adp50.patch b/queue-5.10/power-supply-adp5061-fix-out-of-bounds-read-in-adp50.patch new file mode 100644 index 00000000000..4cb2d478cef --- /dev/null +++ b/queue-5.10/power-supply-adp5061-fix-out-of-bounds-read-in-adp50.patch @@ -0,0 +1,44 @@ +From 3c8799dd813f930a90f338f3c6336f5462d0d6b4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 27 Aug 2022 07:32:23 +0000 +Subject: power: supply: adp5061: fix out-of-bounds read in + adp5061_get_chg_type() + +From: Wei Yongjun + +[ Upstream commit 9d47e01b9d807808224347935562f7043a358054 ] + +ADP5061_CHG_STATUS_1_CHG_STATUS is masked with 0x07, which means a length +of 8, but adp5061_chg_type array size is 4, may end up reading 4 elements +beyond the end of the adp5061_chg_type[] array. + +Signed-off-by: Wei Yongjun +Acked-by: Michael Hennerich +Signed-off-by: Sebastian Reichel +Signed-off-by: Sasha Levin +--- + drivers/power/supply/adp5061.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/power/supply/adp5061.c b/drivers/power/supply/adp5061.c +index 003557043ab3..daee1161c305 100644 +--- a/drivers/power/supply/adp5061.c ++++ b/drivers/power/supply/adp5061.c +@@ -427,11 +427,11 @@ static int adp5061_get_chg_type(struct adp5061_state *st, + if (ret < 0) + return ret; + +- chg_type = adp5061_chg_type[ADP5061_CHG_STATUS_1_CHG_STATUS(status1)]; +- if (chg_type > ADP5061_CHG_FAST_CV) ++ chg_type = ADP5061_CHG_STATUS_1_CHG_STATUS(status1); ++ if (chg_type >= ARRAY_SIZE(adp5061_chg_type)) + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + else +- val->intval = chg_type; ++ val->intval = adp5061_chg_type[chg_type]; + + return ret; + } +-- +2.35.1 + diff --git a/queue-5.10/powercap-intel_rapl-fix-ubsan-shift-out-of-bounds-is.patch b/queue-5.10/powercap-intel_rapl-fix-ubsan-shift-out-of-bounds-is.patch new file mode 100644 index 00000000000..380153ec81b --- /dev/null +++ b/queue-5.10/powercap-intel_rapl-fix-ubsan-shift-out-of-bounds-is.patch @@ -0,0 +1,45 @@ +From b802f1fbdfd21128932497b2f138f908df4044f8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 14:08:26 +0800 +Subject: powercap: intel_rapl: fix UBSAN shift-out-of-bounds issue + +From: Chao Qin + +[ Upstream commit 2d93540014387d1c73b9ccc4d7895320df66d01b ] + +When value < time_unit, the parameter of ilog2() will be zero and +the return value is -1. u64(-1) is too large for shift exponent +and then will trigger shift-out-of-bounds: + +shift exponent 18446744073709551615 is too large for 32-bit type 'int' +Call Trace: + rapl_compute_time_window_core + rapl_write_data_raw + set_time_window + store_constraint_time_window_us + +Signed-off-by: Chao Qin +Acked-by: Zhang Rui +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/powercap/intel_rapl_common.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c +index a13a07f475d2..285420c1eb7c 100644 +--- a/drivers/powercap/intel_rapl_common.c ++++ b/drivers/powercap/intel_rapl_common.c +@@ -938,6 +938,9 @@ static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value, + y = value & 0x1f; + value = (1 << y) * (4 + f) * rp->time_unit / 4; + } else { ++ if (value < rp->time_unit) ++ return 0; ++ + do_div(value, rp->time_unit); + y = ilog2(value); + f = div64_u64(4 * (value - (1 << y)), 1 << y); +-- +2.35.1 + diff --git a/queue-5.10/powerpc-64s-fix-generic_cpu-build-flags-for-ppc970-g.patch b/queue-5.10/powerpc-64s-fix-generic_cpu-build-flags-for-ppc970-g.patch new file mode 100644 index 00000000000..2c3f2270082 --- /dev/null +++ b/queue-5.10/powerpc-64s-fix-generic_cpu-build-flags-for-ppc970-g.patch @@ -0,0 +1,41 @@ +From 5652b06d495b2503dbf5a7dc09578fcc52da8b4d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 11:41:02 +1000 +Subject: powerpc/64s: Fix GENERIC_CPU build flags for PPC970 / G5 + +From: Nicholas Piggin + +[ Upstream commit 58ec7f06b74e0d6e76c4110afce367c8b5f0837d ] + +Big-endian GENERIC_CPU supports 970, but builds with -mcpu=power5. +POWER5 is ISA v2.02 whereas 970 is v2.01 plus Altivec. 2.02 added +the popcntb instruction which a compiler might use. + +Use -mcpu=power4. + +Fixes: 471d7ff8b51b ("powerpc/64s: Remove POWER4 support") +Signed-off-by: Nicholas Piggin +Reviewed-by: Segher Boessenkool +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20220921014103.587954-1-npiggin@gmail.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile +index 59175651f0b9..612254141296 100644 +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -153,7 +153,7 @@ CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power8 + CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power9,-mtune=power8) + else + CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,$(call cc-option,-mtune=power5)) +-CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mcpu=power5,-mcpu=power4) ++CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power4 + endif + else ifdef CONFIG_PPC_BOOK3E_64 + CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64 +-- +2.35.1 + diff --git a/queue-5.10/powerpc-fix-spe-power-isa-properties-for-e500v1-plat.patch b/queue-5.10/powerpc-fix-spe-power-isa-properties-for-e500v1-plat.patch new file mode 100644 index 00000000000..7efc58bb9bd --- /dev/null +++ b/queue-5.10/powerpc-fix-spe-power-isa-properties-for-e500v1-plat.patch @@ -0,0 +1,150 @@ +From 4500d99366c5764daa7188e8bc3b158f7d36b981 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 23:21:02 +0200 +Subject: powerpc: Fix SPE Power ISA properties for e500v1 platforms +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +[ Upstream commit 37b9345ce7f4ab17538ea62def6f6d430f091355 ] + +Commit 2eb28006431c ("powerpc/e500v2: Add Power ISA properties to comply +with ePAPR 1.1") introduced new include file e500v2_power_isa.dtsi and +should have used it for all e500v2 platforms. But apparently it was used +also for e500v1 platforms mpc8540, mpc8541, mpc8555 and mpc8560. + +e500v1 cores compared to e500v2 do not support double precision floating +point SPE instructions. Hence power-isa-sp.fd should not be set on e500v1 +platforms, which is in e500v2_power_isa.dtsi include file. + +Fix this issue by introducing a new e500v1_power_isa.dtsi include file and +use it in all e500v1 device tree files. + +Fixes: 2eb28006431c ("powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1") +Signed-off-by: Pali Rohár +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20220902212103.22534-1-pali@kernel.org +Signed-off-by: Sasha Levin +--- + .../boot/dts/fsl/e500v1_power_isa.dtsi | 51 +++++++++++++++++++ + arch/powerpc/boot/dts/fsl/mpc8540ads.dts | 2 +- + arch/powerpc/boot/dts/fsl/mpc8541cds.dts | 2 +- + arch/powerpc/boot/dts/fsl/mpc8555cds.dts | 2 +- + arch/powerpc/boot/dts/fsl/mpc8560ads.dts | 2 +- + 5 files changed, 55 insertions(+), 4 deletions(-) + create mode 100644 arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi + +diff --git a/arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi +new file mode 100644 +index 000000000000..7e2a90cde72e +--- /dev/null ++++ b/arch/powerpc/boot/dts/fsl/e500v1_power_isa.dtsi +@@ -0,0 +1,51 @@ ++/* ++ * e500v1 Power ISA Device Tree Source (include) ++ * ++ * Copyright 2012 Freescale Semiconductor Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Freescale Semiconductor nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY ++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/ { ++ cpus { ++ power-isa-version = "2.03"; ++ power-isa-b; // Base ++ power-isa-e; // Embedded ++ power-isa-atb; // Alternate Time Base ++ power-isa-cs; // Cache Specification ++ power-isa-e.le; // Embedded.Little-Endian ++ power-isa-e.pm; // Embedded.Performance Monitor ++ power-isa-ecl; // Embedded Cache Locking ++ power-isa-mmc; // Memory Coherence ++ power-isa-sp; // Signal Processing Engine ++ power-isa-sp.fs; // SPE.Embedded Float Scalar Single ++ power-isa-sp.fv; // SPE.Embedded Float Vector ++ mmu-type = "power-embedded"; ++ }; ++}; +diff --git a/arch/powerpc/boot/dts/fsl/mpc8540ads.dts b/arch/powerpc/boot/dts/fsl/mpc8540ads.dts +index 18a885130538..e03ae130162b 100644 +--- a/arch/powerpc/boot/dts/fsl/mpc8540ads.dts ++++ b/arch/powerpc/boot/dts/fsl/mpc8540ads.dts +@@ -7,7 +7,7 @@ + + /dts-v1/; + +-/include/ "e500v2_power_isa.dtsi" ++/include/ "e500v1_power_isa.dtsi" + + / { + model = "MPC8540ADS"; +diff --git a/arch/powerpc/boot/dts/fsl/mpc8541cds.dts b/arch/powerpc/boot/dts/fsl/mpc8541cds.dts +index ac381e7b1c60..a2a6c5cf852e 100644 +--- a/arch/powerpc/boot/dts/fsl/mpc8541cds.dts ++++ b/arch/powerpc/boot/dts/fsl/mpc8541cds.dts +@@ -7,7 +7,7 @@ + + /dts-v1/; + +-/include/ "e500v2_power_isa.dtsi" ++/include/ "e500v1_power_isa.dtsi" + + / { + model = "MPC8541CDS"; +diff --git a/arch/powerpc/boot/dts/fsl/mpc8555cds.dts b/arch/powerpc/boot/dts/fsl/mpc8555cds.dts +index 9f58db2a7e66..901b6ff06dfb 100644 +--- a/arch/powerpc/boot/dts/fsl/mpc8555cds.dts ++++ b/arch/powerpc/boot/dts/fsl/mpc8555cds.dts +@@ -7,7 +7,7 @@ + + /dts-v1/; + +-/include/ "e500v2_power_isa.dtsi" ++/include/ "e500v1_power_isa.dtsi" + + / { + model = "MPC8555CDS"; +diff --git a/arch/powerpc/boot/dts/fsl/mpc8560ads.dts b/arch/powerpc/boot/dts/fsl/mpc8560ads.dts +index a24722ccaebf..c2f9aea78b29 100644 +--- a/arch/powerpc/boot/dts/fsl/mpc8560ads.dts ++++ b/arch/powerpc/boot/dts/fsl/mpc8560ads.dts +@@ -7,7 +7,7 @@ + + /dts-v1/; + +-/include/ "e500v2_power_isa.dtsi" ++/include/ "e500v1_power_isa.dtsi" + + / { + model = "MPC8560ADS"; +-- +2.35.1 + diff --git a/queue-5.10/powerpc-lib-code-patching-don-t-use-struct-ppc_inst-.patch b/queue-5.10/powerpc-lib-code-patching-don-t-use-struct-ppc_inst-.patch new file mode 100644 index 00000000000..9674972da3e --- /dev/null +++ b/queue-5.10/powerpc-lib-code-patching-don-t-use-struct-ppc_inst-.patch @@ -0,0 +1,206 @@ +From dc4771f7058cd7e5d9fa85c421534d86e6116ee4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 20 May 2021 13:50:44 +0000 +Subject: powerpc/lib/code-patching: Don't use struct 'ppc_inst' for runnable + code in tests. + +From: Christophe Leroy + +[ Upstream commit e90a21ea801d1776d9a786ad02354fd3fe23ce09 ] + +'struct ppc_inst' is meant to represent an instruction internally, it +is not meant to dereference code in memory. + +For testing code patching, use patch_instruction() to properly +write into memory the code to be tested. + +Signed-off-by: Christophe Leroy +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/d8425fb42a4adebc35b7509f121817eeb02fac31.1621516826.git.christophe.leroy@csgroup.eu +Stable-dep-of: 97f88a3d7231 ("powerpc/kprobes: Fix null pointer reference in arch_prepare_kprobe()") +Signed-off-by: Sasha Levin +--- + arch/powerpc/lib/code-patching.c | 95 ++++++++++++++++++-------------- + 1 file changed, 53 insertions(+), 42 deletions(-) + +diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c +index a2e4f864b63d..ba3ccadc1a8c 100644 +--- a/arch/powerpc/lib/code-patching.c ++++ b/arch/powerpc/lib/code-patching.c +@@ -422,9 +422,9 @@ static void __init test_branch_iform(void) + { + int err; + struct ppc_inst instr; +- unsigned long addr; +- +- addr = (unsigned long)&instr; ++ u32 tmp[2]; ++ struct ppc_inst *iptr = (struct ppc_inst *)tmp; ++ unsigned long addr = (unsigned long)tmp; + + /* The simplest case, branch to self, no flags */ + check(instr_is_branch_iform(ppc_inst(0x48000000))); +@@ -445,52 +445,57 @@ static void __init test_branch_iform(void) + check(!instr_is_branch_iform(ppc_inst(0x7bfffffd))); + + /* Absolute branch to 0x100 */ +- instr = ppc_inst(0x48000103); +- check(instr_is_branch_to_addr(&instr, 0x100)); ++ patch_instruction(iptr, ppc_inst(0x48000103)); ++ check(instr_is_branch_to_addr(iptr, 0x100)); + /* Absolute branch to 0x420fc */ +- instr = ppc_inst(0x480420ff); +- check(instr_is_branch_to_addr(&instr, 0x420fc)); ++ patch_instruction(iptr, ppc_inst(0x480420ff)); ++ check(instr_is_branch_to_addr(iptr, 0x420fc)); + /* Maximum positive relative branch, + 20MB - 4B */ +- instr = ppc_inst(0x49fffffc); +- check(instr_is_branch_to_addr(&instr, addr + 0x1FFFFFC)); ++ patch_instruction(iptr, ppc_inst(0x49fffffc)); ++ check(instr_is_branch_to_addr(iptr, addr + 0x1FFFFFC)); + /* Smallest negative relative branch, - 4B */ +- instr = ppc_inst(0x4bfffffc); +- check(instr_is_branch_to_addr(&instr, addr - 4)); ++ patch_instruction(iptr, ppc_inst(0x4bfffffc)); ++ check(instr_is_branch_to_addr(iptr, addr - 4)); + /* Largest negative relative branch, - 32 MB */ +- instr = ppc_inst(0x4a000000); +- check(instr_is_branch_to_addr(&instr, addr - 0x2000000)); ++ patch_instruction(iptr, ppc_inst(0x4a000000)); ++ check(instr_is_branch_to_addr(iptr, addr - 0x2000000)); + + /* Branch to self, with link */ +- err = create_branch(&instr, &instr, addr, BRANCH_SET_LINK); +- check(instr_is_branch_to_addr(&instr, addr)); ++ err = create_branch(&instr, iptr, addr, BRANCH_SET_LINK); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr)); + + /* Branch to self - 0x100, with link */ +- err = create_branch(&instr, &instr, addr - 0x100, BRANCH_SET_LINK); +- check(instr_is_branch_to_addr(&instr, addr - 0x100)); ++ err = create_branch(&instr, iptr, addr - 0x100, BRANCH_SET_LINK); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr - 0x100)); + + /* Branch to self + 0x100, no link */ +- err = create_branch(&instr, &instr, addr + 0x100, 0); +- check(instr_is_branch_to_addr(&instr, addr + 0x100)); ++ err = create_branch(&instr, iptr, addr + 0x100, 0); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr + 0x100)); + + /* Maximum relative negative offset, - 32 MB */ +- err = create_branch(&instr, &instr, addr - 0x2000000, BRANCH_SET_LINK); +- check(instr_is_branch_to_addr(&instr, addr - 0x2000000)); ++ err = create_branch(&instr, iptr, addr - 0x2000000, BRANCH_SET_LINK); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr - 0x2000000)); + + /* Out of range relative negative offset, - 32 MB + 4*/ +- err = create_branch(&instr, &instr, addr - 0x2000004, BRANCH_SET_LINK); ++ err = create_branch(&instr, iptr, addr - 0x2000004, BRANCH_SET_LINK); + check(err); + + /* Out of range relative positive offset, + 32 MB */ +- err = create_branch(&instr, &instr, addr + 0x2000000, BRANCH_SET_LINK); ++ err = create_branch(&instr, iptr, addr + 0x2000000, BRANCH_SET_LINK); + check(err); + + /* Unaligned target */ +- err = create_branch(&instr, &instr, addr + 3, BRANCH_SET_LINK); ++ err = create_branch(&instr, iptr, addr + 3, BRANCH_SET_LINK); + check(err); + + /* Check flags are masked correctly */ +- err = create_branch(&instr, &instr, addr, 0xFFFFFFFC); +- check(instr_is_branch_to_addr(&instr, addr)); ++ err = create_branch(&instr, iptr, addr, 0xFFFFFFFC); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr)); + check(ppc_inst_equal(instr, ppc_inst(0x48000000))); + } + +@@ -513,9 +518,10 @@ static void __init test_branch_bform(void) + int err; + unsigned long addr; + struct ppc_inst *iptr, instr; ++ u32 tmp[2]; + unsigned int flags; + +- iptr = &instr; ++ iptr = (struct ppc_inst *)tmp; + addr = (unsigned long)iptr; + + /* The simplest case, branch to self, no flags */ +@@ -528,39 +534,43 @@ static void __init test_branch_bform(void) + check(!instr_is_branch_bform(ppc_inst(0x7bffffff))); + + /* Absolute conditional branch to 0x100 */ +- instr = ppc_inst(0x43ff0103); +- check(instr_is_branch_to_addr(&instr, 0x100)); ++ patch_instruction(iptr, ppc_inst(0x43ff0103)); ++ check(instr_is_branch_to_addr(iptr, 0x100)); + /* Absolute conditional branch to 0x20fc */ +- instr = ppc_inst(0x43ff20ff); +- check(instr_is_branch_to_addr(&instr, 0x20fc)); ++ patch_instruction(iptr, ppc_inst(0x43ff20ff)); ++ check(instr_is_branch_to_addr(iptr, 0x20fc)); + /* Maximum positive relative conditional branch, + 32 KB - 4B */ +- instr = ppc_inst(0x43ff7ffc); +- check(instr_is_branch_to_addr(&instr, addr + 0x7FFC)); ++ patch_instruction(iptr, ppc_inst(0x43ff7ffc)); ++ check(instr_is_branch_to_addr(iptr, addr + 0x7FFC)); + /* Smallest negative relative conditional branch, - 4B */ +- instr = ppc_inst(0x43fffffc); +- check(instr_is_branch_to_addr(&instr, addr - 4)); ++ patch_instruction(iptr, ppc_inst(0x43fffffc)); ++ check(instr_is_branch_to_addr(iptr, addr - 4)); + /* Largest negative relative conditional branch, - 32 KB */ +- instr = ppc_inst(0x43ff8000); +- check(instr_is_branch_to_addr(&instr, addr - 0x8000)); ++ patch_instruction(iptr, ppc_inst(0x43ff8000)); ++ check(instr_is_branch_to_addr(iptr, addr - 0x8000)); + + /* All condition code bits set & link */ + flags = 0x3ff000 | BRANCH_SET_LINK; + + /* Branch to self */ + err = create_cond_branch(&instr, iptr, addr, flags); +- check(instr_is_branch_to_addr(&instr, addr)); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr)); + + /* Branch to self - 0x100 */ + err = create_cond_branch(&instr, iptr, addr - 0x100, flags); +- check(instr_is_branch_to_addr(&instr, addr - 0x100)); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr - 0x100)); + + /* Branch to self + 0x100 */ + err = create_cond_branch(&instr, iptr, addr + 0x100, flags); +- check(instr_is_branch_to_addr(&instr, addr + 0x100)); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr + 0x100)); + + /* Maximum relative negative offset, - 32 KB */ + err = create_cond_branch(&instr, iptr, addr - 0x8000, flags); +- check(instr_is_branch_to_addr(&instr, addr - 0x8000)); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr - 0x8000)); + + /* Out of range relative negative offset, - 32 KB + 4*/ + err = create_cond_branch(&instr, iptr, addr - 0x8004, flags); +@@ -576,7 +586,8 @@ static void __init test_branch_bform(void) + + /* Check flags are masked correctly */ + err = create_cond_branch(&instr, iptr, addr, 0xFFFFFFFC); +- check(instr_is_branch_to_addr(&instr, addr)); ++ patch_instruction(iptr, instr); ++ check(instr_is_branch_to_addr(iptr, addr)); + check(ppc_inst_equal(instr, ppc_inst(0x43FF0000))); + } + +-- +2.35.1 + diff --git a/queue-5.10/powerpc-math_emu-efp-include-module.h.patch b/queue-5.10/powerpc-math_emu-efp-include-module.h.patch new file mode 100644 index 00000000000..785a7533778 --- /dev/null +++ b/queue-5.10/powerpc-math_emu-efp-include-module.h.patch @@ -0,0 +1,53 @@ +From e2745688fa49508407519439c32f844411d0c64d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 18:00:08 +0200 +Subject: powerpc/math_emu/efp: Include module.h + +From: Nathan Chancellor + +[ Upstream commit cfe0d370e0788625ce0df3239aad07a2506c1796 ] + +When building with a recent version of clang, there are a couple of +errors around the call to module_init(): + + arch/powerpc/math-emu/math_efp.c:927:1: error: type specifier missing, defaults to 'int'; ISO C99 and later do not support implicit int [-Wimplicit-int] + module_init(spe_mathemu_init); + ^ + int + arch/powerpc/math-emu/math_efp.c:927:13: error: a parameter list without types is only allowed in a function definition + module_init(spe_mathemu_init); + ^ + 2 errors generated. + +module_init() is a macro, which is not getting expanded because module.h +is not included in this file. Add the include so that the macro can +expand properly, clearing up the build failure. + +Fixes: ac6f120369ff ("powerpc/85xx: Workaroudn e500 CPU erratum A005") +[chleroy: added fixes tag] +Reported-by: kernel test robot +Signed-off-by: Nathan Chancellor +Signed-off-by: Christophe Leroy +Signed-off-by: Michael Ellerman +Reviewed-by: Christophe Leroy +Link: https://lore.kernel.org/r/8403854a4c187459b2f4da3537f51227b70b9223.1662134272.git.christophe.leroy@csgroup.eu +Signed-off-by: Sasha Levin +--- + arch/powerpc/math-emu/math_efp.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c +index 0a05e51964c1..90111c9e7521 100644 +--- a/arch/powerpc/math-emu/math_efp.c ++++ b/arch/powerpc/math-emu/math_efp.c +@@ -17,6 +17,7 @@ + + #include + #include ++#include + + #include + #include +-- +2.35.1 + diff --git a/queue-5.10/powerpc-pci_dn-add-missing-of_node_put.patch b/queue-5.10/powerpc-pci_dn-add-missing-of_node_put.patch new file mode 100644 index 00000000000..d282ce20bb9 --- /dev/null +++ b/queue-5.10/powerpc-pci_dn-add-missing-of_node_put.patch @@ -0,0 +1,38 @@ +From 22a7ba78b86e82a8d5522335ad7ca6965e2ac741 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 1 Jul 2022 21:17:50 +0800 +Subject: powerpc/pci_dn: Add missing of_node_put() + +From: Liang He + +[ Upstream commit 110a1fcb6c4d55144d8179983a475f17a1d6f832 ] + +In pci_add_device_node_info(), use of_node_put() to drop the reference +to 'parent' returned by of_get_parent() to keep refcount balance. + +Fixes: cca87d303c85 ("powerpc/pci: Refactor pci_dn") +Co-authored-by: Miaoqian Lin +Signed-off-by: Liang He +Signed-off-by: Michael Ellerman +Reviewed-by: Tyrel Datwyler +Link: https://lore.kernel.org/r/20220701131750.240170-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/kernel/pci_dn.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c +index e99b7c547d7e..b173ba342645 100644 +--- a/arch/powerpc/kernel/pci_dn.c ++++ b/arch/powerpc/kernel/pci_dn.c +@@ -330,6 +330,7 @@ struct pci_dn *pci_add_device_node_info(struct pci_controller *hose, + INIT_LIST_HEAD(&pdn->list); + parent = of_get_parent(dn); + pdn->parent = parent ? PCI_DN(parent) : NULL; ++ of_node_put(parent); + if (pdn->parent) + list_add_tail(&pdn->list, &pdn->parent->child_list); + +-- +2.35.1 + diff --git a/queue-5.10/powerpc-powernv-add-missing-of_node_put-in-opal_expo.patch b/queue-5.10/powerpc-powernv-add-missing-of_node_put-in-opal_expo.patch new file mode 100644 index 00000000000..c0d60e51cdc --- /dev/null +++ b/queue-5.10/powerpc-powernv-add-missing-of_node_put-in-opal_expo.patch @@ -0,0 +1,36 @@ +From d6088717d2970dcabaf536cb290a05b909ddd316 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 14:17:03 +0000 +Subject: powerpc/powernv: add missing of_node_put() in opal_export_attrs() + +From: Zheng Yongjun + +[ Upstream commit 71a92e99c47900cc164620948b3863382cec4f1a ] + +After using 'np' returned by of_find_node_by_path(), of_node_put() +need be called to decrease the refcount. + +Fixes: 11fe909d2362 ("powerpc/powernv: Add OPAL exports attributes to sysfs") +Signed-off-by: Zheng Yongjun +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20220906141703.118192-1-zhengyongjun3@huawei.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/platforms/powernv/opal.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c +index c61c3b62c8c6..1d05c168c8fb 100644 +--- a/arch/powerpc/platforms/powernv/opal.c ++++ b/arch/powerpc/platforms/powernv/opal.c +@@ -892,6 +892,7 @@ static void opal_export_attrs(void) + kobj = kobject_create_and_add("exports", opal_kobj); + if (!kobj) { + pr_warn("kobject_create_and_add() of exports failed\n"); ++ of_node_put(np); + return; + } + +-- +2.35.1 + diff --git a/queue-5.10/powerpc-sysdev-fsl_msi-add-missing-of_node_put.patch b/queue-5.10/powerpc-sysdev-fsl_msi-add-missing-of_node_put.patch new file mode 100644 index 00000000000..45a13d66462 --- /dev/null +++ b/queue-5.10/powerpc-sysdev-fsl_msi-add-missing-of_node_put.patch @@ -0,0 +1,40 @@ +From eaa8761345d5daefe5bf1d19a5ce8f101461d7c6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Jul 2022 22:52:33 +0800 +Subject: powerpc/sysdev/fsl_msi: Add missing of_node_put() + +From: Liang He + +[ Upstream commit def435c04ee984a5f9ed2711b2bfe946936c6a21 ] + +In fsl_setup_msi_irqs(), use of_node_put() to drop the reference +returned by of_parse_phandle(). + +Fixes: 895d603f945ba ("powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes") +Co-authored-by: Miaoqian Lin +Signed-off-by: Liang He +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20220704145233.278539-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/sysdev/fsl_msi.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c +index 808e7118abfc..d276c5e96445 100644 +--- a/arch/powerpc/sysdev/fsl_msi.c ++++ b/arch/powerpc/sysdev/fsl_msi.c +@@ -211,8 +211,10 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) + dev_err(&pdev->dev, + "node %pOF has an invalid fsl,msi phandle %u\n", + hose->dn, np->phandle); ++ of_node_put(np); + return -EINVAL; + } ++ of_node_put(np); + } + + for_each_pci_msi_entry(entry, pdev) { +-- +2.35.1 + diff --git a/queue-5.10/r8152-rate-limit-overflow-messages.patch b/queue-5.10/r8152-rate-limit-overflow-messages.patch new file mode 100644 index 00000000000..3f1dd4cceca --- /dev/null +++ b/queue-5.10/r8152-rate-limit-overflow-messages.patch @@ -0,0 +1,38 @@ +From 8c1d990b2e4b1869512304e458c55396ca0ab338 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 2 Oct 2022 12:41:28 +0900 +Subject: r8152: Rate limit overflow messages + +From: Andrew Gaul + +[ Upstream commit 93e2be344a7db169b7119de21ac1bf253b8c6907 ] + +My system shows almost 10 million of these messages over a 24-hour +period which pollutes my logs. + +Signed-off-by: Andrew Gaul +Link: https://lore.kernel.org/r/20221002034128.2026653-1-gaul@google.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/usb/r8152.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index 0bb5b1c78654..a526242a3e36 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -1689,7 +1689,9 @@ static void intr_callback(struct urb *urb) + "Stop submitting intr, status %d\n", status); + return; + case -EOVERFLOW: +- netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); ++ if (net_ratelimit()) ++ netif_info(tp, intr, tp->netdev, ++ "intr status -EOVERFLOW\n"); + goto resubmit; + /* -EPIPE: should clear the halt */ + default: +-- +2.35.1 + diff --git a/queue-5.10/rcu-back-off-upon-fill_page_cache_func-allocation-fa.patch b/queue-5.10/rcu-back-off-upon-fill_page_cache_func-allocation-fa.patch new file mode 100644 index 00000000000..11f9f35e201 --- /dev/null +++ b/queue-5.10/rcu-back-off-upon-fill_page_cache_func-allocation-fa.patch @@ -0,0 +1,89 @@ +From 6afa54c4a608ca9e21a9a4c99c5793d400768489 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 13:47:11 +0200 +Subject: rcu: Back off upon fill_page_cache_func() allocation failure + +From: Michal Hocko + +[ Upstream commit 093590c16b447f53e66771c8579ae66c96f6ef61 ] + +The fill_page_cache_func() function allocates couple of pages to store +kvfree_rcu_bulk_data structures. This is a lightweight (GFP_NORETRY) +allocation which can fail under memory pressure. The function will, +however keep retrying even when the previous attempt has failed. + +This retrying is in theory correct, but in practice the allocation is +invoked from workqueue context, which means that if the memory reclaim +gets stuck, these retries can hog the worker for quite some time. +Although the workqueues subsystem automatically adjusts concurrency, such +adjustment is not guaranteed to happen until the worker context sleeps. +And the fill_page_cache_func() function's retry loop is not guaranteed +to sleep (see the should_reclaim_retry() function). + +And we have seen this function cause workqueue lockups: + +kernel: BUG: workqueue lockup - pool cpus=93 node=1 flags=0x1 nice=0 stuck for 32s! +[...] +kernel: pool 74: cpus=37 node=0 flags=0x1 nice=0 hung=32s workers=2 manager: 2146 +kernel: pwq 498: cpus=249 node=1 flags=0x1 nice=0 active=4/256 refcnt=5 +kernel: in-flight: 1917:fill_page_cache_func +kernel: pending: dbs_work_handler, free_work, kfree_rcu_monitor + +Originally, we thought that the root cause of this lockup was several +retries with direct reclaim, but this is not yet confirmed. Furthermore, +we have seen similar lockups without any heavy memory pressure. This +suggests that there are other factors contributing to these lockups. +However, it is not really clear that endless retries are desireable. + +So let's make the fill_page_cache_func() function back off after +allocation failure. + +Cc: Uladzislau Rezki (Sony) +Cc: "Paul E. McKenney" +Cc: Frederic Weisbecker +Cc: Neeraj Upadhyay +Cc: Josh Triplett +Cc: Steven Rostedt +Cc: Mathieu Desnoyers +Cc: Lai Jiangshan +Cc: Joel Fernandes +Signed-off-by: Michal Hocko +Reviewed-by: Uladzislau Rezki (Sony) +Signed-off-by: Paul E. McKenney +Signed-off-by: Sasha Levin +--- + kernel/rcu/tree.c | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c +index b41009a283ca..b10d6bcea77d 100644 +--- a/kernel/rcu/tree.c ++++ b/kernel/rcu/tree.c +@@ -3393,15 +3393,16 @@ static void fill_page_cache_func(struct work_struct *work) + bnode = (struct kvfree_rcu_bulk_data *) + __get_free_page(GFP_KERNEL | __GFP_NORETRY | __GFP_NOMEMALLOC | __GFP_NOWARN); + +- if (bnode) { +- raw_spin_lock_irqsave(&krcp->lock, flags); +- pushed = put_cached_bnode(krcp, bnode); +- raw_spin_unlock_irqrestore(&krcp->lock, flags); ++ if (!bnode) ++ break; + +- if (!pushed) { +- free_page((unsigned long) bnode); +- break; +- } ++ raw_spin_lock_irqsave(&krcp->lock, flags); ++ pushed = put_cached_bnode(krcp, bnode); ++ raw_spin_unlock_irqrestore(&krcp->lock, flags); ++ ++ if (!pushed) { ++ free_page((unsigned long) bnode); ++ break; + } + } + +-- +2.35.1 + diff --git a/queue-5.10/rcu-tasks-convert-rcu_lockdep_warn-to-warn_once.patch b/queue-5.10/rcu-tasks-convert-rcu_lockdep_warn-to-warn_once.patch new file mode 100644 index 00000000000..a0450d4971b --- /dev/null +++ b/queue-5.10/rcu-tasks-convert-rcu_lockdep_warn-to-warn_once.patch @@ -0,0 +1,43 @@ +From 8ed20dbb29c4aeb8634d1db71d60f19e20d544a3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 12 Jul 2022 16:26:05 +0800 +Subject: rcu-tasks: Convert RCU_LOCKDEP_WARN() to WARN_ONCE() + +From: Zqiang + +[ Upstream commit fcd53c8a4dfa38bafb89efdd0b0f718f3a03f884 ] + +Kernels built with CONFIG_PROVE_RCU=y and CONFIG_DEBUG_LOCK_ALLOC=y +attempt to emit a warning when the synchronize_rcu_tasks_generic() +function is called during early boot while the rcu_scheduler_active +variable is RCU_SCHEDULER_INACTIVE. However the warnings is not +actually be printed because the debug_lockdep_rcu_enabled() returns +false, exactly because the rcu_scheduler_active variable is still equal +to RCU_SCHEDULER_INACTIVE. + +This commit therefore replaces RCU_LOCKDEP_WARN() with WARN_ONCE() +to force these warnings to actually be printed. + +Signed-off-by: Zqiang +Signed-off-by: Paul E. McKenney +Signed-off-by: Sasha Levin +--- + kernel/rcu/tasks.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h +index 14af29fe1377..8b51e6a5b386 100644 +--- a/kernel/rcu/tasks.h ++++ b/kernel/rcu/tasks.h +@@ -171,7 +171,7 @@ static void call_rcu_tasks_generic(struct rcu_head *rhp, rcu_callback_t func, + static void synchronize_rcu_tasks_generic(struct rcu_tasks *rtp) + { + /* Complain if the scheduler has not started. */ +- RCU_LOCKDEP_WARN(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE, ++ WARN_ONCE(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE, + "synchronize_rcu_tasks called too soon"); + + /* Wait for the grace period. */ +-- +2.35.1 + diff --git a/queue-5.10/rdma-cm-use-slid-in-the-work-completion-as-the-dlid-.patch b/queue-5.10/rdma-cm-use-slid-in-the-work-completion-as-the-dlid-.patch new file mode 100644 index 00000000000..45c2d2dce51 --- /dev/null +++ b/queue-5.10/rdma-cm-use-slid-in-the-work-completion-as-the-dlid-.patch @@ -0,0 +1,80 @@ +From ed2b2d19cf0f7ff912464ac0a17fdcdfe66031f0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 13:09:02 +0300 +Subject: RDMA/cm: Use SLID in the work completion as the DLID in responder + side + +From: Mark Zhang + +[ Upstream commit b7d95040c13f61a4a6a859c5355faf583eff9658 ] + +The responder should always use WC's SLID as the dlid, to follow the +IB SPEC section "13.5.4.2 COMMON RESPONSE ACTIONS": +A responder always takes the following actions in constructing a +response packet: +- The SLID of the received packet is used as the DLID in the response + packet. + +Fixes: ac3a949fb2ff ("IB/CM: Set appropriate slid and dlid when handling CM request") +Signed-off-by: Mark Zhang +Reviewed-by: Mark Bloch +Link: https://lore.kernel.org/r/cd17c240231e059d2fc07c17dfe555d548b917eb.1662631201.git.leonro@nvidia.com +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/core/cm.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c +index 3cc7a23fa69f..3133b6be6cab 100644 +--- a/drivers/infiniband/core/cm.c ++++ b/drivers/infiniband/core/cm.c +@@ -1643,14 +1643,13 @@ static void cm_path_set_rec_type(struct ib_device *ib_device, u8 port_num, + + static void cm_format_path_lid_from_req(struct cm_req_msg *req_msg, + struct sa_path_rec *primary_path, +- struct sa_path_rec *alt_path) ++ struct sa_path_rec *alt_path, ++ struct ib_wc *wc) + { + u32 lid; + + if (primary_path->rec_type != SA_PATH_REC_TYPE_OPA) { +- sa_path_set_dlid(primary_path, +- IBA_GET(CM_REQ_PRIMARY_LOCAL_PORT_LID, +- req_msg)); ++ sa_path_set_dlid(primary_path, wc->slid); + sa_path_set_slid(primary_path, + IBA_GET(CM_REQ_PRIMARY_REMOTE_PORT_LID, + req_msg)); +@@ -1687,7 +1686,8 @@ static void cm_format_path_lid_from_req(struct cm_req_msg *req_msg, + + static void cm_format_paths_from_req(struct cm_req_msg *req_msg, + struct sa_path_rec *primary_path, +- struct sa_path_rec *alt_path) ++ struct sa_path_rec *alt_path, ++ struct ib_wc *wc) + { + primary_path->dgid = + *IBA_GET_MEM_PTR(CM_REQ_PRIMARY_LOCAL_PORT_GID, req_msg); +@@ -1745,7 +1745,7 @@ static void cm_format_paths_from_req(struct cm_req_msg *req_msg, + if (sa_path_is_roce(alt_path)) + alt_path->roce.route_resolved = false; + } +- cm_format_path_lid_from_req(req_msg, primary_path, alt_path); ++ cm_format_path_lid_from_req(req_msg, primary_path, alt_path, wc); + } + + static u16 cm_get_bth_pkey(struct cm_work *work) +@@ -2163,7 +2163,7 @@ static int cm_req_handler(struct cm_work *work) + if (cm_req_has_alt_path(req_msg)) + work->path[1].rec_type = work->path[0].rec_type; + cm_format_paths_from_req(req_msg, &work->path[0], +- &work->path[1]); ++ &work->path[1], work->mad_recv_wc->wc); + if (cm_id_priv->av.ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE) + sa_path_set_dmac(&work->path[0], + cm_id_priv->av.ah_attr.roce.dmac); +-- +2.35.1 + diff --git a/queue-5.10/rdma-rdmavt-decouple-qp-and-sge-lists-allocations.patch b/queue-5.10/rdma-rdmavt-decouple-qp-and-sge-lists-allocations.patch new file mode 100644 index 00000000000..c0552e6e637 --- /dev/null +++ b/queue-5.10/rdma-rdmavt-decouple-qp-and-sge-lists-allocations.patch @@ -0,0 +1,100 @@ +From c9869aacea83c0fd66a5d3861130dfbf57d30b73 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 23 Jul 2021 14:39:49 +0300 +Subject: RDMA/rdmavt: Decouple QP and SGE lists allocations + +From: Leon Romanovsky + +[ Upstream commit 44da3730e046a784d088157175d9418ba60661fc ] + +The rdmavt QP has fields that are both needed for the control and data +path. Such mixed declaration caused to the very specific allocation flow +with kzalloc_node and SGE list embedded into the struct rvt_qp. + +This patch separates QP creation to two: regular memory allocation for the +control path and specific code for the SGE list, while the access to the +later is performed through derefenced pointer. + +Such pointer and its context are expected to be in the cache, so +performance difference is expected to be negligible, if any exists. + +Link: https://lore.kernel.org/r/f66c1e20ccefba0db3c69c58ca9c897f062b4d1c.1627040189.git.leonro@nvidia.com +Signed-off-by: Leon Romanovsky +Signed-off-by: Jason Gunthorpe +Stable-dep-of: a3c278807a45 ("RDMA/siw: Fix QP destroy to wait for all references dropped.") +Signed-off-by: Sasha Levin +--- + drivers/infiniband/sw/rdmavt/qp.c | 13 ++++++++----- + include/rdma/rdmavt_qp.h | 2 +- + 2 files changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/infiniband/sw/rdmavt/qp.c b/drivers/infiniband/sw/rdmavt/qp.c +index 585a9c76e518..5d300f25ef87 100644 +--- a/drivers/infiniband/sw/rdmavt/qp.c ++++ b/drivers/infiniband/sw/rdmavt/qp.c +@@ -1073,7 +1073,7 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd, + int err; + struct rvt_swqe *swq = NULL; + size_t sz; +- size_t sg_list_sz; ++ size_t sg_list_sz = 0; + struct ib_qp *ret = ERR_PTR(-ENOMEM); + struct rvt_dev_info *rdi = ib_to_rvt(ibpd->device); + void *priv = NULL; +@@ -1120,8 +1120,6 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd, + if (!swq) + return ERR_PTR(-ENOMEM); + +- sz = sizeof(*qp); +- sg_list_sz = 0; + if (init_attr->srq) { + struct rvt_srq *srq = ibsrq_to_rvtsrq(init_attr->srq); + +@@ -1131,10 +1129,13 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd, + } else if (init_attr->cap.max_recv_sge > 1) + sg_list_sz = sizeof(*qp->r_sg_list) * + (init_attr->cap.max_recv_sge - 1); +- qp = kzalloc_node(sz + sg_list_sz, GFP_KERNEL, +- rdi->dparms.node); ++ qp = kzalloc_node(sizeof(*qp), GFP_KERNEL, rdi->dparms.node); + if (!qp) + goto bail_swq; ++ qp->r_sg_list = ++ kzalloc_node(sg_list_sz, GFP_KERNEL, rdi->dparms.node); ++ if (!qp->r_sg_list) ++ goto bail_qp; + qp->allowed_ops = get_allowed_ops(init_attr->qp_type); + + RCU_INIT_POINTER(qp->next, NULL); +@@ -1322,6 +1323,7 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd, + + bail_qp: + kfree(qp->s_ack_queue); ++ kfree(qp->r_sg_list); + kfree(qp); + + bail_swq: +@@ -1752,6 +1754,7 @@ int rvt_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) + kvfree(qp->r_rq.kwq); + rdi->driver_f.qp_priv_free(rdi, qp); + kfree(qp->s_ack_queue); ++ kfree(qp->r_sg_list); + rdma_destroy_ah_attr(&qp->remote_ah_attr); + rdma_destroy_ah_attr(&qp->alt_ah_attr); + free_ud_wq_attr(qp); +diff --git a/include/rdma/rdmavt_qp.h b/include/rdma/rdmavt_qp.h +index 8275954f5ce6..2e58d5e6ac0e 100644 +--- a/include/rdma/rdmavt_qp.h ++++ b/include/rdma/rdmavt_qp.h +@@ -444,7 +444,7 @@ struct rvt_qp { + /* + * This sge list MUST be last. Do not add anything below here. + */ +- struct rvt_sge r_sg_list[] /* verified SGEs */ ++ struct rvt_sge *r_sg_list /* verified SGEs */ + ____cacheline_aligned_in_smp; + }; + +-- +2.35.1 + diff --git a/queue-5.10/rdma-rxe-fix-kernel-null-pointer-dereference-error.patch b/queue-5.10/rdma-rxe-fix-kernel-null-pointer-dereference-error.patch new file mode 100644 index 00000000000..e08e3770dff --- /dev/null +++ b/queue-5.10/rdma-rxe-fix-kernel-null-pointer-dereference-error.patch @@ -0,0 +1,48 @@ +From 326f7d7c91ef63b366abda8678aeeea9914e3364 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 21 Aug 2022 21:16:13 -0400 +Subject: RDMA/rxe: Fix "kernel NULL pointer dereference" error + +From: Zhu Yanjun + +[ Upstream commit a625ca30eff806395175ebad3ac1399014bdb280 ] + +When rxe_queue_init in the function rxe_qp_init_req fails, +both qp->req.task.func and qp->req.task.arg are not initialized. + +Because of creation of qp fails, the function rxe_create_qp will +call rxe_qp_do_cleanup to handle allocated resource. + +Before calling __rxe_do_task, both qp->req.task.func and +qp->req.task.arg should be checked. + +Fixes: 8700e3e7c485 ("Soft RoCE driver") +Link: https://lore.kernel.org/r/20220822011615.805603-2-yanjun.zhu@linux.dev +Reported-by: syzbot+ab99dc4c6e961eed8b8e@syzkaller.appspotmail.com +Signed-off-by: Zhu Yanjun +Reviewed-by: Li Zhijian +Reviewed-by: Bob Pearson +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/sw/rxe/rxe_qp.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c +index 2847ab4d9a5f..6acef6e923de 100644 +--- a/drivers/infiniband/sw/rxe/rxe_qp.c ++++ b/drivers/infiniband/sw/rxe/rxe_qp.c +@@ -775,7 +775,9 @@ void rxe_qp_destroy(struct rxe_qp *qp) + rxe_cleanup_task(&qp->comp.task); + + /* flush out any receive wr's or pending requests */ +- __rxe_do_task(&qp->req.task); ++ if (qp->req.task.func) ++ __rxe_do_task(&qp->req.task); ++ + if (qp->sq.queue) { + __rxe_do_task(&qp->comp.task); + __rxe_do_task(&qp->req.task); +-- +2.35.1 + diff --git a/queue-5.10/rdma-rxe-fix-the-error-caused-by-qp-sk.patch b/queue-5.10/rdma-rxe-fix-the-error-caused-by-qp-sk.patch new file mode 100644 index 00000000000..85ac3ac6933 --- /dev/null +++ b/queue-5.10/rdma-rxe-fix-the-error-caused-by-qp-sk.patch @@ -0,0 +1,48 @@ +From 6ccd8104742eb6747dd801b4e31e118f372d934b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 21 Aug 2022 21:16:14 -0400 +Subject: RDMA/rxe: Fix the error caused by qp->sk + +From: Zhu Yanjun + +[ Upstream commit 548ce2e66725dcba4e27d1e8ac468d5dd17fd509 ] + +When sock_create_kern in the function rxe_qp_init_req fails, +qp->sk is set to NULL. + +Then the function rxe_create_qp will call rxe_qp_do_cleanup +to handle allocated resource. + +Before handling qp->sk, this variable should be checked. + +Fixes: 8700e3e7c485 ("Soft RoCE driver") +Link: https://lore.kernel.org/r/20220822011615.805603-3-yanjun.zhu@linux.dev +Signed-off-by: Zhu Yanjun +Reviewed-by: Li Zhijian +Reviewed-by: Bob Pearson +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/sw/rxe/rxe_qp.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c +index 6acef6e923de..2e4b008f0387 100644 +--- a/drivers/infiniband/sw/rxe/rxe_qp.c ++++ b/drivers/infiniband/sw/rxe/rxe_qp.c +@@ -817,8 +817,10 @@ static void rxe_qp_do_cleanup(struct work_struct *work) + + free_rd_atomic_resources(qp); + +- kernel_sock_shutdown(qp->sk, SHUT_RDWR); +- sock_release(qp->sk); ++ if (qp->sk) { ++ kernel_sock_shutdown(qp->sk, SHUT_RDWR); ++ sock_release(qp->sk); ++ } + } + + /* called when the last reference to the qp is dropped */ +-- +2.35.1 + diff --git a/queue-5.10/rdma-siw-always-consume-all-skbuf-data-in-sk_data_re.patch b/queue-5.10/rdma-siw-always-consume-all-skbuf-data-in-sk_data_re.patch new file mode 100644 index 00000000000..cb62ce8a325 --- /dev/null +++ b/queue-5.10/rdma-siw-always-consume-all-skbuf-data-in-sk_data_re.patch @@ -0,0 +1,99 @@ +From 5f89be1d18980d565b0f63415f09c4028e990073 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 10:12:02 +0200 +Subject: RDMA/siw: Always consume all skbuf data in sk_data_ready() upcall. + +From: Bernard Metzler + +[ Upstream commit 754209850df8367c954ac1de7671c7430b1f342c ] + +For header and trailer/padding processing, siw did not consume new +skb data until minimum amount present to fill current header or trailer +structure, including potential payload padding. Not consuming any +data during upcall may cause a receive stall, since tcp_read_sock() +is not upcalling again if no new data arrive. +A NFSoRDMA client got stuck at RDMA Write reception of unaligned +payload, if the current skb did contain only the expected 3 padding +bytes, but not the 4 bytes CRC trailer. Expecting 4 more bytes already +arrived in another skb, and not consuming those 3 bytes in the current +upcall left the Write incomplete, waiting for the CRC forever. + +Fixes: 8b6a361b8c48 ("rdma/siw: receive path") +Reported-by: Olga Kornievskaia +Tested-by: Olga Kornievskaia +Signed-off-by: Bernard Metzler +Link: https://lore.kernel.org/r/20220920081202.223629-1-bmt@zurich.ibm.com +Signed-off-by: Leon Romanovsky +Signed-off-by: Sasha Levin +--- + drivers/infiniband/sw/siw/siw_qp_rx.c | 27 +++++++++++++++------------ + 1 file changed, 15 insertions(+), 12 deletions(-) + +diff --git a/drivers/infiniband/sw/siw/siw_qp_rx.c b/drivers/infiniband/sw/siw/siw_qp_rx.c +index 875ea6f1b04a..fd721cc19682 100644 +--- a/drivers/infiniband/sw/siw/siw_qp_rx.c ++++ b/drivers/infiniband/sw/siw/siw_qp_rx.c +@@ -961,27 +961,28 @@ int siw_proc_terminate(struct siw_qp *qp) + static int siw_get_trailer(struct siw_qp *qp, struct siw_rx_stream *srx) + { + struct sk_buff *skb = srx->skb; ++ int avail = min(srx->skb_new, srx->fpdu_part_rem); + u8 *tbuf = (u8 *)&srx->trailer.crc - srx->pad; + __wsum crc_in, crc_own = 0; + + siw_dbg_qp(qp, "expected %d, available %d, pad %u\n", + srx->fpdu_part_rem, srx->skb_new, srx->pad); + +- if (srx->skb_new < srx->fpdu_part_rem) +- return -EAGAIN; +- +- skb_copy_bits(skb, srx->skb_offset, tbuf, srx->fpdu_part_rem); ++ skb_copy_bits(skb, srx->skb_offset, tbuf, avail); + +- if (srx->mpa_crc_hd && srx->pad) +- crypto_shash_update(srx->mpa_crc_hd, tbuf, srx->pad); ++ srx->skb_new -= avail; ++ srx->skb_offset += avail; ++ srx->skb_copied += avail; ++ srx->fpdu_part_rem -= avail; + +- srx->skb_new -= srx->fpdu_part_rem; +- srx->skb_offset += srx->fpdu_part_rem; +- srx->skb_copied += srx->fpdu_part_rem; ++ if (srx->fpdu_part_rem) ++ return -EAGAIN; + + if (!srx->mpa_crc_hd) + return 0; + ++ if (srx->pad) ++ crypto_shash_update(srx->mpa_crc_hd, tbuf, srx->pad); + /* + * CRC32 is computed, transmitted and received directly in NBO, + * so there's never a reason to convert byte order. +@@ -1083,10 +1084,9 @@ static int siw_get_hdr(struct siw_rx_stream *srx) + * completely received. + */ + if (iwarp_pktinfo[opcode].hdr_len > sizeof(struct iwarp_ctrl_tagged)) { +- bytes = iwarp_pktinfo[opcode].hdr_len - MIN_DDP_HDR; ++ int hdrlen = iwarp_pktinfo[opcode].hdr_len; + +- if (srx->skb_new < bytes) +- return -EAGAIN; ++ bytes = min_t(int, hdrlen - MIN_DDP_HDR, srx->skb_new); + + skb_copy_bits(skb, srx->skb_offset, + (char *)c_hdr + srx->fpdu_part_rcvd, bytes); +@@ -1096,6 +1096,9 @@ static int siw_get_hdr(struct siw_rx_stream *srx) + srx->skb_new -= bytes; + srx->skb_offset += bytes; + srx->skb_copied += bytes; ++ ++ if (srx->fpdu_part_rcvd < hdrlen) ++ return -EAGAIN; + } + + /* +-- +2.35.1 + diff --git a/queue-5.10/rdma-uverbs-allow-drivers-to-create-a-new-hw-object-.patch b/queue-5.10/rdma-uverbs-allow-drivers-to-create-a-new-hw-object-.patch new file mode 100644 index 00000000000..7ef4cfbf426 --- /dev/null +++ b/queue-5.10/rdma-uverbs-allow-drivers-to-create-a-new-hw-object-.patch @@ -0,0 +1,478 @@ +From 25cc7b8e45206edf688501b4f5ebf66a2187b120 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Nov 2020 09:58:37 +0200 +Subject: RDMA/uverbs: Allow drivers to create a new HW object during rereg_mr + +From: Jason Gunthorpe + +[ Upstream commit 6e0954b11c056570cb29676a84e2f8dc4d1dd05e ] + +mlx5 has an ugly flow where it tries to allocate a new MR and replace the +existing MR in the same memory during rereg. This is very complicated and +buggy. Instead of trying to replace in-place inside the driver, provide +support from uverbs to change the entire HW object assigned to a handle +during rereg_mr. + +Since destroying a MR is allowed to fail (ie if a MW is pointing at it) +and can't be detected in advance, the algorithm creates a completely new +uobject to hold the new MR and swaps the IDR entries of the two objects. + +The old MR in the temporary IDR entry is destroyed, and if it fails +rereg_mr succeeds and destruction is deferred to FD release. This +complexity is why this cannot live in a driver safely. + +Link: https://lore.kernel.org/r/20201130075839.278575-4-leon@kernel.org +Signed-off-by: Leon Romanovsky +Signed-off-by: Jason Gunthorpe +Stable-dep-of: 241f9a27e0fc ("IB: Set IOVA/LENGTH on IB_MR in core/uverbs layers") +Signed-off-by: Sasha Levin +--- + drivers/infiniband/core/rdma_core.c | 51 +++++++++++++ + drivers/infiniband/core/uverbs_cmd.c | 85 ++++++++++++++++----- + drivers/infiniband/hw/hns/hns_roce_device.h | 7 +- + drivers/infiniband/hw/hns/hns_roce_mr.c | 15 ++-- + drivers/infiniband/hw/mlx4/mlx4_ib.h | 8 +- + drivers/infiniband/hw/mlx4/mr.c | 16 ++-- + drivers/infiniband/hw/mlx5/mlx5_ib.h | 6 +- + drivers/infiniband/hw/mlx5/mr.c | 15 ++-- + include/rdma/ib_verbs.h | 7 +- + include/rdma/uverbs_types.h | 5 ++ + 10 files changed, 160 insertions(+), 55 deletions(-) + +diff --git a/drivers/infiniband/core/rdma_core.c b/drivers/infiniband/core/rdma_core.c +index ffe11b03724c..ff45c5f9697e 100644 +--- a/drivers/infiniband/core/rdma_core.c ++++ b/drivers/infiniband/core/rdma_core.c +@@ -609,6 +609,27 @@ static void alloc_commit_idr_uobject(struct ib_uobject *uobj) + WARN_ON(old != NULL); + } + ++static void swap_idr_uobjects(struct ib_uobject *obj_old, ++ struct ib_uobject *obj_new) ++{ ++ struct ib_uverbs_file *ufile = obj_old->ufile; ++ void *old; ++ ++ /* ++ * New must be an object that been allocated but not yet committed, this ++ * moves the pre-committed state to obj_old, new still must be comitted. ++ */ ++ old = xa_cmpxchg(&ufile->idr, obj_old->id, obj_old, XA_ZERO_ENTRY, ++ GFP_KERNEL); ++ if (WARN_ON(old != obj_old)) ++ return; ++ ++ swap(obj_old->id, obj_new->id); ++ ++ old = xa_cmpxchg(&ufile->idr, obj_old->id, NULL, obj_old, GFP_KERNEL); ++ WARN_ON(old != NULL); ++} ++ + static void alloc_commit_fd_uobject(struct ib_uobject *uobj) + { + int fd = uobj->id; +@@ -654,6 +675,35 @@ void rdma_alloc_commit_uobject(struct ib_uobject *uobj, + up_read(&ufile->hw_destroy_rwsem); + } + ++/* ++ * new_uobj will be assigned to the handle currently used by to_uobj, and ++ * to_uobj will be destroyed. ++ * ++ * Upon return the caller must do: ++ * rdma_alloc_commit_uobject(new_uobj) ++ * uobj_put_destroy(to_uobj) ++ * ++ * to_uobj must have a write get but the put mode switches to destroy once ++ * this is called. ++ */ ++void rdma_assign_uobject(struct ib_uobject *to_uobj, struct ib_uobject *new_uobj, ++ struct uverbs_attr_bundle *attrs) ++{ ++ assert_uverbs_usecnt(new_uobj, UVERBS_LOOKUP_WRITE); ++ ++ if (WARN_ON(to_uobj->uapi_object != new_uobj->uapi_object || ++ !to_uobj->uapi_object->type_class->swap_uobjects)) ++ return; ++ ++ to_uobj->uapi_object->type_class->swap_uobjects(to_uobj, new_uobj); ++ ++ /* ++ * If this fails then the uobject is still completely valid (though with ++ * a new ID) and we leak it until context close. ++ */ ++ uverbs_destroy_uobject(to_uobj, RDMA_REMOVE_DESTROY, attrs); ++} ++ + /* + * This consumes the kref for uobj. It is up to the caller to unwind the HW + * object and anything else connected to uobj before calling this. +@@ -761,6 +811,7 @@ const struct uverbs_obj_type_class uverbs_idr_class = { + .lookup_put = lookup_put_idr_uobject, + .destroy_hw = destroy_hw_idr_uobject, + .remove_handle = remove_handle_idr_uobject, ++ .swap_uobjects = swap_idr_uobjects, + }; + EXPORT_SYMBOL(uverbs_idr_class); + +diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c +index 466026825dd7..3e82469c851c 100644 +--- a/drivers/infiniband/core/uverbs_cmd.c ++++ b/drivers/infiniband/core/uverbs_cmd.c +@@ -774,11 +774,14 @@ static int ib_uverbs_rereg_mr(struct uverbs_attr_bundle *attrs) + { + struct ib_uverbs_rereg_mr cmd; + struct ib_uverbs_rereg_mr_resp resp; +- struct ib_pd *pd = NULL; + struct ib_mr *mr; +- struct ib_pd *old_pd; + int ret; + struct ib_uobject *uobj; ++ struct ib_uobject *new_uobj; ++ struct ib_device *ib_dev; ++ struct ib_pd *orig_pd; ++ struct ib_pd *new_pd; ++ struct ib_mr *new_mr; + + ret = uverbs_request(attrs, &cmd, sizeof(cmd)); + if (ret) +@@ -809,31 +812,69 @@ static int ib_uverbs_rereg_mr(struct uverbs_attr_bundle *attrs) + goto put_uobjs; + } + ++ orig_pd = mr->pd; + if (cmd.flags & IB_MR_REREG_PD) { +- pd = uobj_get_obj_read(pd, UVERBS_OBJECT_PD, cmd.pd_handle, +- attrs); +- if (!pd) { ++ new_pd = uobj_get_obj_read(pd, UVERBS_OBJECT_PD, cmd.pd_handle, ++ attrs); ++ if (!new_pd) { + ret = -EINVAL; + goto put_uobjs; + } ++ } else { ++ new_pd = mr->pd; + } + +- old_pd = mr->pd; +- ret = mr->device->ops.rereg_user_mr(mr, cmd.flags, cmd.start, +- cmd.length, cmd.hca_va, +- cmd.access_flags, pd, +- &attrs->driver_udata); +- if (ret) ++ /* ++ * The driver might create a new HW object as part of the rereg, we need ++ * to have a uobject ready to hold it. ++ */ ++ new_uobj = uobj_alloc(UVERBS_OBJECT_MR, attrs, &ib_dev); ++ if (IS_ERR(new_uobj)) { ++ ret = PTR_ERR(new_uobj); + goto put_uobj_pd; +- +- if (cmd.flags & IB_MR_REREG_PD) { +- atomic_inc(&pd->usecnt); +- mr->pd = pd; +- atomic_dec(&old_pd->usecnt); + } + +- if (cmd.flags & IB_MR_REREG_TRANS) +- mr->iova = cmd.hca_va; ++ new_mr = ib_dev->ops.rereg_user_mr(mr, cmd.flags, cmd.start, cmd.length, ++ cmd.hca_va, cmd.access_flags, new_pd, ++ &attrs->driver_udata); ++ if (IS_ERR(new_mr)) { ++ ret = PTR_ERR(new_mr); ++ goto put_new_uobj; ++ } ++ if (new_mr) { ++ new_mr->device = new_pd->device; ++ new_mr->pd = new_pd; ++ new_mr->type = IB_MR_TYPE_USER; ++ new_mr->dm = NULL; ++ new_mr->sig_attrs = NULL; ++ new_mr->uobject = uobj; ++ atomic_inc(&new_pd->usecnt); ++ new_mr->iova = cmd.hca_va; ++ new_uobj->object = new_mr; ++ ++ rdma_restrack_new(&new_mr->res, RDMA_RESTRACK_MR); ++ rdma_restrack_set_name(&new_mr->res, NULL); ++ rdma_restrack_add(&new_mr->res); ++ ++ /* ++ * The new uobj for the new HW object is put into the same spot ++ * in the IDR and the old uobj & HW object is deleted. ++ */ ++ rdma_assign_uobject(uobj, new_uobj, attrs); ++ rdma_alloc_commit_uobject(new_uobj, attrs); ++ uobj_put_destroy(uobj); ++ new_uobj = NULL; ++ uobj = NULL; ++ mr = new_mr; ++ } else { ++ if (cmd.flags & IB_MR_REREG_PD) { ++ atomic_dec(&orig_pd->usecnt); ++ mr->pd = new_pd; ++ atomic_inc(&new_pd->usecnt); ++ } ++ if (cmd.flags & IB_MR_REREG_TRANS) ++ mr->iova = cmd.hca_va; ++ } + + memset(&resp, 0, sizeof(resp)); + resp.lkey = mr->lkey; +@@ -841,12 +882,16 @@ static int ib_uverbs_rereg_mr(struct uverbs_attr_bundle *attrs) + + ret = uverbs_response(attrs, &resp, sizeof(resp)); + ++put_new_uobj: ++ if (new_uobj) ++ uobj_alloc_abort(new_uobj, attrs); + put_uobj_pd: + if (cmd.flags & IB_MR_REREG_PD) +- uobj_put_obj_read(pd); ++ uobj_put_obj_read(new_pd); + + put_uobjs: +- uobj_put_write(uobj); ++ if (uobj) ++ uobj_put_write(uobj); + + return ret; + } +diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h +index d9aa7424d290..d7ceb2c20ba5 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_device.h ++++ b/drivers/infiniband/hw/hns/hns_roce_device.h +@@ -1206,9 +1206,10 @@ struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); + struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, + u64 virt_addr, int access_flags, + struct ib_udata *udata); +-int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, +- u64 virt_addr, int mr_access_flags, struct ib_pd *pd, +- struct ib_udata *udata); ++struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, ++ u64 length, u64 virt_addr, ++ int mr_access_flags, struct ib_pd *pd, ++ struct ib_udata *udata); + struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, + u32 max_num_sg); + int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, +diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c +index 027ec8413ac2..2661dbbd7812 100644 +--- a/drivers/infiniband/hw/hns/hns_roce_mr.c ++++ b/drivers/infiniband/hw/hns/hns_roce_mr.c +@@ -328,9 +328,10 @@ static int rereg_mr_trans(struct ib_mr *ibmr, int flags, + return ret; + } + +-int hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start, u64 length, +- u64 virt_addr, int mr_access_flags, struct ib_pd *pd, +- struct ib_udata *udata) ++struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start, ++ u64 length, u64 virt_addr, ++ int mr_access_flags, struct ib_pd *pd, ++ struct ib_udata *udata) + { + struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device); + struct ib_device *ib_dev = &hr_dev->ib_dev; +@@ -341,11 +342,11 @@ int hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start, u64 length, + int ret; + + if (!mr->enabled) +- return -EINVAL; ++ return ERR_PTR(-EINVAL); + + mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); + if (IS_ERR(mailbox)) +- return PTR_ERR(mailbox); ++ return ERR_CAST(mailbox); + + mtpt_idx = key_to_hw_index(mr->key) & (hr_dev->caps.num_mtpts - 1); + ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, mtpt_idx, 0, +@@ -390,12 +391,12 @@ int hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start, u64 length, + + hns_roce_free_cmd_mailbox(hr_dev, mailbox); + +- return 0; ++ return NULL; + + free_cmd_mbox: + hns_roce_free_cmd_mailbox(hr_dev, mailbox); + +- return ret; ++ return ERR_PTR(ret); + } + + int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) +diff --git a/drivers/infiniband/hw/mlx4/mlx4_ib.h b/drivers/infiniband/hw/mlx4/mlx4_ib.h +index 58df06492d69..78c9bb79ec75 100644 +--- a/drivers/infiniband/hw/mlx4/mlx4_ib.h ++++ b/drivers/infiniband/hw/mlx4/mlx4_ib.h +@@ -908,10 +908,10 @@ int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn); + void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count); + int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, + int is_attach); +-int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, +- u64 start, u64 length, u64 virt_addr, +- int mr_access_flags, struct ib_pd *pd, +- struct ib_udata *udata); ++struct ib_mr *mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, ++ u64 length, u64 virt_addr, ++ int mr_access_flags, struct ib_pd *pd, ++ struct ib_udata *udata); + int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, + const struct ib_gid_attr *attr); + +diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c +index 426fed005d53..50becc0e4b62 100644 +--- a/drivers/infiniband/hw/mlx4/mr.c ++++ b/drivers/infiniband/hw/mlx4/mr.c +@@ -456,10 +456,10 @@ struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, + return ERR_PTR(err); + } + +-int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, +- u64 start, u64 length, u64 virt_addr, +- int mr_access_flags, struct ib_pd *pd, +- struct ib_udata *udata) ++struct ib_mr *mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, ++ u64 length, u64 virt_addr, ++ int mr_access_flags, struct ib_pd *pd, ++ struct ib_udata *udata) + { + struct mlx4_ib_dev *dev = to_mdev(mr->device); + struct mlx4_ib_mr *mmr = to_mmr(mr); +@@ -472,9 +472,8 @@ int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, + * race exists. + */ + err = mlx4_mr_hw_get_mpt(dev->dev, &mmr->mmr, &pmpt_entry); +- + if (err) +- return err; ++ return ERR_PTR(err); + + if (flags & IB_MR_REREG_PD) { + err = mlx4_mr_hw_change_pd(dev->dev, *pmpt_entry, +@@ -542,8 +541,9 @@ int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, + + release_mpt_entry: + mlx4_mr_hw_put_mpt(dev->dev, pmpt_entry); +- +- return err; ++ if (err) ++ return ERR_PTR(err); ++ return NULL; + } + + static int +diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h +index b1f2b34e5955..feb319b00323 100644 +--- a/drivers/infiniband/hw/mlx5/mlx5_ib.h ++++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h +@@ -1189,9 +1189,9 @@ struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, + int access_flags); + void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); + void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); +-int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, +- u64 length, u64 virt_addr, int access_flags, +- struct ib_pd *pd, struct ib_udata *udata); ++struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, ++ u64 length, u64 virt_addr, int access_flags, ++ struct ib_pd *pd, struct ib_udata *udata); + int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); + struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, + u32 max_num_sg); +diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c +index d827a4e44c94..20a788755b3a 100644 +--- a/drivers/infiniband/hw/mlx5/mr.c ++++ b/drivers/infiniband/hw/mlx5/mr.c +@@ -1514,9 +1514,10 @@ static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, + return err; + } + +-int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, +- u64 length, u64 virt_addr, int new_access_flags, +- struct ib_pd *new_pd, struct ib_udata *udata) ++struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, ++ u64 length, u64 virt_addr, ++ int new_access_flags, struct ib_pd *new_pd, ++ struct ib_udata *udata) + { + struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); + struct mlx5_ib_mr *mr = to_mmr(ib_mr); +@@ -1536,10 +1537,10 @@ int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, + start, virt_addr, length, access_flags); + + if (!mr->umem) +- return -EINVAL; ++ return ERR_PTR(-EINVAL); + + if (is_odp_mr(mr)) +- return -EOPNOTSUPP; ++ return ERR_PTR(-EOPNOTSUPP); + + if (flags & IB_MR_REREG_TRANS) { + addr = virt_addr; +@@ -1618,14 +1619,14 @@ int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, + + set_mr_fields(dev, mr, len, access_flags); + +- return 0; ++ return NULL; + + err: + ib_umem_release(mr->umem); + mr->umem = NULL; + + clean_mr(dev, mr); +- return err; ++ return ERR_PTR(err); + } + + static int +diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h +index ac6ffa561884..c88ee4069272 100644 +--- a/include/rdma/ib_verbs.h ++++ b/include/rdma/ib_verbs.h +@@ -2429,9 +2429,10 @@ struct ib_device_ops { + struct ib_mr *(*reg_user_mr)(struct ib_pd *pd, u64 start, u64 length, + u64 virt_addr, int mr_access_flags, + struct ib_udata *udata); +- int (*rereg_user_mr)(struct ib_mr *mr, int flags, u64 start, u64 length, +- u64 virt_addr, int mr_access_flags, +- struct ib_pd *pd, struct ib_udata *udata); ++ struct ib_mr *(*rereg_user_mr)(struct ib_mr *mr, int flags, u64 start, ++ u64 length, u64 virt_addr, ++ int mr_access_flags, struct ib_pd *pd, ++ struct ib_udata *udata); + int (*dereg_mr)(struct ib_mr *mr, struct ib_udata *udata); + struct ib_mr *(*alloc_mr)(struct ib_pd *pd, enum ib_mr_type mr_type, + u32 max_num_sg); +diff --git a/include/rdma/uverbs_types.h b/include/rdma/uverbs_types.h +index 06db27e35f40..cc5cfcad9331 100644 +--- a/include/rdma/uverbs_types.h ++++ b/include/rdma/uverbs_types.h +@@ -71,6 +71,8 @@ struct uverbs_obj_type_class { + enum rdma_remove_reason why, + struct uverbs_attr_bundle *attrs); + void (*remove_handle)(struct ib_uobject *uobj); ++ void (*swap_uobjects)(struct ib_uobject *obj_old, ++ struct ib_uobject *obj_new); + }; + + struct uverbs_obj_type { +@@ -116,6 +118,9 @@ void rdma_alloc_abort_uobject(struct ib_uobject *uobj, + bool hw_obj_valid); + void rdma_alloc_commit_uobject(struct ib_uobject *uobj, + struct uverbs_attr_bundle *attrs); ++void rdma_assign_uobject(struct ib_uobject *to_uobj, ++ struct ib_uobject *new_uobj, ++ struct uverbs_attr_bundle *attrs); + + /* + * uverbs_uobject_get is called in order to increase the reference count on +-- +2.35.1 + diff --git a/queue-5.10/regulator-core-prevent-integer-underflow.patch b/queue-5.10/regulator-core-prevent-integer-underflow.patch new file mode 100644 index 00000000000..78df306376a --- /dev/null +++ b/queue-5.10/regulator-core-prevent-integer-underflow.patch @@ -0,0 +1,41 @@ +From 801a22e26ff49890c6fa1a7716dd352664745d9a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 14:59:53 +0200 +Subject: regulator: core: Prevent integer underflow + +From: Patrick Rudolph + +[ Upstream commit 8d8e16592022c9650df8aedfe6552ed478d7135b ] + +By using a ratio of delay to poll_enabled_time that is not integer +time_remaining underflows and does not exit the loop as expected. +As delay could be derived from DT and poll_enabled_time is defined +in the driver this can easily happen. + +Use a signed iterator to make sure that the loop exits once +the remaining time is negative. + +Signed-off-by: Patrick Rudolph +Link: https://lore.kernel.org/r/20220909125954.577669-1-patrick.rudolph@9elements.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/regulator/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c +index 317d701487ec..bf8ba73d6c7c 100644 +--- a/drivers/regulator/core.c ++++ b/drivers/regulator/core.c +@@ -2544,7 +2544,7 @@ static int _regulator_do_enable(struct regulator_dev *rdev) + * expired, return -ETIMEDOUT. + */ + if (rdev->desc->poll_enabled_time) { +- unsigned int time_remaining = delay; ++ int time_remaining = delay; + + while (time_remaining > 0) { + _regulator_enable_delay(rdev->desc->poll_enabled_time); +-- +2.35.1 + diff --git a/queue-5.10/revert-usb-storage-add-quirk-for-samsung-fit-flash.patch b/queue-5.10/revert-usb-storage-add-quirk-for-samsung-fit-flash.patch new file mode 100644 index 00000000000..025877c3ce2 --- /dev/null +++ b/queue-5.10/revert-usb-storage-add-quirk-for-samsung-fit-flash.patch @@ -0,0 +1,59 @@ +From aea460bdaaa85a4e8fc471549b23485ebec76fa4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 20:49:13 +0900 +Subject: Revert "usb: storage: Add quirk for Samsung Fit flash" + +From: sunghwan jung + +[ Upstream commit ad5dbfc123e6ffbbde194e2a4603323e09f741ee ] + +This reverts commit 86d92f5465958752481269348d474414dccb1552, +which fix the timeout issue for "Samsung Fit Flash". + +But the commit affects not only "Samsung Fit Flash" but also other usb +storages that use the same controller and causes severe performance +regression. + + # hdparm -t /dev/sda (without the quirk) + Timing buffered disk reads: 622 MB in 3.01 seconds = 206.66 MB/sec + + # hdparm -t /dev/sda (with the quirk) + Timing buffered disk reads: 220 MB in 3.00 seconds = 73.32 MB/sec + +The commit author mentioned that "Issue was reproduced after device has +bad block", so this quirk should be applied when we have the timeout +issue with a device that has bad blocks. + +We revert the commit so that we apply this quirk by adding kernel +paramters using a bootloader or other ways when we really need it, +without the performance regression with devices that don't have the +issue. + +Signed-off-by: sunghwan jung +Link: https://lore.kernel.org/r/20220913114913.3073-1-onenowy@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/storage/unusual_devs.h | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h +index 4993227ab293..20dcbccb290b 100644 +--- a/drivers/usb/storage/unusual_devs.h ++++ b/drivers/usb/storage/unusual_devs.h +@@ -1275,12 +1275,6 @@ UNUSUAL_DEV( 0x090a, 0x1200, 0x0000, 0x9999, + USB_SC_RBC, USB_PR_BULK, NULL, + 0 ), + +-UNUSUAL_DEV(0x090c, 0x1000, 0x1100, 0x1100, +- "Samsung", +- "Flash Drive FIT", +- USB_SC_DEVICE, USB_PR_DEVICE, NULL, +- US_FL_MAX_SECTORS_64), +- + /* aeb */ + UNUSUAL_DEV( 0x090c, 0x1132, 0x0000, 0xffff, + "Feiya", +-- +2.35.1 + diff --git a/queue-5.10/sbitmap-avoid-leaving-waitqueue-in-invalid-state-in-.patch b/queue-5.10/sbitmap-avoid-leaving-waitqueue-in-invalid-state-in-.patch new file mode 100644 index 00000000000..bf095318717 --- /dev/null +++ b/queue-5.10/sbitmap-avoid-leaving-waitqueue-in-invalid-state-in-.patch @@ -0,0 +1,77 @@ +From e3b91089200a0c4c3fdfe150a167b9916b4b5220 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 15:09:37 +0200 +Subject: sbitmap: Avoid leaving waitqueue in invalid state in __sbq_wake_up() + +From: Jan Kara + +[ Upstream commit 48c033314f372478548203c583529f53080fd078 ] + +When __sbq_wake_up() decrements wait_cnt to 0 but races with someone +else waking the waiter on the waitqueue (so the waitqueue becomes +empty), it exits without reseting wait_cnt to wake_batch number. Once +wait_cnt is 0, nobody will ever reset the wait_cnt or wake the new +waiters resulting in possible deadlocks or busyloops. Fix the problem by +making sure we reset wait_cnt even if we didn't wake up anybody in the +end. + +Fixes: 040b83fcecfb ("sbitmap: fix possible io hung due to lost wakeup") +Reported-by: Keith Busch +Signed-off-by: Jan Kara +Link: https://lore.kernel.org/r/20220908130937.2795-1-jack@suse.cz +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + lib/sbitmap.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/lib/sbitmap.c b/lib/sbitmap.c +index f5213ac07da3..0658ea4bd930 100644 +--- a/lib/sbitmap.c ++++ b/lib/sbitmap.c +@@ -516,6 +516,7 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq) + struct sbq_wait_state *ws; + unsigned int wake_batch; + int wait_cnt; ++ bool ret; + + ws = sbq_wake_ptr(sbq); + if (!ws) +@@ -526,12 +527,23 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq) + * For concurrent callers of this, callers should call this function + * again to wakeup a new batch on a different 'ws'. + */ +- if (wait_cnt < 0 || !waitqueue_active(&ws->wait)) ++ if (wait_cnt < 0) + return true; + ++ /* ++ * If we decremented queue without waiters, retry to avoid lost ++ * wakeups. ++ */ + if (wait_cnt > 0) +- return false; ++ return !waitqueue_active(&ws->wait); + ++ /* ++ * When wait_cnt == 0, we have to be particularly careful as we are ++ * responsible to reset wait_cnt regardless whether we've actually ++ * woken up anybody. But in case we didn't wakeup anybody, we still ++ * need to retry. ++ */ ++ ret = !waitqueue_active(&ws->wait); + wake_batch = READ_ONCE(sbq->wake_batch); + + /* +@@ -560,7 +572,7 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq) + sbq_index_atomic_inc(&sbq->wake_index); + atomic_set(&ws->wait_cnt, wake_batch); + +- return false; ++ return ret; + } + + void sbitmap_queue_wake_up(struct sbitmap_queue *sbq) +-- +2.35.1 + diff --git a/queue-5.10/sbitmap-fix-possible-io-hung-due-to-lost-wakeup.patch b/queue-5.10/sbitmap-fix-possible-io-hung-due-to-lost-wakeup.patch new file mode 100644 index 00000000000..11e312fd0f4 --- /dev/null +++ b/queue-5.10/sbitmap-fix-possible-io-hung-due-to-lost-wakeup.patch @@ -0,0 +1,141 @@ +From 6f431a716bcc47b7389973a5928e558016ddcb21 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Aug 2022 20:15:04 +0800 +Subject: sbitmap: fix possible io hung due to lost wakeup + +From: Yu Kuai + +[ Upstream commit 040b83fcecfb86f3225d3a5de7fd9b3fbccf83b4 ] + +There are two problems can lead to lost wakeup: + +1) invalid wakeup on the wrong waitqueue: + +For example, 2 * wake_batch tags are put, while only wake_batch threads +are woken: + +__sbq_wake_up + atomic_cmpxchg -> reset wait_cnt + __sbq_wake_up -> decrease wait_cnt + ... + __sbq_wake_up -> wait_cnt is decreased to 0 again + atomic_cmpxchg + sbq_index_atomic_inc -> increase wake_index + wake_up_nr -> wake up and waitqueue might be empty + sbq_index_atomic_inc -> increase again, one waitqueue is skipped + wake_up_nr -> invalid wake up because old wakequeue might be empty + +To fix the problem, increasing 'wake_index' before resetting 'wait_cnt'. + +2) 'wait_cnt' can be decreased while waitqueue is empty + +As pointed out by Jan Kara, following race is possible: + +CPU1 CPU2 +__sbq_wake_up __sbq_wake_up + sbq_wake_ptr() sbq_wake_ptr() -> the same + wait_cnt = atomic_dec_return() + /* decreased to 0 */ + sbq_index_atomic_inc() + /* move to next waitqueue */ + atomic_set() + /* reset wait_cnt */ + wake_up_nr() + /* wake up on the old waitqueue */ + wait_cnt = atomic_dec_return() + /* + * decrease wait_cnt in the old + * waitqueue, while it can be + * empty. + */ + +Fix the problem by waking up before updating 'wake_index' and +'wait_cnt'. + +With this patch, noted that 'wait_cnt' is still decreased in the old +empty waitqueue, however, the wakeup is redirected to a active waitqueue, +and the extra decrement on the old empty waitqueue is not handled. + +Fixes: 88459642cba4 ("blk-mq: abstract tag allocation out into sbitmap library") +Signed-off-by: Yu Kuai +Reviewed-by: Jan Kara +Link: https://lore.kernel.org/r/20220803121504.212071-1-yukuai1@huaweicloud.com +Signed-off-by: Jens Axboe +Signed-off-by: Sasha Levin +--- + lib/sbitmap.c | 55 ++++++++++++++++++++++++++++++--------------------- + 1 file changed, 33 insertions(+), 22 deletions(-) + +diff --git a/lib/sbitmap.c b/lib/sbitmap.c +index 267aa7709416..f5213ac07da3 100644 +--- a/lib/sbitmap.c ++++ b/lib/sbitmap.c +@@ -522,32 +522,43 @@ static bool __sbq_wake_up(struct sbitmap_queue *sbq) + return false; + + wait_cnt = atomic_dec_return(&ws->wait_cnt); +- if (wait_cnt <= 0) { +- int ret; ++ /* ++ * For concurrent callers of this, callers should call this function ++ * again to wakeup a new batch on a different 'ws'. ++ */ ++ if (wait_cnt < 0 || !waitqueue_active(&ws->wait)) ++ return true; + +- wake_batch = READ_ONCE(sbq->wake_batch); ++ if (wait_cnt > 0) ++ return false; + +- /* +- * Pairs with the memory barrier in sbitmap_queue_resize() to +- * ensure that we see the batch size update before the wait +- * count is reset. +- */ +- smp_mb__before_atomic(); ++ wake_batch = READ_ONCE(sbq->wake_batch); + +- /* +- * For concurrent callers of this, the one that failed the +- * atomic_cmpxhcg() race should call this function again +- * to wakeup a new batch on a different 'ws'. +- */ +- ret = atomic_cmpxchg(&ws->wait_cnt, wait_cnt, wake_batch); +- if (ret == wait_cnt) { +- sbq_index_atomic_inc(&sbq->wake_index); +- wake_up_nr(&ws->wait, wake_batch); +- return false; +- } ++ /* ++ * Wake up first in case that concurrent callers decrease wait_cnt ++ * while waitqueue is empty. ++ */ ++ wake_up_nr(&ws->wait, wake_batch); + +- return true; +- } ++ /* ++ * Pairs with the memory barrier in sbitmap_queue_resize() to ++ * ensure that we see the batch size update before the wait ++ * count is reset. ++ * ++ * Also pairs with the implicit barrier between decrementing wait_cnt ++ * and checking for waitqueue_active() to make sure waitqueue_active() ++ * sees result of the wakeup if atomic_dec_return() has seen the result ++ * of atomic_set(). ++ */ ++ smp_mb__before_atomic(); ++ ++ /* ++ * Increase wake_index before updating wait_cnt, otherwise concurrent ++ * callers can see valid wait_cnt in old waitqueue, which can cause ++ * invalid wakeup on the old waitqueue. ++ */ ++ sbq_index_atomic_inc(&sbq->wake_index); ++ atomic_set(&ws->wait_cnt, wake_batch); + + return false; + } +-- +2.35.1 + diff --git a/queue-5.10/scsi-3w-9xxx-avoid-disabling-device-if-failing-to-en.patch b/queue-5.10/scsi-3w-9xxx-avoid-disabling-device-if-failing-to-en.patch new file mode 100644 index 00000000000..acf0f085d84 --- /dev/null +++ b/queue-5.10/scsi-3w-9xxx-avoid-disabling-device-if-failing-to-en.patch @@ -0,0 +1,42 @@ +From 727de57ad20c000b62163b04c8049f4ce6338a5e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 29 Aug 2022 19:01:15 +0800 +Subject: scsi: 3w-9xxx: Avoid disabling device if failing to enable it + +From: Letu Ren + +[ Upstream commit 7eff437b5ee1309b34667844361c6bbb5c97df05 ] + +The original code will "goto out_disable_device" and call +pci_disable_device() if pci_enable_device() fails. The kernel will generate +a warning message like "3w-9xxx 0000:00:05.0: disabling already-disabled +device". + +We shouldn't disable a device that failed to be enabled. A simple return is +fine. + +Link: https://lore.kernel.org/r/20220829110115.38789-1-fantasquex@gmail.com +Reported-by: Zheyu Ma +Signed-off-by: Letu Ren +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/3w-9xxx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c +index 3337b1e80412..f6f92033132a 100644 +--- a/drivers/scsi/3w-9xxx.c ++++ b/drivers/scsi/3w-9xxx.c +@@ -2014,7 +2014,7 @@ static int twa_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id) + retval = pci_enable_device(pdev); + if (retval) { + TW_PRINTK(host, TW_DRIVER, 0x34, "Failed to enable pci device"); +- goto out_disable_device; ++ return -ENODEV; + } + + pci_set_master(pdev); +-- +2.35.1 + diff --git a/queue-5.10/scsi-cgroup-add-cgroup_get_from_id.patch b/queue-5.10/scsi-cgroup-add-cgroup_get_from_id.patch new file mode 100644 index 00000000000..534598893bc --- /dev/null +++ b/queue-5.10/scsi-cgroup-add-cgroup_get_from_id.patch @@ -0,0 +1,97 @@ +From 382b7cee9ee1b4dce0d393c1d94a2bfdc0aff047 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Jun 2021 10:05:44 +0530 +Subject: scsi: cgroup: Add cgroup_get_from_id() + +From: Muneendra Kumar + +[ Upstream commit 6b658c4863c15936872a93c9ee879043bf6393c9 ] + +Add a new function, cgroup_get_from_id(), to retrieve the cgroup associated +with a cgroup id. Also export the function cgroup_get_e_css() as this is +needed in blk-cgroup.h. + +Link: https://lore.kernel.org/r/20210608043556.274139-2-muneendra.kumar@broadcom.com +Reviewed-by: Himanshu Madhani +Reviewed-by: Hannes Reinecke +Acked-by: Tejun Heo +Signed-off-by: Muneendra Kumar +Signed-off-by: Martin K. Petersen +Stable-dep-of: 74e4b956eb1c ("cgroup: Honor caller's cgroup NS when resolving path") +Signed-off-by: Sasha Levin +--- + include/linux/cgroup.h | 6 ++++++ + kernel/cgroup/cgroup.c | 26 ++++++++++++++++++++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h +index 618838c48313..23375d4ccfa0 100644 +--- a/include/linux/cgroup.h ++++ b/include/linux/cgroup.h +@@ -696,6 +696,7 @@ static inline void cgroup_kthread_ready(void) + } + + void cgroup_path_from_kernfs_id(u64 id, char *buf, size_t buflen); ++struct cgroup *cgroup_get_from_id(u64 id); + #else /* !CONFIG_CGROUPS */ + + struct cgroup_subsys_state; +@@ -743,6 +744,11 @@ static inline bool task_under_cgroup_hierarchy(struct task_struct *task, + + static inline void cgroup_path_from_kernfs_id(u64 id, char *buf, size_t buflen) + {} ++ ++static inline struct cgroup *cgroup_get_from_id(u64 id) ++{ ++ return NULL; ++} + #endif /* !CONFIG_CGROUPS */ + + #ifdef CONFIG_CGROUPS +diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c +index 0eb05cbafa71..c420b048466b 100644 +--- a/kernel/cgroup/cgroup.c ++++ b/kernel/cgroup/cgroup.c +@@ -580,6 +580,7 @@ struct cgroup_subsys_state *cgroup_get_e_css(struct cgroup *cgrp, + rcu_read_unlock(); + return css; + } ++EXPORT_SYMBOL_GPL(cgroup_get_e_css); + + static void cgroup_get_live(struct cgroup *cgrp) + { +@@ -5921,6 +5922,31 @@ void cgroup_path_from_kernfs_id(u64 id, char *buf, size_t buflen) + kernfs_put(kn); + } + ++/* ++ * cgroup_get_from_id : get the cgroup associated with cgroup id ++ * @id: cgroup id ++ * On success return the cgrp, on failure return NULL ++ */ ++struct cgroup *cgroup_get_from_id(u64 id) ++{ ++ struct kernfs_node *kn; ++ struct cgroup *cgrp = NULL; ++ ++ mutex_lock(&cgroup_mutex); ++ kn = kernfs_find_and_get_node_by_id(cgrp_dfl_root.kf_root, id); ++ if (!kn) ++ goto out_unlock; ++ ++ cgrp = kn->priv; ++ if (cgroup_is_dead(cgrp) || !cgroup_tryget(cgrp)) ++ cgrp = NULL; ++ kernfs_put(kn); ++out_unlock: ++ mutex_unlock(&cgroup_mutex); ++ return cgrp; ++} ++EXPORT_SYMBOL_GPL(cgroup_get_from_id); ++ + /* + * proc_cgroup_show() + * - Print task's cgroup paths into seq_file, one line for each hierarchy +-- +2.35.1 + diff --git a/queue-5.10/scsi-iscsi-iscsi_tcp-fix-null-ptr-deref-while-callin.patch b/queue-5.10/scsi-iscsi-iscsi_tcp-fix-null-ptr-deref-while-callin.patch new file mode 100644 index 00000000000..61780c25ea2 --- /dev/null +++ b/queue-5.10/scsi-iscsi-iscsi_tcp-fix-null-ptr-deref-while-callin.patch @@ -0,0 +1,224 @@ +From e22da08cc01621d2746814046c00070d444968a4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 17:17:00 -0500 +Subject: scsi: iscsi: iscsi_tcp: Fix null-ptr-deref while calling + getpeername() + +From: Mike Christie + +[ Upstream commit 57569c37f0add1b6489e1a1563c71519daf732cf ] + +Fix a NULL pointer crash that occurs when we are freeing the socket at the +same time we access it via sysfs. + +The problem is that: + + 1. iscsi_sw_tcp_conn_get_param() and iscsi_sw_tcp_host_get_param() take + the frwd_lock and do sock_hold() then drop the frwd_lock. sock_hold() + does a get on the "struct sock". + + 2. iscsi_sw_tcp_release_conn() does sockfd_put() which does the last put + on the "struct socket" and that does __sock_release() which sets the + sock->ops to NULL. + + 3. iscsi_sw_tcp_conn_get_param() and iscsi_sw_tcp_host_get_param() then + call kernel_getpeername() which accesses the NULL sock->ops. + +Above we do a get on the "struct sock", but we needed a get on the "struct +socket". Originally, we just held the frwd_lock the entire time but in +commit bcf3a2953d36 ("scsi: iscsi: iscsi_tcp: Avoid holding spinlock while +calling getpeername()") we switched to refcount based because the network +layer changed and started taking a mutex in that path, so we could no +longer hold the frwd_lock. + +Instead of trying to maintain multiple refcounts, this just has us use a +mutex for accessing the socket in the interface code paths. + +Link: https://lore.kernel.org/r/20220907221700.10302-1-michael.christie@oracle.com +Fixes: bcf3a2953d36 ("scsi: iscsi: iscsi_tcp: Avoid holding spinlock while calling getpeername()") +Signed-off-by: Mike Christie +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/iscsi_tcp.c | 73 ++++++++++++++++++++++++++++------------ + drivers/scsi/iscsi_tcp.h | 2 ++ + 2 files changed, 54 insertions(+), 21 deletions(-) + +diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c +index df47557a02a3..6485c1aa9e74 100644 +--- a/drivers/scsi/iscsi_tcp.c ++++ b/drivers/scsi/iscsi_tcp.c +@@ -558,6 +558,8 @@ iscsi_sw_tcp_conn_create(struct iscsi_cls_session *cls_session, + tcp_conn = conn->dd_data; + tcp_sw_conn = tcp_conn->dd_data; + ++ mutex_init(&tcp_sw_conn->sock_lock); ++ + tfm = crypto_alloc_ahash("crc32c", 0, CRYPTO_ALG_ASYNC); + if (IS_ERR(tfm)) + goto free_conn; +@@ -592,11 +594,15 @@ iscsi_sw_tcp_conn_create(struct iscsi_cls_session *cls_session, + + static void iscsi_sw_tcp_release_conn(struct iscsi_conn *conn) + { +- struct iscsi_session *session = conn->session; + struct iscsi_tcp_conn *tcp_conn = conn->dd_data; + struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data; + struct socket *sock = tcp_sw_conn->sock; + ++ /* ++ * The iscsi transport class will make sure we are not called in ++ * parallel with start, stop, bind and destroys. However, this can be ++ * called twice if userspace does a stop then a destroy. ++ */ + if (!sock) + return; + +@@ -604,9 +610,9 @@ static void iscsi_sw_tcp_release_conn(struct iscsi_conn *conn) + iscsi_sw_tcp_conn_restore_callbacks(conn); + sock_put(sock->sk); + +- spin_lock_bh(&session->frwd_lock); ++ mutex_lock(&tcp_sw_conn->sock_lock); + tcp_sw_conn->sock = NULL; +- spin_unlock_bh(&session->frwd_lock); ++ mutex_unlock(&tcp_sw_conn->sock_lock); + sockfd_put(sock); + } + +@@ -658,7 +664,6 @@ iscsi_sw_tcp_conn_bind(struct iscsi_cls_session *cls_session, + struct iscsi_cls_conn *cls_conn, uint64_t transport_eph, + int is_leading) + { +- struct iscsi_session *session = cls_session->dd_data; + struct iscsi_conn *conn = cls_conn->dd_data; + struct iscsi_tcp_conn *tcp_conn = conn->dd_data; + struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data; +@@ -678,10 +683,10 @@ iscsi_sw_tcp_conn_bind(struct iscsi_cls_session *cls_session, + if (err) + goto free_socket; + +- spin_lock_bh(&session->frwd_lock); ++ mutex_lock(&tcp_sw_conn->sock_lock); + /* bind iSCSI connection and socket */ + tcp_sw_conn->sock = sock; +- spin_unlock_bh(&session->frwd_lock); ++ mutex_unlock(&tcp_sw_conn->sock_lock); + + /* setup Socket parameters */ + sk = sock->sk; +@@ -717,8 +722,15 @@ static int iscsi_sw_tcp_conn_set_param(struct iscsi_cls_conn *cls_conn, + break; + case ISCSI_PARAM_DATADGST_EN: + iscsi_set_param(cls_conn, param, buf, buflen); ++ ++ mutex_lock(&tcp_sw_conn->sock_lock); ++ if (!tcp_sw_conn->sock) { ++ mutex_unlock(&tcp_sw_conn->sock_lock); ++ return -ENOTCONN; ++ } + tcp_sw_conn->sendpage = conn->datadgst_en ? + sock_no_sendpage : tcp_sw_conn->sock->ops->sendpage; ++ mutex_unlock(&tcp_sw_conn->sock_lock); + break; + case ISCSI_PARAM_MAX_R2T: + return iscsi_tcp_set_max_r2t(conn, buf); +@@ -733,8 +745,8 @@ static int iscsi_sw_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn, + enum iscsi_param param, char *buf) + { + struct iscsi_conn *conn = cls_conn->dd_data; +- struct iscsi_tcp_conn *tcp_conn = conn->dd_data; +- struct iscsi_sw_tcp_conn *tcp_sw_conn = tcp_conn->dd_data; ++ struct iscsi_sw_tcp_conn *tcp_sw_conn; ++ struct iscsi_tcp_conn *tcp_conn; + struct sockaddr_in6 addr; + struct socket *sock; + int rc; +@@ -744,21 +756,36 @@ static int iscsi_sw_tcp_conn_get_param(struct iscsi_cls_conn *cls_conn, + case ISCSI_PARAM_CONN_ADDRESS: + case ISCSI_PARAM_LOCAL_PORT: + spin_lock_bh(&conn->session->frwd_lock); +- if (!tcp_sw_conn || !tcp_sw_conn->sock) { ++ if (!conn->session->leadconn) { + spin_unlock_bh(&conn->session->frwd_lock); + return -ENOTCONN; + } +- sock = tcp_sw_conn->sock; +- sock_hold(sock->sk); ++ /* ++ * The conn has been setup and bound, so just grab a ref ++ * incase a destroy runs while we are in the net layer. ++ */ ++ iscsi_get_conn(conn->cls_conn); + spin_unlock_bh(&conn->session->frwd_lock); + ++ tcp_conn = conn->dd_data; ++ tcp_sw_conn = tcp_conn->dd_data; ++ ++ mutex_lock(&tcp_sw_conn->sock_lock); ++ sock = tcp_sw_conn->sock; ++ if (!sock) { ++ rc = -ENOTCONN; ++ goto sock_unlock; ++ } ++ + if (param == ISCSI_PARAM_LOCAL_PORT) + rc = kernel_getsockname(sock, + (struct sockaddr *)&addr); + else + rc = kernel_getpeername(sock, + (struct sockaddr *)&addr); +- sock_put(sock->sk); ++sock_unlock: ++ mutex_unlock(&tcp_sw_conn->sock_lock); ++ iscsi_put_conn(conn->cls_conn); + if (rc < 0) + return rc; + +@@ -796,17 +823,21 @@ static int iscsi_sw_tcp_host_get_param(struct Scsi_Host *shost, + } + tcp_conn = conn->dd_data; + tcp_sw_conn = tcp_conn->dd_data; +- sock = tcp_sw_conn->sock; +- if (!sock) { +- spin_unlock_bh(&session->frwd_lock); +- return -ENOTCONN; +- } +- sock_hold(sock->sk); ++ /* ++ * The conn has been setup and bound, so just grab a ref ++ * incase a destroy runs while we are in the net layer. ++ */ ++ iscsi_get_conn(conn->cls_conn); + spin_unlock_bh(&session->frwd_lock); + +- rc = kernel_getsockname(sock, +- (struct sockaddr *)&addr); +- sock_put(sock->sk); ++ mutex_lock(&tcp_sw_conn->sock_lock); ++ sock = tcp_sw_conn->sock; ++ if (!sock) ++ rc = -ENOTCONN; ++ else ++ rc = kernel_getsockname(sock, (struct sockaddr *)&addr); ++ mutex_unlock(&tcp_sw_conn->sock_lock); ++ iscsi_put_conn(conn->cls_conn); + if (rc < 0) + return rc; + +diff --git a/drivers/scsi/iscsi_tcp.h b/drivers/scsi/iscsi_tcp.h +index 791453195099..1731956326e2 100644 +--- a/drivers/scsi/iscsi_tcp.h ++++ b/drivers/scsi/iscsi_tcp.h +@@ -28,6 +28,8 @@ struct iscsi_sw_tcp_send { + + struct iscsi_sw_tcp_conn { + struct socket *sock; ++ /* Taken when accessing the sock from the netlink/sysfs interface */ ++ struct mutex sock_lock; + + struct iscsi_sw_tcp_send out; + /* old values for socket callbacks */ +-- +2.35.1 + diff --git a/queue-5.10/scsi-libsas-fix-use-after-free-bug-in-smp_execute_ta.patch b/queue-5.10/scsi-libsas-fix-use-after-free-bug-in-smp_execute_ta.patch new file mode 100644 index 00000000000..4072d46b0a2 --- /dev/null +++ b/queue-5.10/scsi-libsas-fix-use-after-free-bug-in-smp_execute_ta.patch @@ -0,0 +1,54 @@ +From e66abea8f354d385b6f220f1a26b222f28c8bb42 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 22:42:13 +0800 +Subject: scsi: libsas: Fix use-after-free bug in smp_execute_task_sg() + +From: Duoming Zhou + +[ Upstream commit 46ba53c30666717cb06c2b3c5d896301cd00d0c0 ] + +When executing SMP task failed, the smp_execute_task_sg() calls del_timer() +to delete "slow_task->timer". However, if the timer handler +sas_task_internal_timedout() is running, the del_timer() in +smp_execute_task_sg() will not stop it and a UAF will happen. The process +is shown below: + + (thread 1) | (thread 2) +smp_execute_task_sg() | sas_task_internal_timedout() + ... | + del_timer() | + ... | ... + sas_free_task(task) | + kfree(task->slow_task) //FREE| + | task->slow_task->... //USE + +Fix by calling del_timer_sync() in smp_execute_task_sg(), which makes sure +the timer handler have finished before the "task->slow_task" is +deallocated. + +Link: https://lore.kernel.org/r/20220920144213.10536-1-duoming@zju.edu.cn +Fixes: 2908d778ab3e ("[SCSI] aic94xx: new driver") +Reviewed-by: Jason Yan +Signed-off-by: Duoming Zhou +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/libsas/sas_expander.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/libsas/sas_expander.c b/drivers/scsi/libsas/sas_expander.c +index 8d6bcc19359f..51485d0251f2 100644 +--- a/drivers/scsi/libsas/sas_expander.c ++++ b/drivers/scsi/libsas/sas_expander.c +@@ -85,7 +85,7 @@ static int smp_execute_task_sg(struct domain_device *dev, + res = i->dft->lldd_execute_task(task, GFP_KERNEL); + + if (res) { +- del_timer(&task->slow_task->timer); ++ del_timer_sync(&task->slow_task->timer); + pr_notice("executing SMP task failed:%d\n", res); + break; + } +-- +2.35.1 + diff --git a/queue-5.10/sctp-handle-the-error-returned-from-sctp_auth_asoc_i.patch b/queue-5.10/sctp-handle-the-error-returned-from-sctp_auth_asoc_i.patch new file mode 100644 index 00000000000..2716aefdc61 --- /dev/null +++ b/queue-5.10/sctp-handle-the-error-returned-from-sctp_auth_asoc_i.patch @@ -0,0 +1,79 @@ +From 5d26c99bc698397e3c367f6ebaa1a3ac75ac5772 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 28 Sep 2022 14:10:13 -0400 +Subject: sctp: handle the error returned from sctp_auth_asoc_init_active_key + +From: Xin Long + +[ Upstream commit 022152aaebe116a25c39818a07e175a8cd3c1e11 ] + +When it returns an error from sctp_auth_asoc_init_active_key(), the +active_key is actually not updated. The old sh_key will be freeed +while it's still used as active key in asoc. Then an use-after-free +will be triggered when sending patckets, as found by syzbot: + + sctp_auth_shkey_hold+0x22/0xa0 net/sctp/auth.c:112 + sctp_set_owner_w net/sctp/socket.c:132 [inline] + sctp_sendmsg_to_asoc+0xbd5/0x1a20 net/sctp/socket.c:1863 + sctp_sendmsg+0x1053/0x1d50 net/sctp/socket.c:2025 + inet_sendmsg+0x99/0xe0 net/ipv4/af_inet.c:819 + sock_sendmsg_nosec net/socket.c:714 [inline] + sock_sendmsg+0xcf/0x120 net/socket.c:734 + +This patch is to fix it by not replacing the sh_key when it returns +errors from sctp_auth_asoc_init_active_key() in sctp_auth_set_key(). +For sctp_auth_set_active_key(), old active_key_id will be set back +to asoc->active_key_id when the same thing happens. + +Fixes: 58acd1009226 ("sctp: update active_key for asoc when old key is being replaced") +Reported-by: syzbot+a236dd8e9622ed8954a3@syzkaller.appspotmail.com +Signed-off-by: Xin Long +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/sctp/auth.c | 18 ++++++++++++++---- + 1 file changed, 14 insertions(+), 4 deletions(-) + +diff --git a/net/sctp/auth.c b/net/sctp/auth.c +index db6b7373d16c..34964145514e 100644 +--- a/net/sctp/auth.c ++++ b/net/sctp/auth.c +@@ -863,12 +863,17 @@ int sctp_auth_set_key(struct sctp_endpoint *ep, + } + + list_del_init(&shkey->key_list); +- sctp_auth_shkey_release(shkey); + list_add(&cur_key->key_list, sh_keys); + +- if (asoc && asoc->active_key_id == auth_key->sca_keynumber) +- sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL); ++ if (asoc && asoc->active_key_id == auth_key->sca_keynumber && ++ sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL)) { ++ list_del_init(&cur_key->key_list); ++ sctp_auth_shkey_release(cur_key); ++ list_add(&shkey->key_list, sh_keys); ++ return -ENOMEM; ++ } + ++ sctp_auth_shkey_release(shkey); + return 0; + } + +@@ -902,8 +907,13 @@ int sctp_auth_set_active_key(struct sctp_endpoint *ep, + return -EINVAL; + + if (asoc) { ++ __u16 active_key_id = asoc->active_key_id; ++ + asoc->active_key_id = key_id; +- sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL); ++ if (sctp_auth_asoc_init_active_key(asoc, GFP_KERNEL)) { ++ asoc->active_key_id = active_key_id; ++ return -ENOMEM; ++ } + } else + ep->active_key_id = key_id; + +-- +2.35.1 + diff --git a/queue-5.10/selftest-tpm2-add-client.__del__-to-close-dev-tpm-ha.patch b/queue-5.10/selftest-tpm2-add-client.__del__-to-close-dev-tpm-ha.patch new file mode 100644 index 00000000000..b85f4ca9742 --- /dev/null +++ b/queue-5.10/selftest-tpm2-add-client.__del__-to-close-dev-tpm-ha.patch @@ -0,0 +1,49 @@ +From 1bab721ac608f50eb6e921d8e89db7e2f230f00d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 09:15:18 -0400 +Subject: selftest: tpm2: Add Client.__del__() to close /dev/tpm* handle + +From: Stefan Berger + +[ Upstream commit 2d869f0b458547386fbcd8cf3004b271b7347b7f ] + +The following output can bee seen when the test is executed: + + test_flush_context (tpm2_tests.SpaceTest) ... \ + /usr/lib64/python3.6/unittest/case.py:605: ResourceWarning: \ + unclosed file <_io.FileIO name='/dev/tpmrm0' mode='rb+' closefd=True> + +An instance of Client does not implicitly close /dev/tpm* handle, once it +gets destroyed. Close the file handle in the class destructor +Client.__del__(). + +Fixes: 6ea3dfe1e0732 ("selftests: add TPM 2.0 tests") +Cc: Shuah Khan +Cc: linux-kselftest@vger.kernel.org +Cc: Jarkko Sakkinen +Signed-off-by: Stefan Berger +Reviewed-by: Jarkko Sakkinen +Signed-off-by: Jarkko Sakkinen +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/tpm2/tpm2.py | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/tools/testing/selftests/tpm2/tpm2.py b/tools/testing/selftests/tpm2/tpm2.py +index f34486cd7342..3e67fdb518ec 100644 +--- a/tools/testing/selftests/tpm2/tpm2.py ++++ b/tools/testing/selftests/tpm2/tpm2.py +@@ -370,6 +370,10 @@ class Client: + fcntl.fcntl(self.tpm, fcntl.F_SETFL, flags) + self.tpm_poll = select.poll() + ++ def __del__(self): ++ if self.tpm: ++ self.tpm.close() ++ + def close(self): + self.tpm.close() + +-- +2.35.1 + diff --git a/queue-5.10/selftests-cpu-hotplug-use-return-instead-of-exit.patch b/queue-5.10/selftests-cpu-hotplug-use-return-instead-of-exit.patch new file mode 100644 index 00000000000..ae17358f505 --- /dev/null +++ b/queue-5.10/selftests-cpu-hotplug-use-return-instead-of-exit.patch @@ -0,0 +1,76 @@ +From f317e539879c89c5e23d871693fd551ebfc1b4ae Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Sep 2022 21:36:12 +0800 +Subject: selftests/cpu-hotplug: Use return instead of exit + +From: Zhao Gongyi + +[ Upstream commit 972cf4ce51ef5532d56822af17defb148aac0ccb ] + +Some cpus will be left in offline state when online +function exits in some error conditions. Use return +instead of exit to fix it. + +Signed-off-by: Zhao Gongyi +Signed-off-by: Shuah Khan +Signed-off-by: Sasha Levin +--- + .../selftests/cpu-hotplug/cpu-on-off-test.sh | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +diff --git a/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh b/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh +index 0d26b5e3f966..940b68c940bb 100755 +--- a/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh ++++ b/tools/testing/selftests/cpu-hotplug/cpu-on-off-test.sh +@@ -4,6 +4,7 @@ + SYSFS= + # Kselftest framework requirement - SKIP code is 4. + ksft_skip=4 ++retval=0 + + prerequisite() + { +@@ -102,10 +103,10 @@ online_cpu_expect_success() + + if ! online_cpu $cpu; then + echo $FUNCNAME $cpu: unexpected fail >&2 +- exit 1 ++ retval=1 + elif ! cpu_is_online $cpu; then + echo $FUNCNAME $cpu: unexpected offline >&2 +- exit 1 ++ retval=1 + fi + } + +@@ -128,10 +129,10 @@ offline_cpu_expect_success() + + if ! offline_cpu $cpu; then + echo $FUNCNAME $cpu: unexpected fail >&2 +- exit 1 ++ retval=1 + elif ! cpu_is_offline $cpu; then + echo $FUNCNAME $cpu: unexpected offline >&2 +- exit 1 ++ retval=1 + fi + } + +@@ -201,7 +202,7 @@ if [ $allcpus -eq 0 ]; then + offline_cpu_expect_success $present_max + online_cpu $present_max + fi +- exit 0 ++ exit $retval + else + echo "Full scope test: all hotplug cpus" + echo -e "\t online all offline cpus" +@@ -291,3 +292,5 @@ done + + echo 0 > $NOTIFIER_ERR_INJECT_DIR/actions/CPU_DOWN_PREPARE/error + /sbin/modprobe -q -r cpu-notifier-error-inject ++ ++exit $retval +-- +2.35.1 + diff --git a/queue-5.10/selftests-xsk-avoid-use-after-free-on-ctx.patch b/queue-5.10/selftests-xsk-avoid-use-after-free-on-ctx.patch new file mode 100644 index 00000000000..3d12cea332e --- /dev/null +++ b/queue-5.10/selftests-xsk-avoid-use-after-free-on-ctx.patch @@ -0,0 +1,47 @@ +From af0f2cb86a92511df114587519c802172505c3f9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 13:26:45 -0700 +Subject: selftests/xsk: Avoid use-after-free on ctx + +From: Ian Rogers + +[ Upstream commit af515a5587b8f45f19e11657746e0c89411b0380 ] + +The put lowers the reference count to 0 and frees ctx, reading it +afterwards is invalid. Move the put after the uses and determine the +last use by the reference count being 1. + +Fixes: 39e940d4abfa ("selftests/xsk: Destroy BPF resources only when ctx refcount drops to 0") +Signed-off-by: Ian Rogers +Signed-off-by: Daniel Borkmann +Acked-by: Magnus Karlsson +Link: https://lore.kernel.org/bpf/20220901202645.1463552-1-irogers@google.com +Signed-off-by: Sasha Levin +--- + tools/lib/bpf/xsk.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/tools/lib/bpf/xsk.c b/tools/lib/bpf/xsk.c +index e8745f646371..fa1f8faf7dfe 100644 +--- a/tools/lib/bpf/xsk.c ++++ b/tools/lib/bpf/xsk.c +@@ -930,13 +930,13 @@ void xsk_socket__delete(struct xsk_socket *xsk) + ctx = xsk->ctx; + umem = ctx->umem; + +- xsk_put_ctx(ctx, true); +- +- if (!ctx->refcount) { ++ if (ctx->refcount == 1) { + xsk_delete_bpf_maps(xsk); + close(ctx->prog_fd); + } + ++ xsk_put_ctx(ctx, true); ++ + err = xsk_get_mmap_offsets(xsk->fd, &off); + if (!err) { + if (xsk->rx) { +-- +2.35.1 + diff --git a/queue-5.10/serial-8250-add-an-empty-line-and-remove-some-useles.patch b/queue-5.10/serial-8250-add-an-empty-line-and-remove-some-useles.patch new file mode 100644 index 00000000000..f8230d920ef --- /dev/null +++ b/queue-5.10/serial-8250-add-an-empty-line-and-remove-some-useles.patch @@ -0,0 +1,50 @@ +From 7e4652de01e2422152d829fa6fc80f3237ed6f23 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 28 Apr 2021 09:30:52 +0200 +Subject: serial: 8250: Add an empty line and remove some useless {} + +From: Christophe JAILLET + +[ Upstream commit 26f7591632d74f637f346f5d642d8ebe6b433fc9 ] + +This fixes the following checkpatch.pl warnings: + WARNING: Missing a blank line after declarations + WARNING: braces {} are not necessary for any arm of this statement + +Reviewed-by: Andy Shevchenko +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/257ffd691b4a062ad017333c9430d69da6dbd29a.1619594713.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: 039d4926379b ("serial: 8250: Toggle IER bits on only after irq has been set up") +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/8250/8250_core.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c +index 98ce484f1089..aae9d26ce4f4 100644 +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -332,9 +332,9 @@ static int univ8250_setup_irq(struct uart_8250_port *up) + * hardware interrupt, we use a timer-based system. The original + * driver used to do this with IRQ0. + */ +- if (!port->irq) { ++ if (!port->irq) + mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); +- } else ++ else + retval = serial_link_irq_chain(up); + + return retval; +@@ -766,6 +766,7 @@ void serial8250_suspend_port(int line) + if (!console_suspend_enabled && uart_console(port) && + port->type != PORT_8250) { + unsigned char canary = 0xa5; ++ + serial_out(up, UART_SCR, canary); + if (serial_in(up, UART_SCR) == canary) + up->canary = canary; +-- +2.35.1 + diff --git a/queue-5.10/serial-8250-fix-restoring-termios-speed-after-suspen.patch b/queue-5.10/serial-8250-fix-restoring-termios-speed-after-suspen.patch new file mode 100644 index 00000000000..f5dc7007578 --- /dev/null +++ b/queue-5.10/serial-8250-fix-restoring-termios-speed-after-suspen.patch @@ -0,0 +1,54 @@ +From f863ab9a0037b77dc935b3df402c1676d4b0fde5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 24 Sep 2022 12:43:24 +0200 +Subject: serial: 8250: Fix restoring termios speed after suspend +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +[ Upstream commit 379a33786d489ab81885ff0b3935cfeb36137fea ] + +Since commit edc6afc54968 ("tty: switch to ktermios and new framework") +termios speed is no longer stored only in c_cflag member but also in new +additional c_ispeed and c_ospeed members. If BOTHER flag is set in c_cflag +then termios speed is stored only in these new members. + +Since commit 027b57170bf8 ("serial: core: Fix initializing and restoring +termios speed") termios speed is available also in struct console. + +So properly restore also c_ispeed and c_ospeed members after suspend to fix +restoring termios speed which is not represented by Bnnn constant. + +Fixes: 4516d50aabed ("serial: 8250: Use canary to restart console after suspend") +Signed-off-by: Pali Rohár +Link: https://lore.kernel.org/r/20220924104324.4035-1-pali@kernel.org +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/8250/8250_port.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c +index 4a0793e1ba61..ecd2b3d252ec 100644 +--- a/drivers/tty/serial/8250/8250_port.c ++++ b/drivers/tty/serial/8250/8250_port.c +@@ -3289,8 +3289,13 @@ static void serial8250_console_restore(struct uart_8250_port *up) + unsigned int baud, quot, frac = 0; + + termios.c_cflag = port->cons->cflag; +- if (port->state->port.tty && termios.c_cflag == 0) ++ termios.c_ispeed = port->cons->ispeed; ++ termios.c_ospeed = port->cons->ospeed; ++ if (port->state->port.tty && termios.c_cflag == 0) { + termios.c_cflag = port->state->port.tty->termios.c_cflag; ++ termios.c_ispeed = port->state->port.tty->termios.c_ispeed; ++ termios.c_ospeed = port->state->port.tty->termios.c_ospeed; ++ } + + baud = serial8250_get_baud_rate(port, &termios, NULL); + quot = serial8250_get_divisor(port, baud, &frac); +-- +2.35.1 + diff --git a/queue-5.10/serial-8250-toggle-ier-bits-on-only-after-irq-has-be.patch b/queue-5.10/serial-8250-toggle-ier-bits-on-only-after-irq-has-be.patch new file mode 100644 index 00000000000..722f8639656 --- /dev/null +++ b/queue-5.10/serial-8250-toggle-ier-bits-on-only-after-irq-has-be.patch @@ -0,0 +1,143 @@ +From f21342f02ced1a14c9d248eed8a65e4aee2c8cec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 10:00:05 +0300 +Subject: serial: 8250: Toggle IER bits on only after irq has been set up +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ilpo Järvinen + +[ Upstream commit 039d4926379b1d1c17b51cf21c500a5eed86899e ] + +Invoking TIOCVHANGUP on 8250_mid port on Ice Lake-D and then reopening +the port triggers these faults during serial8250_do_startup(): + + DMAR: DRHD: handling fault status reg 3 + DMAR: [DMA Write NO_PASID] Request device [00:1a.0] fault addr 0x0 [fault reason 0x05] PTE Write access is not set + +If the IRQ hasn't been set up yet, the UART will have zeroes in its MSI +address/data registers. Disabling the IRQ at the interrupt controller +won't stop the UART from performing a DMA write to the address programmed +in its MSI address register (zero) when it wants to signal an interrupt. + +The UARTs (in Ice Lake-D) implement PCI 2.1 style MSI without masking +capability, so there is no way to mask the interrupt at the source PCI +function level, except disabling the MSI capability entirely, but that +would cause it to fall back to INTx# assertion, and the PCI specification +prohibits disabling the MSI capability as a way to mask a function's +interrupt service request. + +The MSI address register is zeroed by the hangup as the irq is freed. +The interrupt is signalled during serial8250_do_startup() performing a +THRE test that temporarily toggles THRI in IER. The THRE test currently +occurs before UART's irq (and MSI address) is properly set up. + +Refactor serial8250_do_startup() such that irq is set up before the +THRE test. The current irq setup code is intermixed with the timer +setup code. As THRE test must be performed prior to the timer setup, +extract it into own function and call it only after the THRE test. + +The ->setup_timer() needs to be part of the struct uart_8250_ops in +order to not create circular dependency between 8250 and 8250_base +modules. + +Fixes: 40b36daad0ac ("[PATCH] 8250 UART backup timer") +Reported-by: Lennert Buytenhek +Tested-by: Lennert Buytenhek +Reviewed-by: Andy Shevchenko +Signed-off-by: Ilpo Järvinen +Link: https://lore.kernel.org/r/20220922070005.2965-1-ilpo.jarvinen@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/8250/8250_core.c | 16 +++++++++++----- + drivers/tty/serial/8250/8250_port.c | 8 +++++--- + include/linux/serial_8250.h | 1 + + 3 files changed, 17 insertions(+), 8 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c +index aae9d26ce4f4..0a7e9491b4d1 100644 +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -310,10 +310,9 @@ static void serial8250_backup_timeout(struct timer_list *t) + jiffies + uart_poll_timeout(&up->port) + HZ / 5); + } + +-static int univ8250_setup_irq(struct uart_8250_port *up) ++static void univ8250_setup_timer(struct uart_8250_port *up) + { + struct uart_port *port = &up->port; +- int retval = 0; + + /* + * The above check will only give an accurate result the first time +@@ -334,10 +333,16 @@ static int univ8250_setup_irq(struct uart_8250_port *up) + */ + if (!port->irq) + mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); +- else +- retval = serial_link_irq_chain(up); ++} + +- return retval; ++static int univ8250_setup_irq(struct uart_8250_port *up) ++{ ++ struct uart_port *port = &up->port; ++ ++ if (port->irq) ++ return serial_link_irq_chain(up); ++ ++ return 0; + } + + static void univ8250_release_irq(struct uart_8250_port *up) +@@ -393,6 +398,7 @@ static struct uart_ops univ8250_port_ops; + static const struct uart_8250_ops univ8250_driver_ops = { + .setup_irq = univ8250_setup_irq, + .release_irq = univ8250_release_irq, ++ .setup_timer = univ8250_setup_timer, + }; + + static struct uart_8250_port serial8250_ports[UART_NR]; +diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c +index 6de188b121d7..4a0793e1ba61 100644 +--- a/drivers/tty/serial/8250/8250_port.c ++++ b/drivers/tty/serial/8250/8250_port.c +@@ -2277,6 +2277,10 @@ int serial8250_do_startup(struct uart_port *port) + if (port->irq && (up->port.flags & UPF_SHARE_IRQ)) + up->port.irqflags |= IRQF_SHARED; + ++ retval = up->ops->setup_irq(up); ++ if (retval) ++ goto out; ++ + if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) { + unsigned char iir1; + +@@ -2319,9 +2323,7 @@ int serial8250_do_startup(struct uart_port *port) + } + } + +- retval = up->ops->setup_irq(up); +- if (retval) +- goto out; ++ up->ops->setup_timer(up); + + /* + * Now, initialize the UART +diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h +index 2b70f736b091..92f3b778d8c2 100644 +--- a/include/linux/serial_8250.h ++++ b/include/linux/serial_8250.h +@@ -74,6 +74,7 @@ struct uart_8250_port; + struct uart_8250_ops { + int (*setup_irq)(struct uart_8250_port *); + void (*release_irq)(struct uart_8250_port *); ++ void (*setup_timer)(struct uart_8250_port *); + }; + + struct uart_8250_em485 { +-- +2.35.1 + diff --git a/queue-5.10/series b/queue-5.10/series index 404377fdf4c..980fc2400fd 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -89,3 +89,370 @@ drm-i915-fix-watermark-calculations-for-gen12-rc-ccs-modifier.patch drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch smb3-must-initialize-two-acl-struct-fields-to-zero.patch selinux-use-grep-e-instead-of-egrep.patch +userfaultfd-open-userfaultfds-with-o_rdonly.patch +sh-machvec-use-char-for-section-boundaries.patch +mips-sgi-ip27-free-some-unused-memory.patch +mips-sgi-ip27-fix-platform-device-leak-in-bridge_pla.patch +fscrypt-simplify-master-key-locking.patch +fs-security-add-sb_delete-hook.patch +fscrypt-stop-using-keyrings-subsystem-for-fscrypt_ma.patch +arm-9244-1-dump-fix-wrong-pg_level-in-walk_pmd.patch +arm-9247-1-mm-set-readonly-for-mt_memory_ro-with-arm.patch +objtool-preserve-special-st_shndx-indexes-in-elf_upd.patch +nfsd-fix-a-memory-leak-in-an-error-handling-path.patch +wifi-ath10k-add-peer-map-clean-up-for-peer-delete-in.patch +leds-lm3601x-don-t-use-mutex-after-it-was-destroyed.patch +wifi-mac80211-allow-bw-change-during-channel-switch-.patch +bpftool-fix-a-wrong-type-cast-in-btf_dumper_int.patch +spi-mt7621-fix-an-error-message-in-mt7621_spi_probe.patch +x86-resctrl-fix-to-restore-to-original-value-when-re.patch +bluetooth-btusb-fine-tune-mt7663-mechanism.patch +bluetooth-btusb-fix-excessive-stack-usage.patch +bluetooth-btusb-mediatek-fix-wmt-failure-during-runt.patch +wifi-rtl8xxxu-tighten-bounds-checking-in-rtl8xxxu_re.patch +selftests-xsk-avoid-use-after-free-on-ctx.patch +spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch +spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch-14793 +can-rx-offload-can_rx_offload_init_queue-fix-typo.patch +wifi-rtl8xxxu-fix-skb-misuse-in-tx-queue-selection.patch +spi-meson-spicc-do-not-rely-on-busy-flag-in-pow2-clk.patch +bpf-btf-fix-truncated-last_member_type_id-in-btf_str.patch +wifi-rtl8xxxu-gen2-fix-mistake-in-path-b-iq-calibrat.patch +wifi-rtl8xxxu-remove-copy-paste-leftover-in-gen2_upd.patch +net-fs_enet-fix-wrong-check-in-do_pd_setup.patch +bpf-ensure-correct-locking-around-vulnerable-functio.patch +bluetooth-hci_-ldisc-serdev-check-percpu_init_rwsem-.patch +wifi-ath11k-fix-number-of-vht-beamformee-spatial-str.patch +x86-microcode-amd-track-patch-allocation-size-explic.patch +x86-cpu-include-the-header-of-init_ia32_feat_ctl-s-p.patch +spi-dw-fix-pm-disable-depth-imbalance-in-dw_spi_bt1_.patch +spi-omap100k-fix-pm-disable-depth-imbalance-in-omap1.patch +i2c-mlxbf-support-lock-mechanism.patch +bluetooth-hci_core-fix-not-handling-link-timeouts-pr.patch +netfilter-nft_fib-fix-for-rpath-check-with-vrf-devic.patch +spi-s3c64xx-fix-large-transfers-with-dma.patch +wifi-rtl8xxxu-fix-aifs-written-to-reg_edca_-_param.patch +vhost-vsock-use-kvmalloc-kvfree-for-larger-packets.patch +misdn-fix-use-after-free-bugs-in-l1oip-timer-handler.patch +sctp-handle-the-error-returned-from-sctp_auth_asoc_i.patch +tcp-fix-tcp_cwnd_validate-to-not-forget-is_cwnd_limi.patch +spi-ensure-that-sg_table-won-t-be-used-after-being-f.patch +net-rds-don-t-hold-sock-lock-when-cancelling-work-fr.patch +bnx2x-fix-potential-memory-leak-in-bnx2x_tpa_stop.patch +net-ieee802154-reject-zero-sized-raw_sendmsg.patch +once-add-do_once_slow-for-sleepable-contexts.patch +net-mvpp2-fix-mvpp2-debugfs-leak.patch +drm-bridge-adv7511-fix-cec-power-down-control-regist.patch +drm-bridge-avoid-uninitialized-variable-warning.patch +drm-mipi-dsi-detach-devices-when-removing-the-host.patch +drm-bridge-parade-ps8640-use-regmap-apis.patch +drm-bridge-parade-ps8640-add-support-for-aux-channel.patch +drm-bridge-parade-ps8640-enable-runtime-power-manage.patch +drm-bridge-parade-ps8640-fix-regulator-supply-order.patch +net-wwan-t7xx-add-control-dma-interface.patch +drm-dp_mst-fix-drm_dp_dpcd_read-return-value-checks.patch +drm-pl111-add-of_node_put-when-breaking-out-of-for_e.patch +drm-msm-make-.remove-and-.shutdown-hw-shutdown-consi.patch +platform-chrome-fix-double-free-in-chromeos_laptop_p.patch +platform-chrome-fix-memory-corruption-in-ioctl.patch +asoc-tas2764-allow-mono-streams.patch +asoc-tas2764-drop-conflicting-set_bias_level-power-s.patch +asoc-tas2764-fix-mute-unmute.patch +platform-x86-msi-laptop-fix-old-ec-check-for-backlig.patch +platform-x86-msi-laptop-fix-resource-cleanup.patch +drm-fix-drm_mipi_dbi-build-errors.patch +drm-bridge-megachips-fix-a-null-pointer-dereference-.patch +asoc-rsnd-add-check-for-rsnd_mod_power_on.patch +alsa-hda-beep-simplify-keep-power-at-enable-behavior.patch +drm-omap-dss-fix-refcount-leak-bugs.patch +mmc-au1xmmc-fix-an-error-handling-path-in-au1xmmc_pr.patch +asoc-eureka-tlv320-hold-reference-returned-from-of_f.patch +drm-msm-dpu-index-dpu_kms-hw_vbif-using-vbif_idx.patch +drm-msm-dp-correct-1.62g-link-rate-at-dp_catalog_ctr.patch +asoc-da7219-fix-an-error-handling-path-in-da7219_reg.patch +alsa-dmaengine-increment-buffer-pointer-atomically.patch +mmc-wmt-sdmmc-fix-an-error-handling-path-in-wmt_mci_.patch +asoc-wm8997-fix-pm-disable-depth-imbalance-in-wm8997.patch +asoc-wm5110-fix-pm-disable-depth-imbalance-in-wm5110.patch +asoc-wm5102-fix-pm-disable-depth-imbalance-in-wm5102.patch +asoc-mt6660-fix-pm-disable-depth-imbalance-in-mt6660.patch +alsa-hda-hdmi-don-t-skip-notification-handling-durin.patch +memory-pl353-smc-fix-refcount-leak-bug-in-pl353_smc_.patch +memory-of-fix-refcount-leak-bug-in-of_get_ddr_timing.patch +memory-of-fix-refcount-leak-bug-in-of_lpddr3_get_ddr.patch +soc-qcom-smsm-fix-refcount-leak-bugs-in-qcom_smsm_pr.patch +soc-qcom-smem_state-add-refcounting-for-the-state-of.patch +arm-dts-turris-omnia-fix-mpp26-pin-name-and-comment.patch +arm-dts-kirkwood-lsxl-fix-serial-line.patch +arm-dts-kirkwood-lsxl-remove-first-ethernet-port.patch +ia64-export-memory_add_physaddr_to_nid-to-fix-cxl-bu.patch +soc-tegra-fuse-drop-kconfig-dependency-on-tegra20_ap.patch +arm64-dts-qcom-fix-ipq8074-pcie-phy-nodes.patch +arm64-dts-qcom-ipq8074-fix-pcie-phy-serdes-size.patch +arm-dts-exynos-correct-s5k6a3-reset-polarity-on-mida.patch +arm-drop-cmdline_-dependency-on-atags.patch +arm64-ftrace-fix-module-plts-with-mcount.patch +arm-dts-exynos-fix-polarity-of-vbus-gpio-of-origen.patch +iio-adc-at91-sama5d2_adc-fix-at91_sama5d2_mr_trackti.patch +iio-adc-at91-sama5d2_adc-check-return-status-for-pre.patch +iio-adc-at91-sama5d2_adc-lock-around-oversampling-an.patch +iio-adc-at91-sama5d2_adc-disable-prepare-buffer-on-s.patch +iio-inkern-only-release-the-device-node-when-done-wi.patch +iio-abi-fix-wrong-format-of-differential-capacitance.patch +usb-ch9-add-usb-3.2-ssp-attributes.patch +usb-common-parse-for-usb-ssp-genxxy.patch +usb-common-add-function-to-get-interval-expressed-in.patch +usb-common-move-function-s-kerneldoc-next-to-its-def.patch +usb-common-debug-check-non-standard-control-requests.patch +clk-meson-hold-reference-returned-by-of_get_parent.patch +clk-oxnas-hold-reference-returned-by-of_get_parent.patch +clk-qoriq-hold-reference-returned-by-of_get_parent.patch +clk-berlin-add-of_node_put-for-of_get_parent.patch +clk-sprd-hold-reference-returned-by-of_get_parent.patch +clk-tegra-fix-refcount-leak-in-tegra210_clock_init.patch +clk-tegra-fix-refcount-leak-in-tegra114_clock_init.patch +clk-tegra20-fix-refcount-leak-in-tegra20_clock_init.patch +sbitmap-fix-possible-io-hung-due-to-lost-wakeup.patch +hid-uclogic-make-template-placeholder-ids-generic.patch +hid-uclogic-fix-warning-in-uclogic_rdesc_template_ap.patch +hsi-omap_ssi-fix-refcount-leak-in-ssi_probe.patch +hsi-omap_ssi_port-fix-dma_map_sg-error-check.patch +clk-qcom-gcc-sdm660-move-parent-tables-after-plls.patch +clk-qcom-gcc-sdm660-replace-usage-of-parent_names.patch +clk-qcom-gcc-sdm660-use-array_size-for-num_parents.patch +clk-qcom-gcc-sdm660-use-floor-ops-for-sdcc1-clock.patch +media-exynos4-is-fimc-is-add-of_node_put-when-breaki.patch +media-tm6000-fix-unused-value-in-vidioc_try_fmt_vid_.patch +tty-xilinx_uartps-fix-the-ignore_status.patch +media-meson-vdec-add-missing-clk_disable_unprepare-o.patch +media-xilinx-vipp-fix-refcount-leak-in-xvip_graph_dm.patch +rdma-rxe-fix-kernel-null-pointer-dereference-error.patch +rdma-rxe-fix-the-error-caused-by-qp-sk.patch +misc-ocxl-fix-possible-refcount-leak-in-afu_ioctl.patch +fpga-prevent-integer-overflow-in-dfl_feature_ioctl_s.patch +dmaengine-hisilicon-disable-channels-when-unregister.patch +dmaengine-hisilicon-fix-cq-head-update.patch +dmaengine-hisilicon-add-multi-thread-support-for-a-d.patch +dyndbg-fix-static_branch-manipulation.patch +dyndbg-fix-module.dyndbg-handling.patch +dyndbg-let-query-modname-override-actual-module-name.patch +dyndbg-drop-exported-dynamic_debug_exec_queries.patch +sbitmap-avoid-leaving-waitqueue-in-invalid-state-in-.patch +usb-serial-console-move-mutex_unlock-before-usb_seri.patch +mtd-devices-docg3-check-the-return-value-of-devm_ior.patch +phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch +phy-qcom-qmp-combo-disable-runtime-pm-on-unbind.patch +phy-qcom-qmp-usb-disable-runtime-pm-on-unbind.patch +phy-qcom-qmp-pcie-msm8996-drop-all-compatibles-excep.patch +phy-qcom-qmp-pcie-change-symbol-prefix-to-qcom_qmp_p.patch +phy-qcom-qmp-pcie-msm8996-drop-support-for-non-pcie-.patch +phy-qcom-qmp-pcie-msm8996-cleanup-the-driver.patch +phy-qcom-qmp-pcie-msm8996-fix-memleak-on-probe-defer.patch +phy-qcom-qmp-combo-fix-memleak-on-probe-deferral.patch +phy-qcom-qmp-ufs-fix-memleak-on-probe-deferral.patch +phy-qcom-qmp-usb-drop-all-non-usb-compatibles-suppor.patch +phy-qcom-qmp-usb-change-symbol-prefix-to-qcom_qmp_ph.patch +phy-qcom-qmp-usb-drop-support-for-non-usb-phy-types.patch +phy-qcom-qmp-usb-cleanup-the-driver.patch +phy-qcom-qmp-usb-clean-up-pipe-clock-handling.patch +phy-qcom-qmp-usb-drop-pipe-clock-lane-suffix.patch +phy-qcom-qmp-usb-fix-memleak-on-probe-deferral.patch +mtd-rawnand-fsl_elbc-fix-none-ecc-mode.patch +rdma-siw-always-consume-all-skbuf-data-in-sk_data_re.patch +rdma-rdmavt-decouple-qp-and-sge-lists-allocations.patch +ata-fix-ata_id_sense_reporting_enabled-and-ata_id_ha.patch +ata-fix-ata_id_has_devslp.patch +ata-fix-ata_id_has_ncq_autosense.patch +ata-fix-ata_id_has_dipm.patch +mtd-rawnand-meson-fix-bit-map-use-in-meson_nfc_ecc_c.patch +md-raid1-rename-print_msg-with-r1bio_existed.patch +md-add-support-for-req_nowait.patch +md-raid5-add-__rcu-annotation-to-struct-disk_info.patch +md-replace-role-magic-numbers-with-defined-constants.patch +md-remove-most-calls-to-bdevname.patch +md-replace-snprintf-with-scnprintf.patch +md-raid5-ensure-stripe_fill-happens-on-non-read-io-w.patch +rdma-cm-use-slid-in-the-work-completion-as-the-dlid-.patch +rdma-uverbs-allow-drivers-to-create-a-new-hw-object-.patch +ib-set-iova-length-on-ib_mr-in-core-uverbs-layers.patch +xhci-don-t-show-warning-for-reinit-on-known-broken-s.patch +usb-gadget-function-fix-dangling-pnp_string-in-f_pri.patch +drivers-serial-jsm-fix-some-leaks-in-probe.patch +serial-8250-add-an-empty-line-and-remove-some-useles.patch +serial-8250-toggle-ier-bits-on-only-after-irq-has-be.patch +tty-serial-fsl_lpuart-disable-dma-rx-tx-use-flags-in.patch +phy-qualcomm-call-clk_disable_unprepare-in-the-error.patch +staging-vt6655-fix-some-erroneous-memory-clean-up-lo.patch +firmware-google-test-spinlock-on-panic-path-to-avoid.patch +serial-8250-fix-restoring-termios-speed-after-suspen.patch +scsi-libsas-fix-use-after-free-bug-in-smp_execute_ta.patch +scsi-iscsi-iscsi_tcp-fix-null-ptr-deref-while-callin.patch +clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch +clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch +clk-qcom-apss-ipq6018-mark-apcs_alias0_core_clk-as-c.patch +ib-rdmavt-add-__init-__exit-annotations-to-module-in.patch +fsi-core-check-error-number-after-calling-ida_simple.patch +mfd-intel_soc_pmic-fix-an-error-handling-path-in-int.patch +mfd-fsl-imx25-fix-an-error-handling-path-in-mx25_tsa.patch +mfd-lp8788-fix-an-error-handling-path-in-lp8788_prob.patch +mfd-lp8788-fix-an-error-handling-path-in-lp8788_irq_.patch +mfd-fsl-imx25-fix-check-for-platform_get_irq-errors.patch +mfd-sm501-add-check-for-platform_driver_register.patch +clk-mediatek-mt8183-mfgcfg-propagate-rate-changes-to.patch +dmaengine-ioat-stop-mod_timer-from-resurrecting-dele.patch +spmi-pmic-arb-correct-duplicate-apid-to-ppid-mapping.patch +clk-vc5-fix-5p49v6901-outputs-disabling-when-enablin.patch +clk-baikal-t1-fix-invalid-xgmac-ptp-clock-divider.patch +clk-baikal-t1-add-shared-xgmac-ref-ptp-clocks-intern.patch +clk-baikal-t1-add-sata-internal-ref-clock-buffer.patch +clk-bcm2835-fix-bcm2835_clock_rate_from_divisor-decl.patch +clk-ti-dra7-atl-fix-reference-leak-in-of_dra7_atl_cl.patch +clk-ast2600-bclk-comes-from-epll.patch +mailbox-bcm-ferxrm-mailbox-fix-error-check-for-dma_m.patch +kvm-x86-mmu-fix-memoryleak-in-kvm_mmu_vendor_module_.patch +powerpc-math_emu-efp-include-module.h.patch +powerpc-sysdev-fsl_msi-add-missing-of_node_put.patch +powerpc-pci_dn-add-missing-of_node_put.patch +powerpc-powernv-add-missing-of_node_put-in-opal_expo.patch +x86-hyperv-fix-struct-hv_enlightened_vmcs-definition.patch +kvm-x86-pending-exceptions-must-not-be-blocked-by-an.patch +kvm-nvmx-treat-general-detect-db-dr7.gd-1-as-fault-l.patch +kvm-nvmx-prioritize-tss-t-flag-dbs-over-monitor-trap.patch +powerpc-64s-fix-generic_cpu-build-flags-for-ppc970-g.patch +powerpc-fix-spe-power-isa-properties-for-e500v1-plat.patch +powerpc-lib-code-patching-don-t-use-struct-ppc_inst-.patch +crypto-sahara-don-t-sleep-when-in-softirq.patch +crypto-hisilicon-zip-fix-mismatch-in-get-set-sgl_sge.patch +kernel-cgroup-mundane-spelling-fixes-throughout-the-.patch +scsi-cgroup-add-cgroup_get_from_id.patch +cgroup-reduce-dependency-on-cgroup_mutex.patch +cgroup-honor-caller-s-cgroup-ns-when-resolving-path.patch +clk-generalize-devm_clk_get-a-bit.patch +clk-provide-new-devm_clk-helpers-for-prepared-and-en.patch +hwrng-imx-rngc-use-devm_clk_get_enabled.patch +hwrng-imx-rngc-moving-irq-handler-registering-after-.patch +cgroup-cpuset-enable-update_tasks_cpumask-on-top_cpu.patch +iommu-omap-fix-buffer-overflow-in-debugfs.patch +crypto-akcipher-default-implementation-for-setting-a.patch +crypto-ccp-release-dma-channels-before-dmaengine-unr.patch +crypto-inside-secure-change-swab-to-swab32.patch +crypto-qat-fix-use-of-dma_map_single.patch +crypto-qat-use-pre-allocated-buffers-in-datapath.patch +crypto-qat-fix-dma-transfer-direction.patch +iommu-iova-fix-module-config-properly.patch +tracing-kprobe-fix-kprobe-event-gen-test-module-on-e.patch +tracing-kprobe-make-gen-test-module-work-in-arm-and-.patch +kbuild-remove-the-target-in-signal-traps-when-interr.patch +kbuild-rpm-pkg-fix-breakage-when-v-1-is-used.patch +crypto-marvell-octeontx-prevent-integer-overflows.patch +crypto-cavium-prevent-integer-overflow-loading-firmw.patch +thermal-drivers-qcom-tsens-v0_1-fix-msm8939-fourth-s.patch +acpi-apei-do-not-add-task_work-to-kernel-thread-to-a.patch +f2fs-fix-race-condition-on-setting-fi_no_extent-flag.patch +f2fs-fix-to-avoid-req_time-and-cp_time-collision.patch +f2fs-fix-to-account-fs_cp_data_io-correctly.patch +selftest-tpm2-add-client.__del__-to-close-dev-tpm-ha.patch +rcu-back-off-upon-fill_page_cache_func-allocation-fa.patch +rcu-tasks-convert-rcu_lockdep_warn-to-warn_once.patch +acpi-video-add-toshiba-satellite-portege-z830-quirk.patch +mips-bcm47xx-cast-memcmp-of-function-to-void.patch +powercap-intel_rapl-fix-ubsan-shift-out-of-bounds-is.patch +thermal-intel_powerclamp-use-get_cpu-instead-of-smp_.patch +arm-decompressor-include-.data.rel.ro.local.patch +x86-entry-work-around-clang-__bdos-bug.patch +nfsd-return-nfserr_serverfault-if-splice_ok-but-buf-.patch +nfsd-fix-use-after-free-on-source-server-when-doing-.patch +wifi-rtw88-phy-fix-warning-of-possible-buffer-overfl.patch +wifi-brcmfmac-fix-invalid-address-access-when-enabli.patch +bpftool-clear-errno-after-libcap-s-checks.patch +openvswitch-fix-double-reporting-of-drops-in-dropwat.patch +openvswitch-fix-overreporting-of-drops-in-dropwatch.patch +tcp-annotate-data-race-around-tcp_md5sig_pool_popula.patch +micrel-ksz8851-fixes-struct-pointer-issue.patch +wifi-ath9k-avoid-uninit-memory-read-in-ath9k_htc_rx_.patch +xfrm-update-ipcomp_scratches-with-null-when-freed.patch +net-xscale-fix-return-type-for-implementation-of-ndo.patch +net-lantiq_etop-fix-return-type-for-implementation-o.patch +net-ftmac100-fix-endianness-related-issues-from-spar.patch +wifi-brcmfmac-fix-use-after-free-bug-in-brcmf_netdev.patch +regulator-core-prevent-integer-underflow.patch +bluetooth-l2cap-initialize-delayed-works-at-l2cap_ch.patch +net-davicom-fix-return-type-of-dm9000_start_xmit.patch +net-ethernet-ti-davinci_emac-fix-return-type-of-emac.patch +net-korina-fix-return-type-of-korina_send_packet.patch +bluetooth-hci_sysfs-fix-attempting-to-call-device_ad.patch +wifi-ath10k-reset-pointer-after-memory-free-to-avoid.patch +can-bcm-check-the-result-of-can_send-in-bcm_can_tx.patch +wifi-rt2x00-don-t-run-rt5592-iq-calibration-on-mt762.patch +wifi-rt2x00-set-correct-tx_sw_cfg1-mac-register-for-.patch +wifi-rt2x00-set-vgc-gain-for-both-chains-of-mt7620.patch +wifi-rt2x00-set-soc-wmac-clock-register.patch +wifi-rt2x00-correctly-set-bbp-register-86-for-mt7620.patch +net-if-sock-is-dead-don-t-access-sock-s-sk_wq-in-sk_.patch +bluetooth-l2cap-fix-user-after-free.patch +libbpf-fix-overrun-in-netlink-attribute-iteration.patch +r8152-rate-limit-overflow-messages.patch +drm-nouveau-nouveau_bo-fix-potential-memory-leak-in-.patch +drm-use-size_t-type-for-len-variable-in-drm_copy_fie.patch +drm-prevent-drm_copy_field-to-attempt-copying-a-null.patch +gpu-lontium-lt9611-fix-null-pointer-dereference-in-l.patch +drm-amd-display-fix-overflow-on-min_i64-definition.patch +alsa-usb-audio-add-quirk-to-enable-avid-mbox-3-suppo.patch +udmabuf-set-ubuf-sg-null-if-the-creation-of-sg-table.patch +drm-bridge-dw_hdmi-only-trigger-hotplug-event-on-lin.patch +drm-vc4-vec-fix-timings-for-vec-modes.patch +drm-panel-orientation-quirks-add-quirk-for-anbernic-.patch +platform-chrome-cros_ec-notify-the-pm-of-wake-events.patch +platform-x86-msi-laptop-change-dmi-match-alias-strin.patch +asoc-sof-pci-change-dmi-match-info-to-support-all-ch.patch +drm-amdgpu-fix-initial-connector-audio-value.patch +drm-meson-explicitly-remove-aggregate-driver-at-modu.patch +drm-exynos-fix-return-type-for-mixer_mode_valid-and-.patch +mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch +drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch +drm-amd-display-remove-interface-for-periodic-interr.patch +drm-amd-display-fix-array-bounds-error-in-dc_stream_.patch +arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch +arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch +arm-dts-imx6q-add-missing-properties-for-sram.patch +arm-dts-imx6dl-add-missing-properties-for-sram.patch +arm-dts-imx6qp-add-missing-properties-for-sram.patch +arm-dts-imx6sl-add-missing-properties-for-sram.patch +arm-dts-imx6sll-add-missing-properties-for-sram.patch +arm-dts-imx6sx-add-missing-properties-for-sram.patch +kselftest-arm64-fix-validatation-termination-record-.patch +arm64-dts-imx8mq-librem5-add-bq25895-as-max17055-s-p.patch +arm-orion-fix-include-path.patch +btrfs-scrub-try-to-fix-super-block-errors.patch +btrfs-check-superblock-to-ensure-the-fs-was-not-modi.patch +btrfs-add-kcsan-annotations-for-unlocked-access-to-b.patch +arm64-dts-uniphier-add-usb-device-support-for-pxs3-r.patch +selftests-cpu-hotplug-use-return-instead-of-exit.patch +clk-zynqmp-fix-stack-out-of-bounds-in-strncpy.patch +media-cx88-fix-a-null-ptr-deref-bug-in-buffer_prepar.patch +clk-zynqmp-pll-rectify-rate-rounding-in-zynqmp_pll_r.patch +usb-host-xhci-plat-suspend-and-resume-clocks.patch +usb-host-xhci-plat-suspend-resume-clks-for-brcm.patch +dmaengine-ti-k3-udma-reset-udma_chan_rt-byte-counter.patch +scsi-3w-9xxx-avoid-disabling-device-if-failing-to-en.patch +nbd-fix-hung-when-signal-interrupts-nbd_start_device.patch +power-supply-adp5061-fix-out-of-bounds-read-in-adp50.patch +staging-vt6655-fix-potential-memory-leak.patch +blk-throttle-prevent-overflow-while-calculating-wait.patch +ata-libahci_platform-sanity-check-the-dt-child-nodes.patch +bcache-fix-set_at_max_writeback_rate-for-multiple-at.patch +soundwire-cadence-don-t-overwrite-msg-buf-during-wri.patch +soundwire-intel-fix-error-handling-on-dai-registrati.patch +hid-topre-add-driver-fixing-report-descriptor.patch +hid-roccat-fix-use-after-free-in-roccat_read.patch +hsi-ssi_protocol-fix-potential-resource-leak-in-ssip.patch +md-raid5-wait-for-md_sb_change_pending-in-raid5d.patch +usb-host-xhci-fix-potential-memory-leak-in-xhci_allo.patch +usb-musb-fix-musb_gadget.c-rxstate-overflow-bug.patch +revert-usb-storage-add-quirk-for-samsung-fit-flash.patch +staging-rtl8723bs-fix-a-potential-memory-leak-in-rtw.patch +nvme-copy-firmware_rev-on-each-init.patch +nvmet-tcp-add-bounds-check-on-transfer-tag.patch +usb-idmouse-fix-an-uninit-value-in-idmouse_open.patch +fsi-master-ast-cf-fix-missing-of_node_put-in-fsi_mas.patch +clk-bcm2835-make-peripheral-pllc-critical.patch diff --git a/queue-5.10/sh-machvec-use-char-for-section-boundaries.patch b/queue-5.10/sh-machvec-use-char-for-section-boundaries.patch new file mode 100644 index 00000000000..f523ac385f6 --- /dev/null +++ b/queue-5.10/sh-machvec-use-char-for-section-boundaries.patch @@ -0,0 +1,82 @@ +From c311708f9138021971c71f452eaf14439ced3e47 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 16:40:44 -0700 +Subject: sh: machvec: Use char[] for section boundaries + +From: Kees Cook + +[ Upstream commit c5783af354688b24abd359f7086c282ec74de993 ] + +As done for other sections, define the extern as a character array, +which relaxes many of the compiler-time object size checks, which would +otherwise assume it's a single long. Solves the following build error: + +arch/sh/kernel/machvec.c: error: array subscript 'struct sh_machine_vector[0]' is partly outside array bounds of 'long int[1]' [-Werror=array-bounds]: => 105:33 + +Cc: Yoshinori Sato +Cc: Rich Felker +Cc: linux-sh@vger.kernel.org +Reported-by: Geert Uytterhoeven +Link: https://lore.kernel.org/lkml/alpine.DEB.2.22.394.2209050944290.964530@ramsan.of.borg/ +Fixes: 9655ad03af2d ("sh: Fixup machvec support.") +Reviewed-by: Geert Uytterhoeven +Reviewed-by: Gustavo A. R. Silva +Acked-by: Rich Felker +Signed-off-by: Kees Cook +Signed-off-by: Sasha Levin +--- + arch/sh/include/asm/sections.h | 2 +- + arch/sh/kernel/machvec.c | 10 +++++----- + 2 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h +index 8edb824049b9..0cb0ca149ac3 100644 +--- a/arch/sh/include/asm/sections.h ++++ b/arch/sh/include/asm/sections.h +@@ -4,7 +4,7 @@ + + #include + +-extern long __machvec_start, __machvec_end; ++extern char __machvec_start[], __machvec_end[]; + extern char __uncached_start, __uncached_end; + extern char __start_eh_frame[], __stop_eh_frame[]; + +diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c +index d606679a211e..57efaf5b82ae 100644 +--- a/arch/sh/kernel/machvec.c ++++ b/arch/sh/kernel/machvec.c +@@ -20,8 +20,8 @@ + #define MV_NAME_SIZE 32 + + #define for_each_mv(mv) \ +- for ((mv) = (struct sh_machine_vector *)&__machvec_start; \ +- (mv) && (unsigned long)(mv) < (unsigned long)&__machvec_end; \ ++ for ((mv) = (struct sh_machine_vector *)__machvec_start; \ ++ (mv) && (unsigned long)(mv) < (unsigned long)__machvec_end; \ + (mv)++) + + static struct sh_machine_vector * __init get_mv_byname(const char *name) +@@ -87,8 +87,8 @@ void __init sh_mv_setup(void) + if (!machvec_selected) { + unsigned long machvec_size; + +- machvec_size = ((unsigned long)&__machvec_end - +- (unsigned long)&__machvec_start); ++ machvec_size = ((unsigned long)__machvec_end - ++ (unsigned long)__machvec_start); + + /* + * Sanity check for machvec section alignment. Ensure +@@ -102,7 +102,7 @@ void __init sh_mv_setup(void) + * vector (usually the only one) from .machvec.init. + */ + if (machvec_size >= sizeof(struct sh_machine_vector)) +- sh_mv = *(struct sh_machine_vector *)&__machvec_start; ++ sh_mv = *(struct sh_machine_vector *)__machvec_start; + } + + pr_notice("Booting machvec: %s\n", get_system_type()); +-- +2.35.1 + diff --git a/queue-5.10/soc-qcom-smem_state-add-refcounting-for-the-state-of.patch b/queue-5.10/soc-qcom-smem_state-add-refcounting-for-the-state-of.patch new file mode 100644 index 00000000000..2b4e972d9ac --- /dev/null +++ b/queue-5.10/soc-qcom-smem_state-add-refcounting-for-the-state-of.patch @@ -0,0 +1,46 @@ +From 7a7040bfe36db51d71d5c7ce95ecac5cf40e8be1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Jul 2022 21:52:17 +0800 +Subject: soc: qcom: smem_state: Add refcounting for the 'state->of_node' + +From: Liang He + +[ Upstream commit 90681f53b9381c23ff7762a3b13826d620c272de ] + +In qcom_smem_state_register() and qcom_smem_state_release(), we +should better use of_node_get() and of_node_put() for the reference +creation and destruction of 'device_node'. + +Fixes: 9460ae2ff308 ("soc: qcom: Introduce common SMEM state machine code") +Signed-off-by: Liang He +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220721135217.1301039-2-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/soc/qcom/smem_state.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/soc/qcom/smem_state.c b/drivers/soc/qcom/smem_state.c +index d2b558438deb..41e929407196 100644 +--- a/drivers/soc/qcom/smem_state.c ++++ b/drivers/soc/qcom/smem_state.c +@@ -136,6 +136,7 @@ static void qcom_smem_state_release(struct kref *ref) + struct qcom_smem_state *state = container_of(ref, struct qcom_smem_state, refcount); + + list_del(&state->list); ++ of_node_put(state->of_node); + kfree(state); + } + +@@ -169,7 +170,7 @@ struct qcom_smem_state *qcom_smem_state_register(struct device_node *of_node, + + kref_init(&state->refcount); + +- state->of_node = of_node; ++ state->of_node = of_node_get(of_node); + state->ops = *ops; + state->priv = priv; + +-- +2.35.1 + diff --git a/queue-5.10/soc-qcom-smsm-fix-refcount-leak-bugs-in-qcom_smsm_pr.patch b/queue-5.10/soc-qcom-smsm-fix-refcount-leak-bugs-in-qcom_smsm_pr.patch new file mode 100644 index 00000000000..92a46b40f07 --- /dev/null +++ b/queue-5.10/soc-qcom-smsm-fix-refcount-leak-bugs-in-qcom_smsm_pr.patch @@ -0,0 +1,107 @@ +From 86fd4b90b1858c2d7bdf5fb85380857820b2cb28 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Jul 2022 21:52:16 +0800 +Subject: soc: qcom: smsm: Fix refcount leak bugs in qcom_smsm_probe() + +From: Liang He + +[ Upstream commit af8f6f39b8afd772fda4f8e61823ef8c021bf382 ] + +There are two refcount leak bugs in qcom_smsm_probe(): + +(1) The 'local_node' is escaped out from for_each_child_of_node() as +the break of iteration, we should call of_node_put() for it in error +path or when it is not used anymore. +(2) The 'node' is escaped out from for_each_available_child_of_node() +as the 'goto', we should call of_node_put() for it in goto target. + +Fixes: c97c4090ff72 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") +Signed-off-by: Liang He +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220721135217.1301039-1-windhl@126.com +Signed-off-by: Sasha Levin +--- + drivers/soc/qcom/smsm.c | 20 +++++++++++++------- + 1 file changed, 13 insertions(+), 7 deletions(-) + +diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c +index 6564f15c5319..acba67dfbc85 100644 +--- a/drivers/soc/qcom/smsm.c ++++ b/drivers/soc/qcom/smsm.c +@@ -511,7 +511,7 @@ static int qcom_smsm_probe(struct platform_device *pdev) + for (id = 0; id < smsm->num_hosts; id++) { + ret = smsm_parse_ipc(smsm, id); + if (ret < 0) +- return ret; ++ goto out_put; + } + + /* Acquire the main SMSM state vector */ +@@ -519,13 +519,14 @@ static int qcom_smsm_probe(struct platform_device *pdev) + smsm->num_entries * sizeof(u32)); + if (ret < 0 && ret != -EEXIST) { + dev_err(&pdev->dev, "unable to allocate shared state entry\n"); +- return ret; ++ goto out_put; + } + + states = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL); + if (IS_ERR(states)) { + dev_err(&pdev->dev, "Unable to acquire shared state entry\n"); +- return PTR_ERR(states); ++ ret = PTR_ERR(states); ++ goto out_put; + } + + /* Acquire the list of interrupt mask vectors */ +@@ -533,13 +534,14 @@ static int qcom_smsm_probe(struct platform_device *pdev) + ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, size); + if (ret < 0 && ret != -EEXIST) { + dev_err(&pdev->dev, "unable to allocate smsm interrupt mask\n"); +- return ret; ++ goto out_put; + } + + intr_mask = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL); + if (IS_ERR(intr_mask)) { + dev_err(&pdev->dev, "unable to acquire shared memory interrupt mask\n"); +- return PTR_ERR(intr_mask); ++ ret = PTR_ERR(intr_mask); ++ goto out_put; + } + + /* Setup the reference to the local state bits */ +@@ -550,7 +552,8 @@ static int qcom_smsm_probe(struct platform_device *pdev) + smsm->state = qcom_smem_state_register(local_node, &smsm_state_ops, smsm); + if (IS_ERR(smsm->state)) { + dev_err(smsm->dev, "failed to register qcom_smem_state\n"); +- return PTR_ERR(smsm->state); ++ ret = PTR_ERR(smsm->state); ++ goto out_put; + } + + /* Register handlers for remote processor entries of interest. */ +@@ -580,16 +583,19 @@ static int qcom_smsm_probe(struct platform_device *pdev) + } + + platform_set_drvdata(pdev, smsm); ++ of_node_put(local_node); + + return 0; + + unwind_interfaces: ++ of_node_put(node); + for (id = 0; id < smsm->num_entries; id++) + if (smsm->entries[id].domain) + irq_domain_remove(smsm->entries[id].domain); + + qcom_smem_state_unregister(smsm->state); +- ++out_put: ++ of_node_put(local_node); + return ret; + } + +-- +2.35.1 + diff --git a/queue-5.10/soc-tegra-fuse-drop-kconfig-dependency-on-tegra20_ap.patch b/queue-5.10/soc-tegra-fuse-drop-kconfig-dependency-on-tegra20_ap.patch new file mode 100644 index 00000000000..88b8d4e208c --- /dev/null +++ b/queue-5.10/soc-tegra-fuse-drop-kconfig-dependency-on-tegra20_ap.patch @@ -0,0 +1,45 @@ +From 6e80e44557fb317755d3dd70380ac4c4e7fcee96 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 23 Sep 2020 03:34:21 +0300 +Subject: soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMA + +From: Dmitry Osipenko + +[ Upstream commit 2254182807fc09ba9dec9a42ef239e373796f1b2 ] + +The DMA subsystem could be entirely disabled in Kconfig and then the +TEGRA20_APB_DMA option isn't available too. Hence kernel configuration +fails if DMADEVICES Kconfig option is disabled due to the unsatisfiable +dependency. + +The FUSE driver isn't a critical driver and currently it only provides +NVMEM interface to userspace which isn't known to be widely used, and +thus, it's fine if FUSE driver fails to load. + +Let's remove the erroneous Kconfig dependency and let the FUSE driver to +fail the probing if DMA is unavailable. + +Fixes: 19d41e5e9c68 ("soc/tegra: fuse: Add APB DMA dependency for Tegra20") +Reported-by: Necip Fazil Yildiran +Link: https://bugzilla.kernel.org/show_bug.cgi?id=209301 +Signed-off-by: Dmitry Osipenko +Signed-off-by: Sasha Levin +--- + drivers/soc/tegra/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig +index 976dee036470..676807c5a215 100644 +--- a/drivers/soc/tegra/Kconfig ++++ b/drivers/soc/tegra/Kconfig +@@ -136,7 +136,6 @@ config SOC_TEGRA_FUSE + def_bool y + depends on ARCH_TEGRA + select SOC_BUS +- select TEGRA20_APB_DMA if ARCH_TEGRA_2x_SOC + + config SOC_TEGRA_FLOWCTRL + bool +-- +2.35.1 + diff --git a/queue-5.10/soundwire-cadence-don-t-overwrite-msg-buf-during-wri.patch b/queue-5.10/soundwire-cadence-don-t-overwrite-msg-buf-during-wri.patch new file mode 100644 index 00000000000..7557c9a8547 --- /dev/null +++ b/queue-5.10/soundwire-cadence-don-t-overwrite-msg-buf-during-wri.patch @@ -0,0 +1,49 @@ +From e2a5f2600d567153720824256da4592216217461 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 16 Sep 2022 11:35:05 +0100 +Subject: soundwire: cadence: Don't overwrite msg->buf during write commands + +From: Richard Fitzgerald + +[ Upstream commit ba05b39d265bdd16913f7684600d9d41e2796745 ] + +The buf passed in struct sdw_msg must only be written for a READ, +in that case the RDATA part of the response is the data value of the +register. + +For a write command there is no RDATA, and buf should be assumed to +be const and unmodifable. The original caller should not expect its data +buffer to be corrupted by an sdw_nwrite(). + +Signed-off-by: Richard Fitzgerald +Reviewed-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20220916103505.1562210-1-rf@opensource.cirrus.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/soundwire/cadence_master.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c +index c6d421a4b91b..a3247692ddc0 100644 +--- a/drivers/soundwire/cadence_master.c ++++ b/drivers/soundwire/cadence_master.c +@@ -501,9 +501,12 @@ cdns_fill_msg_resp(struct sdw_cdns *cdns, + return SDW_CMD_IGNORED; + } + +- /* fill response */ +- for (i = 0; i < count; i++) +- msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA, cdns->response_buf[i]); ++ if (msg->flags == SDW_MSG_FLAG_READ) { ++ /* fill response */ ++ for (i = 0; i < count; i++) ++ msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA, ++ cdns->response_buf[i]); ++ } + + return SDW_CMD_OK; + } +-- +2.35.1 + diff --git a/queue-5.10/soundwire-intel-fix-error-handling-on-dai-registrati.patch b/queue-5.10/soundwire-intel-fix-error-handling-on-dai-registrati.patch new file mode 100644 index 00000000000..a3267aa2507 --- /dev/null +++ b/queue-5.10/soundwire-intel-fix-error-handling-on-dai-registrati.patch @@ -0,0 +1,39 @@ +From 2207a245c91dab5b38c655950b2cddffbd182cca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 01:57:11 +0800 +Subject: soundwire: intel: fix error handling on dai registration issues + +From: Pierre-Louis Bossart + +[ Upstream commit c6867cda906aadbce5e71efde9c78a26108b2bad ] + +The call to intel_register_dai() may fail because of memory allocation +issues or problems reported by the ASoC core. In all cases, when a +error is thrown the component is not registered, it's invalid to +unregister it. + +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Rander Wang +Signed-off-by: Bard Liao +Link: https://lore.kernel.org/r/20220919175721.354679-2-yung-chuan.liao@linux.intel.com +Signed-off-by: Vinod Koul +Signed-off-by: Sasha Levin +--- + drivers/soundwire/intel.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c +index 824d9f900aca..942d2fe13218 100644 +--- a/drivers/soundwire/intel.c ++++ b/drivers/soundwire/intel.c +@@ -1470,7 +1470,6 @@ int intel_master_startup(struct platform_device *pdev) + ret = intel_register_dai(sdw); + if (ret) { + dev_err(dev, "DAI registration failed: %d\n", ret); +- snd_soc_unregister_component(dev); + goto err_interrupt; + } + +-- +2.35.1 + diff --git a/queue-5.10/spi-dw-fix-pm-disable-depth-imbalance-in-dw_spi_bt1_.patch b/queue-5.10/spi-dw-fix-pm-disable-depth-imbalance-in-dw_spi_bt1_.patch new file mode 100644 index 00000000000..76382d7d0c6 --- /dev/null +++ b/queue-5.10/spi-dw-fix-pm-disable-depth-imbalance-in-dw_spi_bt1_.patch @@ -0,0 +1,42 @@ +From cec42534f9cf971d26884cb51292ab8579df6403 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 24 Sep 2022 20:13:08 +0800 +Subject: spi: dw: Fix PM disable depth imbalance in dw_spi_bt1_probe + +From: Zhang Qilong + +[ Upstream commit 618d815fc93477b1675878f3c04ff32657cc18b4 ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. + +Fixes:abf00907538e2 ("spi: dw: Add Baikal-T1 SPI Controller glue driver") + +Signed-off-by: Zhang Qilong +Link: https://lore.kernel.org/r/20220924121310.78331-3-zhangqilong3@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-dw-bt1.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-dw-bt1.c b/drivers/spi/spi-dw-bt1.c +index bc9d5eab3c58..8f6a1af14456 100644 +--- a/drivers/spi/spi-dw-bt1.c ++++ b/drivers/spi/spi-dw-bt1.c +@@ -293,8 +293,10 @@ static int dw_spi_bt1_probe(struct platform_device *pdev) + pm_runtime_enable(&pdev->dev); + + ret = dw_spi_add_host(&pdev->dev, dws); +- if (ret) ++ if (ret) { ++ pm_runtime_disable(&pdev->dev); + goto err_disable_clk; ++ } + + platform_set_drvdata(pdev, dwsbt1); + +-- +2.35.1 + diff --git a/queue-5.10/spi-ensure-that-sg_table-won-t-be-used-after-being-f.patch b/queue-5.10/spi-ensure-that-sg_table-won-t-be-used-after-being-f.patch new file mode 100644 index 00000000000..42a3d67831d --- /dev/null +++ b/queue-5.10/spi-ensure-that-sg_table-won-t-be-used-after-being-f.patch @@ -0,0 +1,39 @@ +From cb6afcf302c852b61db7a99dce9f901bd9588708 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Sep 2022 13:34:08 +0200 +Subject: spi: Ensure that sg_table won't be used after being freed + +From: Marek Szyprowski + +[ Upstream commit 8e9204cddcc3fea9affcfa411715ba4f66e97587 ] + +SPI code checks for non-zero sgt->orig_nents to determine if the buffer +has been DMA-mapped. Ensure that sg_table is really zeroed after free to +avoid potential NULL pointer dereference if the given SPI xfer object is +reused again without being DMA-mapped. + +Fixes: 0c17ba73c08f ("spi: Fix cache corruption due to DMA/PIO overlap") +Signed-off-by: Marek Szyprowski +Link: https://lore.kernel.org/r/20220930113408.19720-1-m.szyprowski@samsung.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c +index 6ea7b286c80c..857a1399850c 100644 +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -946,6 +946,8 @@ void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev, + if (sgt->orig_nents) { + dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir); + sg_free_table(sgt); ++ sgt->orig_nents = 0; ++ sgt->nents = 0; + } + } + +-- +2.35.1 + diff --git a/queue-5.10/spi-meson-spicc-do-not-rely-on-busy-flag-in-pow2-clk.patch b/queue-5.10/spi-meson-spicc-do-not-rely-on-busy-flag-in-pow2-clk.patch new file mode 100644 index 00000000000..6c6312310cb --- /dev/null +++ b/queue-5.10/spi-meson-spicc-do-not-rely-on-busy-flag-in-pow2-clk.patch @@ -0,0 +1,66 @@ +From 605fda7bb1935be854bc18114c14e8ffe96cbb03 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Sep 2022 14:18:03 +0200 +Subject: spi: meson-spicc: do not rely on busy flag in pow2 clk ops + +From: Neil Armstrong + +[ Upstream commit 36acf80fc0c4b5ebe6fa010b524d442ee7f08fd3 ] + +Since [1], controller's busy flag isn't set anymore when the +__spi_transfer_message_noqueue() is used instead of the +__spi_pump_transfer_message() logic for spi_sync transfers. + +Since the pow2 clock ops were limited to only be available when a +transfer is ongoing (between prepare_transfer_hardware and +unprepare_transfer_hardware callbacks), the only way to track this +down is to check for the controller cur_msg. + +[1] ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") + +Fixes: 09992025dacd ("spi: meson-spicc: add local pow2 clock ops to preserve rate between messages") +Fixes: ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") +Reported-by: Markus Schneider-Pargmann +Signed-off-by: Neil Armstrong +Tested-by: Markus Schneider-Pargmann +Link: https://lore.kernel.org/r/20220908121803.919943-1-narmstrong@baylibre.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-meson-spicc.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c +index e4cb52e1fe26..6974a1c947aa 100644 +--- a/drivers/spi/spi-meson-spicc.c ++++ b/drivers/spi/spi-meson-spicc.c +@@ -537,7 +537,7 @@ static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw, + struct clk_divider *divider = to_clk_divider(hw); + struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); + +- if (!spicc->master->cur_msg || !spicc->master->busy) ++ if (!spicc->master->cur_msg) + return 0; + + return clk_divider_ops.recalc_rate(hw, parent_rate); +@@ -549,7 +549,7 @@ static int meson_spicc_pow2_determine_rate(struct clk_hw *hw, + struct clk_divider *divider = to_clk_divider(hw); + struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); + +- if (!spicc->master->cur_msg || !spicc->master->busy) ++ if (!spicc->master->cur_msg) + return -EINVAL; + + return clk_divider_ops.determine_rate(hw, req); +@@ -561,7 +561,7 @@ static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate, + struct clk_divider *divider = to_clk_divider(hw); + struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); + +- if (!spicc->master->cur_msg || !spicc->master->busy) ++ if (!spicc->master->cur_msg) + return -EINVAL; + + return clk_divider_ops.set_rate(hw, rate, parent_rate); +-- +2.35.1 + diff --git a/queue-5.10/spi-mt7621-fix-an-error-message-in-mt7621_spi_probe.patch b/queue-5.10/spi-mt7621-fix-an-error-message-in-mt7621_spi_probe.patch new file mode 100644 index 00000000000..90398851c21 --- /dev/null +++ b/queue-5.10/spi-mt7621-fix-an-error-message-in-mt7621_spi_probe.patch @@ -0,0 +1,48 @@ +From 7d6c08d00dc7e9803eb4379a733a93d1eb19ec62 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 27 Aug 2022 13:42:07 +0200 +Subject: spi: mt7621: Fix an error message in mt7621_spi_probe() + +From: Christophe JAILLET + +[ Upstream commit 2b2bf6b7faa9010fae10dc7de76627a3fdb525b3 ] + +'status' is known to be 0 at this point. The expected error code is +PTR_ERR(clk). + +Switch to dev_err_probe() in order to display the expected error code (in a +human readable way). +This also filters -EPROBE_DEFER cases, should it happen. + +Fixes: 1ab7f2a43558 ("staging: mt7621-spi: add mt7621 support") +Signed-off-by: Christophe JAILLET +Reviewed-by: Matthias Brugger +Link: https://lore.kernel.org/r/928f3fb507d53ba0774df27cea0bbba4b055993b.1661599671.git.christophe.jaillet@wanadoo.fr +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-mt7621.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c +index b4b9b7309b5e..351b0ef52bbc 100644 +--- a/drivers/spi/spi-mt7621.c ++++ b/drivers/spi/spi-mt7621.c +@@ -340,11 +340,9 @@ static int mt7621_spi_probe(struct platform_device *pdev) + return PTR_ERR(base); + + clk = devm_clk_get(&pdev->dev, NULL); +- if (IS_ERR(clk)) { +- dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", +- status); +- return PTR_ERR(clk); +- } ++ if (IS_ERR(clk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(clk), ++ "unable to get SYS clock\n"); + + status = clk_prepare_enable(clk); + if (status) +-- +2.35.1 + diff --git a/queue-5.10/spi-omap100k-fix-pm-disable-depth-imbalance-in-omap1.patch b/queue-5.10/spi-omap100k-fix-pm-disable-depth-imbalance-in-omap1.patch new file mode 100644 index 00000000000..fd9195d1778 --- /dev/null +++ b/queue-5.10/spi-omap100k-fix-pm-disable-depth-imbalance-in-omap1.patch @@ -0,0 +1,38 @@ +From d4902c08eb6a757af2d70b545e7056f3f1e2e046 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 24 Sep 2022 20:13:09 +0800 +Subject: spi/omap100k:Fix PM disable depth imbalance in omap1_spi100k_probe + +From: Zhang Qilong + +[ Upstream commit 29f65f2171c85a9633daa380df14009a365f42f2 ] + +The pm_runtime_enable will increase power disable depth. Thus +a pairing decrement is needed on the error handling path to +keep it balanced according to context. + +Fixes:db91841b58f9a ("spi/omap100k: Convert to runtime PM") + +Signed-off-by: Zhang Qilong +Link: https://lore.kernel.org/r/20220924121310.78331-4-zhangqilong3@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-omap-100k.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c +index 0d0cd061d356..7c992d1f4abd 100644 +--- a/drivers/spi/spi-omap-100k.c ++++ b/drivers/spi/spi-omap-100k.c +@@ -414,6 +414,7 @@ static int omap1_spi100k_probe(struct platform_device *pdev) + return status; + + err_fck: ++ pm_runtime_disable(&pdev->dev); + clk_disable_unprepare(spi100k->fck); + err_ick: + clk_disable_unprepare(spi100k->ick); +-- +2.35.1 + diff --git a/queue-5.10/spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch b/queue-5.10/spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch new file mode 100644 index 00000000000..521264eb930 --- /dev/null +++ b/queue-5.10/spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch @@ -0,0 +1,61 @@ +From ae2ad4f166bd7bb41a127380fca8dbc044556c6a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 06:53:23 +0000 +Subject: spi: qup: add missing clk_disable_unprepare on error in + spi_qup_resume() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Xu Qiang + +[ Upstream commit 70034320fdc597b8f58b4a43bb547f17c4c5557a ] + +Add the missing clk_disable_unprepare() before return +from spi_qup_resume() in the error handling case. + +Fixes: 64ff247a978f (“spi: Add Qualcomm QUP SPI controller support”) +Signed-off-by: Xu Qiang +Link: https://lore.kernel.org/r/20220825065324.68446-1-xuqiang36@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-qup.c | 17 ++++++++++++++--- + 1 file changed, 14 insertions(+), 3 deletions(-) + +diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c +index d39dec6d1c91..668d79922fac 100644 +--- a/drivers/spi/spi-qup.c ++++ b/drivers/spi/spi-qup.c +@@ -1246,14 +1246,25 @@ static int spi_qup_resume(struct device *device) + return ret; + + ret = clk_prepare_enable(controller->cclk); +- if (ret) ++ if (ret) { ++ clk_disable_unprepare(controller->iclk); + return ret; ++ } + + ret = spi_qup_set_state(controller, QUP_STATE_RESET); + if (ret) +- return ret; ++ goto disable_clk; ++ ++ ret = spi_master_resume(master); ++ if (ret) ++ goto disable_clk; + +- return spi_master_resume(master); ++ return 0; ++ ++disable_clk: ++ clk_disable_unprepare(controller->cclk); ++ clk_disable_unprepare(controller->iclk); ++ return ret; + } + #endif /* CONFIG_PM_SLEEP */ + +-- +2.35.1 + diff --git a/queue-5.10/spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch-14793 b/queue-5.10/spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch-14793 new file mode 100644 index 00000000000..7f7a16284fc --- /dev/null +++ b/queue-5.10/spi-qup-add-missing-clk_disable_unprepare-on-error-i.patch-14793 @@ -0,0 +1,44 @@ +From 1173d4851bfd486f60d2e2aff2fc483aaaf1024c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Aug 2022 06:53:24 +0000 +Subject: spi: qup: add missing clk_disable_unprepare on error in + spi_qup_pm_resume_runtime() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Xu Qiang + +[ Upstream commit 494a22765ce479c9f8ad181c5d24cffda9f534bb ] + +Add the missing clk_disable_unprepare() before return +from spi_qup_pm_resume_runtime() in the error handling case. + +Fixes: dae1a7700b34 (“spi: qup: Handle clocks in pm_runtime suspend and resume”) +Signed-off-by: Xu Qiang +Link: https://lore.kernel.org/r/20220825065324.68446-2-xuqiang36@huawei.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-qup.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c +index 668d79922fac..f3877eeb3da6 100644 +--- a/drivers/spi/spi-qup.c ++++ b/drivers/spi/spi-qup.c +@@ -1199,8 +1199,10 @@ static int spi_qup_pm_resume_runtime(struct device *device) + return ret; + + ret = clk_prepare_enable(controller->cclk); +- if (ret) ++ if (ret) { ++ clk_disable_unprepare(controller->iclk); + return ret; ++ } + + /* Disable clocks auto gaiting */ + config = readl_relaxed(controller->base + QUP_CONFIG); +-- +2.35.1 + diff --git a/queue-5.10/spi-s3c64xx-fix-large-transfers-with-dma.patch b/queue-5.10/spi-s3c64xx-fix-large-transfers-with-dma.patch new file mode 100644 index 00000000000..03a4a52b817 --- /dev/null +++ b/queue-5.10/spi-s3c64xx-fix-large-transfers-with-dma.patch @@ -0,0 +1,60 @@ +From 9bc17170efac4ad75b05a9ce6af25ad46d79e1a7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 27 Sep 2022 13:21:17 +0200 +Subject: spi: s3c64xx: Fix large transfers with DMA + +From: Vincent Whitchurch + +[ Upstream commit 1224e29572f655facfcd850cf0f0a4784f36a903 ] + +The COUNT_VALUE in the PACKET_CNT register is 16-bit so the maximum +value is 65535. Asking the driver to transfer a larger size currently +leads to the DMA transfer timing out. Implement ->max_transfer_size() +and have the core split the transfer as needed. + +Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver") +Signed-off-by: Vincent Whitchurch +Link: https://lore.kernel.org/r/20220927112117.77599-5-vincent.whitchurch@axis.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-s3c64xx.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c +index dfa7c91e13aa..d435df1b715b 100644 +--- a/drivers/spi/spi-s3c64xx.c ++++ b/drivers/spi/spi-s3c64xx.c +@@ -84,6 +84,7 @@ + #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) + + #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) ++#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) + + #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) + #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) +@@ -660,6 +661,13 @@ static int s3c64xx_spi_prepare_message(struct spi_master *master, + return 0; + } + ++static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) ++{ ++ struct spi_controller *ctlr = spi->controller; ++ ++ return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; ++} ++ + static int s3c64xx_spi_transfer_one(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *xfer) +@@ -1135,6 +1143,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) + master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; + master->prepare_message = s3c64xx_spi_prepare_message; + master->transfer_one = s3c64xx_spi_transfer_one; ++ master->max_transfer_size = s3c64xx_spi_max_transfer_size; + master->num_chipselect = sci->num_cs; + master->dma_alignment = 8; + master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | +-- +2.35.1 + diff --git a/queue-5.10/spmi-pmic-arb-correct-duplicate-apid-to-ppid-mapping.patch b/queue-5.10/spmi-pmic-arb-correct-duplicate-apid-to-ppid-mapping.patch new file mode 100644 index 00000000000..f675f0b6d7f --- /dev/null +++ b/queue-5.10/spmi-pmic-arb-correct-duplicate-apid-to-ppid-mapping.patch @@ -0,0 +1,65 @@ +From 85cf935b0a02ede05f0f617a48740aef9204bc3f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Sep 2022 17:50:16 -0700 +Subject: spmi: pmic-arb: correct duplicate APID to PPID mapping logic + +From: David Collins + +[ Upstream commit 1f1693118c2476cb1666ad357edcf3cf48bf9b16 ] + +Correct the way that duplicate PPID mappings are handled for PMIC +arbiter v5. The final APID mapped to a given PPID should be the +one which has write owner = APPS EE, if it exists, or if not +that, then the first APID mapped to the PPID, if it exists. + +Fixes: 40f318f0ed67 ("spmi: pmic-arb: add support for HW version 5") +Signed-off-by: David Collins +Signed-off-by: Fenglin Wu +Link: https://lore.kernel.org/r/1655004286-11493-7-git-send-email-quic_fenglinw@quicinc.com +Signed-off-by: Stephen Boyd +Link: https://lore.kernel.org/r/20220930005019.2663064-8-sboyd@kernel.org +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/spmi/spmi-pmic-arb.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c +index bbbd311eda03..e6de2aeece8d 100644 +--- a/drivers/spmi/spmi-pmic-arb.c ++++ b/drivers/spmi/spmi-pmic-arb.c +@@ -887,7 +887,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) + * version 5, there is more than one APID mapped to each PPID. + * The owner field for each of these mappings specifies the EE which is + * allowed to write to the APID. The owner of the last (highest) APID +- * for a given PPID will receive interrupts from the PPID. ++ * which has the IRQ owner bit set for a given PPID will receive ++ * interrupts from the PPID. + */ + for (i = 0; ; i++, apidd++) { + offset = pmic_arb->ver_ops->apid_map_offset(i); +@@ -910,16 +911,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) + apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; + prev_apidd = &pmic_arb->apid_data[apid]; + +- if (valid && is_irq_ee && +- prev_apidd->write_ee == pmic_arb->ee) { ++ if (!valid || apidd->write_ee == pmic_arb->ee) { ++ /* First PPID mapping or one for this EE */ ++ pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; ++ } else if (valid && is_irq_ee && ++ prev_apidd->write_ee == pmic_arb->ee) { + /* + * Duplicate PPID mapping after the one for this EE; + * override the irq owner + */ + prev_apidd->irq_ee = apidd->irq_ee; +- } else if (!valid || is_irq_ee) { +- /* First PPID mapping or duplicate for another EE */ +- pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; + } + + apidd->ppid = ppid; +-- +2.35.1 + diff --git a/queue-5.10/staging-rtl8723bs-fix-a-potential-memory-leak-in-rtw.patch b/queue-5.10/staging-rtl8723bs-fix-a-potential-memory-leak-in-rtw.patch new file mode 100644 index 00000000000..237ac402de4 --- /dev/null +++ b/queue-5.10/staging-rtl8723bs-fix-a-potential-memory-leak-in-rtw.patch @@ -0,0 +1,79 @@ +From 93913a4b768169fe3b490e9e83b6004157644279 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 19:27:21 +0800 +Subject: staging: rtl8723bs: fix a potential memory leak in + rtw_init_cmd_priv() + +From: Xiaoke Wang + +[ Upstream commit 708056fba733a73d926772ea4ce9a42d240345da ] + +In rtw_init_cmd_priv(), if `pcmdpriv->rsp_allocated_buf` is allocated +in failure, then `pcmdpriv->cmd_allocated_buf` will be not properly +released. Besides, considering there are only two error paths and the +first one can directly return, so we do not need implicitly jump to the +`exit` tag to execute the error handler. + +So this patch added `kfree(pcmdpriv->cmd_allocated_buf);` on the error +path to release the resource and simplified the return logic of +rtw_init_cmd_priv(). As there is no proper device to test with, no runtime +testing was performed. + +Signed-off-by: Xiaoke Wang +Link: https://lore.kernel.org/r/tencent_2B7931B79BA38E22205C5A09EFDF11E48805@qq.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/staging/rtl8723bs/core/rtw_cmd.c | 16 ++++++---------- + 1 file changed, 6 insertions(+), 10 deletions(-) + +diff --git a/drivers/staging/rtl8723bs/core/rtw_cmd.c b/drivers/staging/rtl8723bs/core/rtw_cmd.c +index 2abe205e3453..cee05385f872 100644 +--- a/drivers/staging/rtl8723bs/core/rtw_cmd.c ++++ b/drivers/staging/rtl8723bs/core/rtw_cmd.c +@@ -165,8 +165,6 @@ No irqsave is necessary. + + int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) + { +- int res = 0; +- + init_completion(&pcmdpriv->cmd_queue_comp); + init_completion(&pcmdpriv->terminate_cmdthread_comp); + +@@ -178,18 +176,16 @@ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) + + pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ); + +- if (!pcmdpriv->cmd_allocated_buf) { +- res = -ENOMEM; +- goto exit; +- } ++ if (!pcmdpriv->cmd_allocated_buf) ++ return -ENOMEM; + + pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ-1)); + + pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4); + + if (!pcmdpriv->rsp_allocated_buf) { +- res = -ENOMEM; +- goto exit; ++ kfree(pcmdpriv->cmd_allocated_buf); ++ return -ENOMEM; + } + + pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3); +@@ -199,8 +195,8 @@ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) + pcmdpriv->rsp_cnt = 0; + + mutex_init(&pcmdpriv->sctx_mutex); +-exit: +- return res; ++ ++ return 0; + } + + static void c2h_wk_callback(_workitem * work); +-- +2.35.1 + diff --git a/queue-5.10/staging-vt6655-fix-potential-memory-leak.patch b/queue-5.10/staging-vt6655-fix-potential-memory-leak.patch new file mode 100644 index 00000000000..58cc3cc2bca --- /dev/null +++ b/queue-5.10/staging-vt6655-fix-potential-memory-leak.patch @@ -0,0 +1,42 @@ +From e8e7e3d888ce7c61b77ee4fb941328d52da59bc5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 16:13:39 +0200 +Subject: staging: vt6655: fix potential memory leak + +From: Nam Cao + +[ Upstream commit c8ff91535880d41b49699b3829fb6151942de29e ] + +In function device_init_td0_ring, memory is allocated for member +td_info of priv->apTD0Rings[i], with i increasing from 0. In case of +allocation failure, the memory is freed in reversed order, with i +decreasing to 0. However, the case i=0 is left out and thus memory is +leaked. + +Modify the memory freeing loop to include the case i=0. + +Tested-by: Philipp Hortmann +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/20220909141338.19343-1-namcaov@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/staging/vt6655/device_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c +index 0dd70173a754..343f0de03154 100644 +--- a/drivers/staging/vt6655/device_main.c ++++ b/drivers/staging/vt6655/device_main.c +@@ -675,7 +675,7 @@ static int device_init_td0_ring(struct vnt_private *priv) + return 0; + + err_free_desc: +- while (--i) { ++ while (i--) { + desc = &priv->apTD0Rings[i]; + kfree(desc->td_info); + } +-- +2.35.1 + diff --git a/queue-5.10/staging-vt6655-fix-some-erroneous-memory-clean-up-lo.patch b/queue-5.10/staging-vt6655-fix-some-erroneous-memory-clean-up-lo.patch new file mode 100644 index 00000000000..5baab5b44d2 --- /dev/null +++ b/queue-5.10/staging-vt6655-fix-some-erroneous-memory-clean-up-lo.patch @@ -0,0 +1,68 @@ +From 679213b28930a90d0782cb2283f3c917d2975106 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 12 Sep 2022 19:04:31 +0200 +Subject: staging: vt6655: fix some erroneous memory clean-up loops + +From: Nam Cao + +[ Upstream commit 2a2db520e3ca5aafba7c211abfd397666c9b5f9d ] + +In some initialization functions of this driver, memory is allocated with +'i' acting as an index variable and increasing from 0. The commit in +"Fixes" introduces some clean-up codes in case of allocation failure, +which free memory in reverse order with 'i' decreasing to 0. However, +there are some problems: + - The case i=0 is left out. Thus memory is leaked. + - In case memory allocation fails right from the start, the memory + freeing loops will start with i=-1 and invalid memory locations will + be accessed. + +One of these loops has been fixed in commit c8ff91535880 ("staging: +vt6655: fix potential memory leak"). Fix the remaining erroneous loops. + +Link: https://lore.kernel.org/linux-staging/Yx9H1zSpxmNqx6Xc@kadam/ +Fixes: 5341ee0adb17 ("staging: vt6655: check for memory allocation failures") +Reported-by: Dan Carpenter +Tested-by: Philipp Hortmann +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/20220912170429.29852-1-namcaov@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/staging/vt6655/device_main.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c +index 09ab6d6f2429..0dd70173a754 100644 +--- a/drivers/staging/vt6655/device_main.c ++++ b/drivers/staging/vt6655/device_main.c +@@ -564,7 +564,7 @@ static int device_init_rd0_ring(struct vnt_private *priv) + kfree(desc->rd_info); + + err_free_desc: +- while (--i) { ++ while (i--) { + desc = &priv->aRD0Ring[i]; + device_free_rx_buf(priv, desc); + kfree(desc->rd_info); +@@ -610,7 +610,7 @@ static int device_init_rd1_ring(struct vnt_private *priv) + kfree(desc->rd_info); + + err_free_desc: +- while (--i) { ++ while (i--) { + desc = &priv->aRD1Ring[i]; + device_free_rx_buf(priv, desc); + kfree(desc->rd_info); +@@ -715,7 +715,7 @@ static int device_init_td1_ring(struct vnt_private *priv) + return 0; + + err_free_desc: +- while (--i) { ++ while (i--) { + desc = &priv->apTD1Rings[i]; + kfree(desc->td_info); + } +-- +2.35.1 + diff --git a/queue-5.10/tcp-annotate-data-race-around-tcp_md5sig_pool_popula.patch b/queue-5.10/tcp-annotate-data-race-around-tcp_md5sig_pool_popula.patch new file mode 100644 index 00000000000..6a490c4cbb2 --- /dev/null +++ b/queue-5.10/tcp-annotate-data-race-around-tcp_md5sig_pool_popula.patch @@ -0,0 +1,72 @@ +From 22bcdaa4b5363ed22262f356bff4a5e086087489 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 22 Aug 2022 21:15:28 +0000 +Subject: tcp: annotate data-race around tcp_md5sig_pool_populated + +From: Eric Dumazet + +[ Upstream commit aacd467c0a576e5e44d2de4205855dc0fe43f6fb ] + +tcp_md5sig_pool_populated can be read while another thread +changes its value. + +The race has no consequence because allocations +are protected with tcp_md5sig_mutex. + +This patch adds READ_ONCE() and WRITE_ONCE() to document +the race and silence KCSAN. + +Reported-by: Abhishek Shah +Signed-off-by: Eric Dumazet +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + net/ipv4/tcp.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c +index 24328ad00278..b0aa7cc69d51 100644 +--- a/net/ipv4/tcp.c ++++ b/net/ipv4/tcp.c +@@ -4043,12 +4043,16 @@ static void __tcp_alloc_md5sig_pool(void) + * to memory. See smp_rmb() in tcp_get_md5sig_pool() + */ + smp_wmb(); +- tcp_md5sig_pool_populated = true; ++ /* Paired with READ_ONCE() from tcp_alloc_md5sig_pool() ++ * and tcp_get_md5sig_pool(). ++ */ ++ WRITE_ONCE(tcp_md5sig_pool_populated, true); + } + + bool tcp_alloc_md5sig_pool(void) + { +- if (unlikely(!tcp_md5sig_pool_populated)) { ++ /* Paired with WRITE_ONCE() from __tcp_alloc_md5sig_pool() */ ++ if (unlikely(!READ_ONCE(tcp_md5sig_pool_populated))) { + mutex_lock(&tcp_md5sig_mutex); + + if (!tcp_md5sig_pool_populated) { +@@ -4059,7 +4063,8 @@ bool tcp_alloc_md5sig_pool(void) + + mutex_unlock(&tcp_md5sig_mutex); + } +- return tcp_md5sig_pool_populated; ++ /* Paired with WRITE_ONCE() from __tcp_alloc_md5sig_pool() */ ++ return READ_ONCE(tcp_md5sig_pool_populated); + } + EXPORT_SYMBOL(tcp_alloc_md5sig_pool); + +@@ -4075,7 +4080,8 @@ struct tcp_md5sig_pool *tcp_get_md5sig_pool(void) + { + local_bh_disable(); + +- if (tcp_md5sig_pool_populated) { ++ /* Paired with WRITE_ONCE() from __tcp_alloc_md5sig_pool() */ ++ if (READ_ONCE(tcp_md5sig_pool_populated)) { + /* coupled with smp_wmb() in __tcp_alloc_md5sig_pool() */ + smp_rmb(); + return this_cpu_ptr(&tcp_md5sig_pool); +-- +2.35.1 + diff --git a/queue-5.10/tcp-fix-tcp_cwnd_validate-to-not-forget-is_cwnd_limi.patch b/queue-5.10/tcp-fix-tcp_cwnd_validate-to-not-forget-is_cwnd_limi.patch new file mode 100644 index 00000000000..095020c5931 --- /dev/null +++ b/queue-5.10/tcp-fix-tcp_cwnd_validate-to-not-forget-is_cwnd_limi.patch @@ -0,0 +1,150 @@ +From 18e17f7393e3b319ec4ab195db1137a486b5ad8a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 28 Sep 2022 16:03:31 -0400 +Subject: tcp: fix tcp_cwnd_validate() to not forget is_cwnd_limited + +From: Neal Cardwell + +[ Upstream commit f4ce91ce12a7c6ead19b128ffa8cff6e3ded2a14 ] + +This commit fixes a bug in the tracking of max_packets_out and +is_cwnd_limited. This bug can cause the connection to fail to remember +that is_cwnd_limited is true, causing the connection to fail to grow +cwnd when it should, causing throughput to be lower than it should be. + +The following event sequence is an example that triggers the bug: + + (a) The connection is cwnd_limited, but packets_out is not at its + peak due to TSO deferral deciding not to send another skb yet. + In such cases the connection can advance max_packets_seq and set + tp->is_cwnd_limited to true and max_packets_out to a small + number. + +(b) Then later in the round trip the connection is pacing-limited (not + cwnd-limited), and packets_out is larger. In such cases the + connection would raise max_packets_out to a bigger number but + (unexpectedly) flip tp->is_cwnd_limited from true to false. + +This commit fixes that bug. + +One straightforward fix would be to separately track (a) the next +window after max_packets_out reaches a maximum, and (b) the next +window after tp->is_cwnd_limited is set to true. But this would +require consuming an extra u32 sequence number. + +Instead, to save space we track only the most important +information. Specifically, we track the strongest available signal of +the degree to which the cwnd is fully utilized: + +(1) If the connection is cwnd-limited then we remember that fact for +the current window. + +(2) If the connection not cwnd-limited then we track the maximum +number of outstanding packets in the current window. + +In particular, note that the new logic cannot trigger the buggy +(a)/(b) sequence above because with the new logic a condition where +tp->packets_out > tp->max_packets_out can only trigger an update of +tp->is_cwnd_limited if tp->is_cwnd_limited is false. + +This first showed up in a testing of a BBRv2 dev branch, but this +buggy behavior highlighted a general issue with the +tcp_cwnd_validate() logic that can cause cwnd to fail to increase at +the proper rate for any TCP congestion control, including Reno or +CUBIC. + +Fixes: ca8a22634381 ("tcp: make cwnd-limited checks measurement-based, and gentler") +Signed-off-by: Neal Cardwell +Signed-off-by: Kevin(Yudong) Yang +Signed-off-by: Yuchung Cheng +Signed-off-by: Eric Dumazet +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + include/linux/tcp.h | 2 +- + include/net/tcp.h | 5 ++++- + net/ipv4/tcp.c | 2 ++ + net/ipv4/tcp_output.c | 19 ++++++++++++------- + 4 files changed, 19 insertions(+), 9 deletions(-) + +diff --git a/include/linux/tcp.h b/include/linux/tcp.h +index 2f87377e9af7..6e3340379d85 100644 +--- a/include/linux/tcp.h ++++ b/include/linux/tcp.h +@@ -265,7 +265,7 @@ struct tcp_sock { + u32 packets_out; /* Packets which are "in flight" */ + u32 retrans_out; /* Retransmitted packets out */ + u32 max_packets_out; /* max packets_out in last window */ +- u32 max_packets_seq; /* right edge of max_packets_out flight */ ++ u32 cwnd_usage_seq; /* right edge of cwnd usage tracking flight */ + + u16 urg_data; /* Saved octet of OOB data and control flags */ + u8 ecn_flags; /* ECN status bits. */ +diff --git a/include/net/tcp.h b/include/net/tcp.h +index 8129ce9a0771..bf4af27f5620 100644 +--- a/include/net/tcp.h ++++ b/include/net/tcp.h +@@ -1271,11 +1271,14 @@ static inline bool tcp_is_cwnd_limited(const struct sock *sk) + { + const struct tcp_sock *tp = tcp_sk(sk); + ++ if (tp->is_cwnd_limited) ++ return true; ++ + /* If in slow start, ensure cwnd grows to twice what was ACKed. */ + if (tcp_in_slow_start(tp)) + return tp->snd_cwnd < 2 * tp->max_packets_out; + +- return tp->is_cwnd_limited; ++ return false; + } + + /* BBR congestion control needs pacing. +diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c +index bfeb05f62b94..24328ad00278 100644 +--- a/net/ipv4/tcp.c ++++ b/net/ipv4/tcp.c +@@ -2796,6 +2796,8 @@ int tcp_disconnect(struct sock *sk, int flags) + tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; + tp->snd_cwnd = TCP_INIT_CWND; + tp->snd_cwnd_cnt = 0; ++ tp->is_cwnd_limited = 0; ++ tp->max_packets_out = 0; + tp->window_clamp = 0; + tp->delivered = 0; + tp->delivered_ce = 0; +diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c +index 48fce999dc61..eefd032bc6db 100644 +--- a/net/ipv4/tcp_output.c ++++ b/net/ipv4/tcp_output.c +@@ -1876,15 +1876,20 @@ static void tcp_cwnd_validate(struct sock *sk, bool is_cwnd_limited) + const struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops; + struct tcp_sock *tp = tcp_sk(sk); + +- /* Track the maximum number of outstanding packets in each +- * window, and remember whether we were cwnd-limited then. ++ /* Track the strongest available signal of the degree to which the cwnd ++ * is fully utilized. If cwnd-limited then remember that fact for the ++ * current window. If not cwnd-limited then track the maximum number of ++ * outstanding packets in the current window. (If cwnd-limited then we ++ * chose to not update tp->max_packets_out to avoid an extra else ++ * clause with no functional impact.) + */ +- if (!before(tp->snd_una, tp->max_packets_seq) || +- tp->packets_out > tp->max_packets_out || +- is_cwnd_limited) { +- tp->max_packets_out = tp->packets_out; +- tp->max_packets_seq = tp->snd_nxt; ++ if (!before(tp->snd_una, tp->cwnd_usage_seq) || ++ is_cwnd_limited || ++ (!tp->is_cwnd_limited && ++ tp->packets_out > tp->max_packets_out)) { + tp->is_cwnd_limited = is_cwnd_limited; ++ tp->max_packets_out = tp->packets_out; ++ tp->cwnd_usage_seq = tp->snd_nxt; + } + + if (tcp_is_cwnd_limited(sk)) { +-- +2.35.1 + diff --git a/queue-5.10/thermal-drivers-qcom-tsens-v0_1-fix-msm8939-fourth-s.patch b/queue-5.10/thermal-drivers-qcom-tsens-v0_1-fix-msm8939-fourth-s.patch new file mode 100644 index 00000000000..812d3ce2f4a --- /dev/null +++ b/queue-5.10/thermal-drivers-qcom-tsens-v0_1-fix-msm8939-fourth-s.patch @@ -0,0 +1,44 @@ +From 8d546d98c611c74924dda2cc91f7b4f930c8ba34 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 11 Aug 2022 12:50:14 +0200 +Subject: thermal/drivers/qcom/tsens-v0_1: Fix MSM8939 fourth sensor hw_id + +From: Vincent Knecht + +[ Upstream commit b0c883e900702f408d62cf92b0ef01303ed69be9 ] + +Reading temperature from this sensor fails with 'Invalid argument'. + +Looking at old vendor dts [1], its hw_id should be 3 instead of 4. +Change this hw_id accordingly. + +[1] https://github.com/msm8916-mainline/android_kernel_qcom_msm8916/blob/master/arch/arm/boot/dts/qcom/msm8939-common.dtsi#L511 + +Fixes: 332bc8ebab2c ("thermal: qcom: tsens-v0_1: Add support for MSM8939") +Signed-off-by: Vincent Knecht +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Bjorn Andersson +Reviewed-by: Bryan O'Donoghue +Link: https://lore.kernel.org/r/20220811105014.7194-1-vincent.knecht@mailoo.org +Signed-off-by: Daniel Lezcano +Signed-off-by: Sasha Levin +--- + drivers/thermal/qcom/tsens-v0_1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c +index 4ffa2e2c0145..9b8ba429a304 100644 +--- a/drivers/thermal/qcom/tsens-v0_1.c ++++ b/drivers/thermal/qcom/tsens-v0_1.c +@@ -522,7 +522,7 @@ static const struct tsens_ops ops_8939 = { + struct tsens_plat_data data_8939 = { + .num_sensors = 10, + .ops = &ops_8939, +- .hw_ids = (unsigned int []){ 0, 1, 2, 4, 5, 6, 7, 8, 9, 10 }, ++ .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 }, + + .feat = &tsens_v0_1_feat, + .fields = tsens_v0_1_regfields, +-- +2.35.1 + diff --git a/queue-5.10/thermal-intel_powerclamp-use-get_cpu-instead-of-smp_.patch b/queue-5.10/thermal-intel_powerclamp-use-get_cpu-instead-of-smp_.patch new file mode 100644 index 00000000000..d56e38dfad5 --- /dev/null +++ b/queue-5.10/thermal-intel_powerclamp-use-get_cpu-instead-of-smp_.patch @@ -0,0 +1,61 @@ +From fb51c7ab2196b437228fb8b9d1c6b38f305a8815 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 04:06:57 -0700 +Subject: thermal: intel_powerclamp: Use get_cpu() instead of + smp_processor_id() to avoid crash + +From: Srinivas Pandruvada + +[ Upstream commit 68b99e94a4a2db6ba9b31fe0485e057b9354a640 ] + +When CPU 0 is offline and intel_powerclamp is used to inject +idle, it generates kernel BUG: + +BUG: using smp_processor_id() in preemptible [00000000] code: bash/15687 +caller is debug_smp_processor_id+0x17/0x20 +CPU: 4 PID: 15687 Comm: bash Not tainted 5.19.0-rc7+ #57 +Call Trace: + +dump_stack_lvl+0x49/0x63 +dump_stack+0x10/0x16 +check_preemption_disabled+0xdd/0xe0 +debug_smp_processor_id+0x17/0x20 +powerclamp_set_cur_state+0x7f/0xf9 [intel_powerclamp] +... +... + +Here CPU 0 is the control CPU by default and changed to the current CPU, +if CPU 0 offlined. This check has to be performed under cpus_read_lock(), +hence the above warning. + +Use get_cpu() instead of smp_processor_id() to avoid this BUG. + +Suggested-by: Chen Yu +Signed-off-by: Srinivas Pandruvada +[ rjw: Subject edits ] +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Sasha Levin +--- + drivers/thermal/intel/intel_powerclamp.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/thermal/intel/intel_powerclamp.c b/drivers/thermal/intel/intel_powerclamp.c +index b0eb5ece9243..14381f7587ff 100644 +--- a/drivers/thermal/intel/intel_powerclamp.c ++++ b/drivers/thermal/intel/intel_powerclamp.c +@@ -532,8 +532,10 @@ static int start_power_clamp(void) + + /* prefer BSP */ + control_cpu = 0; +- if (!cpu_online(control_cpu)) +- control_cpu = smp_processor_id(); ++ if (!cpu_online(control_cpu)) { ++ control_cpu = get_cpu(); ++ put_cpu(); ++ } + + clamping = true; + schedule_delayed_work(&poll_pkg_cstate_work, 0); +-- +2.35.1 + diff --git a/queue-5.10/tracing-kprobe-fix-kprobe-event-gen-test-module-on-e.patch b/queue-5.10/tracing-kprobe-fix-kprobe-event-gen-test-module-on-e.patch new file mode 100644 index 00000000000..5d280f2869e --- /dev/null +++ b/queue-5.10/tracing-kprobe-fix-kprobe-event-gen-test-module-on-e.patch @@ -0,0 +1,47 @@ +From 98bb47b125cb39a734f4b88c94213ff4ec8ca9a4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 20:56:28 +0800 +Subject: tracing: kprobe: Fix kprobe event gen test module on exit + +From: Yipeng Zou + +[ Upstream commit ac48e189527fae87253ef2bf58892e782fb36874 ] + +Correct gen_kretprobe_test clr event para on module exit. +This will make it can't to delete. + +Link: https://lkml.kernel.org/r/20220919125629.238242-2-zouyipeng@huawei.com + +Cc: +Cc: +Cc: +Cc: +Cc: +Cc: +Cc: +Cc: +Fixes: 64836248dda2 ("tracing: Add kprobe event command generation test module") +Signed-off-by: Yipeng Zou +Acked-by: Masami Hiramatsu (Google) +Signed-off-by: Steven Rostedt (Google) +Signed-off-by: Sasha Levin +--- + kernel/trace/kprobe_event_gen_test.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/kernel/trace/kprobe_event_gen_test.c b/kernel/trace/kprobe_event_gen_test.c +index 18b0f1cbb947..e023154be0f8 100644 +--- a/kernel/trace/kprobe_event_gen_test.c ++++ b/kernel/trace/kprobe_event_gen_test.c +@@ -206,7 +206,7 @@ static void __exit kprobe_event_gen_test_exit(void) + WARN_ON(kprobe_event_delete("gen_kprobe_test")); + + /* Disable the event or you can't remove it */ +- WARN_ON(trace_array_set_clr_event(gen_kprobe_test->tr, ++ WARN_ON(trace_array_set_clr_event(gen_kretprobe_test->tr, + "kprobes", + "gen_kretprobe_test", false)); + +-- +2.35.1 + diff --git a/queue-5.10/tracing-kprobe-make-gen-test-module-work-in-arm-and-.patch b/queue-5.10/tracing-kprobe-make-gen-test-module-work-in-arm-and-.patch new file mode 100644 index 00000000000..7d41675c9d6 --- /dev/null +++ b/queue-5.10/tracing-kprobe-make-gen-test-module-work-in-arm-and-.patch @@ -0,0 +1,113 @@ +From 02d61c2a68c7089ec41cdcdd1e8af0ea2a5f9a3f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 20:56:29 +0800 +Subject: tracing: kprobe: Make gen test module work in arm and riscv + +From: Yipeng Zou + +[ Upstream commit d8ef45d66c01425ff748e13ef7dd1da7a91cc93c ] + +For now, this selftest module can only work in x86 because of the +kprobe cmd was fixed use of x86 registers. +This patch adapted to register names under arm and riscv, So that +this module can be worked on those platform. + +Link: https://lkml.kernel.org/r/20220919125629.238242-3-zouyipeng@huawei.com + +Cc: +Cc: +Cc: +Cc: +Cc: +Cc: +Cc: +Cc: +Fixes: 64836248dda2 ("tracing: Add kprobe event command generation test module") +Signed-off-by: Yipeng Zou +Acked-by: Masami Hiramatsu (Google) +Signed-off-by: Steven Rostedt (Google) +Signed-off-by: Sasha Levin +--- + kernel/trace/kprobe_event_gen_test.c | 47 +++++++++++++++++++++++++--- + 1 file changed, 43 insertions(+), 4 deletions(-) + +diff --git a/kernel/trace/kprobe_event_gen_test.c b/kernel/trace/kprobe_event_gen_test.c +index e023154be0f8..80e04a1e1977 100644 +--- a/kernel/trace/kprobe_event_gen_test.c ++++ b/kernel/trace/kprobe_event_gen_test.c +@@ -35,6 +35,45 @@ + static struct trace_event_file *gen_kprobe_test; + static struct trace_event_file *gen_kretprobe_test; + ++#define KPROBE_GEN_TEST_FUNC "do_sys_open" ++ ++/* X86 */ ++#if defined(CONFIG_X86_64) || defined(CONFIG_X86_32) ++#define KPROBE_GEN_TEST_ARG0 "dfd=%ax" ++#define KPROBE_GEN_TEST_ARG1 "filename=%dx" ++#define KPROBE_GEN_TEST_ARG2 "flags=%cx" ++#define KPROBE_GEN_TEST_ARG3 "mode=+4($stack)" ++ ++/* ARM64 */ ++#elif defined(CONFIG_ARM64) ++#define KPROBE_GEN_TEST_ARG0 "dfd=%x0" ++#define KPROBE_GEN_TEST_ARG1 "filename=%x1" ++#define KPROBE_GEN_TEST_ARG2 "flags=%x2" ++#define KPROBE_GEN_TEST_ARG3 "mode=%x3" ++ ++/* ARM */ ++#elif defined(CONFIG_ARM) ++#define KPROBE_GEN_TEST_ARG0 "dfd=%r0" ++#define KPROBE_GEN_TEST_ARG1 "filename=%r1" ++#define KPROBE_GEN_TEST_ARG2 "flags=%r2" ++#define KPROBE_GEN_TEST_ARG3 "mode=%r3" ++ ++/* RISCV */ ++#elif defined(CONFIG_RISCV) ++#define KPROBE_GEN_TEST_ARG0 "dfd=%a0" ++#define KPROBE_GEN_TEST_ARG1 "filename=%a1" ++#define KPROBE_GEN_TEST_ARG2 "flags=%a2" ++#define KPROBE_GEN_TEST_ARG3 "mode=%a3" ++ ++/* others */ ++#else ++#define KPROBE_GEN_TEST_ARG0 NULL ++#define KPROBE_GEN_TEST_ARG1 NULL ++#define KPROBE_GEN_TEST_ARG2 NULL ++#define KPROBE_GEN_TEST_ARG3 NULL ++#endif ++ ++ + /* + * Test to make sure we can create a kprobe event, then add more + * fields. +@@ -58,14 +97,14 @@ static int __init test_gen_kprobe_cmd(void) + * fields. + */ + ret = kprobe_event_gen_cmd_start(&cmd, "gen_kprobe_test", +- "do_sys_open", +- "dfd=%ax", "filename=%dx"); ++ KPROBE_GEN_TEST_FUNC, ++ KPROBE_GEN_TEST_ARG0, KPROBE_GEN_TEST_ARG1); + if (ret) + goto free; + + /* Use kprobe_event_add_fields to add the rest of the fields */ + +- ret = kprobe_event_add_fields(&cmd, "flags=%cx", "mode=+4($stack)"); ++ ret = kprobe_event_add_fields(&cmd, KPROBE_GEN_TEST_ARG2, KPROBE_GEN_TEST_ARG3); + if (ret) + goto free; + +@@ -128,7 +167,7 @@ static int __init test_gen_kretprobe_cmd(void) + * Define the kretprobe event. + */ + ret = kretprobe_event_gen_cmd_start(&cmd, "gen_kretprobe_test", +- "do_sys_open", ++ KPROBE_GEN_TEST_FUNC, + "$retval"); + if (ret) + goto free; +-- +2.35.1 + diff --git a/queue-5.10/tty-serial-fsl_lpuart-disable-dma-rx-tx-use-flags-in.patch b/queue-5.10/tty-serial-fsl_lpuart-disable-dma-rx-tx-use-flags-in.patch new file mode 100644 index 00000000000..b3ef84b2b8b --- /dev/null +++ b/queue-5.10/tty-serial-fsl_lpuart-disable-dma-rx-tx-use-flags-in.patch @@ -0,0 +1,103 @@ +From cf727a1648209fd057b24e5b58391d684cfed32d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 19:17:03 +0800 +Subject: tty: serial: fsl_lpuart: disable dma rx/tx use flags in + lpuart_dma_shutdown +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Sherry Sun + +[ Upstream commit 316ae95c175a7d770d1bfe4c011192712f57aa4a ] + +lpuart_dma_shutdown tears down lpuart dma, but lpuart_flush_buffer can +still occur which in turn tries to access dma apis if lpuart_dma_tx_use +flag is true. At this point since dma is torn down, these dma apis can +abort. Set lpuart_dma_tx_use and the corresponding rx flag +lpuart_dma_rx_use to false in lpuart_dma_shutdown so that dmas are not +accessed after they are relinquished. + +Otherwise, when try to kill btattach, kernel may panic. This patch may +fix this issue. +root@imx8ulpevk:~# btattach -B /dev/ttyLP2 -S 115200 +^C[ 90.182296] Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP +[ 90.189806] Modules linked in: moal(O) mlan(O) +[ 90.194258] CPU: 0 PID: 503 Comm: btattach Tainted: G O 5.15.32-06136-g34eecdf2f9e4 #37 +[ 90.203554] Hardware name: NXP i.MX8ULP 9X9 EVK (DT) +[ 90.208513] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) +[ 90.215470] pc : fsl_edma3_disable_request+0x8/0x60 +[ 90.220358] lr : fsl_edma3_terminate_all+0x34/0x20c +[ 90.225237] sp : ffff800013f0bac0 +[ 90.228548] x29: ffff800013f0bac0 x28: 0000000000000001 x27: ffff000008404800 +[ 90.235681] x26: ffff000008404960 x25: ffff000008404a08 x24: ffff000008404a00 +[ 90.242813] x23: ffff000008404a60 x22: 0000000000000002 x21: 0000000000000000 +[ 90.249946] x20: ffff800013f0baf8 x19: ffff00000559c800 x18: 0000000000000000 +[ 90.257078] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 +[ 90.264211] x14: 0000000000000003 x13: 0000000000000000 x12: 0000000000000040 +[ 90.271344] x11: ffff00000600c248 x10: ffff800013f0bb10 x9 : ffff000057bcb090 +[ 90.278477] x8 : fffffc0000241a08 x7 : ffff00000534ee00 x6 : ffff000008404804 +[ 90.285609] x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff0000055b3480 +[ 90.292742] x2 : ffff8000135c0000 x1 : ffff00000534ee00 x0 : ffff00000559c800 +[ 90.299876] Call trace: +[ 90.302321] fsl_edma3_disable_request+0x8/0x60 +[ 90.306851] lpuart_flush_buffer+0x40/0x160 +[ 90.311037] uart_flush_buffer+0x88/0x120 +[ 90.315050] tty_driver_flush_buffer+0x20/0x30 +[ 90.319496] hci_uart_flush+0x44/0x90 +[ 90.323162] +0x34/0x12c +[ 90.327253] tty_ldisc_close+0x38/0x70 +[ 90.331005] tty_ldisc_release+0xa8/0x190 +[ 90.335018] tty_release_struct+0x24/0x8c +[ 90.339022] tty_release+0x3ec/0x4c0 +[ 90.342593] __fput+0x70/0x234 +[ 90.345652] ____fput+0x14/0x20 +[ 90.348790] task_work_run+0x84/0x17c +[ 90.352455] do_exit+0x310/0x96c +[ 90.355688] do_group_exit+0x3c/0xa0 +[ 90.359259] __arm64_sys_exit_group+0x1c/0x20 +[ 90.363609] invoke_syscall+0x48/0x114 +[ 90.367362] el0_svc_common.constprop.0+0xd4/0xfc +[ 90.372068] do_el0_svc+0x2c/0x94 +[ 90.375379] el0_svc+0x28/0x80 +[ 90.378438] el0t_64_sync_handler+0xa8/0x130 +[ 90.382711] el0t_64_sync+0x1a0/0x1a4 +[ 90.386376] Code: 17ffffda d503201f d503233f f9409802 (b9400041) +[ 90.392467] ---[ end trace 2f60524b4a43f1f6 ]--- +[ 90.397073] note: btattach[503] exited with preempt_count 1 +[ 90.402636] Fixing recursive fault but reboot is needed! + +Fixes: 6250cc30c4c4 ("tty: serial: fsl_lpuart: Use scatter/gather DMA for Tx") +Reviewed-by: Ilpo Järvinen +Signed-off-by: Thara Gopinath +Signed-off-by: Sherry Sun +Link: https://lore.kernel.org/r/20220920111703.1532-1-sherry.sun@nxp.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/fsl_lpuart.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c +index a2c4eab0b470..269d1e3a025d 100644 +--- a/drivers/tty/serial/fsl_lpuart.c ++++ b/drivers/tty/serial/fsl_lpuart.c +@@ -1725,6 +1725,7 @@ static void lpuart_dma_shutdown(struct lpuart_port *sport) + if (sport->lpuart_dma_rx_use) { + del_timer_sync(&sport->lpuart_timer); + lpuart_dma_rx_free(&sport->port); ++ sport->lpuart_dma_rx_use = false; + } + + if (sport->lpuart_dma_tx_use) { +@@ -1733,6 +1734,7 @@ static void lpuart_dma_shutdown(struct lpuart_port *sport) + sport->dma_tx_in_progress = false; + dmaengine_terminate_all(sport->dma_tx_chan); + } ++ sport->lpuart_dma_tx_use = false; + } + + if (sport->dma_tx_chan) +-- +2.35.1 + diff --git a/queue-5.10/tty-xilinx_uartps-fix-the-ignore_status.patch b/queue-5.10/tty-xilinx_uartps-fix-the-ignore_status.patch new file mode 100644 index 00000000000..a6c837a63b2 --- /dev/null +++ b/queue-5.10/tty-xilinx_uartps-fix-the-ignore_status.patch @@ -0,0 +1,37 @@ +From 2c01aba67d8f27b8b32b7b7c97bd63bdaf390b9e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 29 Jul 2022 17:17:45 +0530 +Subject: tty: xilinx_uartps: Fix the ignore_status + +From: Shubhrajyoti Datta + +[ Upstream commit b8a6c3b3d4654fba19881cc77da61eac29f57cae ] + +Currently the ignore_status is not considered in the isr. +Add a check to add the ignore_status. + +Fixes: 61ec9016988f ("tty/serial: add support for Xilinx PS UART") +Signed-off-by: Shubhrajyoti Datta +Link: https://lore.kernel.org/r/20220729114748.18332-5-shubhrajyoti.datta@xilinx.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/xilinx_uartps.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c +index b5a8afbc452b..f7dfa123907a 100644 +--- a/drivers/tty/serial/xilinx_uartps.c ++++ b/drivers/tty/serial/xilinx_uartps.c +@@ -375,6 +375,8 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id) + isrstatus &= ~CDNS_UART_IXR_TXEMPTY; + } + ++ isrstatus &= port->read_status_mask; ++ isrstatus &= ~port->ignore_status_mask; + /* + * Skip RX processing if RX is disabled as RXEMPTY will never be set + * as read bytes will not be removed from the FIFO. +-- +2.35.1 + diff --git a/queue-5.10/udmabuf-set-ubuf-sg-null-if-the-creation-of-sg-table.patch b/queue-5.10/udmabuf-set-ubuf-sg-null-if-the-creation-of-sg-table.patch new file mode 100644 index 00000000000..b327847bbe2 --- /dev/null +++ b/queue-5.10/udmabuf-set-ubuf-sg-null-if-the-creation-of-sg-table.patch @@ -0,0 +1,115 @@ +From 98b49aaf9edb5f7cb3e16976e9d501f77bb8840a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 23:35:22 -0700 +Subject: udmabuf: Set ubuf->sg = NULL if the creation of sg table fails + +From: Vivek Kasireddy + +[ Upstream commit d9c04a1b7a15b5e74b2977461d9511e497f05d8f ] + +When userspace tries to map the dmabuf and if for some reason +(e.g. OOM) the creation of the sg table fails, ubuf->sg needs to be +set to NULL. Otherwise, when the userspace subsequently closes the +dmabuf fd, we'd try to erroneously free the invalid sg table from +release_udmabuf resulting in the following crash reported by syzbot: + +general protection fault, probably for non-canonical address +0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN +KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007] +CPU: 0 PID: 3609 Comm: syz-executor487 Not tainted +5.19.0-syzkaller-13930-g7ebfc85e2cd7 #0 +Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS +Google 07/22/2022 +RIP: 0010:dma_unmap_sgtable include/linux/dma-mapping.h:378 [inline] +RIP: 0010:put_sg_table drivers/dma-buf/udmabuf.c:89 [inline] +RIP: 0010:release_udmabuf+0xcb/0x4f0 drivers/dma-buf/udmabuf.c:114 +Code: 48 89 fa 48 c1 ea 03 80 3c 02 00 0f 85 2b 04 00 00 48 8d 7d 0c 4c +8b 63 30 48 b8 00 00 00 00 00 fc ff df 48 89 fa 48 c1 ea 03 <0f> b6 14 +02 48 89 f8 83 e0 07 83 c0 03 38 d0 7c 08 84 d2 0f 85 e2 +RSP: 0018:ffffc900037efd30 EFLAGS: 00010246 +RAX: dffffc0000000000 RBX: ffffffff8cb67800 RCX: 0000000000000000 +RDX: 0000000000000000 RSI: ffffffff84ad27e0 RDI: 0000000000000000 +RBP: fffffffffffffff4 R08: 0000000000000005 R09: 0000000000000000 +R10: 0000000000000000 R11: 000000000008c07c R12: ffff88801fa05000 +R13: ffff888073db07e8 R14: ffff888025c25440 R15: 0000000000000000 +FS: 0000555555fc4300(0000) GS:ffff8880b9a00000(0000) +knlGS:0000000000000000 +CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +CR2: 00007fc1c0ce06e4 CR3: 00000000715e6000 CR4: 00000000003506f0 +DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 +DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 +Call Trace: + + dma_buf_release+0x157/0x2d0 drivers/dma-buf/dma-buf.c:78 + __dentry_kill+0x42b/0x640 fs/dcache.c:612 + dentry_kill fs/dcache.c:733 [inline] + dput+0x806/0xdb0 fs/dcache.c:913 + __fput+0x39c/0x9d0 fs/file_table.c:333 + task_work_run+0xdd/0x1a0 kernel/task_work.c:177 + ptrace_notify+0x114/0x140 kernel/signal.c:2353 + ptrace_report_syscall include/linux/ptrace.h:420 [inline] + ptrace_report_syscall_exit include/linux/ptrace.h:482 [inline] + syscall_exit_work kernel/entry/common.c:249 [inline] + syscall_exit_to_user_mode_prepare+0x129/0x280 kernel/entry/common.c:276 + __syscall_exit_to_user_mode_work kernel/entry/common.c:281 [inline] + syscall_exit_to_user_mode+0x9/0x50 kernel/entry/common.c:294 + do_syscall_64+0x42/0xb0 arch/x86/entry/common.c:86 + entry_SYSCALL_64_after_hwframe+0x63/0xcd +RIP: 0033:0x7fc1c0c35b6b +Code: 0f 05 48 3d 00 f0 ff ff 77 45 c3 0f 1f 40 00 48 83 ec 18 89 7c 24 +0c e8 63 fc ff ff 8b 7c 24 0c 41 89 c0 b8 03 00 00 00 0f 05 <48> 3d 00 +f0 ff ff 77 35 44 89 c7 89 44 24 0c e8 a1 fc ff ff 8b 44 +RSP: 002b:00007ffd78a06090 EFLAGS: 00000293 ORIG_RAX: 0000000000000003 +RAX: 0000000000000000 RBX: 0000000000000007 RCX: 00007fc1c0c35b6b +RDX: 0000000020000280 RSI: 0000000040086200 RDI: 0000000000000006 +RBP: 0000000000000007 R08: 0000000000000000 R09: 0000000000000000 +R10: 0000000000000000 R11: 0000000000000293 R12: 000000000000000c +R13: 0000000000000003 R14: 00007fc1c0cfe4a0 R15: 00007ffd78a06140 + +Modules linked in: +---[ end trace 0000000000000000 ]--- +RIP: 0010:dma_unmap_sgtable include/linux/dma-mapping.h:378 [inline] +RIP: 0010:put_sg_table drivers/dma-buf/udmabuf.c:89 [inline] +RIP: 0010:release_udmabuf+0xcb/0x4f0 drivers/dma-buf/udmabuf.c:114 + +Reported-by: syzbot+c80e9ef5d8bb45894db0@syzkaller.appspotmail.com +Cc: Gerd Hoffmann +Signed-off-by: Vivek Kasireddy +Link: http://patchwork.freedesktop.org/patch/msgid/20220825063522.801264-1-vivek.kasireddy@intel.com +Signed-off-by: Gerd Hoffmann +Signed-off-by: Sasha Levin +--- + drivers/dma-buf/udmabuf.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c +index b624f3d8f0e6..e359c5c6c4df 100644 +--- a/drivers/dma-buf/udmabuf.c ++++ b/drivers/dma-buf/udmabuf.c +@@ -118,17 +118,20 @@ static int begin_cpu_udmabuf(struct dma_buf *buf, + { + struct udmabuf *ubuf = buf->priv; + struct device *dev = ubuf->device->this_device; ++ int ret = 0; + + if (!ubuf->sg) { + ubuf->sg = get_sg_table(dev, buf, direction); +- if (IS_ERR(ubuf->sg)) +- return PTR_ERR(ubuf->sg); ++ if (IS_ERR(ubuf->sg)) { ++ ret = PTR_ERR(ubuf->sg); ++ ubuf->sg = NULL; ++ } + } else { + dma_sync_sg_for_cpu(dev, ubuf->sg->sgl, ubuf->sg->nents, + direction); + } + +- return 0; ++ return ret; + } + + static int end_cpu_udmabuf(struct dma_buf *buf, +-- +2.35.1 + diff --git a/queue-5.10/usb-ch9-add-usb-3.2-ssp-attributes.patch b/queue-5.10/usb-ch9-add-usb-3.2-ssp-attributes.patch new file mode 100644 index 00000000000..7c039b2e7b9 --- /dev/null +++ b/queue-5.10/usb-ch9-add-usb-3.2-ssp-attributes.patch @@ -0,0 +1,74 @@ +From 72fef2bfc16f959014a200d90223322072c24d57 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 13 Jan 2021 18:52:46 -0800 +Subject: usb: ch9: Add USB 3.2 SSP attributes + +From: Thinh Nguyen + +[ Upstream commit f2fc9ff28d1c9bef7760516feadd38164044caae ] + +In preparation for USB 3.2 dual-lane support, add sublink speed +attribute macros and enum usb_ssp_rate. A USB device that operates in +SuperSpeed Plus may operate at different speed and lane count. These +additional macros and enum values help specifying that. + +Signed-off-by: Thinh Nguyen +Link: https://lore.kernel.org/r/ae9293ebd63a29f2a2035054753534d9eb123d74.1610592135.git.Thinh.Nguyen@synopsys.com +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: b6155eaf6b05 ("usb: common: debug: Check non-standard control requests") +Signed-off-by: Sasha Levin +--- + include/linux/usb/ch9.h | 9 +++++++++ + include/uapi/linux/usb/ch9.h | 13 +++++++++++++ + 2 files changed, 22 insertions(+) + +diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h +index 604c6c514a50..86c50907634e 100644 +--- a/include/linux/usb/ch9.h ++++ b/include/linux/usb/ch9.h +@@ -36,6 +36,15 @@ + #include + #include + ++/* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */ ++ ++enum usb_ssp_rate { ++ USB_SSP_GEN_UNKNOWN = 0, ++ USB_SSP_GEN_2x1, ++ USB_SSP_GEN_1x2, ++ USB_SSP_GEN_2x2, ++}; ++ + /** + * usb_ep_type_string() - Returns human readable-name of the endpoint type. + * @ep_type: The endpoint type to return human-readable name for. If it's not +diff --git a/include/uapi/linux/usb/ch9.h b/include/uapi/linux/usb/ch9.h +index 0f865ae4ba89..17ce56198c9a 100644 +--- a/include/uapi/linux/usb/ch9.h ++++ b/include/uapi/linux/usb/ch9.h +@@ -968,9 +968,22 @@ struct usb_ssp_cap_descriptor { + __le32 bmSublinkSpeedAttr[1]; /* list of sublink speed attrib entries */ + #define USB_SSP_SUBLINK_SPEED_SSID (0xf) /* sublink speed ID */ + #define USB_SSP_SUBLINK_SPEED_LSE (0x3 << 4) /* Lanespeed exponent */ ++#define USB_SSP_SUBLINK_SPEED_LSE_BPS 0 ++#define USB_SSP_SUBLINK_SPEED_LSE_KBPS 1 ++#define USB_SSP_SUBLINK_SPEED_LSE_MBPS 2 ++#define USB_SSP_SUBLINK_SPEED_LSE_GBPS 3 ++ + #define USB_SSP_SUBLINK_SPEED_ST (0x3 << 6) /* Sublink type */ ++#define USB_SSP_SUBLINK_SPEED_ST_SYM_RX 0 ++#define USB_SSP_SUBLINK_SPEED_ST_ASYM_RX 1 ++#define USB_SSP_SUBLINK_SPEED_ST_SYM_TX 2 ++#define USB_SSP_SUBLINK_SPEED_ST_ASYM_TX 3 ++ + #define USB_SSP_SUBLINK_SPEED_RSVD (0x3f << 8) /* Reserved */ + #define USB_SSP_SUBLINK_SPEED_LP (0x3 << 14) /* Link protocol */ ++#define USB_SSP_SUBLINK_SPEED_LP_SS 0 ++#define USB_SSP_SUBLINK_SPEED_LP_SSP 1 ++ + #define USB_SSP_SUBLINK_SPEED_LSM (0xff << 16) /* Lanespeed mantissa */ + } __attribute__((packed)); + +-- +2.35.1 + diff --git a/queue-5.10/usb-common-add-function-to-get-interval-expressed-in.patch b/queue-5.10/usb-common-add-function-to-get-interval-expressed-in.patch new file mode 100644 index 00000000000..8b111a442de --- /dev/null +++ b/queue-5.10/usb-common-add-function-to-get-interval-expressed-in.patch @@ -0,0 +1,189 @@ +From 9790499220220f4e8471d3f0110e18ab3b553bcd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Mar 2021 10:52:05 +0800 +Subject: usb: common: add function to get interval expressed in us unit + +From: Chunfeng Yun + +[ Upstream commit fb95c7cf5600b7b74412f27dfb39a1e13fd8a90d ] + +Add a new function to convert bInterval into the time expressed +in 1us unit. + +Signed-off-by: Chunfeng Yun +Link: https://lore.kernel.org/r/25c8a09b055f716c1e5bf11fea72c3418f844482.1615170625.git.chunfeng.yun@mediatek.com +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: b6155eaf6b05 ("usb: common: debug: Check non-standard control requests") +Signed-off-by: Sasha Levin +--- + drivers/usb/common/common.c | 41 +++++++++++++++++++++++++++++++++++++ + drivers/usb/core/devices.c | 21 ++++--------------- + drivers/usb/core/endpoint.c | 35 ++++--------------------------- + include/linux/usb/ch9.h | 3 +++ + 4 files changed, 52 insertions(+), 48 deletions(-) + +diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c +index fc21cf2d36f6..675e8a4e683a 100644 +--- a/drivers/usb/common/common.c ++++ b/drivers/usb/common/common.c +@@ -165,6 +165,47 @@ enum usb_dr_mode usb_get_dr_mode(struct device *dev) + } + EXPORT_SYMBOL_GPL(usb_get_dr_mode); + ++/** ++ * usb_decode_interval - Decode bInterval into the time expressed in 1us unit ++ * @epd: The descriptor of the endpoint ++ * @speed: The speed that the endpoint works as ++ * ++ * Function returns the interval expressed in 1us unit for servicing ++ * endpoint for data transfers. ++ */ ++unsigned int usb_decode_interval(const struct usb_endpoint_descriptor *epd, ++ enum usb_device_speed speed) ++{ ++ unsigned int interval = 0; ++ ++ switch (usb_endpoint_type(epd)) { ++ case USB_ENDPOINT_XFER_CONTROL: ++ /* uframes per NAK */ ++ if (speed == USB_SPEED_HIGH) ++ interval = epd->bInterval; ++ break; ++ case USB_ENDPOINT_XFER_ISOC: ++ interval = 1 << (epd->bInterval - 1); ++ break; ++ case USB_ENDPOINT_XFER_BULK: ++ /* uframes per NAK */ ++ if (speed == USB_SPEED_HIGH && usb_endpoint_dir_out(epd)) ++ interval = epd->bInterval; ++ break; ++ case USB_ENDPOINT_XFER_INT: ++ if (speed >= USB_SPEED_HIGH) ++ interval = 1 << (epd->bInterval - 1); ++ else ++ interval = epd->bInterval; ++ break; ++ } ++ ++ interval *= (speed >= USB_SPEED_HIGH) ? 125 : 1000; ++ ++ return interval; ++} ++EXPORT_SYMBOL_GPL(usb_decode_interval); ++ + #ifdef CONFIG_OF + /** + * of_usb_get_dr_mode_by_phy - Get dual role mode for the controller device +diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c +index 1ef2de6e375a..d8b0041de612 100644 +--- a/drivers/usb/core/devices.c ++++ b/drivers/usb/core/devices.c +@@ -157,38 +157,25 @@ static char *usb_dump_endpoint_descriptor(int speed, char *start, char *end, + switch (usb_endpoint_type(desc)) { + case USB_ENDPOINT_XFER_CONTROL: + type = "Ctrl"; +- if (speed == USB_SPEED_HIGH) /* uframes per NAK */ +- interval = desc->bInterval; +- else +- interval = 0; + dir = 'B'; /* ctrl is bidirectional */ + break; + case USB_ENDPOINT_XFER_ISOC: + type = "Isoc"; +- interval = 1 << (desc->bInterval - 1); + break; + case USB_ENDPOINT_XFER_BULK: + type = "Bulk"; +- if (speed == USB_SPEED_HIGH && dir == 'O') /* uframes per NAK */ +- interval = desc->bInterval; +- else +- interval = 0; + break; + case USB_ENDPOINT_XFER_INT: + type = "Int."; +- if (speed == USB_SPEED_HIGH || speed >= USB_SPEED_SUPER) +- interval = 1 << (desc->bInterval - 1); +- else +- interval = desc->bInterval; + break; + default: /* "can't happen" */ + return start; + } +- interval *= (speed == USB_SPEED_HIGH || +- speed >= USB_SPEED_SUPER) ? 125 : 1000; +- if (interval % 1000) ++ ++ interval = usb_decode_interval(desc, speed); ++ if (interval % 1000) { + unit = 'u'; +- else { ++ } else { + unit = 'm'; + interval /= 1000; + } +diff --git a/drivers/usb/core/endpoint.c b/drivers/usb/core/endpoint.c +index 1c2c04079676..fc3341f2bb61 100644 +--- a/drivers/usb/core/endpoint.c ++++ b/drivers/usb/core/endpoint.c +@@ -84,40 +84,13 @@ static ssize_t interval_show(struct device *dev, struct device_attribute *attr, + char *buf) + { + struct ep_device *ep = to_ep_device(dev); ++ unsigned int interval; + char unit; +- unsigned interval = 0; +- unsigned in; + +- in = (ep->desc->bEndpointAddress & USB_DIR_IN); +- +- switch (usb_endpoint_type(ep->desc)) { +- case USB_ENDPOINT_XFER_CONTROL: +- if (ep->udev->speed == USB_SPEED_HIGH) +- /* uframes per NAK */ +- interval = ep->desc->bInterval; +- break; +- +- case USB_ENDPOINT_XFER_ISOC: +- interval = 1 << (ep->desc->bInterval - 1); +- break; +- +- case USB_ENDPOINT_XFER_BULK: +- if (ep->udev->speed == USB_SPEED_HIGH && !in) +- /* uframes per NAK */ +- interval = ep->desc->bInterval; +- break; +- +- case USB_ENDPOINT_XFER_INT: +- if (ep->udev->speed == USB_SPEED_HIGH) +- interval = 1 << (ep->desc->bInterval - 1); +- else +- interval = ep->desc->bInterval; +- break; +- } +- interval *= (ep->udev->speed == USB_SPEED_HIGH) ? 125 : 1000; +- if (interval % 1000) ++ interval = usb_decode_interval(ep->desc, ep->udev->speed); ++ if (interval % 1000) { + unit = 'u'; +- else { ++ } else { + unit = 'm'; + interval /= 1000; + } +diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h +index abdd310c77f0..74debc824645 100644 +--- a/include/linux/usb/ch9.h ++++ b/include/linux/usb/ch9.h +@@ -90,6 +90,9 @@ extern enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev); + */ + extern const char *usb_state_string(enum usb_device_state state); + ++unsigned int usb_decode_interval(const struct usb_endpoint_descriptor *epd, ++ enum usb_device_speed speed); ++ + #ifdef CONFIG_TRACING + /** + * usb_decode_ctrl - Returns human readable representation of control request. +-- +2.35.1 + diff --git a/queue-5.10/usb-common-debug-check-non-standard-control-requests.patch b/queue-5.10/usb-common-debug-check-non-standard-control-requests.patch new file mode 100644 index 00000000000..ad00f9da37c --- /dev/null +++ b/queue-5.10/usb-common-debug-check-non-standard-control-requests.patch @@ -0,0 +1,139 @@ +From 6cb43ccc2ef3939f05628d1d19f40e6256d5ecb2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Jul 2022 18:38:01 -0700 +Subject: usb: common: debug: Check non-standard control requests + +From: Thinh Nguyen + +[ Upstream commit b6155eaf6b05e558218b44b88a6cad03f15a586c ] + +Previously usb_decode_ctrl() only decodes standard control requests, but +it was used for non-standard requests also. If it's non-standard or +unknown standard bRequest, print the Setup data values. + +Fixes: af32423a2d86 ("usb: dwc3: trace: decode ctrl request") +Signed-off-by: Thinh Nguyen +Link: https://lore.kernel.org/r/8d6a30f2f2f953eff833a5bc5aac640a4cc2fc9f.1658971571.git.Thinh.Nguyen@synopsys.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/common/debug.c | 96 +++++++++++++++++++++++++------------- + 1 file changed, 64 insertions(+), 32 deletions(-) + +diff --git a/drivers/usb/common/debug.c b/drivers/usb/common/debug.c +index a76a086b9c54..f0c0e8db7038 100644 +--- a/drivers/usb/common/debug.c ++++ b/drivers/usb/common/debug.c +@@ -207,30 +207,28 @@ static void usb_decode_set_isoch_delay(__u8 wValue, char *str, size_t size) + snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", wValue); + } + +-/** +- * usb_decode_ctrl - Returns human readable representation of control request. +- * @str: buffer to return a human-readable representation of control request. +- * This buffer should have about 200 bytes. +- * @size: size of str buffer. +- * @bRequestType: matches the USB bmRequestType field +- * @bRequest: matches the USB bRequest field +- * @wValue: matches the USB wValue field (CPU byte order) +- * @wIndex: matches the USB wIndex field (CPU byte order) +- * @wLength: matches the USB wLength field (CPU byte order) +- * +- * Function returns decoded, formatted and human-readable description of +- * control request packet. +- * +- * The usage scenario for this is for tracepoints, so function as a return +- * use the same value as in parameters. This approach allows to use this +- * function in TP_printk +- * +- * Important: wValue, wIndex, wLength parameters before invoking this function +- * should be processed by le16_to_cpu macro. +- */ +-const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType, +- __u8 bRequest, __u16 wValue, __u16 wIndex, +- __u16 wLength) ++static void usb_decode_ctrl_generic(char *str, size_t size, __u8 bRequestType, ++ __u8 bRequest, __u16 wValue, __u16 wIndex, ++ __u16 wLength) ++{ ++ u8 recip = bRequestType & USB_RECIP_MASK; ++ u8 type = bRequestType & USB_TYPE_MASK; ++ ++ snprintf(str, size, ++ "Type=%s Recipient=%s Dir=%s bRequest=%u wValue=%u wIndex=%u wLength=%u", ++ (type == USB_TYPE_STANDARD) ? "Standard" : ++ (type == USB_TYPE_VENDOR) ? "Vendor" : ++ (type == USB_TYPE_CLASS) ? "Class" : "Unknown", ++ (recip == USB_RECIP_DEVICE) ? "Device" : ++ (recip == USB_RECIP_INTERFACE) ? "Interface" : ++ (recip == USB_RECIP_ENDPOINT) ? "Endpoint" : "Unknown", ++ (bRequestType & USB_DIR_IN) ? "IN" : "OUT", ++ bRequest, wValue, wIndex, wLength); ++} ++ ++static void usb_decode_ctrl_standard(char *str, size_t size, __u8 bRequestType, ++ __u8 bRequest, __u16 wValue, __u16 wIndex, ++ __u16 wLength) + { + switch (bRequest) { + case USB_REQ_GET_STATUS: +@@ -271,14 +269,48 @@ const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType, + usb_decode_set_isoch_delay(wValue, str, size); + break; + default: +- snprintf(str, size, "%02x %02x %02x %02x %02x %02x %02x %02x", +- bRequestType, bRequest, +- (u8)(cpu_to_le16(wValue) & 0xff), +- (u8)(cpu_to_le16(wValue) >> 8), +- (u8)(cpu_to_le16(wIndex) & 0xff), +- (u8)(cpu_to_le16(wIndex) >> 8), +- (u8)(cpu_to_le16(wLength) & 0xff), +- (u8)(cpu_to_le16(wLength) >> 8)); ++ usb_decode_ctrl_generic(str, size, bRequestType, bRequest, ++ wValue, wIndex, wLength); ++ break; ++ } ++} ++ ++/** ++ * usb_decode_ctrl - Returns human readable representation of control request. ++ * @str: buffer to return a human-readable representation of control request. ++ * This buffer should have about 200 bytes. ++ * @size: size of str buffer. ++ * @bRequestType: matches the USB bmRequestType field ++ * @bRequest: matches the USB bRequest field ++ * @wValue: matches the USB wValue field (CPU byte order) ++ * @wIndex: matches the USB wIndex field (CPU byte order) ++ * @wLength: matches the USB wLength field (CPU byte order) ++ * ++ * Function returns decoded, formatted and human-readable description of ++ * control request packet. ++ * ++ * The usage scenario for this is for tracepoints, so function as a return ++ * use the same value as in parameters. This approach allows to use this ++ * function in TP_printk ++ * ++ * Important: wValue, wIndex, wLength parameters before invoking this function ++ * should be processed by le16_to_cpu macro. ++ */ ++const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType, ++ __u8 bRequest, __u16 wValue, __u16 wIndex, ++ __u16 wLength) ++{ ++ switch (bRequestType & USB_TYPE_MASK) { ++ case USB_TYPE_STANDARD: ++ usb_decode_ctrl_standard(str, size, bRequestType, bRequest, ++ wValue, wIndex, wLength); ++ break; ++ case USB_TYPE_VENDOR: ++ case USB_TYPE_CLASS: ++ default: ++ usb_decode_ctrl_generic(str, size, bRequestType, bRequest, ++ wValue, wIndex, wLength); ++ break; + } + + return str; +-- +2.35.1 + diff --git a/queue-5.10/usb-common-move-function-s-kerneldoc-next-to-its-def.patch b/queue-5.10/usb-common-move-function-s-kerneldoc-next-to-its-def.patch new file mode 100644 index 00000000000..fd34868ab0d --- /dev/null +++ b/queue-5.10/usb-common-move-function-s-kerneldoc-next-to-its-def.patch @@ -0,0 +1,217 @@ +From 017d84dbea5030db9db7b4f1a8a047a5f526e0e4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Mar 2021 10:52:07 +0800 +Subject: usb: common: move function's kerneldoc next to its definition + +From: Chunfeng Yun + +[ Upstream commit 365038f24b3e9d2b7c9e499f03f432040e28a35c ] + +Following a general rule, add the kerneldoc for a function next +to it's definition, but not next to its declaration in a header +file. + +Suggested-by: Alan Stern +Suggested-by: Greg Kroah-Hartman +Signed-off-by: Chunfeng Yun +Link: https://lore.kernel.org/r/c4d2e010ae2bf67cdfa0b55e6d1deb9339d9d3dc.1615170625.git.chunfeng.yun@mediatek.com +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: b6155eaf6b05 ("usb: common: debug: Check non-standard control requests") +Signed-off-by: Sasha Levin +--- + drivers/usb/common/common.c | 35 +++++++++++++++++++++ + drivers/usb/common/debug.c | 22 +++++++++++-- + include/linux/usb/ch9.h | 61 ------------------------------------- + 3 files changed, 55 insertions(+), 63 deletions(-) + +diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c +index 675e8a4e683a..347fb3d3894a 100644 +--- a/drivers/usb/common/common.c ++++ b/drivers/usb/common/common.c +@@ -25,6 +25,12 @@ static const char *const ep_type_names[] = { + [USB_ENDPOINT_XFER_INT] = "intr", + }; + ++/** ++ * usb_ep_type_string() - Returns human readable-name of the endpoint type. ++ * @ep_type: The endpoint type to return human-readable name for. If it's not ++ * any of the types: USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT}, ++ * usually got by usb_endpoint_type(), the string 'unknown' will be returned. ++ */ + const char *usb_ep_type_string(int ep_type) + { + if (ep_type < 0 || ep_type >= ARRAY_SIZE(ep_type_names)) +@@ -76,6 +82,12 @@ static const char *const ssp_rate[] = { + [USB_SSP_GEN_2x2] = "super-speed-plus-gen2x2", + }; + ++/** ++ * usb_speed_string() - Returns human readable-name of the speed. ++ * @speed: The speed to return human-readable name for. If it's not ++ * any of the speeds defined in usb_device_speed enum, string for ++ * USB_SPEED_UNKNOWN will be returned. ++ */ + const char *usb_speed_string(enum usb_device_speed speed) + { + if (speed < 0 || speed >= ARRAY_SIZE(speed_names)) +@@ -84,6 +96,14 @@ const char *usb_speed_string(enum usb_device_speed speed) + } + EXPORT_SYMBOL_GPL(usb_speed_string); + ++/** ++ * usb_get_maximum_speed - Get maximum requested speed for a given USB ++ * controller. ++ * @dev: Pointer to the given USB controller device ++ * ++ * The function gets the maximum speed string from property "maximum-speed", ++ * and returns the corresponding enum usb_device_speed. ++ */ + enum usb_device_speed usb_get_maximum_speed(struct device *dev) + { + const char *maximum_speed; +@@ -102,6 +122,15 @@ enum usb_device_speed usb_get_maximum_speed(struct device *dev) + } + EXPORT_SYMBOL_GPL(usb_get_maximum_speed); + ++/** ++ * usb_get_maximum_ssp_rate - Get the signaling rate generation and lane count ++ * of a SuperSpeed Plus capable device. ++ * @dev: Pointer to the given USB controller device ++ * ++ * If the string from "maximum-speed" property is super-speed-plus-genXxY where ++ * 'X' is the generation number and 'Y' is the number of lanes, then this ++ * function returns the corresponding enum usb_ssp_rate. ++ */ + enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev) + { + const char *maximum_speed; +@@ -116,6 +145,12 @@ enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev) + } + EXPORT_SYMBOL_GPL(usb_get_maximum_ssp_rate); + ++/** ++ * usb_state_string - Returns human readable name for the state. ++ * @state: The state to return a human-readable name for. If it's not ++ * any of the states devices in usb_device_state_string enum, ++ * the string UNKNOWN will be returned. ++ */ + const char *usb_state_string(enum usb_device_state state) + { + static const char *const names[] = { +diff --git a/drivers/usb/common/debug.c b/drivers/usb/common/debug.c +index ba849c7bc5c7..a76a086b9c54 100644 +--- a/drivers/usb/common/debug.c ++++ b/drivers/usb/common/debug.c +@@ -207,8 +207,26 @@ static void usb_decode_set_isoch_delay(__u8 wValue, char *str, size_t size) + snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", wValue); + } + +-/* +- * usb_decode_ctrl - returns a string representation of ctrl request ++/** ++ * usb_decode_ctrl - Returns human readable representation of control request. ++ * @str: buffer to return a human-readable representation of control request. ++ * This buffer should have about 200 bytes. ++ * @size: size of str buffer. ++ * @bRequestType: matches the USB bmRequestType field ++ * @bRequest: matches the USB bRequest field ++ * @wValue: matches the USB wValue field (CPU byte order) ++ * @wIndex: matches the USB wIndex field (CPU byte order) ++ * @wLength: matches the USB wLength field (CPU byte order) ++ * ++ * Function returns decoded, formatted and human-readable description of ++ * control request packet. ++ * ++ * The usage scenario for this is for tracepoints, so function as a return ++ * use the same value as in parameters. This approach allows to use this ++ * function in TP_printk ++ * ++ * Important: wValue, wIndex, wLength parameters before invoking this function ++ * should be processed by le16_to_cpu macro. + */ + const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType, + __u8 bRequest, __u16 wValue, __u16 wIndex, +diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h +index 74debc824645..1cffa34740b0 100644 +--- a/include/linux/usb/ch9.h ++++ b/include/linux/usb/ch9.h +@@ -45,76 +45,15 @@ enum usb_ssp_rate { + USB_SSP_GEN_2x2, + }; + +-/** +- * usb_ep_type_string() - Returns human readable-name of the endpoint type. +- * @ep_type: The endpoint type to return human-readable name for. If it's not +- * any of the types: USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT}, +- * usually got by usb_endpoint_type(), the string 'unknown' will be returned. +- */ + extern const char *usb_ep_type_string(int ep_type); +- +-/** +- * usb_speed_string() - Returns human readable-name of the speed. +- * @speed: The speed to return human-readable name for. If it's not +- * any of the speeds defined in usb_device_speed enum, string for +- * USB_SPEED_UNKNOWN will be returned. +- */ + extern const char *usb_speed_string(enum usb_device_speed speed); +- +-/** +- * usb_get_maximum_speed - Get maximum requested speed for a given USB +- * controller. +- * @dev: Pointer to the given USB controller device +- * +- * The function gets the maximum speed string from property "maximum-speed", +- * and returns the corresponding enum usb_device_speed. +- */ + extern enum usb_device_speed usb_get_maximum_speed(struct device *dev); +- +-/** +- * usb_get_maximum_ssp_rate - Get the signaling rate generation and lane count +- * of a SuperSpeed Plus capable device. +- * @dev: Pointer to the given USB controller device +- * +- * If the string from "maximum-speed" property is super-speed-plus-genXxY where +- * 'X' is the generation number and 'Y' is the number of lanes, then this +- * function returns the corresponding enum usb_ssp_rate. +- */ + extern enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev); +- +-/** +- * usb_state_string - Returns human readable name for the state. +- * @state: The state to return a human-readable name for. If it's not +- * any of the states devices in usb_device_state_string enum, +- * the string UNKNOWN will be returned. +- */ + extern const char *usb_state_string(enum usb_device_state state); +- + unsigned int usb_decode_interval(const struct usb_endpoint_descriptor *epd, + enum usb_device_speed speed); + + #ifdef CONFIG_TRACING +-/** +- * usb_decode_ctrl - Returns human readable representation of control request. +- * @str: buffer to return a human-readable representation of control request. +- * This buffer should have about 200 bytes. +- * @size: size of str buffer. +- * @bRequestType: matches the USB bmRequestType field +- * @bRequest: matches the USB bRequest field +- * @wValue: matches the USB wValue field (CPU byte order) +- * @wIndex: matches the USB wIndex field (CPU byte order) +- * @wLength: matches the USB wLength field (CPU byte order) +- * +- * Function returns decoded, formatted and human-readable description of +- * control request packet. +- * +- * The usage scenario for this is for tracepoints, so function as a return +- * use the same value as in parameters. This approach allows to use this +- * function in TP_printk +- * +- * Important: wValue, wIndex, wLength parameters before invoking this function +- * should be processed by le16_to_cpu macro. +- */ + extern const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType, + __u8 bRequest, __u16 wValue, __u16 wIndex, + __u16 wLength); +-- +2.35.1 + diff --git a/queue-5.10/usb-common-parse-for-usb-ssp-genxxy.patch b/queue-5.10/usb-common-parse-for-usb-ssp-genxxy.patch new file mode 100644 index 00000000000..c586b29f0ca --- /dev/null +++ b/queue-5.10/usb-common-parse-for-usb-ssp-genxxy.patch @@ -0,0 +1,104 @@ +From d6b0e97071814e94092e4c10fdb614ca20d14a03 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 19 Jan 2021 17:36:14 -0800 +Subject: usb: common: Parse for USB SSP genXxY + +From: Thinh Nguyen + +[ Upstream commit 52c2d15703c3a900d5f78cd599b823db40d5100b ] + +The USB "maximum-speed" property can now take the SSP signaling rate +generation and lane count with these new strings: + +"super-speed-plus-gen2x2" +"super-speed-plus-gen2x1" +"super-speed-plus-gen1x2" + +Introduce usb_get_maximum_ssp_rate() to parse for the corresponding +usb_ssp_rate enum. The original usb_get_maximum_speed() will return +USB_SPEED_SUPER_PLUS if it matches one of these new strings. + +Signed-off-by: Thinh Nguyen +Link: https://lore.kernel.org/r/f8ed896313d8cd8e2d2b540fc82db92b3ddf8a47.1611106162.git.Thinh.Nguyen@synopsys.com +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: b6155eaf6b05 ("usb: common: debug: Check non-standard control requests") +Signed-off-by: Sasha Levin +--- + drivers/usb/common/common.c | 26 +++++++++++++++++++++++++- + include/linux/usb/ch9.h | 11 +++++++++++ + 2 files changed, 36 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c +index 1433260d99b4..fc21cf2d36f6 100644 +--- a/drivers/usb/common/common.c ++++ b/drivers/usb/common/common.c +@@ -69,6 +69,13 @@ static const char *const speed_names[] = { + [USB_SPEED_SUPER_PLUS] = "super-speed-plus", + }; + ++static const char *const ssp_rate[] = { ++ [USB_SSP_GEN_UNKNOWN] = "UNKNOWN", ++ [USB_SSP_GEN_2x1] = "super-speed-plus-gen2x1", ++ [USB_SSP_GEN_1x2] = "super-speed-plus-gen1x2", ++ [USB_SSP_GEN_2x2] = "super-speed-plus-gen2x2", ++}; ++ + const char *usb_speed_string(enum usb_device_speed speed) + { + if (speed < 0 || speed >= ARRAY_SIZE(speed_names)) +@@ -86,12 +93,29 @@ enum usb_device_speed usb_get_maximum_speed(struct device *dev) + if (ret < 0) + return USB_SPEED_UNKNOWN; + +- ret = match_string(speed_names, ARRAY_SIZE(speed_names), maximum_speed); ++ ret = match_string(ssp_rate, ARRAY_SIZE(ssp_rate), maximum_speed); ++ if (ret > 0) ++ return USB_SPEED_SUPER_PLUS; + ++ ret = match_string(speed_names, ARRAY_SIZE(speed_names), maximum_speed); + return (ret < 0) ? USB_SPEED_UNKNOWN : ret; + } + EXPORT_SYMBOL_GPL(usb_get_maximum_speed); + ++enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev) ++{ ++ const char *maximum_speed; ++ int ret; ++ ++ ret = device_property_read_string(dev, "maximum-speed", &maximum_speed); ++ if (ret < 0) ++ return USB_SSP_GEN_UNKNOWN; ++ ++ ret = match_string(ssp_rate, ARRAY_SIZE(ssp_rate), maximum_speed); ++ return (ret < 0) ? USB_SSP_GEN_UNKNOWN : ret; ++} ++EXPORT_SYMBOL_GPL(usb_get_maximum_ssp_rate); ++ + const char *usb_state_string(enum usb_device_state state) + { + static const char *const names[] = { +diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h +index 86c50907634e..abdd310c77f0 100644 +--- a/include/linux/usb/ch9.h ++++ b/include/linux/usb/ch9.h +@@ -71,6 +71,17 @@ extern const char *usb_speed_string(enum usb_device_speed speed); + */ + extern enum usb_device_speed usb_get_maximum_speed(struct device *dev); + ++/** ++ * usb_get_maximum_ssp_rate - Get the signaling rate generation and lane count ++ * of a SuperSpeed Plus capable device. ++ * @dev: Pointer to the given USB controller device ++ * ++ * If the string from "maximum-speed" property is super-speed-plus-genXxY where ++ * 'X' is the generation number and 'Y' is the number of lanes, then this ++ * function returns the corresponding enum usb_ssp_rate. ++ */ ++extern enum usb_ssp_rate usb_get_maximum_ssp_rate(struct device *dev); ++ + /** + * usb_state_string - Returns human readable name for the state. + * @state: The state to return a human-readable name for. If it's not +-- +2.35.1 + diff --git a/queue-5.10/usb-gadget-function-fix-dangling-pnp_string-in-f_pri.patch b/queue-5.10/usb-gadget-function-fix-dangling-pnp_string-in-f_pri.patch new file mode 100644 index 00000000000..7defe7b0507 --- /dev/null +++ b/queue-5.10/usb-gadget-function-fix-dangling-pnp_string-in-f_pri.patch @@ -0,0 +1,76 @@ +From 72072674a900e3032a228f515c4feda7ebe973b6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 11 Sep 2022 15:37:55 -0700 +Subject: usb: gadget: function: fix dangling pnp_string in f_printer.c + +From: Albert Briscoe + +[ Upstream commit 24b7ba2f88e04800b54d462f376512e8c41b8a3c ] + +When opts->pnp_string is changed with configfs, new memory is allocated for +the string. It does not, however, update dev->pnp_string, even though the +memory is freed. When rquesting the string, the host then gets old or +corrupted data rather than the new string. The ieee 1284 id string should +be allowed to change while the device is connected. + +The bug was introduced in commit fdc01cc286be ("usb: gadget: printer: +Remove pnp_string static buffer"), which changed opts->pnp_string from a +char[] to a char*. +This patch changes dev->pnp_string from a char* to a char** pointing to +opts->pnp_string. + +Fixes: fdc01cc286be ("usb: gadget: printer: Remove pnp_string static buffer") +Signed-off-by: Albert Briscoe +Link: https://lore.kernel.org/r/20220911223753.20417-1-albertsbriscoe@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/gadget/function/f_printer.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/usb/gadget/function/f_printer.c b/drivers/usb/gadget/function/f_printer.c +index 236ecc968998..c13bb29a160e 100644 +--- a/drivers/usb/gadget/function/f_printer.c ++++ b/drivers/usb/gadget/function/f_printer.c +@@ -87,7 +87,7 @@ struct printer_dev { + u8 printer_cdev_open; + wait_queue_head_t wait; + unsigned q_len; +- char *pnp_string; /* We don't own memory! */ ++ char **pnp_string; /* We don't own memory! */ + struct usb_function function; + }; + +@@ -999,16 +999,16 @@ static int printer_func_setup(struct usb_function *f, + if ((wIndex>>8) != dev->interface) + break; + +- if (!dev->pnp_string) { ++ if (!*dev->pnp_string) { + value = 0; + break; + } +- value = strlen(dev->pnp_string); ++ value = strlen(*dev->pnp_string); + buf[0] = (value >> 8) & 0xFF; + buf[1] = value & 0xFF; +- memcpy(buf + 2, dev->pnp_string, value); ++ memcpy(buf + 2, *dev->pnp_string, value); + DBG(dev, "1284 PNP String: %x %s\n", value, +- dev->pnp_string); ++ *dev->pnp_string); + break; + + case GET_PORT_STATUS: /* Get Port Status */ +@@ -1471,7 +1471,7 @@ static struct usb_function *gprinter_alloc(struct usb_function_instance *fi) + kref_init(&dev->kref); + ++opts->refcnt; + dev->minor = opts->minor; +- dev->pnp_string = opts->pnp_string; ++ dev->pnp_string = &opts->pnp_string; + dev->q_len = opts->q_len; + mutex_unlock(&opts->lock); + +-- +2.35.1 + diff --git a/queue-5.10/usb-host-xhci-fix-potential-memory-leak-in-xhci_allo.patch b/queue-5.10/usb-host-xhci-fix-potential-memory-leak-in-xhci_allo.patch new file mode 100644 index 00000000000..356291d4586 --- /dev/null +++ b/queue-5.10/usb-host-xhci-fix-potential-memory-leak-in-xhci_allo.patch @@ -0,0 +1,56 @@ +From 0be36f928029664f75236d9862a5428d07454e84 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 15:34:45 +0300 +Subject: usb: host: xhci: Fix potential memory leak in + xhci_alloc_stream_info() + +From: Jianglei Nie + +[ Upstream commit 7e271f42a5cc3768cd2622b929ba66859ae21f97 ] + +xhci_alloc_stream_info() allocates stream context array for stream_info +->stream_ctx_array with xhci_alloc_stream_ctx(). When some error occurs, +stream_info->stream_ctx_array is not released, which will lead to a +memory leak. + +We can fix it by releasing the stream_info->stream_ctx_array with +xhci_free_stream_ctx() on the error path to avoid the potential memory +leak. + +Signed-off-by: Jianglei Nie +Signed-off-by: Mathias Nyman +Link: https://lore.kernel.org/r/20220921123450.671459-2-mathias.nyman@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/host/xhci-mem.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 024e8911df34..1fba5605a88e 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -659,7 +659,7 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, + num_stream_ctxs, &stream_info->ctx_array_dma, + mem_flags); + if (!stream_info->stream_ctx_array) +- goto cleanup_ctx; ++ goto cleanup_ring_array; + memset(stream_info->stream_ctx_array, 0, + sizeof(struct xhci_stream_ctx)*num_stream_ctxs); + +@@ -720,6 +720,11 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, + } + xhci_free_command(xhci, stream_info->free_streams_command); + cleanup_ctx: ++ xhci_free_stream_ctx(xhci, ++ stream_info->num_stream_ctxs, ++ stream_info->stream_ctx_array, ++ stream_info->ctx_array_dma); ++cleanup_ring_array: + kfree(stream_info->stream_rings); + cleanup_info: + kfree(stream_info); +-- +2.35.1 + diff --git a/queue-5.10/usb-host-xhci-plat-suspend-and-resume-clocks.patch b/queue-5.10/usb-host-xhci-plat-suspend-and-resume-clocks.patch new file mode 100644 index 00000000000..22a300fb488 --- /dev/null +++ b/queue-5.10/usb-host-xhci-plat-suspend-and-resume-clocks.patch @@ -0,0 +1,72 @@ +From 19aa90f1e697424d8d1c1410eb3f1913440b9ef7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Aug 2022 15:27:34 -0700 +Subject: usb: host: xhci-plat: suspend and resume clocks + +From: Justin Chen + +[ Upstream commit 8bd954c56197caf5e3a804d989094bc3fe6329aa ] + +Introduce XHCI_SUSPEND_RESUME_CLKS quirk as a means to suspend and resume +clocks if the hardware is capable of doing so. We assume that clocks will +be needed if the device may wake. + +Reviewed-by: Florian Fainelli +Signed-off-by: Justin Chen +Link: https://lore.kernel.org/r/1660170455-15781-2-git-send-email-justinpopo6@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/host/xhci-plat.c | 16 +++++++++++++++- + drivers/usb/host/xhci.h | 1 + + 2 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index dc570ce4e831..2687662f26b6 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -447,7 +447,16 @@ static int __maybe_unused xhci_plat_suspend(struct device *dev) + * xhci_suspend() needs `do_wakeup` to know whether host is allowed + * to do wakeup during suspend. + */ +- return xhci_suspend(xhci, device_may_wakeup(dev)); ++ ret = xhci_suspend(xhci, device_may_wakeup(dev)); ++ if (ret) ++ return ret; ++ ++ if (!device_may_wakeup(dev) && (xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) { ++ clk_disable_unprepare(xhci->clk); ++ clk_disable_unprepare(xhci->reg_clk); ++ } ++ ++ return 0; + } + + static int __maybe_unused xhci_plat_resume(struct device *dev) +@@ -456,6 +465,11 @@ static int __maybe_unused xhci_plat_resume(struct device *dev) + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + int ret; + ++ if (!device_may_wakeup(dev) && (xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) { ++ clk_prepare_enable(xhci->clk); ++ clk_prepare_enable(xhci->reg_clk); ++ } ++ + ret = xhci_priv_resume_quirk(hcd); + if (ret) + return ret; +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 6f16a05b1958..e668740000b2 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1888,6 +1888,7 @@ struct xhci_hcd { + #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) + #define XHCI_NO_SOFT_RETRY BIT_ULL(40) + #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) ++#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) + + unsigned int num_active_eps; + unsigned int limit_active_eps; +-- +2.35.1 + diff --git a/queue-5.10/usb-host-xhci-plat-suspend-resume-clks-for-brcm.patch b/queue-5.10/usb-host-xhci-plat-suspend-resume-clks-for-brcm.patch new file mode 100644 index 00000000000..50931d5447f --- /dev/null +++ b/queue-5.10/usb-host-xhci-plat-suspend-resume-clks-for-brcm.patch @@ -0,0 +1,38 @@ +From a90c4673c55e27bf39e33deae522f87a08c317fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Aug 2022 15:27:35 -0700 +Subject: usb: host: xhci-plat: suspend/resume clks for brcm + +From: Justin Chen + +[ Upstream commit c69400b09e471a3f1167adead55a808f0da6534a ] + +The xhci_plat_brcm xhci block can enter suspend with clock disabled to save +power and re-enable them on resume. Make use of the XHCI_SUSPEND_RESUME_CLKS +quirk to do so. + +Reviewed-by: Florian Fainelli +Signed-off-by: Justin Chen +Link: https://lore.kernel.org/r/1660170455-15781-3-git-send-email-justinpopo6@gmail.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/host/xhci-plat.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 2687662f26b6..972a44b2a7f1 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -134,7 +134,7 @@ static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = { + }; + + static const struct xhci_plat_priv xhci_plat_brcm = { +- .quirks = XHCI_RESET_ON_RESUME, ++ .quirks = XHCI_RESET_ON_RESUME | XHCI_SUSPEND_RESUME_CLKS, + }; + + static const struct of_device_id usb_xhci_of_match[] = { +-- +2.35.1 + diff --git a/queue-5.10/usb-idmouse-fix-an-uninit-value-in-idmouse_open.patch b/queue-5.10/usb-idmouse-fix-an-uninit-value-in-idmouse_open.patch new file mode 100644 index 00000000000..fadcc60a726 --- /dev/null +++ b/queue-5.10/usb-idmouse-fix-an-uninit-value-in-idmouse_open.patch @@ -0,0 +1,59 @@ +From 88daa450501aa0c76f4033a10ac00ba2382078e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 21:48:44 +0800 +Subject: usb: idmouse: fix an uninit-value in idmouse_open + +From: Dongliang Mu + +[ Upstream commit bce2b0539933e485d22d6f6f076c0fcd6f185c4c ] + +In idmouse_create_image, if any ftip_command fails, it will +go to the reset label. However, this leads to the data in +bulk_in_buffer[HEADER..IMGSIZE] uninitialized. And the check +for valid image incurs an uninitialized dereference. + +Fix this by moving the check before reset label since this +check only be valid if the data after bulk_in_buffer[HEADER] +has concrete data. + +Note that this is found by KMSAN, so only kernel compilation +is tested. + +Reported-by: syzbot+79832d33eb89fb3cd092@syzkaller.appspotmail.com +Signed-off-by: Dongliang Mu +Link: https://lore.kernel.org/r/20220922134847.1101921-1-dzm91@hust.edu.cn +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/misc/idmouse.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/usb/misc/idmouse.c b/drivers/usb/misc/idmouse.c +index e9437a176518..ea39243efee3 100644 +--- a/drivers/usb/misc/idmouse.c ++++ b/drivers/usb/misc/idmouse.c +@@ -177,10 +177,6 @@ static int idmouse_create_image(struct usb_idmouse *dev) + bytes_read += bulk_read; + } + +- /* reset the device */ +-reset: +- ftip_command(dev, FTIP_RELEASE, 0, 0); +- + /* check for valid image */ + /* right border should be black (0x00) */ + for (bytes_read = sizeof(HEADER)-1 + WIDTH-1; bytes_read < IMGSIZE; bytes_read += WIDTH) +@@ -192,6 +188,10 @@ static int idmouse_create_image(struct usb_idmouse *dev) + if (dev->bulk_in_buffer[bytes_read] != 0xFF) + return -EAGAIN; + ++ /* reset the device */ ++reset: ++ ftip_command(dev, FTIP_RELEASE, 0, 0); ++ + /* should be IMGSIZE == 65040 */ + dev_dbg(&dev->interface->dev, "read %d bytes fingerprint data\n", + bytes_read); +-- +2.35.1 + diff --git a/queue-5.10/usb-musb-fix-musb_gadget.c-rxstate-overflow-bug.patch b/queue-5.10/usb-musb-fix-musb_gadget.c-rxstate-overflow-bug.patch new file mode 100644 index 00000000000..681abda9fdd --- /dev/null +++ b/queue-5.10/usb-musb-fix-musb_gadget.c-rxstate-overflow-bug.patch @@ -0,0 +1,42 @@ +From c8fba9746ccb5ccbfe7893d9a9e10cf40ebec063 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 10:21:19 +0800 +Subject: usb: musb: Fix musb_gadget.c rxstate overflow bug + +From: Robin Guo + +[ Upstream commit eea4c860c3b366369eff0489d94ee4f0571d467d ] + +The usb function device call musb_gadget_queue() adds the passed +request to musb_ep::req_list,If the (request->length > musb_ep->packet_sz) +and (is_buffer_mapped(req) return false),the rxstate() will copy all data +in fifo to request->buf which may cause request->buf out of bounds. + +Fix it by add the length check : +fifocnt = min_t(unsigned, request->length - request->actual, fifocnt); + +Signed-off-by: Robin Guo +Link: https://lore.kernel.org/r/20220906102119.1b071d07a8391ff115e6d1ef@inspur.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/musb/musb_gadget.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c +index fb806b33178a..c273eee35aaa 100644 +--- a/drivers/usb/musb/musb_gadget.c ++++ b/drivers/usb/musb/musb_gadget.c +@@ -760,6 +760,9 @@ static void rxstate(struct musb *musb, struct musb_request *req) + musb_writew(epio, MUSB_RXCSR, csr); + + buffer_aint_mapped: ++ fifo_count = min_t(unsigned int, ++ request->length - request->actual, ++ (unsigned int)fifo_count); + musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) + (request->buf + request->actual)); + request->actual += fifo_count; +-- +2.35.1 + diff --git a/queue-5.10/usb-serial-console-move-mutex_unlock-before-usb_seri.patch b/queue-5.10/usb-serial-console-move-mutex_unlock-before-usb_seri.patch new file mode 100644 index 00000000000..3624137de0b --- /dev/null +++ b/queue-5.10/usb-serial-console-move-mutex_unlock-before-usb_seri.patch @@ -0,0 +1,39 @@ +From 5db5401988518237efa9f3e295ec3f7b637206ca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 18:48:24 +0800 +Subject: USB: serial: console: move mutex_unlock() before usb_serial_put() + +From: Liang He + +[ Upstream commit 61dfa797c731754642d1ac500a6ac42f9b47f920 ] + +While in current version there is no use-after-free as USB serial +core holds another reference when the console is registered, we +should better unlock before dropping the reference in +usb_console_setup(). + +Fixes: 7bd032dc2793 ("USB serial: update the console driver") +Signed-off-by: Liang He +Signed-off-by: Johan Hovold +Signed-off-by: Sasha Levin +--- + drivers/usb/serial/console.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c +index b97aa40ca4d1..da19a5fa414f 100644 +--- a/drivers/usb/serial/console.c ++++ b/drivers/usb/serial/console.c +@@ -189,8 +189,8 @@ static int usb_console_setup(struct console *co, char *options) + info->port = NULL; + usb_autopm_put_interface(serial->interface); + error_get_interface: +- usb_serial_put(serial); + mutex_unlock(&serial->disc_mutex); ++ usb_serial_put(serial); + return retval; + } + +-- +2.35.1 + diff --git a/queue-5.10/userfaultfd-open-userfaultfds-with-o_rdonly.patch b/queue-5.10/userfaultfd-open-userfaultfds-with-o_rdonly.patch new file mode 100644 index 00000000000..f8ca446b7cd --- /dev/null +++ b/queue-5.10/userfaultfd-open-userfaultfds-with-o_rdonly.patch @@ -0,0 +1,57 @@ +From f092efd73bb325049f9d95552b987d9f6fe827fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 8 Jul 2022 11:34:51 +0200 +Subject: userfaultfd: open userfaultfds with O_RDONLY + +From: Ondrej Mosnacek + +[ Upstream commit abec3d015fdfb7c63105c7e1c956188bf381aa55 ] + +Since userfaultfd doesn't implement a write operation, it is more +appropriate to open it read-only. + +When userfaultfds are opened read-write like it is now, and such fd is +passed from one process to another, SELinux will check both read and +write permissions for the target process, even though it can't actually +do any write operation on the fd later. + +Inspired by the following bug report, which has hit the SELinux scenario +described above: +https://bugzilla.redhat.com/show_bug.cgi?id=1974559 + +Reported-by: Robert O'Callahan +Fixes: 86039bd3b4e6 ("userfaultfd: add new syscall to provide memory externalization") +Signed-off-by: Ondrej Mosnacek +Acked-by: Peter Xu +Acked-by: Christian Brauner (Microsoft) +Signed-off-by: Paul Moore +Signed-off-by: Sasha Levin +--- + fs/userfaultfd.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c +index aef0da5d6f63..a3074a9d71a6 100644 +--- a/fs/userfaultfd.c ++++ b/fs/userfaultfd.c +@@ -974,7 +974,7 @@ static int resolve_userfault_fork(struct userfaultfd_ctx *ctx, + int fd; + + fd = anon_inode_getfd("[userfaultfd]", &userfaultfd_fops, new, +- O_RDWR | (new->flags & UFFD_SHARED_FCNTL_FLAGS)); ++ O_RDONLY | (new->flags & UFFD_SHARED_FCNTL_FLAGS)); + if (fd < 0) + return fd; + +@@ -1987,7 +1987,7 @@ SYSCALL_DEFINE1(userfaultfd, int, flags) + mmgrab(ctx->mm); + + fd = anon_inode_getfd("[userfaultfd]", &userfaultfd_fops, ctx, +- O_RDWR | (flags & UFFD_SHARED_FCNTL_FLAGS)); ++ O_RDONLY | (flags & UFFD_SHARED_FCNTL_FLAGS)); + if (fd < 0) { + mmdrop(ctx->mm); + kmem_cache_free(userfaultfd_ctx_cachep, ctx); +-- +2.35.1 + diff --git a/queue-5.10/vhost-vsock-use-kvmalloc-kvfree-for-larger-packets.patch b/queue-5.10/vhost-vsock-use-kvmalloc-kvfree-for-larger-packets.patch new file mode 100644 index 00000000000..dc62e7e4a2e --- /dev/null +++ b/queue-5.10/vhost-vsock-use-kvmalloc-kvfree-for-larger-packets.patch @@ -0,0 +1,73 @@ +From ac2b95bb5b54fc041efe6e2057c8185d592cc6d6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 28 Sep 2022 15:45:38 +0900 +Subject: vhost/vsock: Use kvmalloc/kvfree for larger packets. + +From: Junichi Uekawa + +[ Upstream commit 0e3f72931fc47bb81686020cc643cde5d9cd0bb8 ] + +When copying a large file over sftp over vsock, data size is usually 32kB, +and kmalloc seems to fail to try to allocate 32 32kB regions. + + vhost-5837: page allocation failure: order:4, mode:0x24040c0 + Call Trace: + [] dump_stack+0x97/0xdb + [] warn_alloc_failed+0x10f/0x138 + [] ? __alloc_pages_direct_compact+0x38/0xc8 + [] __alloc_pages_nodemask+0x84c/0x90d + [] alloc_kmem_pages+0x17/0x19 + [] kmalloc_order_trace+0x2b/0xdb + [] __kmalloc+0x177/0x1f7 + [] ? copy_from_iter+0x8d/0x31d + [] vhost_vsock_handle_tx_kick+0x1fa/0x301 [vhost_vsock] + [] vhost_worker+0xf7/0x157 [vhost] + [] kthread+0xfd/0x105 + [] ? vhost_dev_set_owner+0x22e/0x22e [vhost] + [] ? flush_kthread_worker+0xf3/0xf3 + [] ret_from_fork+0x4e/0x80 + [] ? flush_kthread_worker+0xf3/0xf3 + +Work around by doing kvmalloc instead. + +Fixes: 433fc58e6bf2 ("VSOCK: Introduce vhost_vsock.ko") +Signed-off-by: Junichi Uekawa +Reviewed-by: Stefano Garzarella +Acked-by: Michael S. Tsirkin +Link: https://lore.kernel.org/r/20220928064538.667678-1-uekawa@chromium.org +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/vhost/vsock.c | 2 +- + net/vmw_vsock/virtio_transport_common.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/vhost/vsock.c b/drivers/vhost/vsock.c +index 5d2d6ce7ff41..b0153617fe0e 100644 +--- a/drivers/vhost/vsock.c ++++ b/drivers/vhost/vsock.c +@@ -359,7 +359,7 @@ vhost_vsock_alloc_pkt(struct vhost_virtqueue *vq, + return NULL; + } + +- pkt->buf = kmalloc(pkt->len, GFP_KERNEL); ++ pkt->buf = kvmalloc(pkt->len, GFP_KERNEL); + if (!pkt->buf) { + kfree(pkt); + return NULL; +diff --git a/net/vmw_vsock/virtio_transport_common.c b/net/vmw_vsock/virtio_transport_common.c +index d6d3a05c008a..c9ee9259af48 100644 +--- a/net/vmw_vsock/virtio_transport_common.c ++++ b/net/vmw_vsock/virtio_transport_common.c +@@ -1196,7 +1196,7 @@ EXPORT_SYMBOL_GPL(virtio_transport_recv_pkt); + + void virtio_transport_free_pkt(struct virtio_vsock_pkt *pkt) + { +- kfree(pkt->buf); ++ kvfree(pkt->buf); + kfree(pkt); + } + EXPORT_SYMBOL_GPL(virtio_transport_free_pkt); +-- +2.35.1 + diff --git a/queue-5.10/wifi-ath10k-add-peer-map-clean-up-for-peer-delete-in.patch b/queue-5.10/wifi-ath10k-add-peer-map-clean-up-for-peer-delete-in.patch new file mode 100644 index 00000000000..bc8c6efe07f --- /dev/null +++ b/queue-5.10/wifi-ath10k-add-peer-map-clean-up-for-peer-delete-in.patch @@ -0,0 +1,206 @@ +From d02e06b98718ed17eefcc9702f796755cca31a72 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 1 Aug 2022 10:19:30 -0400 +Subject: wifi: ath10k: add peer map clean up for peer delete in + ath10k_sta_state() + +From: Wen Gong + +[ Upstream commit f020d9570a04df0762a2ac5c50cf1d8c511c9164 ] + +When peer delete failed in a disconnect operation, use-after-free +detected by KFENCE in below log. It is because for each vdev_id and +address, it has only one struct ath10k_peer, it is allocated in +ath10k_peer_map_event(). When connected to an AP, it has more than +one HTT_T2H_MSG_TYPE_PEER_MAP reported from firmware, then the +array peer_map of struct ath10k will be set muti-elements to the +same ath10k_peer in ath10k_peer_map_event(). When peer delete failed +in ath10k_sta_state(), the ath10k_peer will be free for the 1st peer +id in array peer_map of struct ath10k, and then use-after-free happened +for the 2nd peer id because they map to the same ath10k_peer. + +And clean up all peers in array peer_map for the ath10k_peer, then +user-after-free disappeared + +peer map event log: +[ 306.911021] wlan0: authenticate with b0:2a:43:e6:75:0e +[ 306.957187] ath10k_pci 0000:01:00.0: mac vdev 0 peer create b0:2a:43:e6:75:0e (new sta) sta 1 / 32 peer 1 / 33 +[ 306.957395] ath10k_pci 0000:01:00.0: htt peer map vdev 0 peer b0:2a:43:e6:75:0e id 246 +[ 306.957404] ath10k_pci 0000:01:00.0: htt peer map vdev 0 peer b0:2a:43:e6:75:0e id 198 +[ 306.986924] ath10k_pci 0000:01:00.0: htt peer map vdev 0 peer b0:2a:43:e6:75:0e id 166 + +peer unmap event log: +[ 435.715691] wlan0: deauthenticating from b0:2a:43:e6:75:0e by local choice (Reason: 3=DEAUTH_LEAVING) +[ 435.716802] ath10k_pci 0000:01:00.0: mac vdev 0 peer delete b0:2a:43:e6:75:0e sta ffff990e0e9c2b50 (sta gone) +[ 435.717177] ath10k_pci 0000:01:00.0: htt peer unmap vdev 0 peer b0:2a:43:e6:75:0e id 246 +[ 435.717186] ath10k_pci 0000:01:00.0: htt peer unmap vdev 0 peer b0:2a:43:e6:75:0e id 198 +[ 435.717193] ath10k_pci 0000:01:00.0: htt peer unmap vdev 0 peer b0:2a:43:e6:75:0e id 166 + +use-after-free log: +[21705.888627] wlan0: deauthenticating from d0:76:8f:82:be:75 by local choice (Reason: 3=DEAUTH_LEAVING) +[21713.799910] ath10k_pci 0000:01:00.0: failed to delete peer d0:76:8f:82:be:75 for vdev 0: -110 +[21713.799925] ath10k_pci 0000:01:00.0: found sta peer d0:76:8f:82:be:75 (ptr 0000000000000000 id 102) entry on vdev 0 after it was supposedly removed +[21713.799968] ================================================================== +[21713.799991] BUG: KFENCE: use-after-free read in ath10k_sta_state+0x265/0xb8a [ath10k_core] +[21713.799991] +[21713.799997] Use-after-free read at 0x00000000abe1c75e (in kfence-#69): +[21713.800010] ath10k_sta_state+0x265/0xb8a [ath10k_core] +[21713.800041] drv_sta_state+0x115/0x677 [mac80211] +[21713.800059] __sta_info_destroy_part2+0xb1/0x133 [mac80211] +[21713.800076] __sta_info_flush+0x11d/0x162 [mac80211] +[21713.800093] ieee80211_set_disassoc+0x12d/0x2f4 [mac80211] +[21713.800110] ieee80211_mgd_deauth+0x26c/0x29b [mac80211] +[21713.800137] cfg80211_mlme_deauth+0x13f/0x1bb [cfg80211] +[21713.800153] nl80211_deauthenticate+0xf8/0x121 [cfg80211] +[21713.800161] genl_rcv_msg+0x38e/0x3be +[21713.800166] netlink_rcv_skb+0x89/0xf7 +[21713.800171] genl_rcv+0x28/0x36 +[21713.800176] netlink_unicast+0x179/0x24b +[21713.800181] netlink_sendmsg+0x3a0/0x40e +[21713.800187] sock_sendmsg+0x72/0x76 +[21713.800192] ____sys_sendmsg+0x16d/0x1e3 +[21713.800196] ___sys_sendmsg+0x95/0xd1 +[21713.800200] __sys_sendmsg+0x85/0xbf +[21713.800205] do_syscall_64+0x43/0x55 +[21713.800210] entry_SYSCALL_64_after_hwframe+0x44/0xa9 +[21713.800213] +[21713.800219] kfence-#69: 0x000000009149b0d5-0x000000004c0697fb, size=1064, cache=kmalloc-2k +[21713.800219] +[21713.800224] allocated by task 13 on cpu 0 at 21705.501373s: +[21713.800241] ath10k_peer_map_event+0x7e/0x154 [ath10k_core] +[21713.800254] ath10k_htt_t2h_msg_handler+0x586/0x1039 [ath10k_core] +[21713.800265] ath10k_htt_htc_t2h_msg_handler+0x12/0x28 [ath10k_core] +[21713.800277] ath10k_htc_rx_completion_handler+0x14c/0x1b5 [ath10k_core] +[21713.800283] ath10k_pci_process_rx_cb+0x195/0x1df [ath10k_pci] +[21713.800294] ath10k_ce_per_engine_service+0x55/0x74 [ath10k_core] +[21713.800305] ath10k_ce_per_engine_service_any+0x76/0x84 [ath10k_core] +[21713.800310] ath10k_pci_napi_poll+0x49/0x144 [ath10k_pci] +[21713.800316] net_rx_action+0xdc/0x361 +[21713.800320] __do_softirq+0x163/0x29a +[21713.800325] asm_call_irq_on_stack+0x12/0x20 +[21713.800331] do_softirq_own_stack+0x3c/0x48 +[21713.800337] __irq_exit_rcu+0x9b/0x9d +[21713.800342] common_interrupt+0xc9/0x14d +[21713.800346] asm_common_interrupt+0x1e/0x40 +[21713.800351] ksoftirqd_should_run+0x5/0x16 +[21713.800357] smpboot_thread_fn+0x148/0x211 +[21713.800362] kthread+0x150/0x15f +[21713.800367] ret_from_fork+0x22/0x30 +[21713.800370] +[21713.800374] freed by task 708 on cpu 1 at 21713.799953s: +[21713.800498] ath10k_sta_state+0x2c6/0xb8a [ath10k_core] +[21713.800515] drv_sta_state+0x115/0x677 [mac80211] +[21713.800532] __sta_info_destroy_part2+0xb1/0x133 [mac80211] +[21713.800548] __sta_info_flush+0x11d/0x162 [mac80211] +[21713.800565] ieee80211_set_disassoc+0x12d/0x2f4 [mac80211] +[21713.800581] ieee80211_mgd_deauth+0x26c/0x29b [mac80211] +[21713.800598] cfg80211_mlme_deauth+0x13f/0x1bb [cfg80211] +[21713.800614] nl80211_deauthenticate+0xf8/0x121 [cfg80211] +[21713.800619] genl_rcv_msg+0x38e/0x3be +[21713.800623] netlink_rcv_skb+0x89/0xf7 +[21713.800628] genl_rcv+0x28/0x36 +[21713.800632] netlink_unicast+0x179/0x24b +[21713.800637] netlink_sendmsg+0x3a0/0x40e +[21713.800642] sock_sendmsg+0x72/0x76 +[21713.800646] ____sys_sendmsg+0x16d/0x1e3 +[21713.800651] ___sys_sendmsg+0x95/0xd1 +[21713.800655] __sys_sendmsg+0x85/0xbf +[21713.800659] do_syscall_64+0x43/0x55 +[21713.800663] entry_SYSCALL_64_after_hwframe+0x44/0xa9 + +Tested-on: QCA6174 hw3.2 PCI WLAN.RM.4.4.1-00288-QCARMSWPZ-1 + +Fixes: d0eeafad1189 ("ath10k: Clean up peer when sta goes away.") +Signed-off-by: Wen Gong +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220801141930.16794-1-quic_wgong@quicinc.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ath/ath10k/mac.c | 54 ++++++++++++++------------- + 1 file changed, 29 insertions(+), 25 deletions(-) + +diff --git a/drivers/net/wireless/ath/ath10k/mac.c b/drivers/net/wireless/ath/ath10k/mac.c +index b61cd275fbda..15f02bf23e9b 100644 +--- a/drivers/net/wireless/ath/ath10k/mac.c ++++ b/drivers/net/wireless/ath/ath10k/mac.c +@@ -853,11 +853,36 @@ static int ath10k_peer_delete(struct ath10k *ar, u32 vdev_id, const u8 *addr) + return 0; + } + ++static void ath10k_peer_map_cleanup(struct ath10k *ar, struct ath10k_peer *peer) ++{ ++ int peer_id, i; ++ ++ lockdep_assert_held(&ar->conf_mutex); ++ ++ for_each_set_bit(peer_id, peer->peer_ids, ++ ATH10K_MAX_NUM_PEER_IDS) { ++ ar->peer_map[peer_id] = NULL; ++ } ++ ++ /* Double check that peer is properly un-referenced from ++ * the peer_map ++ */ ++ for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) { ++ if (ar->peer_map[i] == peer) { ++ ath10k_warn(ar, "removing stale peer_map entry for %pM (ptr %pK idx %d)\n", ++ peer->addr, peer, i); ++ ar->peer_map[i] = NULL; ++ } ++ } ++ ++ list_del(&peer->list); ++ kfree(peer); ++ ar->num_peers--; ++} ++ + static void ath10k_peer_cleanup(struct ath10k *ar, u32 vdev_id) + { + struct ath10k_peer *peer, *tmp; +- int peer_id; +- int i; + + lockdep_assert_held(&ar->conf_mutex); + +@@ -869,25 +894,7 @@ static void ath10k_peer_cleanup(struct ath10k *ar, u32 vdev_id) + ath10k_warn(ar, "removing stale peer %pM from vdev_id %d\n", + peer->addr, vdev_id); + +- for_each_set_bit(peer_id, peer->peer_ids, +- ATH10K_MAX_NUM_PEER_IDS) { +- ar->peer_map[peer_id] = NULL; +- } +- +- /* Double check that peer is properly un-referenced from +- * the peer_map +- */ +- for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) { +- if (ar->peer_map[i] == peer) { +- ath10k_warn(ar, "removing stale peer_map entry for %pM (ptr %pK idx %d)\n", +- peer->addr, peer, i); +- ar->peer_map[i] = NULL; +- } +- } +- +- list_del(&peer->list); +- kfree(peer); +- ar->num_peers--; ++ ath10k_peer_map_cleanup(ar, peer); + } + spin_unlock_bh(&ar->data_lock); + } +@@ -7470,10 +7477,7 @@ static int ath10k_sta_state(struct ieee80211_hw *hw, + /* Clean up the peer object as well since we + * must have failed to do this above. + */ +- list_del(&peer->list); +- ar->peer_map[i] = NULL; +- kfree(peer); +- ar->num_peers--; ++ ath10k_peer_map_cleanup(ar, peer); + } + } + spin_unlock_bh(&ar->data_lock); +-- +2.35.1 + diff --git a/queue-5.10/wifi-ath10k-reset-pointer-after-memory-free-to-avoid.patch b/queue-5.10/wifi-ath10k-reset-pointer-after-memory-free-to-avoid.patch new file mode 100644 index 00000000000..f16a98d6e31 --- /dev/null +++ b/queue-5.10/wifi-ath10k-reset-pointer-after-memory-free-to-avoid.patch @@ -0,0 +1,64 @@ +From 2d2a66729c0f2e378145a56f79d5270ca79e4fbb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Sep 2022 18:23:54 +0300 +Subject: wifi: ath10k: reset pointer after memory free to avoid potential + use-after-free + +From: Wen Gong + +[ Upstream commit 1e1cb8e0b73e6f39a9d4a7a15d940b1265387eb5 ] + +When running suspend test, kernel crash happened in ath10k, and it is +fixed by commit b72a4aff947b ("ath10k: skip ath10k_halt during suspend +for driver state RESTARTING"). + +Currently the crash is fixed, but as a common code style, it is better +to set the pointer to NULL after memory is free. + +This is to address the code style and it will avoid potential bug of +use-after-free. + +Tested-on: QCA6174 hw3.2 PCI WLAN.RM.4.4.1-00110-QCARMSWP-1 +Signed-off-by: Wen Gong +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220505092248.787-1-quic_wgong@quicinc.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ath/ath10k/htt_rx.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c +index 28ec3c5b4d1f..1b34f12b7eca 100644 +--- a/drivers/net/wireless/ath/ath10k/htt_rx.c ++++ b/drivers/net/wireless/ath/ath10k/htt_rx.c +@@ -297,12 +297,16 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt) + ath10k_htt_get_vaddr_ring(htt), + htt->rx_ring.base_paddr); + ++ ath10k_htt_config_paddrs_ring(htt, NULL); ++ + dma_free_coherent(htt->ar->dev, + sizeof(*htt->rx_ring.alloc_idx.vaddr), + htt->rx_ring.alloc_idx.vaddr, + htt->rx_ring.alloc_idx.paddr); ++ htt->rx_ring.alloc_idx.vaddr = NULL; + + kfree(htt->rx_ring.netbufs_ring); ++ htt->rx_ring.netbufs_ring = NULL; + } + + static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt) +@@ -823,8 +827,10 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt) + ath10k_htt_get_rx_ring_size(htt), + vaddr_ring, + htt->rx_ring.base_paddr); ++ ath10k_htt_config_paddrs_ring(htt, NULL); + err_dma_ring: + kfree(htt->rx_ring.netbufs_ring); ++ htt->rx_ring.netbufs_ring = NULL; + err_netbuf: + return -ENOMEM; + } +-- +2.35.1 + diff --git a/queue-5.10/wifi-ath11k-fix-number-of-vht-beamformee-spatial-str.patch b/queue-5.10/wifi-ath11k-fix-number-of-vht-beamformee-spatial-str.patch new file mode 100644 index 00000000000..3a37a82211a --- /dev/null +++ b/queue-5.10/wifi-ath11k-fix-number-of-vht-beamformee-spatial-str.patch @@ -0,0 +1,101 @@ +From 596ac01c7e140792cfe0e779163e5aed69c23cff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 10:35:14 +0300 +Subject: wifi: ath11k: fix number of VHT beamformee spatial streams + +From: Jesus Fernandez Manzano + +[ Upstream commit 55b5ee3357d7bb98ee578cf9b84a652e7a1bc199 ] + +The number of spatial streams used when acting as a beamformee in VHT +mode are reported by the firmware as 7 (8 sts - 1) both in IPQ6018 and +IPQ8074 which respectively have 2 and 4 sts each. So the firmware should +report 1 (2 - 1) and 3 (4 - 1). + +Fix this by checking that the number of VHT beamformee sts reported by +the firmware is not greater than the number of receiving antennas - 1. +The fix is based on the same approach used in this same function for +sanitizing the number of sounding dimensions reported by the firmware. + +Without this change, acting as a beamformee in VHT mode is not working +properly. + +Tested-on: IPQ6018 hw1.0 AHB WLAN.HK.2.5.0.1-01208-QCAHKSWPL_SILICONZ-1 +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1-01208-QCAHKSWPL_SILICONZ-1 + +Fixes: d5c65159f289 ("ath11k: driver for Qualcomm IEEE 802.11ax devices") +Signed-off-by: Jesus Fernandez Manzano +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220616173947.21901-1-jesus.manzano@galgus.net +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ath/ath11k/mac.c | 25 ++++++++++++++++++++----- + 1 file changed, 20 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/wireless/ath/ath11k/mac.c b/drivers/net/wireless/ath/ath11k/mac.c +index 44282aec069d..67faf62999de 100644 +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3419,6 +3419,8 @@ static int ath11k_mac_set_txbf_conf(struct ath11k_vif *arvif) + if (vht_cap & (IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE)) { + nsts = vht_cap & IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK; + nsts >>= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; ++ if (nsts > (ar->num_rx_chains - 1)) ++ nsts = ar->num_rx_chains - 1; + value |= SM(nsts, WMI_TXBF_STS_CAP_OFFSET); + } + +@@ -3459,7 +3461,7 @@ static int ath11k_mac_set_txbf_conf(struct ath11k_vif *arvif) + static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap) + { + bool subfer, subfee; +- int sound_dim = 0; ++ int sound_dim = 0, nsts = 0; + + subfer = !!(*vht_cap & (IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)); + subfee = !!(*vht_cap & (IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE)); +@@ -3469,6 +3471,11 @@ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap) + subfer = false; + } + ++ if (ar->num_rx_chains < 2) { ++ *vht_cap &= ~(IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE); ++ subfee = false; ++ } ++ + /* If SU Beaformer is not set, then disable MU Beamformer Capability */ + if (!subfer) + *vht_cap &= ~(IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); +@@ -3481,7 +3488,9 @@ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap) + sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT; + *vht_cap &= ~IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK; + +- /* TODO: Need to check invalid STS and Sound_dim values set by FW? */ ++ nsts = (*vht_cap & IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK); ++ nsts >>= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; ++ *vht_cap &= ~IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK; + + /* Enable Sounding Dimension Field only if SU BF is enabled */ + if (subfer) { +@@ -3493,9 +3502,15 @@ static void ath11k_set_vht_txbf_cap(struct ath11k *ar, u32 *vht_cap) + *vht_cap |= sound_dim; + } + +- /* Use the STS advertised by FW unless SU Beamformee is not supported*/ +- if (!subfee) +- *vht_cap &= ~(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK); ++ /* Enable Beamformee STS Field only if SU BF is enabled */ ++ if (subfee) { ++ if (nsts > (ar->num_rx_chains - 1)) ++ nsts = ar->num_rx_chains - 1; ++ ++ nsts <<= IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; ++ nsts &= IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK; ++ *vht_cap |= nsts; ++ } + } + + static struct ieee80211_sta_vht_cap +-- +2.35.1 + diff --git a/queue-5.10/wifi-ath9k-avoid-uninit-memory-read-in-ath9k_htc_rx_.patch b/queue-5.10/wifi-ath9k-avoid-uninit-memory-read-in-ath9k_htc_rx_.patch new file mode 100644 index 00000000000..1c5ef160373 --- /dev/null +++ b/queue-5.10/wifi-ath9k-avoid-uninit-memory-read-in-ath9k_htc_rx_.patch @@ -0,0 +1,152 @@ +From 55a42da0b6391d6ee99f8d542fb12eb1ea75b314 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Aug 2022 23:46:13 +0900 +Subject: wifi: ath9k: avoid uninit memory read in ath9k_htc_rx_msg() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Tetsuo Handa + +[ Upstream commit b383e8abed41cc6ff1a3b34de75df9397fa4878c ] + +syzbot is reporting uninit value at ath9k_htc_rx_msg() [1], for +ioctl(USB_RAW_IOCTL_EP_WRITE) can call ath9k_hif_usb_rx_stream() with +pkt_len = 0 but ath9k_hif_usb_rx_stream() uses +__dev_alloc_skb(pkt_len + 32, GFP_ATOMIC) based on an assumption that +pkt_len is valid. As a result, ath9k_hif_usb_rx_stream() allocates skb +with uninitialized memory and ath9k_htc_rx_msg() is reading from +uninitialized memory. + +Since bytes accessed by ath9k_htc_rx_msg() is not known until +ath9k_htc_rx_msg() is called, it would be difficult to check minimal valid +pkt_len at "if (pkt_len > 2 * MAX_RX_BUF_SIZE) {" line in +ath9k_hif_usb_rx_stream(). + +We have two choices. One is to workaround by adding __GFP_ZERO so that +ath9k_htc_rx_msg() sees 0 if pkt_len is invalid. The other is to let +ath9k_htc_rx_msg() validate pkt_len before accessing. This patch chose +the latter. + +Note that I'm not sure threshold condition is correct, for I can't find +details on possible packet length used by this protocol. + +Link: https://syzkaller.appspot.com/bug?extid=2ca247c2d60c7023de7f [1] +Reported-by: syzbot +Signed-off-by: Tetsuo Handa +Acked-by: Toke Høiland-Jørgensen +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/7acfa1be-4b5c-b2ce-de43-95b0593fb3e5@I-love.SAKURA.ne.jp +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ath/ath9k/htc_hst.c | 43 +++++++++++++++--------- + 1 file changed, 28 insertions(+), 15 deletions(-) + +diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c +index 994ec48b2f66..ca05b07a45e6 100644 +--- a/drivers/net/wireless/ath/ath9k/htc_hst.c ++++ b/drivers/net/wireless/ath/ath9k/htc_hst.c +@@ -364,33 +364,27 @@ void ath9k_htc_txcompletion_cb(struct htc_target *htc_handle, + } + + static void ath9k_htc_fw_panic_report(struct htc_target *htc_handle, +- struct sk_buff *skb) ++ struct sk_buff *skb, u32 len) + { + uint32_t *pattern = (uint32_t *)skb->data; + +- switch (*pattern) { +- case 0x33221199: +- { ++ if (*pattern == 0x33221199 && len >= sizeof(struct htc_panic_bad_vaddr)) { + struct htc_panic_bad_vaddr *htc_panic; + htc_panic = (struct htc_panic_bad_vaddr *) skb->data; + dev_err(htc_handle->dev, "ath: firmware panic! " + "exccause: 0x%08x; pc: 0x%08x; badvaddr: 0x%08x.\n", + htc_panic->exccause, htc_panic->pc, + htc_panic->badvaddr); +- break; +- } +- case 0x33221299: +- { ++ return; ++ } ++ if (*pattern == 0x33221299) { + struct htc_panic_bad_epid *htc_panic; + htc_panic = (struct htc_panic_bad_epid *) skb->data; + dev_err(htc_handle->dev, "ath: firmware panic! " + "bad epid: 0x%08x\n", htc_panic->epid); +- break; +- } +- default: +- dev_err(htc_handle->dev, "ath: unknown panic pattern!\n"); +- break; ++ return; + } ++ dev_err(htc_handle->dev, "ath: unknown panic pattern!\n"); + } + + /* +@@ -411,16 +405,26 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle, + if (!htc_handle || !skb) + return; + ++ /* A valid message requires len >= 8. ++ * ++ * sizeof(struct htc_frame_hdr) == 8 ++ * sizeof(struct htc_ready_msg) == 8 ++ * sizeof(struct htc_panic_bad_vaddr) == 16 ++ * sizeof(struct htc_panic_bad_epid) == 8 ++ */ ++ if (unlikely(len < sizeof(struct htc_frame_hdr))) ++ goto invalid; + htc_hdr = (struct htc_frame_hdr *) skb->data; + epid = htc_hdr->endpoint_id; + + if (epid == 0x99) { +- ath9k_htc_fw_panic_report(htc_handle, skb); ++ ath9k_htc_fw_panic_report(htc_handle, skb, len); + kfree_skb(skb); + return; + } + + if (epid < 0 || epid >= ENDPOINT_MAX) { ++invalid: + if (pipe_id != USB_REG_IN_PIPE) + dev_kfree_skb_any(skb); + else +@@ -432,21 +436,30 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle, + + /* Handle trailer */ + if (htc_hdr->flags & HTC_FLAGS_RECV_TRAILER) { +- if (be32_to_cpu(*(__be32 *) skb->data) == 0x00C60000) ++ if (be32_to_cpu(*(__be32 *) skb->data) == 0x00C60000) { + /* Move past the Watchdog pattern */ + htc_hdr = (struct htc_frame_hdr *)(skb->data + 4); ++ len -= 4; ++ } + } + + /* Get the message ID */ ++ if (unlikely(len < sizeof(struct htc_frame_hdr) + sizeof(__be16))) ++ goto invalid; + msg_id = (__be16 *) ((void *) htc_hdr + + sizeof(struct htc_frame_hdr)); + + /* Now process HTC messages */ + switch (be16_to_cpu(*msg_id)) { + case HTC_MSG_READY_ID: ++ if (unlikely(len < sizeof(struct htc_ready_msg))) ++ goto invalid; + htc_process_target_rdy(htc_handle, htc_hdr); + break; + case HTC_MSG_CONNECT_SERVICE_RESPONSE_ID: ++ if (unlikely(len < sizeof(struct htc_frame_hdr) + ++ sizeof(struct htc_conn_svc_rspmsg))) ++ goto invalid; + htc_process_conn_rsp(htc_handle, htc_hdr); + break; + default: +-- +2.35.1 + diff --git a/queue-5.10/wifi-brcmfmac-fix-invalid-address-access-when-enabli.patch b/queue-5.10/wifi-brcmfmac-fix-invalid-address-access-when-enabli.patch new file mode 100644 index 00000000000..16d2d38cbb5 --- /dev/null +++ b/queue-5.10/wifi-brcmfmac-fix-invalid-address-access-when-enabli.patch @@ -0,0 +1,110 @@ +From 4b8956861b008d8dde1d155032b6b5b693a05002 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 22 Jul 2022 13:56:28 +0200 +Subject: wifi: brcmfmac: fix invalid address access when enabling SCAN log + level +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Wright Feng + +[ Upstream commit aa666b68e73fc06d83c070d96180b9010cf5a960 ] + +The variable i is changed when setting random MAC address and causes +invalid address access when printing the value of pi->reqs[i]->reqid. + +We replace reqs index with ri to fix the issue. + +[ 136.726473] Unable to handle kernel access to user memory outside uaccess routines at virtual address 0000000000000000 +[ 136.737365] Mem abort info: +[ 136.740172] ESR = 0x96000004 +[ 136.743359] Exception class = DABT (current EL), IL = 32 bits +[ 136.749294] SET = 0, FnV = 0 +[ 136.752481] EA = 0, S1PTW = 0 +[ 136.755635] Data abort info: +[ 136.758514] ISV = 0, ISS = 0x00000004 +[ 136.762487] CM = 0, WnR = 0 +[ 136.765522] user pgtable: 4k pages, 48-bit VAs, pgdp = 000000005c4e2577 +[ 136.772265] [0000000000000000] pgd=0000000000000000 +[ 136.777160] Internal error: Oops: 96000004 [#1] PREEMPT SMP +[ 136.782732] Modules linked in: brcmfmac(O) brcmutil(O) cfg80211(O) compat(O) +[ 136.789788] Process wificond (pid: 3175, stack limit = 0x00000000053048fb) +[ 136.796664] CPU: 3 PID: 3175 Comm: wificond Tainted: G O 4.19.42-00001-g531a5f5 #1 +[ 136.805532] Hardware name: Freescale i.MX8MQ EVK (DT) +[ 136.810584] pstate: 60400005 (nZCv daif +PAN -UAO) +[ 136.815429] pc : brcmf_pno_config_sched_scans+0x6cc/0xa80 [brcmfmac] +[ 136.821811] lr : brcmf_pno_config_sched_scans+0x67c/0xa80 [brcmfmac] +[ 136.828162] sp : ffff00000e9a3880 +[ 136.831475] x29: ffff00000e9a3890 x28: ffff800020543400 +[ 136.836786] x27: ffff8000b1008880 x26: ffff0000012bf6a0 +[ 136.842098] x25: ffff80002054345c x24: ffff800088d22400 +[ 136.847409] x23: ffff0000012bf638 x22: ffff0000012bf6d8 +[ 136.852721] x21: ffff8000aced8fc0 x20: ffff8000ac164400 +[ 136.858032] x19: ffff00000e9a3946 x18: 0000000000000000 +[ 136.863343] x17: 0000000000000000 x16: 0000000000000000 +[ 136.868655] x15: ffff0000093f3b37 x14: 0000000000000050 +[ 136.873966] x13: 0000000000003135 x12: 0000000000000000 +[ 136.879277] x11: 0000000000000000 x10: ffff000009a61888 +[ 136.884589] x9 : 000000000000000f x8 : 0000000000000008 +[ 136.889900] x7 : 303a32303d726464 x6 : ffff00000a1f957d +[ 136.895211] x5 : 0000000000000000 x4 : ffff00000e9a3942 +[ 136.900523] x3 : 0000000000000000 x2 : ffff0000012cead8 +[ 136.905834] x1 : ffff0000012bf6d8 x0 : 0000000000000000 +[ 136.911146] Call trace: +[ 136.913623] brcmf_pno_config_sched_scans+0x6cc/0xa80 [brcmfmac] +[ 136.919658] brcmf_pno_start_sched_scan+0xa4/0x118 [brcmfmac] +[ 136.925430] brcmf_cfg80211_sched_scan_start+0x80/0xe0 [brcmfmac] +[ 136.931636] nl80211_start_sched_scan+0x140/0x308 [cfg80211] +[ 136.937298] genl_rcv_msg+0x358/0x3f4 +[ 136.940960] netlink_rcv_skb+0xb4/0x118 +[ 136.944795] genl_rcv+0x34/0x48 +[ 136.947935] netlink_unicast+0x264/0x300 +[ 136.951856] netlink_sendmsg+0x2e4/0x33c +[ 136.955781] __sys_sendto+0x120/0x19c + +Signed-off-by: Wright Feng +Signed-off-by: Chi-hsien Lin +Signed-off-by: Ahmad Fatoum +Signed-off-by: Alvin Å ipraga +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220722115632.620681-4-alvin@pqrs.dk +Signed-off-by: Sasha Levin +--- + .../net/wireless/broadcom/brcm80211/brcmfmac/pno.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c +index fabfbb0b40b0..d0a7465be586 100644 +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pno.c +@@ -158,12 +158,12 @@ static int brcmf_pno_set_random(struct brcmf_if *ifp, struct brcmf_pno_info *pi) + struct brcmf_pno_macaddr_le pfn_mac; + u8 *mac_addr = NULL; + u8 *mac_mask = NULL; +- int err, i; ++ int err, i, ri; + +- for (i = 0; i < pi->n_reqs; i++) +- if (pi->reqs[i]->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { +- mac_addr = pi->reqs[i]->mac_addr; +- mac_mask = pi->reqs[i]->mac_addr_mask; ++ for (ri = 0; ri < pi->n_reqs; ri++) ++ if (pi->reqs[ri]->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { ++ mac_addr = pi->reqs[ri]->mac_addr; ++ mac_mask = pi->reqs[ri]->mac_addr_mask; + break; + } + +@@ -185,7 +185,7 @@ static int brcmf_pno_set_random(struct brcmf_if *ifp, struct brcmf_pno_info *pi) + pfn_mac.mac[0] |= 0x02; + + brcmf_dbg(SCAN, "enabling random mac: reqid=%llu mac=%pM\n", +- pi->reqs[i]->reqid, pfn_mac.mac); ++ pi->reqs[ri]->reqid, pfn_mac.mac); + err = brcmf_fil_iovar_data_set(ifp, "pfn_macaddr", &pfn_mac, + sizeof(pfn_mac)); + if (err) +-- +2.35.1 + diff --git a/queue-5.10/wifi-brcmfmac-fix-use-after-free-bug-in-brcmf_netdev.patch b/queue-5.10/wifi-brcmfmac-fix-use-after-free-bug-in-brcmf_netdev.patch new file mode 100644 index 00000000000..1242b13d895 --- /dev/null +++ b/queue-5.10/wifi-brcmfmac-fix-use-after-free-bug-in-brcmf_netdev.patch @@ -0,0 +1,140 @@ +From e4f7e3847fb67000063cf0ad99ee14411ce2c764 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Aug 2022 10:49:26 -0700 +Subject: wifi: brcmfmac: fix use-after-free bug in brcmf_netdev_start_xmit() + +From: Alexander Coffin + +[ Upstream commit 3f42faf6db431e04bf942d2ebe3ae88975723478 ] + +> ret = brcmf_proto_tx_queue_data(drvr, ifp->ifidx, skb); + +may be schedule, and then complete before the line + +> ndev->stats.tx_bytes += skb->len; + +[ 46.912801] ================================================================== +[ 46.920552] BUG: KASAN: use-after-free in brcmf_netdev_start_xmit+0x718/0x8c8 [brcmfmac] +[ 46.928673] Read of size 4 at addr ffffff803f5882e8 by task systemd-resolve/328 +[ 46.935991] +[ 46.937514] CPU: 1 PID: 328 Comm: systemd-resolve Tainted: G O 5.4.199-[REDACTED] #1 +[ 46.947255] Hardware name: [REDACTED] +[ 46.954568] Call trace: +[ 46.957037] dump_backtrace+0x0/0x2b8 +[ 46.960719] show_stack+0x24/0x30 +[ 46.964052] dump_stack+0x128/0x194 +[ 46.967557] print_address_description.isra.0+0x64/0x380 +[ 46.972877] __kasan_report+0x1d4/0x240 +[ 46.976723] kasan_report+0xc/0x18 +[ 46.980138] __asan_report_load4_noabort+0x18/0x20 +[ 46.985027] brcmf_netdev_start_xmit+0x718/0x8c8 [brcmfmac] +[ 46.990613] dev_hard_start_xmit+0x1bc/0xda0 +[ 46.994894] sch_direct_xmit+0x198/0xd08 +[ 46.998827] __qdisc_run+0x37c/0x1dc0 +[ 47.002500] __dev_queue_xmit+0x1528/0x21f8 +[ 47.006692] dev_queue_xmit+0x24/0x30 +[ 47.010366] neigh_resolve_output+0x37c/0x678 +[ 47.014734] ip_finish_output2+0x598/0x2458 +[ 47.018927] __ip_finish_output+0x300/0x730 +[ 47.023118] ip_output+0x2e0/0x430 +[ 47.026530] ip_local_out+0x90/0x140 +[ 47.030117] igmpv3_sendpack+0x14c/0x228 +[ 47.034049] igmpv3_send_cr+0x384/0x6b8 +[ 47.037895] igmp_ifc_timer_expire+0x4c/0x118 +[ 47.042262] call_timer_fn+0x1cc/0xbe8 +[ 47.046021] __run_timers+0x4d8/0xb28 +[ 47.049693] run_timer_softirq+0x24/0x40 +[ 47.053626] __do_softirq+0x2c0/0x117c +[ 47.057387] irq_exit+0x2dc/0x388 +[ 47.060715] __handle_domain_irq+0xb4/0x158 +[ 47.064908] gic_handle_irq+0x58/0xb0 +[ 47.068581] el0_irq_naked+0x50/0x5c +[ 47.072162] +[ 47.073665] Allocated by task 328: +[ 47.077083] save_stack+0x24/0xb0 +[ 47.080410] __kasan_kmalloc.isra.0+0xc0/0xe0 +[ 47.084776] kasan_slab_alloc+0x14/0x20 +[ 47.088622] kmem_cache_alloc+0x15c/0x468 +[ 47.092643] __alloc_skb+0xa4/0x498 +[ 47.096142] igmpv3_newpack+0x158/0xd78 +[ 47.099987] add_grhead+0x210/0x288 +[ 47.103485] add_grec+0x6b0/0xb70 +[ 47.106811] igmpv3_send_cr+0x2e0/0x6b8 +[ 47.110657] igmp_ifc_timer_expire+0x4c/0x118 +[ 47.115027] call_timer_fn+0x1cc/0xbe8 +[ 47.118785] __run_timers+0x4d8/0xb28 +[ 47.122457] run_timer_softirq+0x24/0x40 +[ 47.126389] __do_softirq+0x2c0/0x117c +[ 47.130142] +[ 47.131643] Freed by task 180: +[ 47.134712] save_stack+0x24/0xb0 +[ 47.138041] __kasan_slab_free+0x108/0x180 +[ 47.142146] kasan_slab_free+0x10/0x18 +[ 47.145904] slab_free_freelist_hook+0xa4/0x1b0 +[ 47.150444] kmem_cache_free+0x8c/0x528 +[ 47.154292] kfree_skbmem+0x94/0x108 +[ 47.157880] consume_skb+0x10c/0x5a8 +[ 47.161466] __dev_kfree_skb_any+0x88/0xa0 +[ 47.165598] brcmu_pkt_buf_free_skb+0x44/0x68 [brcmutil] +[ 47.171023] brcmf_txfinalize+0xec/0x190 [brcmfmac] +[ 47.176016] brcmf_proto_bcdc_txcomplete+0x1c0/0x210 [brcmfmac] +[ 47.182056] brcmf_sdio_sendfromq+0x8dc/0x1e80 [brcmfmac] +[ 47.187568] brcmf_sdio_dpc+0xb48/0x2108 [brcmfmac] +[ 47.192529] brcmf_sdio_dataworker+0xc8/0x238 [brcmfmac] +[ 47.197859] process_one_work+0x7fc/0x1a80 +[ 47.201965] worker_thread+0x31c/0xc40 +[ 47.205726] kthread+0x2d8/0x370 +[ 47.208967] ret_from_fork+0x10/0x18 +[ 47.212546] +[ 47.214051] The buggy address belongs to the object at ffffff803f588280 +[ 47.214051] which belongs to the cache skbuff_head_cache of size 208 +[ 47.227086] The buggy address is located 104 bytes inside of +[ 47.227086] 208-byte region [ffffff803f588280, ffffff803f588350) +[ 47.238814] The buggy address belongs to the page: +[ 47.243618] page:ffffffff00dd6200 refcount:1 mapcount:0 mapping:ffffff804b6bf800 index:0xffffff803f589900 compound_mapcount: 0 +[ 47.255007] flags: 0x10200(slab|head) +[ 47.258689] raw: 0000000000010200 ffffffff00dfa980 0000000200000002 ffffff804b6bf800 +[ 47.266439] raw: ffffff803f589900 0000000080190018 00000001ffffffff 0000000000000000 +[ 47.274180] page dumped because: kasan: bad access detected +[ 47.279752] +[ 47.281251] Memory state around the buggy address: +[ 47.286051] ffffff803f588180: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb +[ 47.293277] ffffff803f588200: fb fb fc fc fc fc fc fc fc fc fc fc fc fc fc fc +[ 47.300502] >ffffff803f588280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb +[ 47.307723] ^ +[ 47.314343] ffffff803f588300: fb fb fb fb fb fb fb fb fb fb fc fc fc fc fc fc +[ 47.321569] ffffff803f588380: fc fc fc fc fc fc fc fc fb fb fb fb fb fb fb fb +[ 47.328789] ================================================================== + +Signed-off-by: Alexander Coffin +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220808174925.3922558-1-alex.coffin@matician.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c +index 61039538a15b..c8e1d505f7b5 100644 +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c +@@ -290,6 +290,7 @@ static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb, + struct brcmf_pub *drvr = ifp->drvr; + struct ethhdr *eh; + int head_delta; ++ unsigned int tx_bytes = skb->len; + + brcmf_dbg(DATA, "Enter, bsscfgidx=%d\n", ifp->bsscfgidx); + +@@ -364,7 +365,7 @@ static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb, + ndev->stats.tx_dropped++; + } else { + ndev->stats.tx_packets++; +- ndev->stats.tx_bytes += skb->len; ++ ndev->stats.tx_bytes += tx_bytes; + } + + /* Return ok: we always eat the packet */ +-- +2.35.1 + diff --git a/queue-5.10/wifi-mac80211-allow-bw-change-during-channel-switch-.patch b/queue-5.10/wifi-mac80211-allow-bw-change-during-channel-switch-.patch new file mode 100644 index 00000000000..9f288a835ca --- /dev/null +++ b/queue-5.10/wifi-mac80211-allow-bw-change-during-channel-switch-.patch @@ -0,0 +1,47 @@ +From 7de39f369cb4e50a4c1f8935c6c6718c86e26748 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Jul 2022 12:02:29 +0530 +Subject: wifi: mac80211: allow bw change during channel switch in mesh + +From: Hari Chandrakanthan + +[ Upstream commit 6b75f133fe05c36c52d691ff21545d5757fff721 ] + +From 'IEEE Std 802.11-2020 section 11.8.8.4.1': + The mesh channel switch may be triggered by the need to avoid + interference to a detected radar signal, or to reassign mesh STA + channels to ensure the MBSS connectivity. + + A 20/40 MHz MBSS may be changed to a 20 MHz MBSS and a 20 MHz + MBSS may be changed to a 20/40 MHz MBSS. + +Since the standard allows the change of bandwidth during +the channel switch in mesh, remove the bandwidth check present in +ieee80211_set_csa_beacon. + +Fixes: c6da674aff94 ("{nl,cfg,mac}80211: enable the triggering of CSA frame in mesh") +Signed-off-by: Hari Chandrakanthan +Link: https://lore.kernel.org/r/1658903549-21218-1-git-send-email-quic_haric@quicinc.com +Signed-off-by: Johannes Berg +Signed-off-by: Sasha Levin +--- + net/mac80211/cfg.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c +index 8010967a6874..c6a7f1c99abc 100644 +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -3357,9 +3357,6 @@ static int ieee80211_set_csa_beacon(struct ieee80211_sub_if_data *sdata, + case NL80211_IFTYPE_MESH_POINT: { + struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; + +- if (params->chandef.width != sdata->vif.bss_conf.chandef.width) +- return -EINVAL; +- + /* changes into another band are not supported */ + if (sdata->vif.bss_conf.chandef.chan->band != + params->chandef.chan->band) +-- +2.35.1 + diff --git a/queue-5.10/wifi-rt2x00-correctly-set-bbp-register-86-for-mt7620.patch b/queue-5.10/wifi-rt2x00-correctly-set-bbp-register-86-for-mt7620.patch new file mode 100644 index 00000000000..b60d754b7ce --- /dev/null +++ b/queue-5.10/wifi-rt2x00-correctly-set-bbp-register-86-for-mt7620.patch @@ -0,0 +1,40 @@ +From 24a9e4d165c9f525f81c3b4a9d74a6f01b2394dd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 17 Sep 2022 21:30:09 +0100 +Subject: wifi: rt2x00: correctly set BBP register 86 for MT7620 + +From: Daniel Golle + +[ Upstream commit c9aada64fe6493461127f1522d7e2f01792d2424 ] + +Instead of 0 set the correct value for BBP register 86 for MT7620. + +Reported-by: Serge Vasilugin +Signed-off-by: Daniel Golle +Acked-by: Stanislaw Gruszka +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/257267247ee4fa7ebc6a5d0c4948b3f8119c0d77.1663445157.git.daniel@makrotopia.org +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +index f237fc17dedc..4bdd3a95f2d2 100644 +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -4151,7 +4151,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, + rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); + rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); + rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); +- rt2800_bbp_write(rt2x00dev, 86, 0); ++ if (rt2x00_rt(rt2x00dev, RT6352)) ++ rt2800_bbp_write(rt2x00dev, 86, 0x38); ++ else ++ rt2800_bbp_write(rt2x00dev, 86, 0); + } + + if (rf->channel <= 14) { +-- +2.35.1 + diff --git a/queue-5.10/wifi-rt2x00-don-t-run-rt5592-iq-calibration-on-mt762.patch b/queue-5.10/wifi-rt2x00-don-t-run-rt5592-iq-calibration-on-mt762.patch new file mode 100644 index 00000000000..c4451690791 --- /dev/null +++ b/queue-5.10/wifi-rt2x00-don-t-run-rt5592-iq-calibration-on-mt762.patch @@ -0,0 +1,38 @@ +From 5560613e1805223193ee565239a7477f49a1bc9c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 17 Sep 2022 21:28:29 +0100 +Subject: wifi: rt2x00: don't run Rt5592 IQ calibration on MT7620 + +From: Daniel Golle + +[ Upstream commit d3aad83d05aec0cfd7670cf0028f2ad4b81de92e ] + +The function rt2800_iq_calibrate is intended for Rt5592 only. +Don't call it for MT7620 which has it's own calibration functions. + +Reported-by: Serge Vasilugin +Signed-off-by: Daniel Golle +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/31a1c34ddbd296b82f38c18c9ae7339059215fdc.1663445157.git.daniel@makrotopia.org +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +index fed6d21cd6ce..3f2c10c2aaf8 100644 +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -4352,7 +4352,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, + reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); + +- rt2800_iq_calibrate(rt2x00dev, rf->channel); ++ if (rt2x00_rt(rt2x00dev, RT5592)) ++ rt2800_iq_calibrate(rt2x00dev, rf->channel); + } + + bbp = rt2800_bbp_read(rt2x00dev, 4); +-- +2.35.1 + diff --git a/queue-5.10/wifi-rt2x00-set-correct-tx_sw_cfg1-mac-register-for-.patch b/queue-5.10/wifi-rt2x00-set-correct-tx_sw_cfg1-mac-register-for-.patch new file mode 100644 index 00000000000..ed977a90573 --- /dev/null +++ b/queue-5.10/wifi-rt2x00-set-correct-tx_sw_cfg1-mac-register-for-.patch @@ -0,0 +1,39 @@ +From 3e59db86d5d24763a3a53cbb8eb79586bbb08511 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 17 Sep 2022 21:29:26 +0100 +Subject: wifi: rt2x00: set correct TX_SW_CFG1 MAC register for MT7620 + +From: Daniel Golle + +[ Upstream commit eeb50acf15762b61921f9df18663f839f387c054 ] + +Set correct TX_SW_CFG1 MAC register as it is done also in v3 of the +vendor driver[1]. + +[1]: https://gitlab.com/dm38/padavan-ng/-/blob/master/trunk/proprietary/rt_wifi/rtpci/3.0.X.X/mt76x2/chips/rt6352.c#L531 +Reported-by: Serge Vasilugin +Signed-off-by: Daniel Golle +Acked-by: Stanislaw Gruszka +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/4be38975ce600a34249e12d09a3cb758c6e71071.1663445157.git.daniel@makrotopia.org +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +index 3f2c10c2aaf8..327f19cae4d7 100644 +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -5849,7 +5849,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); + } else if (rt2x00_rt(rt2x00dev, RT6352)) { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); +- rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); ++ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001); + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); + rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); +-- +2.35.1 + diff --git a/queue-5.10/wifi-rt2x00-set-soc-wmac-clock-register.patch b/queue-5.10/wifi-rt2x00-set-soc-wmac-clock-register.patch new file mode 100644 index 00000000000..311c3483388 --- /dev/null +++ b/queue-5.10/wifi-rt2x00-set-soc-wmac-clock-register.patch @@ -0,0 +1,58 @@ +From cd3430934b78c2af54594dd1e65fc1389f91ff57 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 17 Sep 2022 21:29:55 +0100 +Subject: wifi: rt2x00: set SoC wmac clock register + +From: Daniel Golle + +[ Upstream commit cbde6ed406a51092d9e8a2df058f5f8490f27443 ] + +Instead of using the default value 33 (pci), set US_CYC_CNT init based +on Programming guide: +If available, set chipset bus clock with fallback to cpu clock/3. + +Reported-by: Serge Vasilugin +Signed-off-by: Daniel Golle +Acked-by: Stanislaw Gruszka +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/3e275d259f476f597dab91a9c395015ef3fe3284.1663445157.git.daniel@makrotopia.org +Signed-off-by: Sasha Levin +--- + .../net/wireless/ralink/rt2x00/rt2800lib.c | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +index 94e5c3c373ba..f237fc17dedc 100644 +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -6112,6 +6112,27 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) + reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); + rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); + rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); ++ } else if (rt2x00_is_soc(rt2x00dev)) { ++ struct clk *clk = clk_get_sys("bus", NULL); ++ int rate; ++ ++ if (IS_ERR(clk)) { ++ clk = clk_get_sys("cpu", NULL); ++ ++ if (IS_ERR(clk)) { ++ rate = 125; ++ } else { ++ rate = clk_get_rate(clk) / 3000000; ++ clk_put(clk); ++ } ++ } else { ++ rate = clk_get_rate(clk) / 1000000; ++ clk_put(clk); ++ } ++ ++ reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); ++ rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); ++ rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); + } + + reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); +-- +2.35.1 + diff --git a/queue-5.10/wifi-rt2x00-set-vgc-gain-for-both-chains-of-mt7620.patch b/queue-5.10/wifi-rt2x00-set-vgc-gain-for-both-chains-of-mt7620.patch new file mode 100644 index 00000000000..c7a28c022d1 --- /dev/null +++ b/queue-5.10/wifi-rt2x00-set-vgc-gain-for-both-chains-of-mt7620.patch @@ -0,0 +1,38 @@ +From 1ba4cdae220bbb4a6dc5e88d0c6143c4d7285b28 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 17 Sep 2022 21:29:40 +0100 +Subject: wifi: rt2x00: set VGC gain for both chains of MT7620 + +From: Daniel Golle + +[ Upstream commit 0e09768c085709e10ece3b68f6ac921d3f6a9caa ] + +Set bbp66 for all chains of the MT7620. + +Reported-by: Serge Vasilugin +Signed-off-by: Daniel Golle +Acked-by: Stanislaw Gruszka +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/29e161397e5c9d9399da0fe87d44458aa2b90a78.1663445157.git.daniel@makrotopia.org +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +index 327f19cae4d7..94e5c3c373ba 100644 +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +@@ -5626,7 +5626,8 @@ static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, + if (qual->vgc_level != vgc_level) { + if (rt2x00_rt(rt2x00dev, RT3572) || + rt2x00_rt(rt2x00dev, RT3593) || +- rt2x00_rt(rt2x00dev, RT3883)) { ++ rt2x00_rt(rt2x00dev, RT3883) || ++ rt2x00_rt(rt2x00dev, RT6352)) { + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, + vgc_level); + } else if (rt2x00_rt(rt2x00dev, RT5592)) { +-- +2.35.1 + diff --git a/queue-5.10/wifi-rtl8xxxu-fix-aifs-written-to-reg_edca_-_param.patch b/queue-5.10/wifi-rtl8xxxu-fix-aifs-written-to-reg_edca_-_param.patch new file mode 100644 index 00000000000..0800c131904 --- /dev/null +++ b/queue-5.10/wifi-rtl8xxxu-fix-aifs-written-to-reg_edca_-_param.patch @@ -0,0 +1,98 @@ +From dc24a8bc3e596daa0af034ae890e027fc1fa29fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 18 Sep 2022 15:42:25 +0300 +Subject: wifi: rtl8xxxu: Fix AIFS written to REG_EDCA_*_PARAM + +From: Bitterblue Smith + +[ Upstream commit 5574d3290449916397f3092dcd2bac92415498e1 ] + +ieee80211_tx_queue_params.aifs is not supposed to be written directly +to the REG_EDCA_*_PARAM registers. Instead process it like the vendor +drivers do. It's kinda hacky but it works. + +This change boosts the download speed and makes it more stable. + +Tested with RTL8188FU but all the other supported chips should also +benefit. + +Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)") +Signed-off-by: Bitterblue Smith +Acked-by: Jes Sorensen +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/038cc03f-3567-77ba-a7bd-c4930e3b2fad@gmail.com +Signed-off-by: Sasha Levin +--- + .../wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 49 +++++++++++++++++++ + 1 file changed, 49 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +index 7818a7ea0498..e34cd6fed7e8 100644 +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +@@ -4507,6 +4507,53 @@ rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) + return network_type; + } + ++static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) ++{ ++ u32 reg_edca_param[IEEE80211_NUM_ACS] = { ++ [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, ++ [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, ++ [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, ++ [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, ++ }; ++ u32 val32; ++ u16 wireless_mode = 0; ++ u8 aifs, aifsn, sifs; ++ int i; ++ ++ if (priv->vif) { ++ struct ieee80211_sta *sta; ++ ++ rcu_read_lock(); ++ sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid); ++ if (sta) ++ wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); ++ rcu_read_unlock(); ++ } ++ ++ if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || ++ (wireless_mode & WIRELESS_MODE_N_24G)) ++ sifs = 16; ++ else ++ sifs = 10; ++ ++ for (i = 0; i < IEEE80211_NUM_ACS; i++) { ++ val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); ++ ++ /* It was set in conf_tx. */ ++ aifsn = val32 & 0xff; ++ ++ /* aifsn not set yet or already fixed */ ++ if (aifsn < 2 || aifsn > 15) ++ continue; ++ ++ aifs = aifsn * slot_time + sifs; ++ ++ val32 &= ~0xff; ++ val32 |= aifs; ++ rtl8xxxu_write32(priv, reg_edca_param[i], val32); ++ } ++} ++ + static void + rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_bss_conf *bss_conf, u32 changed) +@@ -4592,6 +4639,8 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + else + val8 = 20; + rtl8xxxu_write8(priv, REG_SLOT, val8); ++ ++ rtl8xxxu_set_aifs(priv, val8); + } + + if (changed & BSS_CHANGED_BSSID) { +-- +2.35.1 + diff --git a/queue-5.10/wifi-rtl8xxxu-fix-skb-misuse-in-tx-queue-selection.patch b/queue-5.10/wifi-rtl8xxxu-fix-skb-misuse-in-tx-queue-selection.patch new file mode 100644 index 00000000000..510c5915ca4 --- /dev/null +++ b/queue-5.10/wifi-rtl8xxxu-fix-skb-misuse-in-tx-queue-selection.patch @@ -0,0 +1,47 @@ +From 5f85a75fcc768647dfc5f84468ac4135b7aa5a77 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 31 Aug 2022 19:12:36 +0300 +Subject: wifi: rtl8xxxu: Fix skb misuse in TX queue selection + +From: Bitterblue Smith + +[ Upstream commit edd5747aa12ed61a5ecbfa58d3908623fddbf1e8 ] + +rtl8xxxu_queue_select() selects the wrong TX queues because it's +reading memory from the wrong address. It expects to find ieee80211_hdr +at skb->data, but that's not the case after skb_push(). Move the call +to rtl8xxxu_queue_select() before the call to skb_push(). + +Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)") +Signed-off-by: Bitterblue Smith +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/7fa4819a-4f20-b2af-b7a6-8ee01ac49295@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +index 9f646964055d..e8b4544b5b15 100644 +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +@@ -4984,6 +4984,8 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw, + if (control && control->sta) + sta = control->sta; + ++ queue = rtl8xxxu_queue_select(hw, skb); ++ + tx_desc = skb_push(skb, tx_desc_size); + + memset(tx_desc, 0, tx_desc_size); +@@ -4996,7 +4998,6 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw, + is_broadcast_ether_addr(ieee80211_get_DA(hdr))) + tx_desc->txdw0 |= TXDESC_BROADMULTICAST; + +- queue = rtl8xxxu_queue_select(hw, skb); + tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); + + if (tx_info->control.hw_key) { +-- +2.35.1 + diff --git a/queue-5.10/wifi-rtl8xxxu-gen2-fix-mistake-in-path-b-iq-calibrat.patch b/queue-5.10/wifi-rtl8xxxu-gen2-fix-mistake-in-path-b-iq-calibrat.patch new file mode 100644 index 00000000000..24e7cf7cb9a --- /dev/null +++ b/queue-5.10/wifi-rtl8xxxu-gen2-fix-mistake-in-path-b-iq-calibrat.patch @@ -0,0 +1,46 @@ +From 266e5715f17e4ed1aa32c2ae56ef55eb60f2e7bf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 14:48:32 +0300 +Subject: wifi: rtl8xxxu: gen2: Fix mistake in path B IQ calibration + +From: Bitterblue Smith + +[ Upstream commit e963a19c64ac0d2f8785d36a27391abd91ac77aa ] + +Found by comparing with the vendor driver. Currently this affects +only the RTL8192EU, which is the only gen2 chip with 2 TX paths +supported by this driver. It's unclear what kind of effect the +mistake had in practice, since I don't have any RTL8192EU devices +to test it. + +Fixes: e1547c535ede ("rtl8xxxu: First stab at adding IQK calibration for 8723bu parts") +Signed-off-by: Bitterblue Smith +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/30a59f3a-cfa9-8379-7af0-78a8f4c77cfd@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +index e8b4544b5b15..8668b03bd8c7 100644 +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +@@ -2925,12 +2925,12 @@ bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, + } + + if (!(simubitmap & 0x30) && priv->tx_paths > 1) { +- /* path B RX OK */ ++ /* path B TX OK */ + for (i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + } + +- if (!(simubitmap & 0x30) && priv->tx_paths > 1) { ++ if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { + /* path B RX OK */ + for (i = 6; i < 8; i++) + result[3][i] = result[c1][i]; +-- +2.35.1 + diff --git a/queue-5.10/wifi-rtl8xxxu-remove-copy-paste-leftover-in-gen2_upd.patch b/queue-5.10/wifi-rtl8xxxu-remove-copy-paste-leftover-in-gen2_upd.patch new file mode 100644 index 00000000000..c30de974e8a --- /dev/null +++ b/queue-5.10/wifi-rtl8xxxu-remove-copy-paste-leftover-in-gen2_upd.patch @@ -0,0 +1,49 @@ +From 9f69d41bace81b9424c8dcef6b195d324213d101 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Sep 2022 16:15:30 +0300 +Subject: wifi: rtl8xxxu: Remove copy-paste leftover in gen2_update_rate_mask + +From: Bitterblue Smith + +[ Upstream commit d5350756c03cdf18696295c6b11d7acc4dbf825c ] + +It looks like a leftover from copying rtl8xxxu_update_rate_mask, +which is used with the gen1 chips. + +It wasn't causing any problems for my RTL8188FU test device, but it's +clearly a mistake, so remove it. + +Fixes: f653e69009c6 ("rtl8xxxu: Implement basic 8723b specific update_rate_mask() function") +Signed-off-by: Bitterblue Smith +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/d5544fe8-9798-28f1-54bd-6839a1974b10@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +index 8668b03bd8c7..7818a7ea0498 100644 +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +@@ -4338,15 +4338,14 @@ void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, + h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; + h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; + +- h2c.ramask.arg = 0x80; + h2c.b_macid_cfg.data1 = rateid; + if (sgi) + h2c.b_macid_cfg.data1 |= BIT(7); + + h2c.b_macid_cfg.data2 = bw; + +- dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", +- __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg)); ++ dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", ++ __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); + } + +-- +2.35.1 + diff --git a/queue-5.10/wifi-rtl8xxxu-tighten-bounds-checking-in-rtl8xxxu_re.patch b/queue-5.10/wifi-rtl8xxxu-tighten-bounds-checking-in-rtl8xxxu_re.patch new file mode 100644 index 00000000000..b3cd11c5355 --- /dev/null +++ b/queue-5.10/wifi-rtl8xxxu-tighten-bounds-checking-in-rtl8xxxu_re.patch @@ -0,0 +1,59 @@ +From 5b0f711ef32a8d1f8d2cb74e5d76de66f0f930a1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Aug 2022 08:22:32 +0300 +Subject: wifi: rtl8xxxu: tighten bounds checking in rtl8xxxu_read_efuse() + +From: Dan Carpenter + +[ Upstream commit 620d5eaeb9059636864bda83ca1c68c20ede34a5 ] + +There some bounds checking to ensure that "map_addr" is not out of +bounds before the start of the loop. But the checking needs to be +done as we iterate through the loop because "map_addr" gets larger as +we iterate. + +Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)") +Signed-off-by: Dan Carpenter +Acked-by: Jes Sorensen +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/Yv8eGLdBslLAk3Ct@kili +Signed-off-by: Sasha Levin +--- + .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +index 0d374a294840..9f646964055d 100644 +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +@@ -1874,13 +1874,6 @@ static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) + + /* We have 8 bits to indicate validity */ + map_addr = offset * 8; +- if (map_addr >= EFUSE_MAP_LEN) { +- dev_warn(dev, "%s: Illegal map_addr (%04x), " +- "efuse corrupt!\n", +- __func__, map_addr); +- ret = -EINVAL; +- goto exit; +- } + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (word_mask & BIT(i)) { +@@ -1891,6 +1884,13 @@ static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) + ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); + if (ret) + goto exit; ++ if (map_addr >= EFUSE_MAP_LEN - 1) { ++ dev_warn(dev, "%s: Illegal map_addr (%04x), " ++ "efuse corrupt!\n", ++ __func__, map_addr); ++ ret = -EINVAL; ++ goto exit; ++ } + priv->efuse_wifi.raw[map_addr++] = val8; + + ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); +-- +2.35.1 + diff --git a/queue-5.10/wifi-rtw88-phy-fix-warning-of-possible-buffer-overfl.patch b/queue-5.10/wifi-rtw88-phy-fix-warning-of-possible-buffer-overfl.patch new file mode 100644 index 00000000000..018c1cc32b1 --- /dev/null +++ b/queue-5.10/wifi-rtw88-phy-fix-warning-of-possible-buffer-overfl.patch @@ -0,0 +1,68 @@ +From ba167126fd171934bf173a0db147ec9f6b20bfb7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 27 Jul 2022 14:50:03 +0800 +Subject: wifi: rtw88: phy: fix warning of possible buffer overflow + +From: Zong-Zhe Yang + +[ Upstream commit 86331c7e0cd819bf0c1d0dcf895e0c90b0aa9a6f ] + +reported by smatch + +phy.c:854 rtw_phy_linear_2_db() error: buffer overflow 'db_invert_table[i]' +8 <= 8 (assuming for loop doesn't break) + +However, it seems to be a false alarm because we prevent it originally via + if (linear >= db_invert_table[11][7]) + return 96; /* maximum 96 dB */ + +Still, we adjust the code to be more readable and avoid smatch warning. + +Signed-off-by: Zong-Zhe Yang +Signed-off-by: Ping-Ke Shih +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220727065003.28340-5-pkshih@realtek.com +Signed-off-by: Sasha Levin +--- + drivers/net/wireless/realtek/rtw88/phy.c | 21 ++++++++------------- + 1 file changed, 8 insertions(+), 13 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw88/phy.c b/drivers/net/wireless/realtek/rtw88/phy.c +index af8b703d11d4..0fc5a893c395 100644 +--- a/drivers/net/wireless/realtek/rtw88/phy.c ++++ b/drivers/net/wireless/realtek/rtw88/phy.c +@@ -604,23 +604,18 @@ static u8 rtw_phy_linear_2_db(u64 linear) + u8 j; + u32 dB; + +- if (linear >= db_invert_table[11][7]) +- return 96; /* maximum 96 dB */ +- + for (i = 0; i < 12; i++) { +- if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7]) +- break; +- else if (i > 2 && linear <= db_invert_table[i][7]) +- break; ++ for (j = 0; j < 8; j++) { ++ if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j]) ++ goto cnt; ++ else if (i > 2 && linear <= db_invert_table[i][j]) ++ goto cnt; ++ } + } + +- for (j = 0; j < 8; j++) { +- if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j]) +- break; +- else if (i > 2 && linear <= db_invert_table[i][j]) +- break; +- } ++ return 96; /* maximum 96 dB */ + ++cnt: + if (j == 0 && i == 0) + goto end; + +-- +2.35.1 + diff --git a/queue-5.10/x86-cpu-include-the-header-of-init_ia32_feat_ctl-s-p.patch b/queue-5.10/x86-cpu-include-the-header-of-init_ia32_feat_ctl-s-p.patch new file mode 100644 index 00000000000..e89a135a9b5 --- /dev/null +++ b/queue-5.10/x86-cpu-include-the-header-of-init_ia32_feat_ctl-s-p.patch @@ -0,0 +1,66 @@ +From 150fdc475b9855a1cc30bdd59083389d02dcf66a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 22 Sep 2022 17:00:54 -0300 +Subject: x86/cpu: Include the header of init_ia32_feat_ctl()'s prototype +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Luciano Leão + +[ Upstream commit 30ea703a38ef76ca119673cd8bdd05c6e068e2ac ] + +Include the header containing the prototype of init_ia32_feat_ctl(), +solving the following warning: + + $ make W=1 arch/x86/kernel/cpu/feat_ctl.o + arch/x86/kernel/cpu/feat_ctl.c:112:6: warning: no previous prototype for ‘init_ia32_feat_ctl’ [-Wmissing-prototypes] + 112 | void init_ia32_feat_ctl(struct cpuinfo_x86 *c) + +This warning appeared after commit + + 5d5103595e9e5 ("x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup") + +had moved the function init_ia32_feat_ctl()'s prototype from +arch/x86/kernel/cpu/cpu.h to arch/x86/include/asm/cpu.h. + +Note that, before the commit mentioned above, the header include "cpu.h" +(arch/x86/kernel/cpu/cpu.h) was added by commit + + 0e79ad863df43 ("x86/cpu: Fix a -Wmissing-prototypes warning for init_ia32_feat_ctl()") + +solely to fix init_ia32_feat_ctl()'s missing prototype. So, the header +include "cpu.h" is no longer necessary. + + [ bp: Massage commit message. ] + +Fixes: 5d5103595e9e5 ("x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup") +Signed-off-by: Luciano Leão +Signed-off-by: Borislav Petkov +Reviewed-by: Nícolas F. R. A. Prado +Link: https://lore.kernel.org/r/20220922200053.1357470-1-lucianorsleao@gmail.com +Signed-off-by: Sasha Levin +--- + arch/x86/kernel/cpu/feat_ctl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c +index 29a3bedabd06..d7541851288e 100644 +--- a/arch/x86/kernel/cpu/feat_ctl.c ++++ b/arch/x86/kernel/cpu/feat_ctl.c +@@ -1,11 +1,11 @@ + // SPDX-License-Identifier: GPL-2.0 + #include + ++#include + #include + #include + #include + #include +-#include "cpu.h" + + #undef pr_fmt + #define pr_fmt(fmt) "x86/cpu: " fmt +-- +2.35.1 + diff --git a/queue-5.10/x86-entry-work-around-clang-__bdos-bug.patch b/queue-5.10/x86-entry-work-around-clang-__bdos-bug.patch new file mode 100644 index 00000000000..e37d2dba11a --- /dev/null +++ b/queue-5.10/x86-entry-work-around-clang-__bdos-bug.patch @@ -0,0 +1,66 @@ +From 700fcd28dfafb4eb61b209126a99d607b6e7da7c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 19 Sep 2022 19:45:14 -0700 +Subject: x86/entry: Work around Clang __bdos() bug + +From: Kees Cook + +[ Upstream commit 3e1730842f142add55dc658929221521a9ea62b6 ] + +Clang produces a false positive when building with CONFIG_FORTIFY_SOURCE=y +and CONFIG_UBSAN_BOUNDS=y when operating on an array with a dynamic +offset. Work around this by using a direct assignment of an empty +instance. Avoids this warning: + +../include/linux/fortify-string.h:309:4: warning: call to __write_overflow_field declared with 'warn +ing' attribute: detected write beyond size of field (1st parameter); maybe use struct_group()? [-Wat +tribute-warning] + __write_overflow_field(p_size_field, size); + ^ + +which was isolated to the memset() call in xen_load_idt(). + +Note that this looks very much like another bug that was worked around: +https://github.com/ClangBuiltLinux/linux/issues/1592 + +Cc: Juergen Gross +Cc: Boris Ostrovsky +Cc: Thomas Gleixner +Cc: Ingo Molnar +Cc: Borislav Petkov +Cc: Dave Hansen +Cc: x86@kernel.org +Cc: "H. Peter Anvin" +Cc: xen-devel@lists.xenproject.org +Reviewed-by: Boris Ostrovsky +Link: https://lore.kernel.org/lkml/41527d69-e8ab-3f86-ff37-6b298c01d5bc@oracle.com +Signed-off-by: Kees Cook +Signed-off-by: Sasha Levin +--- + arch/x86/xen/enlighten_pv.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c +index 804c65d2b95f..815030b7f6fa 100644 +--- a/arch/x86/xen/enlighten_pv.c ++++ b/arch/x86/xen/enlighten_pv.c +@@ -768,6 +768,7 @@ static void xen_load_idt(const struct desc_ptr *desc) + { + static DEFINE_SPINLOCK(lock); + static struct trap_info traps[257]; ++ static const struct trap_info zero = { }; + unsigned out; + + trace_xen_cpu_load_idt(desc); +@@ -777,7 +778,7 @@ static void xen_load_idt(const struct desc_ptr *desc) + memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); + + out = xen_convert_trap_info(desc, traps, false); +- memset(&traps[out], 0, sizeof(traps[0])); ++ traps[out] = zero; + + xen_mc_flush(); + if (HYPERVISOR_set_trap_table(traps)) +-- +2.35.1 + diff --git a/queue-5.10/x86-hyperv-fix-struct-hv_enlightened_vmcs-definition.patch b/queue-5.10/x86-hyperv-fix-struct-hv_enlightened_vmcs-definition.patch new file mode 100644 index 00000000000..0575f696b71 --- /dev/null +++ b/queue-5.10/x86-hyperv-fix-struct-hv_enlightened_vmcs-definition.patch @@ -0,0 +1,68 @@ +From f0b4332738ba434be623f8345a48e308e4b59514 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 15:37:05 +0200 +Subject: x86/hyperv: Fix 'struct hv_enlightened_vmcs' definition + +From: Vitaly Kuznetsov + +[ Upstream commit ea9da788a61e47e7ab9cbad397453e51cd82ac0d ] + +Section 1.9 of TLFS v6.0b says: + +"All structures are padded in such a way that fields are aligned +naturally (that is, an 8-byte field is aligned to an offset of 8 bytes +and so on)". + +'struct enlightened_vmcs' has a glitch: + +... + struct { + u32 nested_flush_hypercall:1; /* 836: 0 4 */ + u32 msr_bitmap:1; /* 836: 1 4 */ + u32 reserved:30; /* 836: 2 4 */ + } hv_enlightenments_control; /* 836 4 */ + u32 hv_vp_id; /* 840 4 */ + u64 hv_vm_id; /* 844 8 */ + u64 partition_assist_page; /* 852 8 */ +... + +And the observed values in 'partition_assist_page' make no sense at +all. Fix the layout by padding the structure properly. + +Fixes: 68d1eb72ee99 ("x86/hyper-v: define struct hv_enlightened_vmcs and clean field bits") +Reviewed-by: Maxim Levitsky +Reviewed-by: Michael Kelley +Signed-off-by: Vitaly Kuznetsov +Signed-off-by: Sean Christopherson +Link: https://lore.kernel.org/r/20220830133737.1539624-2-vkuznets@redhat.com +Signed-off-by: Paolo Bonzini +Signed-off-by: Sasha Levin +--- + arch/x86/include/asm/hyperv-tlfs.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h +index 0ed20e8bba9e..ae7192b75136 100644 +--- a/arch/x86/include/asm/hyperv-tlfs.h ++++ b/arch/x86/include/asm/hyperv-tlfs.h +@@ -474,7 +474,7 @@ struct hv_enlightened_vmcs { + u64 guest_rip; + + u32 hv_clean_fields; +- u32 hv_padding_32; ++ u32 padding32_1; + u32 hv_synthetic_controls; + struct { + u32 nested_flush_hypercall:1; +@@ -482,7 +482,7 @@ struct hv_enlightened_vmcs { + u32 reserved:30; + } __packed hv_enlightenments_control; + u32 hv_vp_id; +- ++ u32 padding32_2; + u64 hv_vm_id; + u64 partition_assist_page; + u64 padding64_4[4]; +-- +2.35.1 + diff --git a/queue-5.10/x86-microcode-amd-track-patch-allocation-size-explic.patch b/queue-5.10/x86-microcode-amd-track-patch-allocation-size-explic.patch new file mode 100644 index 00000000000..17f4e675dc5 --- /dev/null +++ b/queue-5.10/x86-microcode-amd-track-patch-allocation-size-explic.patch @@ -0,0 +1,64 @@ +From 601ef622e8422f03e1551f7b392215b55d1f9f94 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 20:10:10 -0700 +Subject: x86/microcode/AMD: Track patch allocation size explicitly + +From: Kees Cook + +[ Upstream commit 712f210a457d9c32414df246a72781550bc23ef6 ] + +In preparation for reducing the use of ksize(), record the actual +allocation size for later memcpy(). This avoids copying extra +(uninitialized!) bytes into the patch buffer when the requested +allocation size isn't exactly the size of a kmalloc bucket. +Additionally, fix potential future issues where runtime bounds checking +will notice that the buffer was allocated to a smaller value than +returned by ksize(). + +Fixes: 757885e94a22 ("x86, microcode, amd: Early microcode patch loading support for AMD") +Suggested-by: Daniel Micay +Signed-off-by: Kees Cook +Signed-off-by: Borislav Petkov +Link: https://lore.kernel.org/lkml/CA+DvKQ+bp7Y7gmaVhacjv9uF6Ar-o4tet872h4Q8RPYPJjcJQA@mail.gmail.com/ +Signed-off-by: Sasha Levin +--- + arch/x86/include/asm/microcode.h | 1 + + arch/x86/kernel/cpu/microcode/amd.c | 3 ++- + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h +index 91a06cef50c1..f73327397b89 100644 +--- a/arch/x86/include/asm/microcode.h ++++ b/arch/x86/include/asm/microcode.h +@@ -9,6 +9,7 @@ + struct ucode_patch { + struct list_head plist; + void *data; /* Intel uses only this one */ ++ unsigned int size; + u32 patch_id; + u16 equiv_cpu; + }; +diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c +index 3f6b137ef4e6..c87936441339 100644 +--- a/arch/x86/kernel/cpu/microcode/amd.c ++++ b/arch/x86/kernel/cpu/microcode/amd.c +@@ -783,6 +783,7 @@ static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover, + kfree(patch); + return -EINVAL; + } ++ patch->size = *patch_size; + + mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE); + proc_id = mc_hdr->processor_rev_id; +@@ -864,7 +865,7 @@ load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) + return ret; + + memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); +- memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); ++ memcpy(amd_ucode_patch, p->data, min_t(u32, p->size, PATCH_MAX_SIZE)); + + return ret; + } +-- +2.35.1 + diff --git a/queue-5.10/x86-resctrl-fix-to-restore-to-original-value-when-re.patch b/queue-5.10/x86-resctrl-fix-to-restore-to-original-value-when-re.patch new file mode 100644 index 00000000000..c657a34f0ae --- /dev/null +++ b/queue-5.10/x86-resctrl-fix-to-restore-to-original-value-when-re.patch @@ -0,0 +1,108 @@ +From 7d09c4196f8eeea8bb45ab1c7c1b602d662b2c53 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 24 Aug 2022 09:44:10 -0700 +Subject: x86/resctrl: Fix to restore to original value when re-enabling + hardware prefetch register + +From: Kohei Tarumizu + +[ Upstream commit 499c8bb4693d1c8d8f3d6dd38e5bdde3ff5bd906 ] + +The current pseudo_lock.c code overwrites the value of the +MSR_MISC_FEATURE_CONTROL to 0 even if the original value is not 0. +Therefore, modify it to save and restore the original values. + +Fixes: 018961ae5579 ("x86/intel_rdt: Pseudo-lock region creation/removal core") +Fixes: 443810fe6160 ("x86/intel_rdt: Create debugfs files for pseudo-locking testing") +Fixes: 8a2fc0e1bc0c ("x86/intel_rdt: More precise L2 hit/miss measurements") +Signed-off-by: Kohei Tarumizu +Signed-off-by: Dave Hansen +Acked-by: Reinette Chatre +Link: https://lkml.kernel.org/r/eb660f3c2010b79a792c573c02d01e8e841206ad.1661358182.git.reinette.chatre@intel.com +Signed-off-by: Sasha Levin +--- + arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +index 0daf2f1cf7a8..465dce141bfc 100644 +--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c ++++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +@@ -416,6 +416,7 @@ static int pseudo_lock_fn(void *_rdtgrp) + struct pseudo_lock_region *plr = rdtgrp->plr; + u32 rmid_p, closid_p; + unsigned long i; ++ u64 saved_msr; + #ifdef CONFIG_KASAN + /* + * The registers used for local register variables are also used +@@ -459,6 +460,7 @@ static int pseudo_lock_fn(void *_rdtgrp) + * the buffer and evict pseudo-locked memory read earlier from the + * cache. + */ ++ saved_msr = __rdmsr(MSR_MISC_FEATURE_CONTROL); + __wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); + closid_p = this_cpu_read(pqr_state.cur_closid); + rmid_p = this_cpu_read(pqr_state.cur_rmid); +@@ -510,7 +512,7 @@ static int pseudo_lock_fn(void *_rdtgrp) + __wrmsr(IA32_PQR_ASSOC, rmid_p, closid_p); + + /* Re-enable the hardware prefetcher(s) */ +- wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0); ++ wrmsrl(MSR_MISC_FEATURE_CONTROL, saved_msr); + local_irq_enable(); + + plr->thread_done = 1; +@@ -867,6 +869,7 @@ bool rdtgroup_pseudo_locked_in_hierarchy(struct rdt_domain *d) + static int measure_cycles_lat_fn(void *_plr) + { + struct pseudo_lock_region *plr = _plr; ++ u32 saved_low, saved_high; + unsigned long i; + u64 start, end; + void *mem_r; +@@ -875,6 +878,7 @@ static int measure_cycles_lat_fn(void *_plr) + /* + * Disable hardware prefetchers. + */ ++ rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); + mem_r = READ_ONCE(plr->kmem); + /* +@@ -891,7 +895,7 @@ static int measure_cycles_lat_fn(void *_plr) + end = rdtsc_ordered(); + trace_pseudo_lock_mem_latency((u32)(end - start)); + } +- wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0); ++ wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + local_irq_enable(); + plr->thread_done = 1; + wake_up_interruptible(&plr->lock_thread_wq); +@@ -936,6 +940,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr, + u64 hits_before = 0, hits_after = 0, miss_before = 0, miss_after = 0; + struct perf_event *miss_event, *hit_event; + int hit_pmcnum, miss_pmcnum; ++ u32 saved_low, saved_high; + unsigned int line_size; + unsigned int size; + unsigned long i; +@@ -969,6 +974,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr, + /* + * Disable hardware prefetchers. + */ ++ rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); + + /* Initialize rest of local variables */ +@@ -1027,7 +1033,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr, + */ + rmb(); + /* Re-enable hardware prefetchers */ +- wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0); ++ wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + local_irq_enable(); + out_hit: + perf_event_release_kernel(hit_event); +-- +2.35.1 + diff --git a/queue-5.10/xfrm-update-ipcomp_scratches-with-null-when-freed.patch b/queue-5.10/xfrm-update-ipcomp_scratches-with-null-when-freed.patch new file mode 100644 index 00000000000..bf6bfcb328b --- /dev/null +++ b/queue-5.10/xfrm-update-ipcomp_scratches-with-null-when-freed.patch @@ -0,0 +1,72 @@ +From 1b7197ae21c1570ecb53ea6e97b77f45326552c7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Sep 2022 13:12:10 +0600 +Subject: xfrm: Update ipcomp_scratches with NULL when freed + +From: Khalid Masum + +[ Upstream commit 8a04d2fc700f717104bfb95b0f6694e448a4537f ] + +Currently if ipcomp_alloc_scratches() fails to allocate memory +ipcomp_scratches holds obsolete address. So when we try to free the +percpu scratches using ipcomp_free_scratches() it tries to vfree non +existent vm area. Described below: + +static void * __percpu *ipcomp_alloc_scratches(void) +{ + ... + scratches = alloc_percpu(void *); + if (!scratches) + return NULL; +ipcomp_scratches does not know about this allocation failure. +Therefore holding the old obsolete address. + ... +} + +So when we free, + +static void ipcomp_free_scratches(void) +{ + ... + scratches = ipcomp_scratches; +Assigning obsolete address from ipcomp_scratches + + if (!scratches) + return; + + for_each_possible_cpu(i) + vfree(*per_cpu_ptr(scratches, i)); +Trying to free non existent page, causing warning: trying to vfree +existent vm area. + ... +} + +Fix this breakage by updating ipcomp_scrtches with NULL when scratches +is freed + +Suggested-by: Herbert Xu +Reported-by: syzbot+5ec9bb042ddfe9644773@syzkaller.appspotmail.com +Tested-by: syzbot+5ec9bb042ddfe9644773@syzkaller.appspotmail.com +Signed-off-by: Khalid Masum +Acked-by: Herbert Xu +Signed-off-by: Steffen Klassert +Signed-off-by: Sasha Levin +--- + net/xfrm/xfrm_ipcomp.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/net/xfrm/xfrm_ipcomp.c b/net/xfrm/xfrm_ipcomp.c +index 0814320472f1..24ac6805275e 100644 +--- a/net/xfrm/xfrm_ipcomp.c ++++ b/net/xfrm/xfrm_ipcomp.c +@@ -212,6 +212,7 @@ static void ipcomp_free_scratches(void) + vfree(*per_cpu_ptr(scratches, i)); + + free_percpu(scratches); ++ ipcomp_scratches = NULL; + } + + static void * __percpu *ipcomp_alloc_scratches(void) +-- +2.35.1 + diff --git a/queue-5.10/xhci-don-t-show-warning-for-reinit-on-known-broken-s.patch b/queue-5.10/xhci-don-t-show-warning-for-reinit-on-known-broken-s.patch new file mode 100644 index 00000000000..81fe7b07c17 --- /dev/null +++ b/queue-5.10/xhci-don-t-show-warning-for-reinit-on-known-broken-s.patch @@ -0,0 +1,48 @@ +From 43d640e9737e04372493e7e67809f22368617d37 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 21 Sep 2022 15:34:47 +0300 +Subject: xhci: Don't show warning for reinit on known broken suspend + +From: Mario Limonciello + +[ Upstream commit 484d6f7aa3283d082c87654b7fe7a7f725423dfb ] + +commit 8b328f8002bc ("xhci: re-initialize the HC during resume if HCE was +set") introduced a new warning message when the host controller error +was set and re-initializing. + +This is expected behavior on some designs which already set +`xhci->broken_suspend` so the new warning is alarming to some users. + +Modify the code to only show the warning if this was a surprising behavior +to the XHCI driver. + +Link: https://bugzilla.kernel.org/show_bug.cgi?id=216470 +Fixes: 8b328f8002bc ("xhci: re-initialize the HC during resume if HCE was set") +Reported-by: Artem S. Tashkinov +Signed-off-by: Mario Limonciello +Signed-off-by: Mathias Nyman +Link: https://lore.kernel.org/r/20220921123450.671459-4-mathias.nyman@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/host/xhci.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 7b16b6b45af7..8918e6ae5c4b 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1163,7 +1163,8 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) + /* re-initialize the HC on Restore Error, or Host Controller Error */ + if (temp & (STS_SRE | STS_HCE)) { + reinit_xhc = true; +- xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp); ++ if (!xhci->broken_suspend) ++ xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp); + } + + if (reinit_xhc) { +-- +2.35.1 +