From: Shubhrajyoti Datta Date: Fri, 5 Sep 2025 09:10:02 +0000 (+0530) Subject: clk: clocking-wizard: Fix output clock register offset for Versal platforms X-Git-Tag: v6.18-rc1~50^2~2^3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7c2e86f7b5af93d0e78c16e4359318fe7797671d;p=thirdparty%2Fkernel%2Fstable.git clk: clocking-wizard: Fix output clock register offset for Versal platforms The output clock register offset used in clk_wzrd_register_output_clocks was incorrectly referencing 0x3C instead of 0x38, which caused misconfiguration of output dividers on Versal platforms. Correcting the off-by-one error ensures proper configuration of output clocks. Signed-off-by: Shubhrajyoti Datta Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index 6af41d207ab5..d016f716d98c 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1112,7 +1112,7 @@ static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs) (dev, clkout_name, clk_name, 0, clk_wzrd->base, - (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8), + (WZRD_CLK_CFG_REG(is_versal, 2) + i * 8), WZRD_CLKOUT_DIVIDE_SHIFT, WZRD_CLKOUT_DIVIDE_WIDTH, CLK_DIVIDER_ONE_BASED |