From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 23 Jul 2021 16:21:45 +0000 (+0100)
Subject: hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
X-Git-Tag: v6.1.0-rc1~1^2~7
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7caad65756c0afaf4b238b068ab61481eb68a1dc;p=thirdparty%2Fqemu.git

hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING

The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
the register.  We were incorrectly masking it to 8 bits, so it would
report the wrong value if the pending exception was greater than 256.
Fix the bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
---

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 2aba2136822..c9149a3b221 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1039,7 +1039,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         /* VECTACTIVE */
         val = cpu->env.v7m.exception;
         /* VECTPENDING */
-        val |= (s->vectpending & 0xff) << 12;
+        val |= (s->vectpending & 0x1ff) << 12;
         /* ISRPENDING - set if any external IRQ is pending */
         if (nvic_isrpending(s)) {
             val |= (1 << 22);