From: Venkatesh Yadav Abbarapu Date: Mon, 7 Jul 2025 04:37:38 +0000 (+0530) Subject: xilinx: zynqmp: disable CONFIG_SPI_FLASH_BAR X-Git-Tag: v2025.10-rc1~131^2~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7d8eafcf98e3fbc6df6d423c6d35c42af67b5e93;p=thirdparty%2Fu-boot.git xilinx: zynqmp: disable CONFIG_SPI_FLASH_BAR Legacy SPI flash devices used a 24-bit (3-byte) addressing scheme, limiting the addressable memory to 16 MB. To support larger densities (256 Mbit and higher), extended addressing schemes, such as 32-bit (4-byte) addressing, were introduced. If the flash density exceeds 16 MB and CONFIG_SPI_FLASH_BAR is disabled, the device will use a 4-byte addressing mode. Signed-off-by: Prasad Kummari Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250707043738.795179-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index c6eae387b92..65c8a4bbaad 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -163,7 +163,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ARASAN=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_MAX_CHIPS=2 -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y