From: Guenter Roeck <linux@roeck-us.net>
Date: Fri, 25 Apr 2014 15:39:48 +0000 (-0700)
Subject: xilinx_timer: Fix writes into TCSR register
X-Git-Tag: v2.1.0-rc0~134
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe;p=thirdparty%2Fqemu.git

xilinx_timer: Fix writes into TCSR register

The TCSR register has only 11 valid bits. This is now used by the
linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits
before writing the register to solve the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---

diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 6113b975bf8..3ff1da9cafb 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
             if (value & TCSR_TINT)
                 value &= ~TCSR_TINT;
 
-            xt->regs[addr] = value;
+            xt->regs[addr] = value & 0x7ff;
             if (value & TCSR_ENT)
                 timer_enable(xt);
             break;