From: Sasha Levin Date: Tue, 2 Jul 2024 10:20:07 +0000 (-0400) Subject: Fixes for 6.9 X-Git-Tag: v4.19.317~36^2~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7ee32693ce691230ae7056000534354a368fd0c0;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.9 Signed-off-by: Sasha Levin --- diff --git a/queue-6.9/arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch b/queue-6.9/arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch new file mode 100644 index 00000000000..7be906fc983 --- /dev/null +++ b/queue-6.9/arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch @@ -0,0 +1,37 @@ +From 572871974ddbfc3dfe6377ffa7f06531c855af36 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Jun 2024 20:08:10 +0200 +Subject: ARM: dts: rockchip: rk3066a: add #sound-dai-cells to hdmi node + +From: Johan Jonker + +[ Upstream commit cca46f811d0000c1522a5e18ea48c27a15e45c05 ] + +'#sound-dai-cells' is required to properly interpret +the list of DAI specified in the 'sound-dai' property, +so add them to the 'hdmi' node for 'rk3066a.dtsi'. + +Fixes: fadc78062477 ("ARM: dts: rockchip: add rk3066 hdmi nodes") +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/8b229dcc-94e4-4bbc-9efc-9d5ddd694532@gmail.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/rockchip/rk3066a.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/rockchip/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi +index 30139f21de64d..15cbd94d7ec05 100644 +--- a/arch/arm/boot/dts/rockchip/rk3066a.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3066a.dtsi +@@ -128,6 +128,7 @@ + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch b/queue-6.9/arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch new file mode 100644 index 00000000000..c942013fe34 --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch @@ -0,0 +1,52 @@ +From edfe8c66cd209e7355c58fe2dd86e3f008c0bf03 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 23 Jun 2024 11:01:15 +0200 +Subject: arm64: dts: rockchip: Add sound-dai-cells for RK3368 + +From: Alex Bee + +[ Upstream commit 8d7ec44aa5d1eb94a30319074762a1740440cdc8 ] + +Add the missing #sound-dai-cells for RK3368's I2S and S/PDIF controllers. + +Fixes: f7d89dfe1e31 ("arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs") +Fixes: 0328d68ea76d ("arm64: dts: rockchip: add rk3368 spdif node") +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20240623090116.670607-4-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3368.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +index 62af0cb94839b..5ce82b64b6836 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +@@ -793,6 +793,7 @@ + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; ++ #sound-dai-cells = <0>; + status = "disabled"; + }; + +@@ -804,6 +805,7 @@ + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; + dmas = <&dmac_bus 6>, <&dmac_bus 7>; + dma-names = "tx", "rx"; ++ #sound-dai-cells = <0>; + status = "disabled"; + }; + +@@ -817,6 +819,7 @@ + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_bus>; ++ #sound-dai-cells = <0>; + status = "disabled"; + }; + +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch b/queue-6.9/arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch new file mode 100644 index 00000000000..3aa33d4f5b7 --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch @@ -0,0 +1,39 @@ +From 3359647b60d2d5dd24ac06bb2f7657c43254e61c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 19 Jun 2024 14:00:46 +0900 +Subject: arm64: dts: rockchip: fix PMIC interrupt pin on ROCK Pi E + +From: FUKAUMI Naoki + +[ Upstream commit 02afd3d5b9fa4ffed284c0f7e7bec609097804fc ] + +use GPIO0_A2 as interrupt pin for PMIC. GPIO2_A6 was used for +pre-production board. + +Fixes: b918e81f2145 ("arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E") +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240619050047.1217-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +index f09d60bbe6c4f..a608a219543e5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +@@ -241,8 +241,8 @@ + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch b/queue-6.9/arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch new file mode 100644 index 00000000000..594fba96ace --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch @@ -0,0 +1,58 @@ +From 0e0b0492c0d1a9948a704e6e98115a10eb730f1a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 May 2024 21:10:06 +0000 +Subject: arm64: dts: rockchip: Fix SD NAND and eMMC init on rk3308-rock-pi-s + +From: Jonas Karlman + +[ Upstream commit 1fb98c855ccd7bc7f50c7a9626fbb8440454760b ] + +Radxa ROCK Pi S have optional onboard SD NAND on board revision v1.1, +v1.2 and v1.3, revision v1.5 changed to use optional onboard eMMC. + +The optional SD NAND typically fails to initialize: + + mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) + mmc0: error -110 whilst initialising SD card + mmc_host mmc0: Bus speed (slot 0) = 300000Hz (slot req 300000Hz, actual 300000HZ div = 0) + mmc0: error -110 whilst initialising SD card + mmc_host mmc0: Bus speed (slot 0) = 200000Hz (slot req 200000Hz, actual 200000HZ div = 0) + mmc0: error -110 whilst initialising SD card + mmc_host mmc0: Bus speed (slot 0) = 100000Hz (slot req 100000Hz, actual 100000HZ div = 0) + mmc0: error -110 whilst initialising SD card + +Add pinctrl and cap-sd-highspeed to fix SD NAND initialization. Also +drop bus-width and mmc-hs200-1_8v to fix eMMC initialization on the new +v1.5 board revision, only 3v3 signal voltage is used. + +Fixes: 2e04c25b1320 ("arm64: dts: rockchip: add ROCK Pi S DTS support") +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-4-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +index b47fe02c33fbd..84f4b4a44644c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -126,10 +126,12 @@ + }; + + &emmc { +- bus-width = <4>; + cap-mmc-highspeed; +- mmc-hs200-1_8v; ++ cap-sd-highspeed; ++ no-sdio; + non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_io>; + status = "okay"; + }; +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-fix-the-i2c-address-of-es8316-on-.patch b/queue-6.9/arm64-dts-rockchip-fix-the-i2c-address-of-es8316-on-.patch new file mode 100644 index 00000000000..9226558f53e --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-fix-the-i2c-address-of-es8316-on-.patch @@ -0,0 +1,46 @@ +From 1ddae3ccf91b2294b2344ac7b882485c939a48bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 23 Jun 2024 19:55:26 +0800 +Subject: arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi 4B + +From: Andy Yan + +[ Upstream commit 5d101df8fc3261607bd946a222248dd193956a0a ] + +According to the hardware design, the i2c address of audio codec es8316 +on Cool Pi 4B is 0x10. + +This fix the read/write error like bellow: +es8316 7-0011: ASoC: error at soc_component_write_no_lock on es8316.7-0011 for register: [0x0000000c] -6 +es8316 7-0011: ASoC: error at soc_component_write_no_lock on es8316.7-0011 for register: [0x00000003] -6 +es8316 7-0011: ASoC: error at soc_component_read_no_lock on es8316.7-0011 for register: [0x00000016] -6 +es8316 7-0011: ASoC: error at soc_component_read_no_lock on es8316.7-0011 for register: [0x00000016] -6 + +Fixes: 3f5d336d64d6 ("arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B") +Signed-off-by: Andy Yan +Link: https://lore.kernel.org/r/20240623115526.2154645-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +index e037bf9db75af..adba82c6e2e1e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +@@ -283,9 +283,9 @@ + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + +- es8316: audio-codec@11 { ++ es8316: audio-codec@10 { + compatible = "everest,es8316"; +- reg = <0x11>; ++ reg = <0x10>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch b/queue-6.9/arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch new file mode 100644 index 00000000000..79be95374a9 --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch @@ -0,0 +1,39 @@ +From 393ae8abbac8d226de9a713bd9d10a6e712ad47e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Jun 2024 11:58:55 +0000 +Subject: arm64: dts: rockchip: Fix the value of `dlg,jack-det-rate` mismatch + on rk3399-gru + +From: Hsin-Te Yuan + +[ Upstream commit a500c0b4b589ae6fb79140c9d96bd5cd31393d41 ] + +According to Documentation/devicetree/bindings/sound/dialog,da7219.yaml, +the value of `dlg,jack-det-rate` property should be "32_64" instead of +"32ms_64ms". + +Fixes: dc0ff0fa3a9b ("ASoC: da7219: Add Jack insertion detection polarity") +Signed-off-by: Hsin-Te Yuan +Link: https://lore.kernel.org/r/20240613-jack-rate-v2-2-ebc5f9f37931@chromium.org +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +index 789fd0dcc88ba..3cd63d1e8f15b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +@@ -450,7 +450,7 @@ ap_i2c_audio: &i2c8 { + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; +- dlg,jack-det-rate = "32ms_64ms"; ++ dlg,jack-det-rate = "32_64"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch b/queue-6.9/arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch new file mode 100644 index 00000000000..4155451dab1 --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch @@ -0,0 +1,37 @@ +From 1bdda92386d65d3b7b4786c90d65131860dcbeda Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Jun 2024 12:35:23 +0900 +Subject: arm64: dts: rockchip: make poweroff(8) work on Radxa ROCK 5A + +From: FUKAUMI Naoki + +[ Upstream commit d05f7aff7ac23884ed9103a876325047ff9049aa ] + +Designate the RK806 PMIC on the Radxa ROCK 5A as the system power +controller, so the board shuts down properly on poweroff(8). + +Fixes: 75fdcbc8f4c1 ("arm64: dts: rockchip: add PMIC to rock-5a") +Reviewed-by: Dragan Simic +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240612033523.37166-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 2002fd0221fa3..ef776aec9d4b5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -394,6 +394,7 @@ + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; ++ system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch b/queue-6.9/arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch new file mode 100644 index 00000000000..93f7b1bf26f --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch @@ -0,0 +1,83 @@ +From 12fc917674fb3c1df34d628db2c99fe04727c0ee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 May 2024 21:10:09 +0000 +Subject: arm64: dts: rockchip: Rename LED related pinctrl nodes on + rk3308-rock-pi-s + +From: Jonas Karlman + +[ Upstream commit d2a52f678883fe4bc00bca89366b1ba504750abf ] + +The nodename, -gpio, of referenced pinctrl nodes for the two LEDs +on the ROCK Pi S cause DT schema validation error: + + leds: green-led-gpio: {'rockchip,pins': [[0, 6, 0, 90]], 'phandle': [[98]]} is not of type 'array' + from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# + leds: heartbeat-led-gpio: {'rockchip,pins': [[0, 5, 0, 90]], 'phandle': [[99]]} is not of type 'array' + from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# + +Rename the pinctrl nodes and symbols to pass DT schema validation, also +extend LED nodes with information about color and function. + +Fixes: 2e04c25b1320 ("arm64: dts: rockchip: add ROCK Pi S DTS support") +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-7-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +index 84f4b4a44644c..079101cddd65f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -5,6 +5,8 @@ + */ + + /dts-v1/; ++ ++#include + #include "rk3308.dtsi" + + / { +@@ -24,17 +26,21 @@ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +- pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; ++ pinctrl-0 = <&green_led>, <&heartbeat_led>; + + green-led { ++ color = ; + default-state = "on"; ++ function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "rockpis:green:power"; + linux,default-trigger = "default-on"; + }; + + blue-led { ++ color = ; + default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "rockpis:blue:user"; + linux,default-trigger = "heartbeat"; +@@ -216,11 +222,11 @@ + pinctrl-0 = <&rtc_32k>; + + leds { +- green_led_gio: green-led-gpio { ++ green_led: green-led { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + +- heartbeat_led_gpio: heartbeat-led-gpio { ++ heartbeat_led: heartbeat-led { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +-- +2.43.0 + diff --git a/queue-6.9/arm64-dts-rockchip-set-correct-pwm0-pinctrl-on-rk358.patch b/queue-6.9/arm64-dts-rockchip-set-correct-pwm0-pinctrl-on-rk358.patch new file mode 100644 index 00000000000..46031770f42 --- /dev/null +++ b/queue-6.9/arm64-dts-rockchip-set-correct-pwm0-pinctrl-on-rk358.patch @@ -0,0 +1,46 @@ +From 744a174db8d9944e29f2a630019cd4dfecc60129 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Jun 2024 21:22:54 +0200 +Subject: arm64: dts: rockchip: set correct pwm0 pinctrl on rk3588-tiger + +From: Heiko Stuebner + +[ Upstream commit a21d2cc2f9039023105bf9f9bf1acf324d5ebf9d ] + +PWM0 on rk3588-tiger is connected to the BLT_CTRL pin of the Q7 connector +meant as the name implies to control a backlight device. + +Therefore set the correct M1 pinctrl variant for it. The M0 variant +cannot ever be used because that pin is routed to a connector pin on the +Q7 connector that is reserved for CAN use and the pin reachable by the M2 +variant is reserved for the embedded MCU on the SoM. + +Fixes: 6173ef24b35b ("arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM") +Signed-off-by: Heiko Stuebner +Reviewed-by: Quentin Schulz +Link: https://lore.kernel.org/r/20240603192254.2441025-1-heiko@sntech.de +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +index 1eb2543a5fde6..64ff1c90afe2c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +@@ -324,6 +324,11 @@ + }; + }; + ++&pwm0 { ++ pinctrl-0 = <&pwm0m1_pins>; ++ pinctrl-names = "default"; ++}; ++ + &saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +-- +2.43.0 + diff --git a/queue-6.9/cxl-mem-fix-no-cxl_nvd-during-pmem-region-auto-assem.patch b/queue-6.9/cxl-mem-fix-no-cxl_nvd-during-pmem-region-auto-assem.patch new file mode 100644 index 00000000000..d0f01f08e23 --- /dev/null +++ b/queue-6.9/cxl-mem-fix-no-cxl_nvd-during-pmem-region-auto-assem.patch @@ -0,0 +1,177 @@ +From 73e1be76584ca6235a9aff2625db0b780fa20934 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Jun 2024 14:44:23 +0800 +Subject: cxl/mem: Fix no cxl_nvd during pmem region auto-assembling + +From: Li Ming + +[ Upstream commit 84ec985944ef34a34a1605b93ce401aa8737af96 ] + +When CXL subsystem is auto-assembling a pmem region during cxl +endpoint port probing, always hit below calltrace. + + BUG: kernel NULL pointer dereference, address: 0000000000000078 + #PF: supervisor read access in kernel mode + #PF: error_code(0x0000) - not-present page + RIP: 0010:cxl_pmem_region_probe+0x22e/0x360 [cxl_pmem] + Call Trace: + + ? __die+0x24/0x70 + ? page_fault_oops+0x82/0x160 + ? do_user_addr_fault+0x65/0x6b0 + ? exc_page_fault+0x7d/0x170 + ? asm_exc_page_fault+0x26/0x30 + ? cxl_pmem_region_probe+0x22e/0x360 [cxl_pmem] + ? cxl_pmem_region_probe+0x1ac/0x360 [cxl_pmem] + cxl_bus_probe+0x1b/0x60 [cxl_core] + really_probe+0x173/0x410 + ? __pfx___device_attach_driver+0x10/0x10 + __driver_probe_device+0x80/0x170 + driver_probe_device+0x1e/0x90 + __device_attach_driver+0x90/0x120 + bus_for_each_drv+0x84/0xe0 + __device_attach+0xbc/0x1f0 + bus_probe_device+0x90/0xa0 + device_add+0x51c/0x710 + devm_cxl_add_pmem_region+0x1b5/0x380 [cxl_core] + cxl_bus_probe+0x1b/0x60 [cxl_core] + +The cxl_nvd of the memdev needs to be available during the pmem region +probe. Currently the cxl_nvd is registered after the endpoint port probe. +The endpoint probe, in the case of autoassembly of regions, can cause a +pmem region probe requiring the not yet available cxl_nvd. Adjust the +sequence so this dependency is met. + +This requires adding a port parameter to cxl_find_nvdimm_bridge() that +can be used to query the ancestor root port. The endpoint port is not +yet available, but will share a common ancestor with its parent, so +start the query from there instead. + +Fixes: f17b558d6663 ("cxl/pmem: Refactor nvdimm device registration, delete the workqueue") +Co-developed-by: Dan Williams +Signed-off-by: Dan Williams +Signed-off-by: Li Ming +Tested-by: Alison Schofield +Reviewed-by: Jonathan Cameron +Reviewed-by: Alison Schofield +Link: https://patch.msgid.link/20240612064423.2567625-1-ming4.li@intel.com +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/pmem.c | 16 +++++++++++----- + drivers/cxl/core/region.c | 2 +- + drivers/cxl/cxl.h | 4 ++-- + drivers/cxl/mem.c | 17 +++++++++-------- + 4 files changed, 23 insertions(+), 16 deletions(-) + +diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c +index e69625a8d6a1d..c00f3a933164f 100644 +--- a/drivers/cxl/core/pmem.c ++++ b/drivers/cxl/core/pmem.c +@@ -62,10 +62,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data) + return is_cxl_nvdimm_bridge(dev); + } + +-struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd) ++/** ++ * cxl_find_nvdimm_bridge() - find a bridge device relative to a port ++ * @port: any descendant port of an nvdimm-bridge associated ++ * root-cxl-port ++ */ ++struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port) + { +- struct cxl_root *cxl_root __free(put_cxl_root) = +- find_cxl_root(cxlmd->endpoint); ++ struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port); + struct device *dev; + + if (!cxl_root) +@@ -242,18 +246,20 @@ static void cxlmd_release_nvdimm(void *_cxlmd) + + /** + * devm_cxl_add_nvdimm() - add a bridge between a cxl_memdev and an nvdimm ++ * @parent_port: parent port for the (to be added) @cxlmd endpoint port + * @cxlmd: cxl_memdev instance that will perform LIBNVDIMM operations + * + * Return: 0 on success negative error code on failure. + */ +-int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd) ++int devm_cxl_add_nvdimm(struct cxl_port *parent_port, ++ struct cxl_memdev *cxlmd) + { + struct cxl_nvdimm_bridge *cxl_nvb; + struct cxl_nvdimm *cxl_nvd; + struct device *dev; + int rc; + +- cxl_nvb = cxl_find_nvdimm_bridge(cxlmd); ++ cxl_nvb = cxl_find_nvdimm_bridge(parent_port); + if (!cxl_nvb) + return -ENODEV; + +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index bcb30e04e0963..857afc8b72ff1 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2712,7 +2712,7 @@ static int cxl_pmem_region_alloc(struct cxl_region *cxlr) + * bridge for one device is the same for all. + */ + if (i == 0) { +- cxl_nvb = cxl_find_nvdimm_bridge(cxlmd); ++ cxl_nvb = cxl_find_nvdimm_bridge(cxlmd->endpoint); + if (!cxl_nvb) + return -ENODEV; + cxlr->cxl_nvb = cxl_nvb; +diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h +index 72fa477407689..2b82dcaf70aa6 100644 +--- a/drivers/cxl/cxl.h ++++ b/drivers/cxl/cxl.h +@@ -848,8 +848,8 @@ struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, + struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); + bool is_cxl_nvdimm(struct device *dev); + bool is_cxl_nvdimm_bridge(struct device *dev); +-int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); +-struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); ++int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd); ++struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); + + #ifdef CONFIG_CXL_REGION + bool is_cxl_pmem_region(struct device *dev); +diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c +index 0c79d9ce877cc..2f1b49bfe162f 100644 +--- a/drivers/cxl/mem.c ++++ b/drivers/cxl/mem.c +@@ -152,6 +152,15 @@ static int cxl_mem_probe(struct device *dev) + return -ENXIO; + } + ++ if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) { ++ rc = devm_cxl_add_nvdimm(parent_port, cxlmd); ++ if (rc) { ++ if (rc == -ENODEV) ++ dev_info(dev, "PMEM disabled by platform\n"); ++ return rc; ++ } ++ } ++ + if (dport->rch) + endpoint_parent = parent_port->uport_dev; + else +@@ -174,14 +183,6 @@ static int cxl_mem_probe(struct device *dev) + if (rc) + return rc; + +- if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) { +- rc = devm_cxl_add_nvdimm(cxlmd); +- if (rc == -ENODEV) +- dev_info(dev, "PMEM disabled by platform\n"); +- else +- return rc; +- } +- + /* + * The kernel may be operating out of CXL memory on this device, + * there is no spec defined way to determine whether this device +-- +2.43.0 + diff --git a/queue-6.9/cxl-region-avoid-null-pointer-dereference-in-region-.patch b/queue-6.9/cxl-region-avoid-null-pointer-dereference-in-region-.patch new file mode 100644 index 00000000000..f8180cf9f37 --- /dev/null +++ b/queue-6.9/cxl-region-avoid-null-pointer-dereference-in-region-.patch @@ -0,0 +1,85 @@ +From 9eba043a3688668901d7a8674c7ec24da94ee6f4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Jun 2024 17:36:09 -0700 +Subject: cxl/region: Avoid null pointer dereference in region lookup + +From: Alison Schofield + +[ Upstream commit 285f2a08841432fc3e498b1cd00cce5216cdf189 ] + +cxl_dpa_to_region() looks up a region based on a memdev and DPA. +It wrongly assumes an endpoint found mapping the DPA is also of +a fully assembled region. When not true it leads to a null pointer +dereference looking up the region name. + +This appears during testing of region lookup after a failure to +assemble a BIOS defined region or if the lookup raced with the +assembly of the BIOS defined region. + +Failure to clean up BIOS defined regions that fail assembly is an +issue in itself and a fix to that problem will alleviate some of +the impact. It will not alleviate the race condition so let's harden +this path. + +The behavior change is that the kernel oops due to a null pointer +dereference is replaced with a dev_dbg() message noting that an +endpoint was mapped. + +Additional comments are added so that future users of this function +can more clearly understand what it provides. + +Fixes: 0a105ab28a4d ("cxl/memdev: Warn of poison inject or clear to a mapped region") +Signed-off-by: Alison Schofield +Reviewed-by: Jonathan Cameron +Link: https://patch.msgid.link/20240604003609.202682-1-alison.schofield@intel.com +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/region.c | 19 +++++++++++++++---- + 1 file changed, 15 insertions(+), 4 deletions(-) + +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index 52061edf4bd97..a083893c0afe0 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2688,22 +2688,33 @@ static int __cxl_dpa_to_region(struct device *dev, void *arg) + { + struct cxl_dpa_to_region_context *ctx = arg; + struct cxl_endpoint_decoder *cxled; ++ struct cxl_region *cxlr; + u64 dpa = ctx->dpa; + + if (!is_endpoint_decoder(dev)) + return 0; + + cxled = to_cxl_endpoint_decoder(dev); +- if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) ++ if (!cxled || !cxled->dpa_res || !resource_size(cxled->dpa_res)) + return 0; + + if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) + return 0; + +- dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, +- dev_name(&cxled->cxld.region->dev)); ++ /* ++ * Stop the region search (return 1) when an endpoint mapping is ++ * found. The region may not be fully constructed so offering ++ * the cxlr in the context structure is not guaranteed. ++ */ ++ cxlr = cxled->cxld.region; ++ if (cxlr) ++ dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, ++ dev_name(&cxlr->dev)); ++ else ++ dev_dbg(dev, "dpa:0x%llx mapped in endpoint:%s\n", dpa, ++ dev_name(dev)); + +- ctx->cxlr = cxled->cxld.region; ++ ctx->cxlr = cxlr; + + return 1; + } +-- +2.43.0 + diff --git a/queue-6.9/cxl-region-check-interleave-capability.patch b/queue-6.9/cxl-region-check-interleave-capability.patch new file mode 100644 index 00000000000..7fe90f47127 --- /dev/null +++ b/queue-6.9/cxl-region-check-interleave-capability.patch @@ -0,0 +1,265 @@ +From 77227358c58fe25b2beaf9f678e3d57f24eaff97 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 14 Jun 2024 04:47:54 -0400 +Subject: cxl/region: check interleave capability + +From: Yao Xingtao + +[ Upstream commit 84328c5acebc10c8cdcf17283ab6c6d548885bfc ] + +Since interleave capability is not verified, if the interleave +capability of a target does not match the region need, committing decoder +should have failed at the device end. + +In order to checkout this error as quickly as possible, driver needs +to check the interleave capability of target during attaching it to +region. + +Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register), +bits 11 and 12 indicate the capability to establish interleaving in 3, 6, +12 and 16 ways. If these bits are not set, the target cannot be attached to +a region utilizing such interleave ways. + +Additionally, bits 8 and 9 represent the capability of the bits used for +interleaving in the address, Linux tracks this in the cxl_port +interleave_mask. + +Per CXL specification r3.1(8.2.4.20.13 Decoder Protection): + eIW means encoded Interleave Ways. + eIG means encoded Interleave Granularity. + + in HPA: + if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used, + the interleave bits are none, the following check is ignored. + + if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits + start at bit position eIG + 8 and end at eIG + eIW + 8 - 1. + + if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits + start at bit position eIG + 8 and end at eIG + eIW - 1. + + if the interleave mask is insufficient to cover the required interleave + bits, the target cannot be attached to the region. + +Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders") +Signed-off-by: Yao Xingtao +Reviewed-by: Dan Williams +Reviewed-by: Jonathan Cameron +Link: https://patch.msgid.link/20240614084755.59503-2-yaoxt.fnst@fujitsu.com +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/hdm.c | 13 ++++++ + drivers/cxl/core/region.c | 82 ++++++++++++++++++++++++++++++++++++ + drivers/cxl/cxl.h | 2 + + drivers/cxl/cxlmem.h | 10 +++++ + tools/testing/cxl/test/cxl.c | 4 ++ + 5 files changed, 111 insertions(+) + +diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c +index 7d97790b893d7..e01c16fdc7575 100644 +--- a/drivers/cxl/core/hdm.c ++++ b/drivers/cxl/core/hdm.c +@@ -52,6 +52,14 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port) + struct cxl_dport *dport = NULL; + int single_port_map[1]; + unsigned long index; ++ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); ++ ++ /* ++ * Capability checks are moot for passthrough decoders, support ++ * any and all possibilities. ++ */ ++ cxlhdm->interleave_mask = ~0U; ++ cxlhdm->iw_cap_mask = ~0UL; + + cxlsd = cxl_switch_decoder_alloc(port, 1); + if (IS_ERR(cxlsd)) +@@ -79,6 +87,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) + cxlhdm->interleave_mask |= GENMASK(11, 8); + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap)) + cxlhdm->interleave_mask |= GENMASK(14, 12); ++ cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8); ++ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap)) ++ cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12); ++ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap)) ++ cxlhdm->iw_cap_mask |= BIT(16); + } + + static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index a083893c0afe0..a600feb8a4ed5 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -1101,6 +1101,26 @@ static int cxl_port_attach_region(struct cxl_port *port, + } + cxld = cxl_rr->decoder; + ++ /* ++ * the number of targets should not exceed the target_count ++ * of the decoder ++ */ ++ if (is_switch_decoder(&cxld->dev)) { ++ struct cxl_switch_decoder *cxlsd; ++ ++ cxlsd = to_cxl_switch_decoder(&cxld->dev); ++ if (cxl_rr->nr_targets > cxlsd->nr_targets) { ++ dev_dbg(&cxlr->dev, ++ "%s:%s %s add: %s:%s @ %d overflows targets: %d\n", ++ dev_name(port->uport_dev), dev_name(&port->dev), ++ dev_name(&cxld->dev), dev_name(&cxlmd->dev), ++ dev_name(&cxled->cxld.dev), pos, ++ cxlsd->nr_targets); ++ rc = -ENXIO; ++ goto out_erase; ++ } ++ } ++ + rc = cxl_rr_ep_add(cxl_rr, cxled); + if (rc) { + dev_dbg(&cxlr->dev, +@@ -1210,6 +1230,50 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, + return 0; + } + ++static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig) ++{ ++ struct cxl_port *port = to_cxl_port(cxld->dev.parent); ++ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); ++ unsigned int interleave_mask; ++ u8 eiw; ++ u16 eig; ++ int high_pos, low_pos; ++ ++ if (!test_bit(iw, &cxlhdm->iw_cap_mask)) ++ return -ENXIO; ++ /* ++ * Per CXL specification r3.1(8.2.4.20.13 Decoder Protection), ++ * if eiw < 8: ++ * DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + 8 + eiw] ++ * DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0] ++ * ++ * when the eiw is 0, all the bits of HPAOFFSET[51: 0] are used, the ++ * interleave bits are none. ++ * ++ * if eiw >= 8: ++ * DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + eiw] / 3 ++ * DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0] ++ * ++ * when the eiw is 8, all the bits of HPAOFFSET[51: 0] are used, the ++ * interleave bits are none. ++ */ ++ ways_to_eiw(iw, &eiw); ++ if (eiw == 0 || eiw == 8) ++ return 0; ++ ++ granularity_to_eig(ig, &eig); ++ if (eiw > 8) ++ high_pos = eiw + eig - 1; ++ else ++ high_pos = eiw + eig + 7; ++ low_pos = eig + 8; ++ interleave_mask = GENMASK(high_pos, low_pos); ++ if (interleave_mask & ~cxlhdm->interleave_mask) ++ return -ENXIO; ++ ++ return 0; ++} ++ + static int cxl_port_setup_targets(struct cxl_port *port, + struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled) +@@ -1360,6 +1424,15 @@ static int cxl_port_setup_targets(struct cxl_port *port, + return -ENXIO; + } + } else { ++ rc = check_interleave_cap(cxld, iw, ig); ++ if (rc) { ++ dev_dbg(&cxlr->dev, ++ "%s:%s iw: %d ig: %d is not supported\n", ++ dev_name(port->uport_dev), ++ dev_name(&port->dev), iw, ig); ++ return rc; ++ } ++ + cxld->interleave_ways = iw; + cxld->interleave_granularity = ig; + cxld->hpa_range = (struct range) { +@@ -1796,6 +1869,15 @@ static int cxl_region_attach(struct cxl_region *cxlr, + struct cxl_dport *dport; + int rc = -ENXIO; + ++ rc = check_interleave_cap(&cxled->cxld, p->interleave_ways, ++ p->interleave_granularity); ++ if (rc) { ++ dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n", ++ dev_name(&cxled->cxld.dev), p->interleave_ways, ++ p->interleave_granularity); ++ return rc; ++ } ++ + if (cxled->mode != cxlr->mode) { + dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n", + dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode); +diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h +index 2b82dcaf70aa6..6f9270f2faf96 100644 +--- a/drivers/cxl/cxl.h ++++ b/drivers/cxl/cxl.h +@@ -45,6 +45,8 @@ + #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) + #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) + #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) ++#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) ++#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) + #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 + #define CXL_HDM_DECODER_ENABLE BIT(1) + #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) +diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h +index 36cee9c30cebd..07e65a7605f3e 100644 +--- a/drivers/cxl/cxlmem.h ++++ b/drivers/cxl/cxlmem.h +@@ -848,11 +848,21 @@ static inline void cxl_mem_active_dec(void) + + int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); + ++/** ++ * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities ++ * @regs: mapped registers, see devm_cxl_setup_hdm() ++ * @decoder_count: number of decoders for this port ++ * @target_count: for switch decoders, max downstream port targets ++ * @interleave_mask: interleave granularity capability, see check_interleave_cap() ++ * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() ++ * @port: mapped cxl_port, see devm_cxl_setup_hdm() ++ */ + struct cxl_hdm { + struct cxl_component_regs regs; + unsigned int decoder_count; + unsigned int target_count; + unsigned int interleave_mask; ++ unsigned long iw_cap_mask; + struct cxl_port *port; + }; + +diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c +index 3482248aa3442..90d5afd52dd06 100644 +--- a/tools/testing/cxl/test/cxl.c ++++ b/tools/testing/cxl/test/cxl.c +@@ -630,11 +630,15 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port, + struct cxl_endpoint_dvsec_info *info) + { + struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL); ++ struct device *dev = &port->dev; + + if (!cxlhdm) + return ERR_PTR(-ENOMEM); + + cxlhdm->port = port; ++ cxlhdm->interleave_mask = ~0U; ++ cxlhdm->iw_cap_mask = ~0UL; ++ dev_set_drvdata(dev, cxlhdm); + return cxlhdm; + } + +-- +2.43.0 + diff --git a/queue-6.9/cxl-region-convert-cxl_pmem_region_alloc-to-scope-ba.patch b/queue-6.9/cxl-region-convert-cxl_pmem_region_alloc-to-scope-ba.patch new file mode 100644 index 00000000000..cbbe19476cc --- /dev/null +++ b/queue-6.9/cxl-region-convert-cxl_pmem_region_alloc-to-scope-ba.patch @@ -0,0 +1,129 @@ +From 4512fababe29c692c143ee5936e130fda19d254b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Apr 2024 14:59:00 -0700 +Subject: cxl/region: Convert cxl_pmem_region_alloc to scope-based resource + management + +From: Dan Williams + +[ Upstream commit d357dd8ad2f154376e5cb930284e7bf4fe21ffaa ] + +A recent bugfix to cxl_pmem_region_alloc() to fix an +error-unwind-memleak [1], highlighted a use case for scope-based resource +management. + +Delete the goto for releasing @cxl_region_rwsem, and return error codes +directly from error condition paths. + +The caller, devm_cxl_add_pmem_region(), is no longer given @cxlr_pmem +directly it must retrieve it from @cxlr->cxlr_pmem. This retrieval from +@cxlr was already in place for @cxlr->cxl_nvb, and converting +cxl_pmem_region_alloc() to return an int makes it less awkward to handle +no_free_ptr(). + +Cc: Li Zhijian +Reported-by: Jonathan Cameron +Closes: http://lore.kernel.org/r/20240430174540.000039ce@Huawei.com +Link: http://lore.kernel.org/r/20240428030748.318985-1-lizhijian@fujitsu.com +Signed-off-by: Dan Williams +Reviewed-by: Jonathan Cameron +Link: https://lore.kernel.org/r/171451430965.1147997.15782562063090960666.stgit@dwillia2-xfh.jf.intel.com +Signed-off-by: Dave Jiang +Stable-dep-of: 84ec985944ef ("cxl/mem: Fix no cxl_nvd during pmem region auto-assembling") +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/region.c | 43 ++++++++++++++++----------------------- + 1 file changed, 17 insertions(+), 26 deletions(-) + +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index 18b95149640b6..bcb30e04e0963 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2681,26 +2681,21 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port) + + static struct lock_class_key cxl_pmem_region_key; + +-static struct cxl_pmem_region *cxl_pmem_region_alloc(struct cxl_region *cxlr) ++static int cxl_pmem_region_alloc(struct cxl_region *cxlr) + { + struct cxl_region_params *p = &cxlr->params; + struct cxl_nvdimm_bridge *cxl_nvb; +- struct cxl_pmem_region *cxlr_pmem; + struct device *dev; + int i; + +- down_read(&cxl_region_rwsem); +- if (p->state != CXL_CONFIG_COMMIT) { +- cxlr_pmem = ERR_PTR(-ENXIO); +- goto out; +- } ++ guard(rwsem_read)(&cxl_region_rwsem); ++ if (p->state != CXL_CONFIG_COMMIT) ++ return -ENXIO; + +- cxlr_pmem = kzalloc(struct_size(cxlr_pmem, mapping, p->nr_targets), +- GFP_KERNEL); +- if (!cxlr_pmem) { +- cxlr_pmem = ERR_PTR(-ENOMEM); +- goto out; +- } ++ struct cxl_pmem_region *cxlr_pmem __free(kfree) = ++ kzalloc(struct_size(cxlr_pmem, mapping, p->nr_targets), GFP_KERNEL); ++ if (!cxlr_pmem) ++ return -ENOMEM; + + cxlr_pmem->hpa_range.start = p->res->start; + cxlr_pmem->hpa_range.end = p->res->end; +@@ -2718,11 +2713,8 @@ static struct cxl_pmem_region *cxl_pmem_region_alloc(struct cxl_region *cxlr) + */ + if (i == 0) { + cxl_nvb = cxl_find_nvdimm_bridge(cxlmd); +- if (!cxl_nvb) { +- kfree(cxlr_pmem); +- cxlr_pmem = ERR_PTR(-ENODEV); +- goto out; +- } ++ if (!cxl_nvb) ++ return -ENODEV; + cxlr->cxl_nvb = cxl_nvb; + } + m->cxlmd = cxlmd; +@@ -2733,18 +2725,16 @@ static struct cxl_pmem_region *cxl_pmem_region_alloc(struct cxl_region *cxlr) + } + + dev = &cxlr_pmem->dev; +- cxlr_pmem->cxlr = cxlr; +- cxlr->cxlr_pmem = cxlr_pmem; + device_initialize(dev); + lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); + device_set_pm_not_required(dev); + dev->parent = &cxlr->dev; + dev->bus = &cxl_bus_type; + dev->type = &cxl_pmem_region_type; +-out: +- up_read(&cxl_region_rwsem); ++ cxlr_pmem->cxlr = cxlr; ++ cxlr->cxlr_pmem = no_free_ptr(cxlr_pmem); + +- return cxlr_pmem; ++ return 0; + } + + static void cxl_dax_region_release(struct device *dev) +@@ -2861,9 +2851,10 @@ static int devm_cxl_add_pmem_region(struct cxl_region *cxlr) + struct device *dev; + int rc; + +- cxlr_pmem = cxl_pmem_region_alloc(cxlr); +- if (IS_ERR(cxlr_pmem)) +- return PTR_ERR(cxlr_pmem); ++ rc = cxl_pmem_region_alloc(cxlr); ++ if (rc) ++ return rc; ++ cxlr_pmem = cxlr->cxlr_pmem; + cxl_nvb = cxlr->cxl_nvb; + + dev = &cxlr_pmem->dev; +-- +2.43.0 + diff --git a/queue-6.9/cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch b/queue-6.9/cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch new file mode 100644 index 00000000000..9c0278b18ca --- /dev/null +++ b/queue-6.9/cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch @@ -0,0 +1,158 @@ +From 295bd15fe313c91e159d0646ab15211f40b6e605 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Apr 2024 10:28:04 -0700 +Subject: cxl/region: Move cxl_dpa_to_region() work to the region driver + +From: Alison Schofield + +[ Upstream commit b98d042698a32518c93e47730e9ad86b387a9c21 ] + +This helper belongs in the region driver as it is only useful +with CONFIG_CXL_REGION. Add a stub in core.h for when the region +driver is not built. + +Signed-off-by: Alison Schofield +Reviewed-by: Jonathan Cameron +Reviewed-by: Ira Weiny +Link: https://lore.kernel.org/r/05e30f788d62b3dd398aff2d2ea50a6aaa7c3313.1714496730.git.alison.schofield@intel.com +Signed-off-by: Dave Jiang +Stable-dep-of: 285f2a088414 ("cxl/region: Avoid null pointer dereference in region lookup") +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/core.h | 7 +++++++ + drivers/cxl/core/memdev.c | 44 --------------------------------------- + drivers/cxl/core/region.c | 44 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 51 insertions(+), 44 deletions(-) + +diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h +index bc5a95665aa0a..87008505f8a9e 100644 +--- a/drivers/cxl/core/core.h ++++ b/drivers/cxl/core/core.h +@@ -27,7 +27,14 @@ void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled); + int cxl_region_init(void); + void cxl_region_exit(void); + int cxl_get_poison_by_endpoint(struct cxl_port *port); ++struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); ++ + #else ++static inline ++struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) ++{ ++ return NULL; ++} + static inline int cxl_get_poison_by_endpoint(struct cxl_port *port) + { + return 0; +diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c +index d4e259f3a7e91..0277726afd049 100644 +--- a/drivers/cxl/core/memdev.c ++++ b/drivers/cxl/core/memdev.c +@@ -251,50 +251,6 @@ int cxl_trigger_poison_list(struct cxl_memdev *cxlmd) + } + EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL); + +-struct cxl_dpa_to_region_context { +- struct cxl_region *cxlr; +- u64 dpa; +-}; +- +-static int __cxl_dpa_to_region(struct device *dev, void *arg) +-{ +- struct cxl_dpa_to_region_context *ctx = arg; +- struct cxl_endpoint_decoder *cxled; +- u64 dpa = ctx->dpa; +- +- if (!is_endpoint_decoder(dev)) +- return 0; +- +- cxled = to_cxl_endpoint_decoder(dev); +- if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) +- return 0; +- +- if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) +- return 0; +- +- dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, +- dev_name(&cxled->cxld.region->dev)); +- +- ctx->cxlr = cxled->cxld.region; +- +- return 1; +-} +- +-static struct cxl_region *cxl_dpa_to_region(struct cxl_memdev *cxlmd, u64 dpa) +-{ +- struct cxl_dpa_to_region_context ctx; +- struct cxl_port *port; +- +- ctx = (struct cxl_dpa_to_region_context) { +- .dpa = dpa, +- }; +- port = cxlmd->endpoint; +- if (port && is_cxl_endpoint(port) && cxl_num_decoders_committed(port)) +- device_for_each_child(&port->dev, &ctx, __cxl_dpa_to_region); +- +- return ctx.cxlr; +-} +- + static int cxl_validate_poison_dpa(struct cxl_memdev *cxlmd, u64 dpa) + { + struct cxl_dev_state *cxlds = cxlmd->cxlds; +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index 857afc8b72ff1..52061edf4bd97 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2679,6 +2679,50 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port) + return rc; + } + ++struct cxl_dpa_to_region_context { ++ struct cxl_region *cxlr; ++ u64 dpa; ++}; ++ ++static int __cxl_dpa_to_region(struct device *dev, void *arg) ++{ ++ struct cxl_dpa_to_region_context *ctx = arg; ++ struct cxl_endpoint_decoder *cxled; ++ u64 dpa = ctx->dpa; ++ ++ if (!is_endpoint_decoder(dev)) ++ return 0; ++ ++ cxled = to_cxl_endpoint_decoder(dev); ++ if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) ++ return 0; ++ ++ if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) ++ return 0; ++ ++ dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, ++ dev_name(&cxled->cxld.region->dev)); ++ ++ ctx->cxlr = cxled->cxld.region; ++ ++ return 1; ++} ++ ++struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) ++{ ++ struct cxl_dpa_to_region_context ctx; ++ struct cxl_port *port; ++ ++ ctx = (struct cxl_dpa_to_region_context) { ++ .dpa = dpa, ++ }; ++ port = cxlmd->endpoint; ++ if (port && is_cxl_endpoint(port) && cxl_num_decoders_committed(port)) ++ device_for_each_child(&port->dev, &ctx, __cxl_dpa_to_region); ++ ++ return ctx.cxlr; ++} ++ + static struct lock_class_key cxl_pmem_region_key; + + static int cxl_pmem_region_alloc(struct cxl_region *cxlr) +-- +2.43.0 + diff --git a/queue-6.9/netfs-fix-netfs_page_mkwrite-to-check-folio-mapping-.patch b/queue-6.9/netfs-fix-netfs_page_mkwrite-to-check-folio-mapping-.patch new file mode 100644 index 00000000000..c6cb1be6a82 --- /dev/null +++ b/queue-6.9/netfs-fix-netfs_page_mkwrite-to-check-folio-mapping-.patch @@ -0,0 +1,93 @@ +From 395a2e93407160e835a34dd040cb2e8fcf569814 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jun 2024 13:29:06 +0100 +Subject: netfs: Fix netfs_page_mkwrite() to check folio->mapping is valid + +From: David Howells + +[ Upstream commit a81c98bfa40c11f8ea79b5a9b3f5fda73bfbb4d2 ] + +Fix netfs_page_mkwrite() to check that folio->mapping is valid once it has +taken the folio lock (as filemap_page_mkwrite() does). Without this, +generic/247 occasionally oopses with something like the following: + + BUG: kernel NULL pointer dereference, address: 0000000000000000 + #PF: supervisor read access in kernel mode + #PF: error_code(0x0000) - not-present page + + RIP: 0010:trace_event_raw_event_netfs_folio+0x61/0xc0 + ... + Call Trace: + + ? __die_body+0x1a/0x60 + ? page_fault_oops+0x6e/0xa0 + ? exc_page_fault+0xc2/0xe0 + ? asm_exc_page_fault+0x22/0x30 + ? trace_event_raw_event_netfs_folio+0x61/0xc0 + trace_netfs_folio+0x39/0x40 + netfs_page_mkwrite+0x14c/0x1d0 + do_page_mkwrite+0x50/0x90 + do_pte_missing+0x184/0x200 + __handle_mm_fault+0x42d/0x500 + handle_mm_fault+0x121/0x1f0 + do_user_addr_fault+0x23e/0x3c0 + exc_page_fault+0xc2/0xe0 + asm_exc_page_fault+0x22/0x30 + +This is due to the invalidate_inode_pages2_range() issued at the end of the +DIO write interfering with the mmap'd writes. + +Fixes: 102a7e2c598c ("netfs: Allow buffered shared-writeable mmap through netfs_page_mkwrite()") +Signed-off-by: David Howells +Link: https://lore.kernel.org/r/780211.1719318546@warthog.procyon.org.uk +Reviewed-by: Jeff Layton +cc: Matthew Wilcox +cc: Jeff Layton +cc: netfs@lists.linux.dev +cc: v9fs@lists.linux.dev +cc: linux-afs@lists.infradead.org +cc: linux-cifs@vger.kernel.org +cc: linux-mm@kvack.org +cc: linux-fsdevel@vger.kernel.org +Signed-off-by: Christian Brauner +Signed-off-by: Sasha Levin +--- + fs/netfs/buffered_write.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/fs/netfs/buffered_write.c b/fs/netfs/buffered_write.c +index 912ad0a1df021..72e4fa233c526 100644 +--- a/fs/netfs/buffered_write.c ++++ b/fs/netfs/buffered_write.c +@@ -507,6 +507,7 @@ vm_fault_t netfs_page_mkwrite(struct vm_fault *vmf, struct netfs_group *netfs_gr + { + struct folio *folio = page_folio(vmf->page); + struct file *file = vmf->vma->vm_file; ++ struct address_space *mapping = file->f_mapping; + struct inode *inode = file_inode(file); + vm_fault_t ret = VM_FAULT_RETRY; + int err; +@@ -520,6 +521,11 @@ vm_fault_t netfs_page_mkwrite(struct vm_fault *vmf, struct netfs_group *netfs_gr + + if (folio_lock_killable(folio) < 0) + goto out; ++ if (folio->mapping != mapping) { ++ folio_unlock(folio); ++ ret = VM_FAULT_NOPAGE; ++ goto out; ++ } + + /* Can we see a streaming write here? */ + if (WARN_ON(!folio_test_uptodate(folio))) { +@@ -529,7 +535,7 @@ vm_fault_t netfs_page_mkwrite(struct vm_fault *vmf, struct netfs_group *netfs_gr + + if (netfs_folio_group(folio) != netfs_group) { + folio_unlock(folio); +- err = filemap_fdatawait_range(inode->i_mapping, ++ err = filemap_fdatawait_range(mapping, + folio_pos(folio), + folio_pos(folio) + folio_size(folio)); + switch (err) { +-- +2.43.0 + diff --git a/queue-6.9/netfs-fix-netfs_page_mkwrite-to-flush-conflicting-da.patch b/queue-6.9/netfs-fix-netfs_page_mkwrite-to-flush-conflicting-da.patch new file mode 100644 index 00000000000..039fb6d2584 --- /dev/null +++ b/queue-6.9/netfs-fix-netfs_page_mkwrite-to-flush-conflicting-da.patch @@ -0,0 +1,49 @@ +From 2872b117b9a2d5c218d2cd1031d8e4c4c7843746 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 24 Jun 2024 12:24:03 +0100 +Subject: netfs: Fix netfs_page_mkwrite() to flush conflicting data, not wait + +From: David Howells + +[ Upstream commit 9d66154f73b7c7007c3be1113dfb50b99b791f8f ] + +Fix netfs_page_mkwrite() to use filemap_fdatawrite_range(), not +filemap_fdatawait_range() to flush conflicting data. + +Fixes: 102a7e2c598c ("netfs: Allow buffered shared-writeable mmap through netfs_page_mkwrite()") +Signed-off-by: David Howells +Link: https://lore.kernel.org/r/614300.1719228243@warthog.procyon.org.uk +cc: Matthew Wilcox +cc: Jeff Layton +cc: netfs@lists.linux.dev +cc: v9fs@lists.linux.dev +cc: linux-afs@lists.infradead.org +cc: linux-cifs@vger.kernel.org +cc: linux-mm@kvack.org +cc: linux-fsdevel@vger.kernel.org +Signed-off-by: Christian Brauner +Signed-off-by: Sasha Levin +--- + fs/netfs/buffered_write.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/fs/netfs/buffered_write.c b/fs/netfs/buffered_write.c +index 72e4fa233c526..d2ce0849bb53d 100644 +--- a/fs/netfs/buffered_write.c ++++ b/fs/netfs/buffered_write.c +@@ -535,9 +535,9 @@ vm_fault_t netfs_page_mkwrite(struct vm_fault *vmf, struct netfs_group *netfs_gr + + if (netfs_folio_group(folio) != netfs_group) { + folio_unlock(folio); +- err = filemap_fdatawait_range(mapping, +- folio_pos(folio), +- folio_pos(folio) + folio_size(folio)); ++ err = filemap_fdatawrite_range(mapping, ++ folio_pos(folio), ++ folio_pos(folio) + folio_size(folio)); + switch (err) { + case 0: + ret = VM_FAULT_RETRY; +-- +2.43.0 + diff --git a/queue-6.9/reset-gpio-fix-missing-gpiolib-dependency-for-gpio-r.patch b/queue-6.9/reset-gpio-fix-missing-gpiolib-dependency-for-gpio-r.patch new file mode 100644 index 00000000000..8460da9e07e --- /dev/null +++ b/queue-6.9/reset-gpio-fix-missing-gpiolib-dependency-for-gpio-r.patch @@ -0,0 +1,43 @@ +From d6bad4dfdd1b9a592d4707f77ff4832a1d311e01 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 25 Mar 2024 16:51:03 +0000 +Subject: reset: gpio: Fix missing gpiolib dependency for GPIO reset controller + +From: Mark Brown + +[ Upstream commit 01f6a84c7a3eaabafd787608d630db31c6904f5c ] + +The GPIO reset controller uses gpiolib but there is no Kconfig +dependency reflecting this fact, add one. + +With the addition of the controller to the arm64 defconfig this is +causing build breaks for arm64 virtconfig in -next: + +aarch64-linux-gnu-ld: drivers/reset/core.o: in function `__reset_add_reset_gpio_lookup': +/build/stage/linux/drivers/reset/core.c:861:(.text+0xccc): undefined reference to `gpio_device_find_by_fwnode' + +Fixes: cee544a40e44 ("reset: gpio: Add GPIO-based reset controller") +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Mark Brown +Link: https://lore.kernel.org/r/20240325-reset-gpiolib-deps-v2-1-3ed2517f5f53@kernel.org +Signed-off-by: Philipp Zabel +Signed-off-by: Sasha Levin +--- + drivers/reset/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 85b27c42cf65b..f426b4c391796 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -68,6 +68,7 @@ config RESET_BRCMSTB_RESCAL + + config RESET_GPIO + tristate "GPIO reset controller" ++ depends on GPIOLIB + help + This enables a generic reset controller for resets attached via + GPIOs. Typically for OF platforms this driver expects "reset-gpios" +-- +2.43.0 + diff --git a/queue-6.9/revert-arm64-dts-rockchip-remove-redundant-cd-gpios-.patch b/queue-6.9/revert-arm64-dts-rockchip-remove-redundant-cd-gpios-.patch new file mode 100644 index 00000000000..4865ff72c3e --- /dev/null +++ b/queue-6.9/revert-arm64-dts-rockchip-remove-redundant-cd-gpios-.patch @@ -0,0 +1,85 @@ +From f00446f3e409fe8f338ddcc9e06976a850928df3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Jun 2024 09:17:57 +0900 +Subject: Revert "arm64: dts: rockchip: remove redundant cd-gpios from rk3588 + sdmmc nodes" + +From: FUKAUMI Naoki + +[ Upstream commit b56aed4a613e2d2cb3bfe05fd222dbf480f6b5d8 ] + +This reverts commit d859ad305ed19d9a77d8c8ecd22459b73da36ba6. + +Inserting and removing microSD card is not detected since above commit. +Reverting it fixes this problem. + +This is probably the same thing as 5 years ago on rk3399 +https://lore.kernel.org/all/0608599d485117a9d99f5fb274fbb1b55f6ba9f7.1547466003.git.robin.murphy@arm.com/ + +So we'll go back to cd-gpios for now. + +this patch is tested on Radxa ROCK 5A and 5B. + +Fixes: d859ad305ed1 ("arm64: dts: rockchip: remove redundant cd-gpios from rk3588 sdmmc nodes") +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240613001757.1350-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 + + arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 + + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 + + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 + + 4 files changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +index 1a604429fb266..e74871491ef56 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +@@ -444,6 +444,7 @@ + &sdmmc { + bus-width = <4>; + cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +index 22bbfbe729c11..b6628889b707e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +@@ -429,6 +429,7 @@ + &sdmmc { + bus-width = <4>; + cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +index 1fe8b2a0ed75e..9b7bf6cec8bd1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -378,6 +378,7 @@ + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 00afb90d4eb10..2002fd0221fa3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -366,6 +366,7 @@ + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; +-- +2.43.0 + diff --git a/queue-6.9/series b/queue-6.9/series index f7012521fc6..f58d1314938 100644 --- a/queue-6.9/series +++ b/queue-6.9/series @@ -202,3 +202,21 @@ revert-net-sfp-enhance-quirk-for-fibrestore-2.5g-copper-sfp-module.patch mm-page_alloc-separate-thp-pcp-into-movable-and-non-movable-categories.patch pwm-stm32-fix-calculation-of-prescaler.patch pwm-stm32-fix-error-message-to-not-describe-the-previous-error-path.patch +arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch +arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch +arm64-dts-rockchip-set-correct-pwm0-pinctrl-on-rk358.patch +arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch +arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch +revert-arm64-dts-rockchip-remove-redundant-cd-gpios-.patch +arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch +cxl-region-convert-cxl_pmem_region_alloc-to-scope-ba.patch +cxl-mem-fix-no-cxl_nvd-during-pmem-region-auto-assem.patch +arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch +reset-gpio-fix-missing-gpiolib-dependency-for-gpio-r.patch +arm64-dts-rockchip-fix-the-i2c-address-of-es8316-on-.patch +arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch +cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch +cxl-region-avoid-null-pointer-dereference-in-region-.patch +cxl-region-check-interleave-capability.patch +netfs-fix-netfs_page_mkwrite-to-check-folio-mapping-.patch +netfs-fix-netfs_page_mkwrite-to-flush-conflicting-da.patch