From: Greg Kroah-Hartman Date: Thu, 5 Jul 2018 15:59:26 +0000 (+0200) Subject: 4.17-stable patches X-Git-Tag: v4.14.54~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7f581ea83251b849c89ff36188526f9809cb7011;p=thirdparty%2Fkernel%2Fstable-queue.git 4.17-stable patches added patches: drm-amd-display-clear-connector-s-edid-pointer.patch drm-amd-display-release-spinlock-before-committing-updates-to-stream.patch drm-amdgpu-count-disabled-crtcs-in-commit-tail-earlier.patch drm-amdgpu-don-t-default-to-dc-support-for-kaveri-and-older.patch drm-amdgpu-gpu-vs-cpu-page-size-fixes-in-amdgpu_vm_bo_split_mapping.patch drm-amdgpu-make-amdgpu_vram_mgr_bo_invisible_size-always-accurate.patch drm-amdgpu-refactor-amdgpu_vram_mgr_bo_invisible_size-helper.patch drm-amdgpu-update-pin_size-values-before-unpinning-bo.patch drm-amdgpu-use-kvmalloc_array-for-allocating-vram-manager-nodes-array.patch drm-atmel-hlcdc-check-stride-values-in-the-first-plane.patch drm-i915-allow-dblscan-user-modes-with-edp-lvds-dsi.patch drm-i915-disallow-interlaced-modes-on-g4x-dp-outputs.patch drm-i915-dp-send-dpcd-on-for-mst-before-phy_up.patch drm-i915-enable-provoking-vertex-fix-on-gen9-systems.patch drm-i915-fix-pipestat-irq-ack-on-i965-g4x.patch drm-i915-turn-off-g4x-dp-port-in-.post_disable.patch drm-qxl-call-qxl_bo_unref-outside-atomic-context.patch drm-sti-depend-on-of-rather-than-selecting-it.patch revert-drm-sun4i-handle-drm_bus_flag_pixdata_-edge.patch --- diff --git a/queue-4.17/drm-amd-display-clear-connector-s-edid-pointer.patch b/queue-4.17/drm-amd-display-clear-connector-s-edid-pointer.patch new file mode 100644 index 00000000000..5cda24fa534 --- /dev/null +++ b/queue-4.17/drm-amd-display-clear-connector-s-edid-pointer.patch @@ -0,0 +1,34 @@ +From 5326c4525d1b2d5f1519268dd305e19c9bd4ef56 Mon Sep 17 00:00:00 2001 +From: Mikita Lipski +Date: Fri, 27 Apr 2018 09:09:52 -0400 +Subject: drm/amd/display: Clear connector's edid pointer + +From: Mikita Lipski + +commit 5326c4525d1b2d5f1519268dd305e19c9bd4ef56 upstream. + +Clear connector's edid pointer on coonnector update, when unplugging +the display. + +Fix poison EDID when hotplugging on previously used connector. + +Signed-off-by: Mikita Lipski +Reviewed-by: Harry Wentland +Cc: stable@vger.kernel.org +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -928,6 +928,7 @@ amdgpu_dm_update_connector_after_detect( + drm_mode_connector_update_edid_property(connector, NULL); + aconnector->num_modes = 0; + aconnector->dc_sink = NULL; ++ aconnector->edid = NULL; + } + + mutex_unlock(&dev->mode_config.mutex); diff --git a/queue-4.17/drm-amd-display-release-spinlock-before-committing-updates-to-stream.patch b/queue-4.17/drm-amd-display-release-spinlock-before-committing-updates-to-stream.patch new file mode 100644 index 00000000000..6c842c94bf5 --- /dev/null +++ b/queue-4.17/drm-amd-display-release-spinlock-before-committing-updates-to-stream.patch @@ -0,0 +1,60 @@ +From 4de9f38bb2cce3a4821ffb8a83d6b08f6e37d905 Mon Sep 17 00:00:00 2001 +From: Shirish S +Date: Tue, 26 Jun 2018 09:32:39 +0530 +Subject: drm/amd/display: release spinlock before committing updates to stream +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Shirish S + +commit 4de9f38bb2cce3a4821ffb8a83d6b08f6e37d905 upstream. + +Currently, amdgpu_do_flip() spinlocks crtc->dev->event_lock and +releases it only after committing updates to the stream. + +dc_commit_updates_for_stream() should be moved out of +spinlock for the below reasons: + +1. event_lock is supposed to protect access to acrct->pflip_status _only_ +2. dc_commit_updates_for_stream() has potential sleep's + and also its not appropriate to be in an atomic state + for such long sequences of code. + +Signed-off-by: Shirish S +Suggested-by: Andrey Grodzovsky +Reviewed-by: Michel Dänzer +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -3967,10 +3967,11 @@ static void amdgpu_dm_do_flip(struct drm + if (acrtc->base.state->event) + prepare_flip_isr(acrtc); + ++ spin_unlock_irqrestore(&crtc->dev->event_lock, flags); ++ + surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0]; + surface_updates->flip_addr = &addr; + +- + dc_commit_updates_for_stream(adev->dm.dc, + surface_updates, + 1, +@@ -3983,9 +3984,6 @@ static void amdgpu_dm_do_flip(struct drm + __func__, + addr.address.grph.addr.high_part, + addr.address.grph.addr.low_part); +- +- +- spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + } + + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, diff --git a/queue-4.17/drm-amdgpu-count-disabled-crtcs-in-commit-tail-earlier.patch b/queue-4.17/drm-amdgpu-count-disabled-crtcs-in-commit-tail-earlier.patch new file mode 100644 index 00000000000..5284b10973f --- /dev/null +++ b/queue-4.17/drm-amdgpu-count-disabled-crtcs-in-commit-tail-earlier.patch @@ -0,0 +1,198 @@ +From fe2a19652918a5247418aed48a247414a5e45fe2 Mon Sep 17 00:00:00 2001 +From: Lyude Paul +Date: Thu, 21 Jun 2018 16:48:26 -0400 +Subject: drm/amdgpu: Count disabled CRTCs in commit tail earlier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Lyude Paul + +commit fe2a19652918a5247418aed48a247414a5e45fe2 upstream. + +This fixes a regression I accidentally reduced that was picked up by +kasan, where we were checking the CRTC atomic states after DRM's helpers +had already freed them. Example: + +================================================================== +BUG: KASAN: use-after-free in amdgpu_dm_atomic_commit_tail.cold.50+0x13d/0x15a [amdgpu] +Read of size 1 at addr ffff8803a697b071 by task kworker/u16:0/7 + +CPU: 7 PID: 7 Comm: kworker/u16:0 Tainted: G O 4.18.0-rc1Lyude-Upstream+ #1 +Hardware name: HP HP ZBook 15 G4/8275, BIOS P70 Ver. 01.21 05/02/2018 +Workqueue: events_unbound commit_work [drm_kms_helper] +Call Trace: + dump_stack+0xc1/0x169 + ? dump_stack_print_info.cold.1+0x42/0x42 + ? kmsg_dump_rewind_nolock+0xd9/0xd9 + ? printk+0x9f/0xc5 + ? amdgpu_dm_atomic_commit_tail.cold.50+0x13d/0x15a [amdgpu] + print_address_description+0x6c/0x23c + ? amdgpu_dm_atomic_commit_tail.cold.50+0x13d/0x15a [amdgpu] + kasan_report.cold.6+0x241/0x2fd + amdgpu_dm_atomic_commit_tail.cold.50+0x13d/0x15a [amdgpu] + ? commit_planes_to_stream.constprop.45+0x13b0/0x13b0 [amdgpu] + ? cpu_load_update_active+0x290/0x290 + ? finish_task_switch+0x2bd/0x840 + ? __switch_to_asm+0x34/0x70 + ? read_word_at_a_time+0xe/0x20 + ? strscpy+0x14b/0x460 + ? drm_atomic_helper_wait_for_dependencies+0x47d/0x7e0 [drm_kms_helper] + commit_tail+0x96/0xe0 [drm_kms_helper] + process_one_work+0x88a/0x1360 + ? create_worker+0x540/0x540 + ? __sched_text_start+0x8/0x8 + ? move_queued_task+0x760/0x760 + ? call_rcu_sched+0x20/0x20 + ? vsnprintf+0xcda/0x1350 + ? wait_woken+0x1c0/0x1c0 + ? mutex_unlock+0x1d/0x40 + ? init_timer_key+0x190/0x230 + ? schedule+0xea/0x390 + ? __schedule+0x1ea0/0x1ea0 + ? need_to_create_worker+0xe4/0x210 + ? init_worker_pool+0x700/0x700 + ? try_to_del_timer_sync+0xbf/0x110 + ? del_timer+0x120/0x120 + ? __mutex_lock_slowpath+0x10/0x10 + worker_thread+0x196/0x11f0 + ? flush_rcu_work+0x50/0x50 + ? __switch_to_asm+0x34/0x70 + ? __switch_to_asm+0x34/0x70 + ? __switch_to_asm+0x40/0x70 + ? __switch_to_asm+0x34/0x70 + ? __switch_to_asm+0x40/0x70 + ? __switch_to_asm+0x34/0x70 + ? __switch_to_asm+0x40/0x70 + ? __schedule+0x7d6/0x1ea0 + ? migrate_swap_stop+0x850/0x880 + ? __sched_text_start+0x8/0x8 + ? save_stack+0x8c/0xb0 + ? kasan_kmalloc+0xbf/0xe0 + ? kmem_cache_alloc_trace+0xe4/0x190 + ? kthread+0x98/0x390 + ? ret_from_fork+0x35/0x40 + ? ret_from_fork+0x35/0x40 + ? deactivate_slab.isra.67+0x3c4/0x5c0 + ? kthread+0x98/0x390 + ? kthread+0x98/0x390 + ? set_track+0x76/0x120 + ? schedule+0xea/0x390 + ? __schedule+0x1ea0/0x1ea0 + ? wait_woken+0x1c0/0x1c0 + ? kasan_unpoison_shadow+0x30/0x40 + ? parse_args.cold.15+0x17a/0x17a + ? flush_rcu_work+0x50/0x50 + kthread+0x2d4/0x390 + ? kthread_create_worker_on_cpu+0xc0/0xc0 + ret_from_fork+0x35/0x40 + +Allocated by task 1124: + kasan_kmalloc+0xbf/0xe0 + kmem_cache_alloc_trace+0xe4/0x190 + dm_crtc_duplicate_state+0x78/0x130 [amdgpu] + drm_atomic_get_crtc_state+0x147/0x410 [drm] + page_flip_common+0x57/0x230 [drm_kms_helper] + drm_atomic_helper_page_flip+0xa6/0x110 [drm_kms_helper] + drm_mode_page_flip_ioctl+0xc4b/0x10a0 [drm] + drm_ioctl_kernel+0x1d4/0x260 [drm] + drm_ioctl+0x433/0x920 [drm] + amdgpu_drm_ioctl+0x11d/0x290 [amdgpu] + do_vfs_ioctl+0x1a1/0x13d0 + ksys_ioctl+0x60/0x90 + __x64_sys_ioctl+0x6f/0xb0 + do_syscall_64+0x147/0x440 + entry_SYSCALL_64_after_hwframe+0x44/0xa9 + +Freed by task 1124: + __kasan_slab_free+0x12e/0x180 + kfree+0x92/0x1a0 + drm_atomic_state_default_clear+0x315/0xc40 [drm] + __drm_atomic_state_free+0x35/0xd0 [drm] + drm_atomic_helper_update_plane+0xac/0x350 [drm_kms_helper] + __setplane_internal+0x2d6/0x840 [drm] + drm_mode_cursor_universal+0x41e/0xbe0 [drm] + drm_mode_cursor_common+0x49f/0x880 [drm] + drm_mode_cursor_ioctl+0xd8/0x130 [drm] + drm_ioctl_kernel+0x1d4/0x260 [drm] + drm_ioctl+0x433/0x920 [drm] + amdgpu_drm_ioctl+0x11d/0x290 [amdgpu] + do_vfs_ioctl+0x1a1/0x13d0 + ksys_ioctl+0x60/0x90 + __x64_sys_ioctl+0x6f/0xb0 + do_syscall_64+0x147/0x440 + entry_SYSCALL_64_after_hwframe+0x44/0xa9 + +The buggy address belongs to the object at ffff8803a697b068 + which belongs to the cache kmalloc-1024 of size 1024 +The buggy address is located 9 bytes inside of + 1024-byte region [ffff8803a697b068, ffff8803a697b468) +The buggy address belongs to the page: +page:ffffea000e9a5e00 count:1 mapcount:0 mapping:ffff88041e00efc0 index:0x0 compound_mapcount: 0 +flags: 0x8000000000008100(slab|head) +raw: 8000000000008100 ffffea000ecbc208 ffff88041e000c70 ffff88041e00efc0 +raw: 0000000000000000 0000000000170017 00000001ffffffff 0000000000000000 +page dumped because: kasan: bad access detected + +Memory state around the buggy address: + ffff8803a697af00: fb fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc + ffff8803a697af80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc +>ffff8803a697b000: fc fc fc fc fc fc fc fc fc fc fc fc fc fb fb fb + ^ + ffff8803a697b080: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb + ffff8803a697b100: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb +================================================================== + +So, we fix this by counting the number of CRTCs this atomic commit disabled +early on in the function before their atomic states have been freed, then use +that count later to do the appropriate number of RPM puts at the end of the +function. + +Acked-by: Michel Dänzer +Reviewed-by: Harry Wentland +Cc: stable@vger.kernel.org +Fixes: 97028037a38ae ("drm/amdgpu: Grab/put runtime PM references in atomic_commit_tail()") +Signed-off-by: Lyude Paul +Cc: Michel Dänzer +Reported-by: Michel Dänzer +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -4151,6 +4151,7 @@ static void amdgpu_dm_atomic_commit_tail + struct drm_connector *connector; + struct drm_connector_state *old_con_state, *new_con_state; + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; ++ int crtc_disable_count = 0; + + drm_atomic_helper_update_legacy_modeset_state(dev, state); + +@@ -4352,6 +4353,9 @@ static void amdgpu_dm_atomic_commit_tail + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + bool modeset_needed; + ++ if (old_crtc_state->active && !new_crtc_state->active) ++ crtc_disable_count++; ++ + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + modeset_needed = modeset_required( +@@ -4405,11 +4409,9 @@ static void amdgpu_dm_atomic_commit_tail + * so we can put the GPU into runtime suspend if we're not driving any + * displays anymore + */ ++ for (i = 0; i < crtc_disable_count; i++) ++ pm_runtime_put_autosuspend(dev->dev); + pm_runtime_mark_last_busy(dev->dev); +- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { +- if (old_crtc_state->active && !new_crtc_state->active) +- pm_runtime_put_autosuspend(dev->dev); +- } + } + + diff --git a/queue-4.17/drm-amdgpu-don-t-default-to-dc-support-for-kaveri-and-older.patch b/queue-4.17/drm-amdgpu-don-t-default-to-dc-support-for-kaveri-and-older.patch new file mode 100644 index 00000000000..c23c677f571 --- /dev/null +++ b/queue-4.17/drm-amdgpu-don-t-default-to-dc-support-for-kaveri-and-older.patch @@ -0,0 +1,60 @@ +From d9fda248046ac035f18a6e663f2f9245b4bf9470 Mon Sep 17 00:00:00 2001 +From: Harry Wentland +Date: Tue, 8 May 2018 11:33:42 -0400 +Subject: drm/amdgpu: Don't default to DC support for Kaveri and older + +From: Harry Wentland + +commit d9fda248046ac035f18a6e663f2f9245b4bf9470 upstream. + +We've had a number of users report failures to detect and light up +display with DC with LVDS and VGA. These connector types are not +currently supported with DC. I'd like to add support but unfortunately +don't have a system with LVDS or VGA available. + +In order not to cause regressions we should probably fallback to the +non-DC driver for ASICs that support VGA and LVDS. + +These ASICs are: + * Bonaire + * Kabini + * Kaveri + * Mullins + +ASIC support can always be force enabled with amdgpu.dc=1 + +v2: Keep Hawaii on DC +v3: Added Mullins to the list + +Cc: stable@vger.kernel.org +Signed-off-by: Harry Wentland +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2080,10 +2080,18 @@ bool amdgpu_device_asic_has_dc_support(e + switch (asic_type) { + #if defined(CONFIG_DRM_AMD_DC) + case CHIP_BONAIRE: +- case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: ++ /* ++ * We have systems in the wild with these ASICs that require ++ * LVDS and VGA support which is not supported with DC. ++ * ++ * Fallback to the non-DC driver here by default so as not to ++ * cause regressions. ++ */ ++ return amdgpu_dc > 0; ++ case CHIP_HAWAII: + case CHIP_CARRIZO: + case CHIP_STONEY: + case CHIP_POLARIS11: diff --git a/queue-4.17/drm-amdgpu-gpu-vs-cpu-page-size-fixes-in-amdgpu_vm_bo_split_mapping.patch b/queue-4.17/drm-amdgpu-gpu-vs-cpu-page-size-fixes-in-amdgpu_vm_bo_split_mapping.patch new file mode 100644 index 00000000000..5cf1041c348 --- /dev/null +++ b/queue-4.17/drm-amdgpu-gpu-vs-cpu-page-size-fixes-in-amdgpu_vm_bo_split_mapping.patch @@ -0,0 +1,62 @@ +From 38e624a18f9a05b8c894409be6b14709a7206c7c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= +Date: Thu, 21 Jun 2018 11:27:46 +0200 +Subject: drm/amdgpu: GPU vs CPU page size fixes in amdgpu_vm_bo_split_mapping +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michel Dänzer + +commit 38e624a18f9a05b8c894409be6b14709a7206c7c upstream. + +start / last / max_entries are numbers of GPU pages, pfn / count are +numbers of CPU pages. Convert between them accordingly. + +Fixes badness on systems with > 4K page size. + +Cc: stable@vger.kernel.org +Bugzilla: https://bugs.freedesktop.org/106258 +Reported-by: Matt Corallo +Tested-by: foxbat@ruin.net +Reviewed-by: Alex Deucher +Reviewed-by: Christian König +Signed-off-by: Michel Dänzer +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -1442,7 +1442,9 @@ static int amdgpu_vm_bo_split_mapping(st + uint64_t count; + + max_entries = min(max_entries, 16ull * 1024ull); +- for (count = 1; count < max_entries; ++count) { ++ for (count = 1; ++ count < max_entries / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); ++ ++count) { + uint64_t idx = pfn + count; + + if (pages_addr[idx] != +@@ -1455,7 +1457,7 @@ static int amdgpu_vm_bo_split_mapping(st + dma_addr = pages_addr; + } else { + addr = pages_addr[pfn]; +- max_entries = count; ++ max_entries = count * (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); + } + + } else if (flags & AMDGPU_PTE_VALID) { +@@ -1470,7 +1472,7 @@ static int amdgpu_vm_bo_split_mapping(st + if (r) + return r; + +- pfn += last - start + 1; ++ pfn += (last - start + 1) / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); + if (nodes && nodes->size == pfn) { + pfn = 0; + ++nodes; diff --git a/queue-4.17/drm-amdgpu-make-amdgpu_vram_mgr_bo_invisible_size-always-accurate.patch b/queue-4.17/drm-amdgpu-make-amdgpu_vram_mgr_bo_invisible_size-always-accurate.patch new file mode 100644 index 00000000000..db081546ca5 --- /dev/null +++ b/queue-4.17/drm-amdgpu-make-amdgpu_vram_mgr_bo_invisible_size-always-accurate.patch @@ -0,0 +1,60 @@ +From 7303b39e46b2f523334591f05fd9566cf929eb26 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= +Date: Thu, 14 Jun 2018 13:02:07 +0200 +Subject: drm/amdgpu: Make amdgpu_vram_mgr_bo_invisible_size always accurate +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michel Dänzer + +commit 7303b39e46b2f523334591f05fd9566cf929eb26 upstream. + +Even BOs with AMDGPU_GEM_CREATE_NO_CPU_ACCESS may end up at least +partially in CPU visible VRAM, in particular when all VRAM is visible. + +v2: +* Don't take VRAM mgr spinlock, not needed (Christian König) +* Make loop logic simpler and clearer. + +Cc: stable@vger.kernel.org +Signed-off-by: Michel Dänzer +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 20 ++++++++++++++++++-- + 1 file changed, 18 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +@@ -106,10 +106,26 @@ static u64 amdgpu_vram_mgr_vis_size(stru + */ + u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo) + { +- if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) ++ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); ++ struct ttm_mem_reg *mem = &bo->tbo.mem; ++ struct drm_mm_node *nodes = mem->mm_node; ++ unsigned pages = mem->num_pages; ++ u64 usage = 0; ++ ++ if (adev->gmc.visible_vram_size == adev->gmc.real_vram_size) ++ return 0; ++ ++ if (mem->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT) + return amdgpu_bo_size(bo); + +- return 0; ++ while (nodes && pages) { ++ usage += nodes->size << PAGE_SHIFT; ++ usage -= amdgpu_vram_mgr_vis_size(adev, nodes); ++ pages -= nodes->size; ++ ++nodes; ++ } ++ ++ return usage; + } + + /** diff --git a/queue-4.17/drm-amdgpu-refactor-amdgpu_vram_mgr_bo_invisible_size-helper.patch b/queue-4.17/drm-amdgpu-refactor-amdgpu_vram_mgr_bo_invisible_size-helper.patch new file mode 100644 index 00000000000..3d2866474a4 --- /dev/null +++ b/queue-4.17/drm-amdgpu-refactor-amdgpu_vram_mgr_bo_invisible_size-helper.patch @@ -0,0 +1,83 @@ +From 5e9244ff585239630f15f8ad8e676bc91a94ca9e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= +Date: Tue, 12 Jun 2018 12:07:33 +0200 +Subject: drm/amdgpu: Refactor amdgpu_vram_mgr_bo_invisible_size helper +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michel Dänzer + +commit 5e9244ff585239630f15f8ad8e676bc91a94ca9e upstream. + +Preparation for the following fix, no functional change intended. + +Cc: stable@vger.kernel.org +Signed-off-by: Michel Dänzer +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 ++---- + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 16 ++++++++++++++++ + 3 files changed, 19 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +@@ -749,8 +749,7 @@ int amdgpu_bo_pin_restricted(struct amdg + domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); + if (domain == AMDGPU_GEM_DOMAIN_VRAM) { + adev->vram_pin_size += amdgpu_bo_size(bo); +- if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) +- adev->invisible_pin_size += amdgpu_bo_size(bo); ++ adev->invisible_pin_size += amdgpu_vram_mgr_bo_invisible_size(bo); + } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { + adev->gart_pin_size += amdgpu_bo_size(bo); + } +@@ -789,8 +788,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo + + if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { + adev->vram_pin_size -= amdgpu_bo_size(bo); +- if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) +- adev->invisible_pin_size -= amdgpu_bo_size(bo); ++ adev->invisible_pin_size -= amdgpu_vram_mgr_bo_invisible_size(bo); + } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { + adev->gart_pin_size -= amdgpu_bo_size(bo); + } +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +@@ -73,6 +73,7 @@ bool amdgpu_gtt_mgr_has_gart_addr(struct + uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man); + int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man); + ++u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo); + uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); + uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man); + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +@@ -97,6 +97,22 @@ static u64 amdgpu_vram_mgr_vis_size(stru + } + + /** ++ * amdgpu_vram_mgr_bo_invisible_size - CPU invisible BO size ++ * ++ * @bo: &amdgpu_bo buffer object (must be in VRAM) ++ * ++ * Returns: ++ * How much of the given &amdgpu_bo buffer object lies in CPU invisible VRAM. ++ */ ++u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo) ++{ ++ if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) ++ return amdgpu_bo_size(bo); ++ ++ return 0; ++} ++ ++/** + * amdgpu_vram_mgr_new - allocate new ranges + * + * @man: TTM memory type manager diff --git a/queue-4.17/drm-amdgpu-update-pin_size-values-before-unpinning-bo.patch b/queue-4.17/drm-amdgpu-update-pin_size-values-before-unpinning-bo.patch new file mode 100644 index 00000000000..3b88b9569f3 --- /dev/null +++ b/queue-4.17/drm-amdgpu-update-pin_size-values-before-unpinning-bo.patch @@ -0,0 +1,59 @@ +From 34d6d59986abb1d2cb5415a49b6c50f51ba1d2e4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= +Date: Fri, 15 Jun 2018 11:06:56 +0200 +Subject: drm/amdgpu: Update pin_size values before unpinning BO +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michel Dänzer + +commit 34d6d59986abb1d2cb5415a49b6c50f51ba1d2e4 upstream. + +At least in theory, ttm_bo_validate may move the BO, in which case the +pin_size accounting would be inconsistent with when the BO was pinned. + +Cc: stable@vger.kernel.org +Signed-off-by: Michel Dänzer +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 18 ++++++++---------- + 1 file changed, 8 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +@@ -776,15 +776,6 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo + bo->pin_count--; + if (bo->pin_count) + return 0; +- for (i = 0; i < bo->placement.num_placement; i++) { +- bo->placements[i].lpfn = 0; +- bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; +- } +- r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); +- if (unlikely(r)) { +- dev_err(adev->dev, "%p validate failed for unpin\n", bo); +- goto error; +- } + + if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { + adev->vram_pin_size -= amdgpu_bo_size(bo); +@@ -793,7 +784,14 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo + adev->gart_pin_size -= amdgpu_bo_size(bo); + } + +-error: ++ for (i = 0; i < bo->placement.num_placement; i++) { ++ bo->placements[i].lpfn = 0; ++ bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; ++ } ++ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); ++ if (unlikely(r)) ++ dev_err(adev->dev, "%p validate failed for unpin\n", bo); ++ + return r; + } + diff --git a/queue-4.17/drm-amdgpu-use-kvmalloc_array-for-allocating-vram-manager-nodes-array.patch b/queue-4.17/drm-amdgpu-use-kvmalloc_array-for-allocating-vram-manager-nodes-array.patch new file mode 100644 index 00000000000..ca1ca3973b2 --- /dev/null +++ b/queue-4.17/drm-amdgpu-use-kvmalloc_array-for-allocating-vram-manager-nodes-array.patch @@ -0,0 +1,56 @@ +From 6fa39bc1e01dab8b4f54b23e95a181a2ed5a2d38 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= +Date: Fri, 8 Jun 2018 12:58:15 +0200 +Subject: drm/amdgpu: Use kvmalloc_array for allocating VRAM manager nodes array +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michel Dänzer + +commit 6fa39bc1e01dab8b4f54b23e95a181a2ed5a2d38 upstream. + +It can be quite big, and there's no need for it to be physically +contiguous. This is less likely to fail under memory pressure (has +actually happened while running piglit). + +Cc: stable@vger.kernel.org +Signed-off-by: Michel Dänzer +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +@@ -135,7 +135,8 @@ static int amdgpu_vram_mgr_new(struct tt + num_nodes = DIV_ROUND_UP(mem->num_pages, pages_per_node); + } + +- nodes = kcalloc(num_nodes, sizeof(*nodes), GFP_KERNEL); ++ nodes = kvmalloc_array(num_nodes, sizeof(*nodes), ++ GFP_KERNEL | __GFP_ZERO); + if (!nodes) + return -ENOMEM; + +@@ -190,7 +191,7 @@ error: + drm_mm_remove_node(&nodes[i]); + spin_unlock(&mgr->lock); + +- kfree(nodes); ++ kvfree(nodes); + return r == -ENOSPC ? 0 : r; + } + +@@ -229,7 +230,7 @@ static void amdgpu_vram_mgr_del(struct t + atomic64_sub(usage, &mgr->usage); + atomic64_sub(vis_usage, &mgr->vis_usage); + +- kfree(mem->mm_node); ++ kvfree(mem->mm_node); + mem->mm_node = NULL; + } + diff --git a/queue-4.17/drm-atmel-hlcdc-check-stride-values-in-the-first-plane.patch b/queue-4.17/drm-atmel-hlcdc-check-stride-values-in-the-first-plane.patch new file mode 100644 index 00000000000..db2285500aa --- /dev/null +++ b/queue-4.17/drm-atmel-hlcdc-check-stride-values-in-the-first-plane.patch @@ -0,0 +1,39 @@ +From 9fcf2b3c1c0276650fea537c71b513d27d929b05 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Sun, 17 Jun 2018 10:48:22 +0200 +Subject: drm/atmel-hlcdc: check stride values in the first plane + +From: Stefan Agner + +commit 9fcf2b3c1c0276650fea537c71b513d27d929b05 upstream. + +The statement always evaluates to true since the struct fields +are arrays. This has shown up as a warning when compiling with +clang: + warning: address of array 'desc->layout.xstride' will always + evaluate to 'true' [-Wpointer-bool-conversion] + +Check for values in the first plane instead. + +Fixes: 1a396789f65a ("drm: add Atmel HLCDC Display Controller support") +Cc: +Signed-off-by: Stefan Agner +Signed-off-by: Boris Brezillon +Link: https://patchwork.freedesktop.org/patch/msgid/20180617084826.31885-1-stefan@agner.ch +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ++++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +@@ -875,7 +875,7 @@ static int atmel_hlcdc_plane_init_proper + drm_object_attach_property(&plane->base.base, + props->alpha, 255); + +- if (desc->layout.xstride && desc->layout.pstride) { ++ if (desc->layout.xstride[0] && desc->layout.pstride[0]) { + int ret; + + ret = drm_plane_create_rotation_property(&plane->base, diff --git a/queue-4.17/drm-i915-allow-dblscan-user-modes-with-edp-lvds-dsi.patch b/queue-4.17/drm-i915-allow-dblscan-user-modes-with-edp-lvds-dsi.patch new file mode 100644 index 00000000000..d3cd4c24305 --- /dev/null +++ b/queue-4.17/drm-i915-allow-dblscan-user-modes-with-edp-lvds-dsi.patch @@ -0,0 +1,322 @@ +From 541ab84d2b6ea79021d5df0b54d81600334fa2a4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Thu, 24 May 2018 15:54:03 +0300 +Subject: drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 541ab84d2b6ea79021d5df0b54d81600334fa2a4 upstream. + +When encountering a connector with the scaling mode property both +intel and modesetting ddxs sometimes add tons of DBLSCAN modes +to the output's mode list. The idea presumably being that since the +output will be going through the panel fitter anyway we can pretend +to use any kind of mode. + +Sadly that means we can't reject user modes with the DBLSCAN flag +until we know whether we're going to be using the panel's native +mode or the user mode directly. Doing otherwise means X clients using +xf86vidmode/xrandr will get a protocol error (and often self +terminate as a result) when the kernel refuses to use the requested +mode with the DBLSCAN flag. + +To undo the regression we'll move the DBLSCAN checks into the +connector->mode_valid() and encoder->compute_config() hooks. + +Cc: stable@vger.kernel.org +Cc: Vito Caputo +Reported-by: Vito Caputo +Fixes: e995ca0b8139 ("drm/i915: Provide a device level .mode_valid() hook") +References: https://lkml.org/lkml/2018/5/21/715 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20180524125403.23445-1-ville.syrjala@linux.intel.com +Reviewed-by: Maarten Lankhorst +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106804 +Tested-by: Arkadiusz Miskiewicz +(cherry picked from commit e4dd27aadd205417a2e9ea9902b698a0252ec3a0) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_crt.c | 20 ++++++++++++++++++++ + drivers/gpu/drm/i915/intel_display.c | 16 +++++++++++++--- + drivers/gpu/drm/i915/intel_dp.c | 6 ++++++ + drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++++ + drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++ + drivers/gpu/drm/i915/intel_dvo.c | 6 ++++++ + drivers/gpu/drm/i915/intel_hdmi.c | 6 ++++++ + drivers/gpu/drm/i915/intel_lvds.c | 5 +++++ + drivers/gpu/drm/i915/intel_sdvo.c | 6 ++++++ + drivers/gpu/drm/i915/intel_tv.c | 12 ++++++++++-- + 10 files changed, 84 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_crt.c ++++ b/drivers/gpu/drm/i915/intel_crt.c +@@ -304,6 +304,9 @@ intel_crt_mode_valid(struct drm_connecto + int max_dotclk = dev_priv->max_dotclk_freq; + int max_clock; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + if (mode->clock < 25000) + return MODE_CLOCK_LOW; + +@@ -337,6 +340,12 @@ static bool intel_crt_compute_config(str + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) + { ++ struct drm_display_mode *adjusted_mode = ++ &pipe_config->base.adjusted_mode; ++ ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + return true; + } + +@@ -344,6 +353,12 @@ static bool pch_crt_compute_config(struc + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) + { ++ struct drm_display_mode *adjusted_mode = ++ &pipe_config->base.adjusted_mode; ++ ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + pipe_config->has_pch_encoder = true; + + return true; +@@ -354,6 +369,11 @@ static bool hsw_crt_compute_config(struc + struct drm_connector_state *conn_state) + { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); ++ struct drm_display_mode *adjusted_mode = ++ &pipe_config->base.adjusted_mode; ++ ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; + + pipe_config->has_pch_encoder = true; + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -14211,12 +14211,22 @@ static enum drm_mode_status + intel_mode_valid(struct drm_device *dev, + const struct drm_display_mode *mode) + { ++ /* ++ * Can't reject DBLSCAN here because Xorg ddxen can add piles ++ * of DBLSCAN modes to the output's mode list when they detect ++ * the scaling mode property on the connector. And they don't ++ * ask the kernel to validate those modes in any way until ++ * modeset time at which point the client gets a protocol error. ++ * So in order to not upset those clients we silently ignore the ++ * DBLSCAN flag on such connectors. For other connectors we will ++ * reject modes with the DBLSCAN flag in encoder->compute_config(). ++ * And we always reject DBLSCAN modes in connector->mode_valid() ++ * as we never want such modes on the connector's mode list. ++ */ ++ + if (mode->vscan > 1) + return MODE_NO_VSCAN; + +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- return MODE_NO_DBLESCAN; +- + if (mode->flags & DRM_MODE_FLAG_HSKEW) + return MODE_H_ILLEGAL; + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -423,6 +423,9 @@ intel_dp_mode_valid(struct drm_connector + int max_rate, mode_rate, max_lanes, max_link_clock; + int max_dotclk; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); + + if (intel_dp_is_edp(intel_dp) && fixed_mode) { +@@ -1760,6 +1763,9 @@ intel_dp_compute_config(struct intel_enc + conn_state->scaling_mode); + } + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) + return false; +--- a/drivers/gpu/drm/i915/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/intel_dp_mst.c +@@ -48,6 +48,9 @@ static bool intel_dp_mst_compute_config( + bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_LIMITED_M_N); + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + pipe_config->has_pch_encoder = false; + bpp = 24; + if (intel_dp->compliance.test_data.bpc) { +@@ -366,6 +369,9 @@ intel_dp_mst_mode_valid(struct drm_conne + if (!intel_dp) + return MODE_ERROR; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + max_link_clock = intel_dp_max_link_rate(intel_dp); + max_lanes = intel_dp_max_lane_count(intel_dp); + +--- a/drivers/gpu/drm/i915/intel_dsi.c ++++ b/drivers/gpu/drm/i915/intel_dsi.c +@@ -326,6 +326,9 @@ static bool intel_dsi_compute_config(str + conn_state->scaling_mode); + } + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + /* DSI uses short packets for sync events, so clear mode flags for DSI */ + adjusted_mode->flags = 0; + +@@ -1266,6 +1269,9 @@ intel_dsi_mode_valid(struct drm_connecto + + DRM_DEBUG_KMS("\n"); + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + if (fixed_mode) { + if (mode->hdisplay > fixed_mode->hdisplay) + return MODE_PANEL; +--- a/drivers/gpu/drm/i915/intel_dvo.c ++++ b/drivers/gpu/drm/i915/intel_dvo.c +@@ -219,6 +219,9 @@ intel_dvo_mode_valid(struct drm_connecto + int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + int target_clock = mode->clock; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + /* XXX: Validate clock range */ + + if (fixed_mode) { +@@ -254,6 +257,9 @@ static bool intel_dvo_compute_config(str + if (fixed_mode) + intel_fixed_panel_mode(fixed_mode, adjusted_mode); + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + return true; + } + +--- a/drivers/gpu/drm/i915/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/intel_hdmi.c +@@ -1557,6 +1557,9 @@ intel_hdmi_mode_valid(struct drm_connect + bool force_dvi = + READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + clock = mode->clock; + + if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) +@@ -1677,6 +1680,9 @@ bool intel_hdmi_compute_config(struct in + int desired_bpp; + bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; + + if (pipe_config->has_hdmi_sink) +--- a/drivers/gpu/drm/i915/intel_lvds.c ++++ b/drivers/gpu/drm/i915/intel_lvds.c +@@ -380,6 +380,8 @@ intel_lvds_mode_valid(struct drm_connect + struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; + int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; + if (mode->hdisplay > fixed_mode->hdisplay) + return MODE_PANEL; + if (mode->vdisplay > fixed_mode->vdisplay) +@@ -429,6 +431,9 @@ static bool intel_lvds_compute_config(st + intel_fixed_panel_mode(intel_connector->panel.fixed_mode, + adjusted_mode); + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + if (HAS_PCH_SPLIT(dev_priv)) { + pipe_config->has_pch_encoder = true; + +--- a/drivers/gpu/drm/i915/intel_sdvo.c ++++ b/drivers/gpu/drm/i915/intel_sdvo.c +@@ -1160,6 +1160,9 @@ static bool intel_sdvo_compute_config(st + adjusted_mode); + } + ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ + /* + * Make the CRTC code factor in the SDVO pixel multiplier. The + * SDVO device will factor out the multiplier during mode_set. +@@ -1621,6 +1624,9 @@ intel_sdvo_mode_valid(struct drm_connect + struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); + int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + if (intel_sdvo->pixel_clock_min > mode->clock) + return MODE_CLOCK_LOW; + +--- a/drivers/gpu/drm/i915/intel_tv.c ++++ b/drivers/gpu/drm/i915/intel_tv.c +@@ -850,6 +850,9 @@ intel_tv_mode_valid(struct drm_connector + const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); + int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + ++ if (mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return MODE_NO_DBLESCAN; ++ + if (mode->clock > max_dotclk) + return MODE_CLOCK_HIGH; + +@@ -877,16 +880,21 @@ intel_tv_compute_config(struct intel_enc + struct drm_connector_state *conn_state) + { + const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state); ++ struct drm_display_mode *adjusted_mode = ++ &pipe_config->base.adjusted_mode; + + if (!tv_mode) + return false; + +- pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock; ++ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) ++ return false; ++ ++ adjusted_mode->crtc_clock = tv_mode->clock; + DRM_DEBUG_KMS("forcing bpc to 8 for TV\n"); + pipe_config->pipe_bpp = 8*3; + + /* TV has it's own notion of sync and other mode flags, so clear them. */ +- pipe_config->base.adjusted_mode.flags = 0; ++ adjusted_mode->flags = 0; + + /* + * FIXME: We don't check whether the input mode is actually what we want diff --git a/queue-4.17/drm-i915-disallow-interlaced-modes-on-g4x-dp-outputs.patch b/queue-4.17/drm-i915-disallow-interlaced-modes-on-g4x-dp-outputs.patch new file mode 100644 index 00000000000..88dc48ae01c --- /dev/null +++ b/queue-4.17/drm-i915-disallow-interlaced-modes-on-g4x-dp-outputs.patch @@ -0,0 +1,48 @@ +From 1e34f1d36804be1a446212a33ca5397bf0e5acdd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Wed, 13 Jun 2018 19:05:52 +0300 +Subject: drm/i915: Disallow interlaced modes on g4x DP outputs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 1e34f1d36804be1a446212a33ca5397bf0e5acdd upstream. + +Looks like interlaced DP output doesn't work on g4x either. Not all +that surprising considering we already established that interlaced +DP output is busted on VLV/CHV. + +Cc: stable@vger.kernel.org +Signed-off-by: Ville Syrjälä +Reviewed-by: Jani Nikula +Link: https://patchwork.freedesktop.org/patch/msgid/20180613160553.11664-1-ville.syrjala@linux.intel.com +(cherry picked from commit 929168c5f3df5d9ea0ef426c33e971157d045eab) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dp.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -1766,7 +1766,7 @@ intel_dp_compute_config(struct intel_enc + if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) + return false; + +- if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && ++ if (HAS_GMCH_DISPLAY(dev_priv) && + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) + return false; + +@@ -6333,7 +6333,7 @@ intel_dp_init_connector(struct intel_dig + drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); + drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); + +- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) ++ if (!HAS_GMCH_DISPLAY(dev_priv)) + connector->interlace_allowed = true; + connector->doublescan_allowed = 0; + diff --git a/queue-4.17/drm-i915-dp-send-dpcd-on-for-mst-before-phy_up.patch b/queue-4.17/drm-i915-dp-send-dpcd-on-for-mst-before-phy_up.patch new file mode 100644 index 00000000000..12c26e7930c --- /dev/null +++ b/queue-4.17/drm-i915-dp-send-dpcd-on-for-mst-before-phy_up.patch @@ -0,0 +1,116 @@ +From be1c63c8017bb00a4041abace6cc1e9f0bf26aa9 Mon Sep 17 00:00:00 2001 +From: Lyude Paul +Date: Fri, 6 Apr 2018 21:10:53 -0400 +Subject: drm/i915/dp: Send DPCD ON for MST before phy_up +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Lyude Paul + +commit be1c63c8017bb00a4041abace6cc1e9f0bf26aa9 upstream. + +When doing a modeset where the sink is transitioning from D3 to D0 , it +would sometimes be possible for the initial power_up_phy() to start +timing out. This would only be observed in the last action before the +sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We +originally thought this might be an issue with us accidentally shutting +off the aux block when putting the sink into D3, but since the DP spec +mandates that sinks must wake up within 1ms while we have 100ms to +respond to an ESI irq, this didn't really add up. Turns out that the +problem is more subtle then that: + +It turns out that the timeout is from us not enabling DPMS on the MST +hub before actually trying to initiate sideband communications. This +would cause the first sideband communication (power_up_phy()), to start +timing out because the sink wasn't ready to respond. Afterwards, we +would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in +intel_ddi_pre_enable_dp(), which would actually result in waking up the +sink so that sideband requests would work again. + +Since DPMS is what lets us actually bring the hub up into a state where +sideband communications become functional again, we just need to make +sure to enable DPMS on the display before attempting to perform sideband +communications. + +Changes since v1: +- Remove comment above if (!intel_dp->is_mst) - vsryjala +- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to + keep enable/disable paths symmetrical +- Improve commit message - dhnkrn +Changes since v2: +- Only send DPMS off when we're disabling the last sink, and only send + DPMS on when we're enabling the first sink - dhnkrn +Changes since v3: +- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala + +Signed-off-by: Lyude Paul +Reviewed-by: Dhinakaran Pandiyan +Reviewed-by: Ville Syrjälä +Tested-by: Laura Abbott +Cc: stable@vger.kernel.org +Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.") +Link: https://patchwork.freedesktop.org/patch/msgid/20180407011053.22437-1-lyude@redhat.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- + drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- + 2 files changed, 13 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_ddi.c ++++ b/drivers/gpu/drm/i915/intel_ddi.c +@@ -2205,7 +2205,8 @@ static void intel_ddi_pre_enable_dp(stru + intel_prepare_dp_ddi_buffers(encoder, crtc_state); + + intel_ddi_init_dp_buf_reg(encoder); +- intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); ++ if (!is_mst) ++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); + intel_dp_start_link_train(intel_dp); + if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) + intel_dp_stop_link_train(intel_dp); +@@ -2303,12 +2304,15 @@ static void intel_ddi_post_disable_dp(st + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); + struct intel_dp *intel_dp = &dig_port->dp; ++ bool is_mst = intel_crtc_has_type(old_crtc_state, ++ INTEL_OUTPUT_DP_MST); + + /* + * Power down sink before disabling the port, otherwise we end + * up getting interrupts from the sink on detecting link loss. + */ +- intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); ++ if (!is_mst) ++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); + + intel_disable_ddi_buf(encoder); + +--- a/drivers/gpu/drm/i915/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/intel_dp_mst.c +@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(st + intel_dp->active_mst_links--; + + intel_mst->connector = NULL; +- if (intel_dp->active_mst_links == 0) ++ if (intel_dp->active_mst_links == 0) { ++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); + intel_dig_port->base.post_disable(&intel_dig_port->base, + old_crtc_state, NULL); ++ } + + DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); + } +@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(stru + + DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); + ++ if (intel_dp->active_mst_links == 0) ++ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); ++ + drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); ++ + if (intel_dp->active_mst_links == 0) + intel_dig_port->base.pre_enable(&intel_dig_port->base, + pipe_config, NULL); diff --git a/queue-4.17/drm-i915-enable-provoking-vertex-fix-on-gen9-systems.patch b/queue-4.17/drm-i915-enable-provoking-vertex-fix-on-gen9-systems.patch new file mode 100644 index 00000000000..804851e2c4d --- /dev/null +++ b/queue-4.17/drm-i915-enable-provoking-vertex-fix-on-gen9-systems.patch @@ -0,0 +1,77 @@ +From 7a3727f385dc64773db1c144f6b15c1e9d4735bb Mon Sep 17 00:00:00 2001 +From: Kenneth Graunke +Date: Fri, 15 Jun 2018 20:06:05 +0100 +Subject: drm/i915: Enable provoking vertex fix on Gen9 systems. + +From: Kenneth Graunke + +commit 7a3727f385dc64773db1c144f6b15c1e9d4735bb upstream. + +The SF and clipper units mishandle the provoking vertex in some cases, +which can cause misrendering with shaders that use flat shaded inputs. + +There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN +(for the clipper) that work around the issue. These registers are +unfortunately not part of the logical context (even the power context), +and so we must reload them every time we start executing in a context. + +Bugzilla: https://bugs.freedesktop.org/103047 +Signed-off-by: Kenneth Graunke +Signed-off-by: Chris Wilson +Link: https://patchwork.freedesktop.org/patch/msgid/20180615190605.16238-1-chris@chris-wilson.co.uk +Reviewed-by: Joonas Lahtinen +Cc: stable@vger.kernel.org +(cherry picked from commit b77422f80337d363eed60c8c48db9cb6e33085c9) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_reg.h | 5 +++++ + drivers/gpu/drm/i915/intel_lrc.c | 12 +++++++++++- + 2 files changed, 16 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -2565,12 +2565,17 @@ enum i915_power_well_id { + #define _3D_CHICKEN _MMIO(0x2084) + #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) + #define _3D_CHICKEN2 _MMIO(0x208c) ++ ++#define FF_SLICE_CHICKEN _MMIO(0x2088) ++#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) ++ + /* Disables pipelining of read flushes past the SF-WIZ interface. + * Required on all Ironlake steppings according to the B-Spec, but the + * particular danger of not doing so is not specified. + */ + # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) + #define _3D_CHICKEN3 _MMIO(0x2090) ++#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) + #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) + #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) + #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) +--- a/drivers/gpu/drm/i915/intel_lrc.c ++++ b/drivers/gpu/drm/i915/intel_lrc.c +@@ -1386,11 +1386,21 @@ static u32 *gen9_init_indirectctx_bb(str + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ + batch = gen8_emit_flush_coherentl3_wa(engine, batch); + ++ *batch++ = MI_LOAD_REGISTER_IMM(3); ++ + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ +- *batch++ = MI_LOAD_REGISTER_IMM(1); + *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); + *batch++ = _MASKED_BIT_DISABLE( + GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); ++ ++ /* BSpec: 11391 */ ++ *batch++ = i915_mmio_reg_offset(FF_SLICE_CHICKEN); ++ *batch++ = _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX); ++ ++ /* BSpec: 11299 */ ++ *batch++ = i915_mmio_reg_offset(_3D_CHICKEN3); ++ *batch++ = _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX); ++ + *batch++ = MI_NOOP; + + /* WaClearSlmSpaceAtContextSwitch:kbl */ diff --git a/queue-4.17/drm-i915-fix-pipestat-irq-ack-on-i965-g4x.patch b/queue-4.17/drm-i915-fix-pipestat-irq-ack-on-i965-g4x.patch new file mode 100644 index 00000000000..0a6a6a2a6eb --- /dev/null +++ b/queue-4.17/drm-i915-fix-pipestat-irq-ack-on-i965-g4x.patch @@ -0,0 +1,72 @@ +From 4dc055c9cc8b3dac966b54d3cd5cf463a988299b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 11 Jun 2018 23:02:55 +0300 +Subject: drm/i915: Fix PIPESTAT irq ack on i965/g4x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 4dc055c9cc8b3dac966b54d3cd5cf463a988299b upstream. + +On i965/g4x IIR is edge triggered. So in order for IIR to notice that +there is still a pending interrupt we have to force and edge in ISR. +For the ISR/IIR pipe event bits we can do that by temporarily +clearing all the PIPESTAT enable bits when we ack the status bits. +This will force the ISR pipe event bit low, and it can then go back +high when we restore the PIPESTAT enable bits. + +This avoids the following race: +1. stat = read(PIPESTAT) +2. an enabled PIPESTAT status bit goes high +3. write(PIPESTAT, enable|stat); +4. write(IIR, PIPE_EVENT) + +The end result is IIR==0 and ISR!=0. This can lead to nasty +vblank wait/flip_done timeouts if another interrupt source +doesn't trick us into looking at the PIPESTAT status bits despite +the IIR PIPE_EVENT bit being low. + +Before i965 IIR was level triggered so this problem can't actually +happen there. And curiously VLV/CHV went back to the level triggered +scheme as well. But for simplicity we'll use the same i965/g4x +compatible code for all platforms. + +Cc: stable@vger.kernel.org +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20180611200258.27121-1-ville.syrjala@linux.intel.com +Reviewed-by: Chris Wilson +(cherry picked from commit 132c27c97cb958f637dc05adc35a61b47779bcd8) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -1862,9 +1862,17 @@ static void i9xx_pipestat_irq_ack(struct + + /* + * Clear the PIPE*STAT regs before the IIR ++ * ++ * Toggle the enable bits to make sure we get an ++ * edge in the ISR pipe event bit if we don't clear ++ * all the enabled status bits. Otherwise the edge ++ * triggered IIR on i965/g4x wouldn't notice that ++ * an interrupt is still pending. + */ +- if (pipe_stats[pipe]) +- I915_WRITE(reg, enable_mask | pipe_stats[pipe]); ++ if (pipe_stats[pipe]) { ++ I915_WRITE(reg, pipe_stats[pipe]); ++ I915_WRITE(reg, enable_mask); ++ } + } + spin_unlock(&dev_priv->irq_lock); + } diff --git a/queue-4.17/drm-i915-turn-off-g4x-dp-port-in-.post_disable.patch b/queue-4.17/drm-i915-turn-off-g4x-dp-port-in-.post_disable.patch new file mode 100644 index 00000000000..4019cab5afe --- /dev/null +++ b/queue-4.17/drm-i915-turn-off-g4x-dp-port-in-.post_disable.patch @@ -0,0 +1,106 @@ +From 4dccc4d517481282e84335c7acbfd7a1481004b8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Wed, 13 Jun 2018 19:05:53 +0300 +Subject: drm/i915: Turn off g4x DP port in .post_disable() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 4dccc4d517481282e84335c7acbfd7a1481004b8 upstream. + +While Bspec doesn't list a specific sequence for turning off the DP port +on g4x we are getting an underrun if the port is disabled in the +.disable() hook. Looks like the pipe stops when the port stops, and by +that time the plane disable may not have completed yet. Also the plane(s) +seem to end up in some wonky state when this happens as they also signal +another underrun immediately after we turn them back on during the next +enable sequence. + +We could add a vblank wait in .disable() to avoid wedging the planes, +but I assume we're still tripping up the pipe in some way. So it seems +better to me to just follow the ILK+ sequence and turn off the DP port +in .post_disable() instead. This sequence doesn't seem to suffer from +this problem. Could be it was always the intended sequence for DP and +the gen4 bspec was just never updated to include it. + +Originally we used the bad sequence even on ilk+, but I changed that +in commit 08aff3fe26ae ("drm/i915: Move DP port disable to post_disable +for pch platforms") as it was causing issues on those platforms as well. +I left out g4x then only because I didn't have the hardware to test it. +Now that I do it's fairly clear that the ilk+ sequence is also the +right choice for g4x. + +v2: Fix whitespace fail (Jani) + Mention the ilk+ commit (Jani) + +Cc: stable@vger.kernel.org +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20180613160553.11664-2-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +(cherry picked from commit 51a9f6dfc00d35f927ecfaf6f0ae8ebaba39b3fe) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++---------------- + 1 file changed, 8 insertions(+), 16 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -2767,16 +2767,6 @@ static void g4x_disable_dp(struct intel_ + const struct drm_connector_state *old_conn_state) + { + intel_disable_dp(encoder, old_crtc_state, old_conn_state); +- +- /* disable the port before the pipe on g4x */ +- intel_dp_link_down(encoder, old_crtc_state); +-} +- +-static void ilk_disable_dp(struct intel_encoder *encoder, +- const struct intel_crtc_state *old_crtc_state, +- const struct drm_connector_state *old_conn_state) +-{ +- intel_disable_dp(encoder, old_crtc_state, old_conn_state); + } + + static void vlv_disable_dp(struct intel_encoder *encoder, +@@ -2790,13 +2780,19 @@ static void vlv_disable_dp(struct intel_ + intel_disable_dp(encoder, old_crtc_state, old_conn_state); + } + +-static void ilk_post_disable_dp(struct intel_encoder *encoder, ++static void g4x_post_disable_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *old_crtc_state, + const struct drm_connector_state *old_conn_state) + { + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + enum port port = encoder->port; + ++ /* ++ * Bspec does not list a specific disable sequence for g4x DP. ++ * Follow the ilk+ sequence (disable pipe before the port) for ++ * g4x DP as it does not suffer from underruns like the normal ++ * g4x modeset sequence (disable pipe after the port). ++ */ + intel_dp_link_down(encoder, old_crtc_state); + + /* Only ilk+ has port A */ +@@ -6432,15 +6428,11 @@ bool intel_dp_init(struct drm_i915_priva + intel_encoder->enable = vlv_enable_dp; + intel_encoder->disable = vlv_disable_dp; + intel_encoder->post_disable = vlv_post_disable_dp; +- } else if (INTEL_GEN(dev_priv) >= 5) { +- intel_encoder->pre_enable = g4x_pre_enable_dp; +- intel_encoder->enable = g4x_enable_dp; +- intel_encoder->disable = ilk_disable_dp; +- intel_encoder->post_disable = ilk_post_disable_dp; + } else { + intel_encoder->pre_enable = g4x_pre_enable_dp; + intel_encoder->enable = g4x_enable_dp; + intel_encoder->disable = g4x_disable_dp; ++ intel_encoder->post_disable = g4x_post_disable_dp; + } + + intel_dig_port->dp.output_reg = output_reg; diff --git a/queue-4.17/drm-qxl-call-qxl_bo_unref-outside-atomic-context.patch b/queue-4.17/drm-qxl-call-qxl_bo_unref-outside-atomic-context.patch new file mode 100644 index 00000000000..c12339c0f64 --- /dev/null +++ b/queue-4.17/drm-qxl-call-qxl_bo_unref-outside-atomic-context.patch @@ -0,0 +1,60 @@ +From 889ad63d41eea20184b0483e7e585e5b20fb6cfe Mon Sep 17 00:00:00 2001 +From: Jeremy Cline +Date: Fri, 1 Jun 2018 16:05:32 -0400 +Subject: drm/qxl: Call qxl_bo_unref outside atomic context + +From: Jeremy Cline + +commit 889ad63d41eea20184b0483e7e585e5b20fb6cfe upstream. + +"qxl_bo_unref" may sleep, but calling "qxl_release_map" causes +"preempt_disable()" to be called and "preempt_enable()" isn't called +until "qxl_release_unmap" is used. Move the call to "qxl_bo_unref" out +from in between the two to avoid sleeping from an atomic context. + +This issue can be demonstrated on a kernel with CONFIG_LOCKDEP=y by +creating a VM using QXL, using a desktop environment using Xorg, then +moving the cursor on or off a window. + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1571128 +Fixes: 9428088c90b6 ("drm/qxl: reapply cursor after resetting primary") +Cc: stable@vger.kernel.org +Signed-off-by: Jeremy Cline +Link: http://patchwork.freedesktop.org/patch/msgid/20180601200532.13619-1-jcline@redhat.com +Signed-off-by: Gerd Hoffmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/qxl/qxl_display.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/qxl/qxl_display.c ++++ b/drivers/gpu/drm/qxl/qxl_display.c +@@ -630,7 +630,7 @@ static void qxl_cursor_atomic_update(str + struct qxl_cursor_cmd *cmd; + struct qxl_cursor *cursor; + struct drm_gem_object *obj; +- struct qxl_bo *cursor_bo = NULL, *user_bo = NULL; ++ struct qxl_bo *cursor_bo = NULL, *user_bo = NULL, *old_cursor_bo = NULL; + int ret; + void *user_ptr; + int size = 64*64*4; +@@ -684,7 +684,7 @@ static void qxl_cursor_atomic_update(str + cursor_bo, 0); + cmd->type = QXL_CURSOR_SET; + +- qxl_bo_unref(&qcrtc->cursor_bo); ++ old_cursor_bo = qcrtc->cursor_bo; + qcrtc->cursor_bo = cursor_bo; + cursor_bo = NULL; + } else { +@@ -704,6 +704,9 @@ static void qxl_cursor_atomic_update(str + qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false); + qxl_release_fence_buffer_objects(release); + ++ if (old_cursor_bo) ++ qxl_bo_unref(&old_cursor_bo); ++ + qxl_bo_unref(&cursor_bo); + + return; diff --git a/queue-4.17/drm-sti-depend-on-of-rather-than-selecting-it.patch b/queue-4.17/drm-sti-depend-on-of-rather-than-selecting-it.patch new file mode 100644 index 00000000000..93cbd6e6ca4 --- /dev/null +++ b/queue-4.17/drm-sti-depend-on-of-rather-than-selecting-it.patch @@ -0,0 +1,60 @@ +From c9fea6f4379c72b7c59e1efceab09a35bc7eac43 Mon Sep 17 00:00:00 2001 +From: Oliver O'Halloran +Date: Tue, 3 Apr 2018 15:34:01 +1000 +Subject: drm/sti: Depend on OF rather than selecting it + +From: Oliver O'Halloran + +commit c9fea6f4379c72b7c59e1efceab09a35bc7eac43 upstream. + +Commit cc6b741c6f63 ("drm: sti: remove useless fields from vtg +structure") reworked some code inside of this driver and made it select +CONFIG_OF. This results in the entire OF layer being enabled when +building an allmodconfig on ia64. OF on ia64 is completely unsupported +so this isn't a great state of affairs. + +The 0day robot noticed a link-time failure on ia64 caused by +using of_node_to_nid() in an otherwise unrelated driver. The +generic fallback for of_node_to_nid() only exists when: + + defined(CONFIG_OF) && defined(CONFIG_NUMA) == false + +Since CONFIG_NUMA is usually selected for IA64 we get the link failure. +Fix this by making the driver depend on OF rather than selecting it, +odds are that was the original intent. + +Link: https://lists.01.org/pipermail/kbuild-all/2018-March/045172.html +Fixes: cc6b741c6f63 ("drm: sti: remove useless fields from vtg structure") +Cc: Benjamin Gaignard +Cc: Vincent Abriou +Cc: David Airlie +Cc: dri-devel@lists.freedesktop.org +Cc: linux-ia64@vger.kernel.org +Cc: stable@vger.kernel.org +Signed-off-by: Oliver O'Halloran +Reviewed-by: Benjamin Gaignard +Signed-off-by: Philippe Cornu +Link: https://patchwork.freedesktop.org/patch/msgid/20180403053401.30045-1-oohall@gmail.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/sti/Kconfig | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/gpu/drm/sti/Kconfig ++++ b/drivers/gpu/drm/sti/Kconfig +@@ -1,6 +1,6 @@ + config DRM_STI + tristate "DRM Support for STMicroelectronics SoC stiH4xx Series" +- depends on DRM && (ARCH_STI || ARCH_MULTIPLATFORM) ++ depends on OF && DRM && (ARCH_STI || ARCH_MULTIPLATFORM) + select RESET_CONTROLLER + select DRM_KMS_HELPER + select DRM_GEM_CMA_HELPER +@@ -8,6 +8,5 @@ config DRM_STI + select DRM_PANEL + select FW_LOADER + select SND_SOC_HDMI_CODEC if SND_SOC +- select OF + help + Choose this option to enable DRM on STM stiH4xx chipset diff --git a/queue-4.17/revert-drm-sun4i-handle-drm_bus_flag_pixdata_-edge.patch b/queue-4.17/revert-drm-sun4i-handle-drm_bus_flag_pixdata_-edge.patch new file mode 100644 index 00000000000..c64a327dd0e --- /dev/null +++ b/queue-4.17/revert-drm-sun4i-handle-drm_bus_flag_pixdata_-edge.patch @@ -0,0 +1,79 @@ +From 58b3d02f066e5b1480d80bd308c545526eea3250 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Wed, 13 Jun 2018 10:16:47 +0200 +Subject: Revert "drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE" + +From: Paul Kocialkowski + +commit 58b3d02f066e5b1480d80bd308c545526eea3250 upstream. + +This reverts commit 2c17a4368aad2b88b68e4390c819e226cf320f70. + +The offending commit triggers a run-time fault when accessing the panel +element of the sun4i_tcon structure when no such panel is attached. + +It was apparently assumed in said commit that a panel is always used with +the TCON. Although it is often the case, this is not always true. +For instance a bridge might be used instead of a panel. + +This issue was discovered using an A13-OLinuXino, that uses the TCON +in RGB mode for a simple DAC-based VGA bridge. + +Cc: stable@vger.kernel.org +Signed-off-by: Paul Kocialkowski +Signed-off-by: Maxime Ripard +Link: https://patchwork.freedesktop.org/patch/msgid/20180613081647.31183-1-paul.kocialkowski@bootlin.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 ------------------------- + 1 file changed, 25 deletions(-) + +--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c ++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c +@@ -17,7 +17,6 @@ + #include + #include + #include +-#include + + #include + +@@ -350,9 +349,6 @@ static void sun4i_tcon0_mode_set_lvds(st + static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, + const struct drm_display_mode *mode) + { +- struct drm_panel *panel = tcon->panel; +- struct drm_connector *connector = panel->connector; +- struct drm_display_info display_info = connector->display_info; + unsigned int bp, hsync, vsync; + u8 clk_delay; + u32 val = 0; +@@ -410,27 +406,6 @@ static void sun4i_tcon0_mode_set_rgb(str + if (mode->flags & DRM_MODE_FLAG_PVSYNC) + val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; + +- /* +- * On A20 and similar SoCs, the only way to achieve Positive Edge +- * (Rising Edge), is setting dclk clock phase to 2/3(240°). +- * By default TCON works in Negative Edge(Falling Edge), +- * this is why phase is set to 0 in that case. +- * Unfortunately there's no way to logically invert dclk through +- * IO_POL register. +- * The only acceptable way to work, triple checked with scope, +- * is using clock phase set to 0° for Negative Edge and set to 240° +- * for Positive Edge. +- * On A33 and similar SoCs there would be a 90° phase option, +- * but it divides also dclk by 2. +- * Following code is a way to avoid quirks all around TCON +- * and DOTCLOCK drivers. +- */ +- if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE) +- clk_set_phase(tcon->dclk, 240); +- +- if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE) +- clk_set_phase(tcon->dclk, 0); +- + regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, + SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE, + val); diff --git a/queue-4.17/series b/queue-4.17/series index 4b52e5233c3..d0bef43db1e 100644 --- a/queue-4.17/series +++ b/queue-4.17/series @@ -19,3 +19,22 @@ drm-amdgpu-add-apu-support-in-vi_set_vce_clocks.patch drm-amdgpu-fix-the-missed-vcn-fw-version-report.patch drm-amdgpu-grab-put-runtime-pm-references-in-atomic_commit_tail.patch drm-amdgpu-fix-clear_all-and-replace-handling-in-the-vm-v2.patch +drm-sti-depend-on-of-rather-than-selecting-it.patch +drm-amd-display-clear-connector-s-edid-pointer.patch +drm-i915-dp-send-dpcd-on-for-mst-before-phy_up.patch +drm-qxl-call-qxl_bo_unref-outside-atomic-context.patch +drm-atmel-hlcdc-check-stride-values-in-the-first-plane.patch +revert-drm-sun4i-handle-drm_bus_flag_pixdata_-edge.patch +drm-amdgpu-don-t-default-to-dc-support-for-kaveri-and-older.patch +drm-amdgpu-use-kvmalloc_array-for-allocating-vram-manager-nodes-array.patch +drm-amdgpu-refactor-amdgpu_vram_mgr_bo_invisible_size-helper.patch +drm-amdgpu-make-amdgpu_vram_mgr_bo_invisible_size-always-accurate.patch +drm-amdgpu-update-pin_size-values-before-unpinning-bo.patch +drm-amdgpu-gpu-vs-cpu-page-size-fixes-in-amdgpu_vm_bo_split_mapping.patch +drm-amdgpu-count-disabled-crtcs-in-commit-tail-earlier.patch +drm-amd-display-release-spinlock-before-committing-updates-to-stream.patch +drm-i915-allow-dblscan-user-modes-with-edp-lvds-dsi.patch +drm-i915-fix-pipestat-irq-ack-on-i965-g4x.patch +drm-i915-disallow-interlaced-modes-on-g4x-dp-outputs.patch +drm-i915-turn-off-g4x-dp-port-in-.post_disable.patch +drm-i915-enable-provoking-vertex-fix-on-gen9-systems.patch