From: Greg Kroah-Hartman Date: Mon, 5 Aug 2019 06:03:54 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v4.4.188~13 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7fe01138ff20536e87ab4fa67d5836b0f8745334;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch drm-i915-perf-fix-icl-perf-register-offsets.patch --- diff --git a/queue-4.19/drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch b/queue-4.19/drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch new file mode 100644 index 00000000000..6d5222046b5 --- /dev/null +++ b/queue-4.19/drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch @@ -0,0 +1,49 @@ +From 7366aeb77cd840f3edea02c65065d40affaa7f45 Mon Sep 17 00:00:00 2001 +From: Xiaolin Zhang +Date: Thu, 18 Jul 2019 01:10:24 +0800 +Subject: drm/i915/gvt: fix incorrect cache entry for guest page mapping + +From: Xiaolin Zhang + +commit 7366aeb77cd840f3edea02c65065d40affaa7f45 upstream. + +GPU hang observed during the guest OCL conformance test which is caused +by THP GTT feature used durning the test. + +It was observed the same GFN with different size (4K and 2M) requested +from the guest in GVT. So during the guest page dma map stage, it is +required to unmap first with orginal size and then remap again with +requested size. + +Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support") +Cc: stable@vger.kernel.org +Reviewed-by: Zhenyu Wang +Signed-off-by: Xiaolin Zhang +Signed-off-by: Zhenyu Wang +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/gvt/kvmgt.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/gpu/drm/i915/gvt/kvmgt.c ++++ b/drivers/gpu/drm/i915/gvt/kvmgt.c +@@ -1748,6 +1748,18 @@ int kvmgt_dma_map_guest_page(unsigned lo + ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size); + if (ret) + goto err_unmap; ++ } else if (entry->size != size) { ++ /* the same gfn with different size: unmap and re-map */ ++ gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); ++ __gvt_cache_remove_entry(vgpu, entry); ++ ++ ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); ++ if (ret) ++ goto err_unlock; ++ ++ ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size); ++ if (ret) ++ goto err_unmap; + } else { + kref_get(&entry->ref); + *dma_addr = entry->dma_addr; diff --git a/queue-4.19/drm-i915-perf-fix-icl-perf-register-offsets.patch b/queue-4.19/drm-i915-perf-fix-icl-perf-register-offsets.patch new file mode 100644 index 00000000000..aac97e0bbd3 --- /dev/null +++ b/queue-4.19/drm-i915-perf-fix-icl-perf-register-offsets.patch @@ -0,0 +1,45 @@ +From 95eef14cdad150fed43147bcd4f29eea3d0a3f03 Mon Sep 17 00:00:00 2001 +From: Lionel Landwerlin +Date: Mon, 10 Jun 2019 11:19:14 +0300 +Subject: drm/i915/perf: fix ICL perf register offsets + +From: Lionel Landwerlin + +commit 95eef14cdad150fed43147bcd4f29eea3d0a3f03 upstream. + +We got the wrong offsets (could they have changed?). New values were +computed off an error state by looking up the register offset in the +context image as written by the HW. + +Signed-off-by: Lionel Landwerlin +Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL") +Cc: # v4.18+ +Acked-by: Kenneth Graunke +Link: https://patchwork.freedesktop.org/patch/msgid/20190610081914.25428-1-lionel.g.landwerlin@intel.com +(cherry picked from commit 8dcfdfb4501012a8d36d2157dc73925715f2befb) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_perf.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_perf.c ++++ b/drivers/gpu/drm/i915/i915_perf.c +@@ -3552,9 +3552,13 @@ void i915_perf_init(struct drm_i915_priv + dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set; + +- dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; +- dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; +- ++ if (IS_GEN(dev_priv, 10)) { ++ dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; ++ dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; ++ } else { ++ dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124; ++ dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e; ++ } + dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); + } + } diff --git a/queue-4.19/series b/queue-4.19/series index b3ff9545f62..bba6add7bbd 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -65,3 +65,5 @@ ib-mlx5-move-mrs-to-a-kernel-pd-when-freeing-them-to-the-mr-cache.patch ib-mlx5-fix-clean_mr-to-work-in-the-expected-order.patch ib-mlx5-fix-rss-toeplitz-setup-to-be-aligned-with-the-hw-specification.patch ib-hfi1-check-for-error-on-call-to-alloc_rsm_map_table.patch +drm-i915-perf-fix-icl-perf-register-offsets.patch +drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch