From: Greg Kroah-Hartman Date: Wed, 13 Feb 2019 14:07:17 +0000 (+0100) Subject: 4.9-stable patches X-Git-Tag: v4.9.157~19 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=81778d50e5fbef6ce94d704ce9f84857c58c7b6c;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: arm-iop32x-n2100-fix-pci-irq-mapping.patch arm-tango-improve-arch_multiplatform-compatibility.patch drm-modes-prevent-division-by-zero-htotal.patch drm-vmwgfx-fix-setting-of-dma-masks.patch drm-vmwgfx-return-error-code-from-vmw_execbuf_copy_fence_user.patch mac80211-ensure-that-mgmt-tx-skbs-have-tailroom-for-encryption.patch mips-cm-reprime-error-cause.patch mips-octeon-don-t-set-octeon_dma_bar_type-if-pci-is-disabled.patch mips-vdso-include-ccflags-vdso-in-o32-n32-.lds-builds.patch --- diff --git a/queue-4.9/arm-iop32x-n2100-fix-pci-irq-mapping.patch b/queue-4.9/arm-iop32x-n2100-fix-pci-irq-mapping.patch new file mode 100644 index 00000000000..3bd6c4a3282 --- /dev/null +++ b/queue-4.9/arm-iop32x-n2100-fix-pci-irq-mapping.patch @@ -0,0 +1,33 @@ +From db4090920ba2d61a5827a23e441447926a02ffee Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Fri, 25 Jan 2019 20:10:15 +0000 +Subject: ARM: iop32x/n2100: fix PCI IRQ mapping + +From: Russell King + +commit db4090920ba2d61a5827a23e441447926a02ffee upstream. + +Booting 4.20 on a TheCUS N2100 results in a kernel oops while probing +PCI, due to n2100_pci_map_irq() having been discarded during boot. + +Signed-off-by: Russell King +Cc: stable@vger.kernel.org # 2.6.18+ +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-iop32x/n2100.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/arch/arm/mach-iop32x/n2100.c ++++ b/arch/arm/mach-iop32x/n2100.c +@@ -75,8 +75,7 @@ void __init n2100_map_io(void) + /* + * N2100 PCI. + */ +-static int __init +-n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++static int n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { + int irq; + diff --git a/queue-4.9/arm-tango-improve-arch_multiplatform-compatibility.patch b/queue-4.9/arm-tango-improve-arch_multiplatform-compatibility.patch new file mode 100644 index 00000000000..1c8ba67f0ae --- /dev/null +++ b/queue-4.9/arm-tango-improve-arch_multiplatform-compatibility.patch @@ -0,0 +1,74 @@ +From d0f9f16788e15d9eb40f68b047732d49658c5a3a Mon Sep 17 00:00:00 2001 +From: Marc Gonzalez +Date: Wed, 16 Jan 2019 16:49:58 +0100 +Subject: ARM: tango: Improve ARCH_MULTIPLATFORM compatibility + +From: Marc Gonzalez + +commit d0f9f16788e15d9eb40f68b047732d49658c5a3a upstream. + +Calling platform-specific code unconditionally blows up when running +an ARCH_MULTIPLATFORM kernel on a different platform. Don't do it. + +Reported-by: Paolo Pisati +Signed-off-by: Marc Gonzalez +Acked-by: Pavel Machek +Cc: stable@vger.kernel.org # v4.8+ +Fixes: a30eceb7a59d ("ARM: tango: add Suspend-to-RAM support") +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-tango/pm.c | 6 ++---- + arch/arm/mach-tango/pm.h | 7 +++++++ + arch/arm/mach-tango/setup.c | 2 ++ + 3 files changed, 11 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-tango/pm.c ++++ b/arch/arm/mach-tango/pm.c +@@ -2,6 +2,7 @@ + #include + #include + #include "smc.h" ++#include "pm.h" + + static int tango_pm_powerdown(unsigned long arg) + { +@@ -23,10 +24,7 @@ static const struct platform_suspend_ops + .valid = suspend_valid_only_mem, + }; + +-static int __init tango_pm_init(void) ++void __init tango_pm_init(void) + { + suspend_set_ops(&tango_pm_ops); +- return 0; + } +- +-late_initcall(tango_pm_init); +--- /dev/null ++++ b/arch/arm/mach-tango/pm.h +@@ -0,0 +1,7 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifdef CONFIG_SUSPEND ++void __init tango_pm_init(void); ++#else ++#define tango_pm_init NULL ++#endif +--- a/arch/arm/mach-tango/setup.c ++++ b/arch/arm/mach-tango/setup.c +@@ -1,6 +1,7 @@ + #include + #include + #include "smc.h" ++#include "pm.h" + + static void tango_l2c_write(unsigned long val, unsigned int reg) + { +@@ -14,4 +15,5 @@ DT_MACHINE_START(TANGO_DT, "Sigma Tango + .dt_compat = tango_dt_compat, + .l2c_aux_mask = ~0, + .l2c_write_sec = tango_l2c_write, ++ .init_late = tango_pm_init, + MACHINE_END diff --git a/queue-4.9/drm-modes-prevent-division-by-zero-htotal.patch b/queue-4.9/drm-modes-prevent-division-by-zero-htotal.patch new file mode 100644 index 00000000000..e06fa8a53f1 --- /dev/null +++ b/queue-4.9/drm-modes-prevent-division-by-zero-htotal.patch @@ -0,0 +1,102 @@ +From a2fcd5c84f7a7825e028381b10182439067aa90d Mon Sep 17 00:00:00 2001 +From: Tina Zhang +Date: Wed, 23 Jan 2019 15:28:59 +0800 +Subject: drm/modes: Prevent division by zero htotal + +From: Tina Zhang + +commit a2fcd5c84f7a7825e028381b10182439067aa90d upstream. + +This patch prevents division by zero htotal. + +In a follow-up mail Tina writes: + +> > How did you manage to get here with htotal == 0? This needs backtraces (or if +> > this is just about static checkers, a mention of that). +> > -Daniel +> +> In GVT-g, we are trying to enable a virtual display w/o setting timings for a pipe +> (a.k.a htotal=0), then we met the following kernel panic: +> +> [ 32.832048] divide error: 0000 [#1] SMP PTI +> [ 32.833614] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.18.0-rc4-sriov+ #33 +> [ 32.834438] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.10.1-0-g8891697-dirty-20180511_165818-tinazhang-linux-1 04/01/2014 +> [ 32.835901] RIP: 0010:drm_mode_hsync+0x1e/0x40 +> [ 32.836004] Code: 31 c0 c3 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 8b 87 d8 00 00 00 85 c0 75 22 8b 4f 68 85 c9 78 1b 69 47 58 e8 03 00 00 99 f9 b9 d3 4d 62 10 05 f4 01 00 00 f7 e1 89 d0 c1 e8 06 f3 c3 66 +> [ 32.836004] RSP: 0000:ffffc900000ebb90 EFLAGS: 00010206 +> [ 32.836004] RAX: 0000000000000000 RBX: ffff88001c67c8a0 RCX: 0000000000000000 +> [ 32.836004] RDX: 0000000000000000 RSI: ffff88001c67c000 RDI: ffff88001c67c8a0 +> [ 32.836004] RBP: ffff88001c7d03a0 R08: ffff88001c67c8a0 R09: ffff88001c7d0330 +> [ 32.836004] R10: ffffffff822c3a98 R11: 0000000000000001 R12: ffff88001c67c000 +> [ 32.836004] R13: ffff88001c7d0370 R14: ffffffff8207eb78 R15: ffff88001c67c800 +> [ 32.836004] FS: 0000000000000000(0000) GS:ffff88001da00000(0000) knlGS:0000000000000000 +> [ 32.836004] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +> [ 32.836004] CR2: 0000000000000000 CR3: 000000000220a000 CR4: 00000000000006f0 +> [ 32.836004] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 +> [ 32.836004] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 +> [ 32.836004] Call Trace: +> [ 32.836004] intel_mode_from_pipe_config+0x72/0x90 +> [ 32.836004] intel_modeset_setup_hw_state+0x569/0xf90 +> [ 32.836004] intel_modeset_init+0x905/0x1db0 +> [ 32.836004] i915_driver_load+0xb8c/0x1120 +> [ 32.836004] i915_pci_probe+0x4d/0xb0 +> [ 32.836004] local_pci_probe+0x44/0xa0 +> [ 32.836004] ? pci_assign_irq+0x27/0x130 +> [ 32.836004] pci_device_probe+0x102/0x1c0 +> [ 32.836004] driver_probe_device+0x2b8/0x480 +> [ 32.836004] __driver_attach+0x109/0x110 +> [ 32.836004] ? driver_probe_device+0x480/0x480 +> [ 32.836004] bus_for_each_dev+0x67/0xc0 +> [ 32.836004] ? klist_add_tail+0x3b/0x70 +> [ 32.836004] bus_add_driver+0x1e8/0x260 +> [ 32.836004] driver_register+0x5b/0xe0 +> [ 32.836004] ? mipi_dsi_bus_init+0x11/0x11 +> [ 32.836004] do_one_initcall+0x4d/0x1eb +> [ 32.836004] kernel_init_freeable+0x197/0x237 +> [ 32.836004] ? rest_init+0xd0/0xd0 +> [ 32.836004] kernel_init+0xa/0x110 +> [ 32.836004] ret_from_fork+0x35/0x40 +> [ 32.836004] Modules linked in: +> [ 32.859183] ---[ end trace 525608b0ed0e8665 ]--- +> [ 32.859722] RIP: 0010:drm_mode_hsync+0x1e/0x40 +> [ 32.860287] Code: 31 c0 c3 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 8b 87 d8 00 00 00 85 c0 75 22 8b 4f 68 85 c9 78 1b 69 47 58 e8 03 00 00 99 f9 b9 d3 4d 62 10 05 f4 01 00 00 f7 e1 89 d0 c1 e8 06 f3 c3 66 +> [ 32.862680] RSP: 0000:ffffc900000ebb90 EFLAGS: 00010206 +> [ 32.863309] RAX: 0000000000000000 RBX: ffff88001c67c8a0 RCX: 0000000000000000 +> [ 32.864182] RDX: 0000000000000000 RSI: ffff88001c67c000 RDI: ffff88001c67c8a0 +> [ 32.865206] RBP: ffff88001c7d03a0 R08: ffff88001c67c8a0 R09: ffff88001c7d0330 +> [ 32.866359] R10: ffffffff822c3a98 R11: 0000000000000001 R12: ffff88001c67c000 +> [ 32.867213] R13: ffff88001c7d0370 R14: ffffffff8207eb78 R15: ffff88001c67c800 +> [ 32.868075] FS: 0000000000000000(0000) GS:ffff88001da00000(0000) knlGS:0000000000000000 +> [ 32.868983] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +> [ 32.869659] CR2: 0000000000000000 CR3: 000000000220a000 CR4: 00000000000006f0 +> [ 32.870599] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 +> [ 32.871598] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 +> [ 32.872549] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b +> +> Since drm_mode_hsync() has the logic to check mode->htotal, I just extend it to cover the case htotal==0. + +Signed-off-by: Tina Zhang +Cc: Adam Jackson +Cc: Dave Airlie +Cc: Daniel Vetter +[danvet: Add additional explanations + cc: stable.] +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Vetter +Link: https://patchwork.freedesktop.org/patch/msgid/1548228539-3061-1-git-send-email-tina.zhang@intel.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_modes.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/drm_modes.c ++++ b/drivers/gpu/drm/drm_modes.c +@@ -753,7 +753,7 @@ int drm_mode_hsync(const struct drm_disp + if (mode->hsync) + return mode->hsync; + +- if (mode->htotal < 0) ++ if (mode->htotal <= 0) + return 0; + + calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ diff --git a/queue-4.9/drm-vmwgfx-fix-setting-of-dma-masks.patch b/queue-4.9/drm-vmwgfx-fix-setting-of-dma-masks.patch new file mode 100644 index 00000000000..d5a83e11ee8 --- /dev/null +++ b/queue-4.9/drm-vmwgfx-fix-setting-of-dma-masks.patch @@ -0,0 +1,44 @@ +From 4cbfa1e6c09e98450aab3240e5119b0ab2c9795b Mon Sep 17 00:00:00 2001 +From: Thomas Hellstrom +Date: Mon, 28 Jan 2019 10:31:33 +0100 +Subject: drm/vmwgfx: Fix setting of dma masks + +From: Thomas Hellstrom + +commit 4cbfa1e6c09e98450aab3240e5119b0ab2c9795b upstream. + +Previously we set only the dma mask and not the coherent mask. Fix that. +Also, for clarity, make sure both are initially set to 64 bits. + +Cc: +Fixes: 0d00c488f3de: ("drm/vmwgfx: Fix the driver for large dma addresses") +Signed-off-by: Thomas Hellstrom +Reviewed-by: Deepak Rawat +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +@@ -605,13 +605,16 @@ out_fixup: + static int vmw_dma_masks(struct vmw_private *dev_priv) + { + struct drm_device *dev = dev_priv->dev; ++ int ret = 0; + +- if (intel_iommu_enabled && ++ ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); ++ if (dev_priv->map_mode != vmw_dma_phys && + (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { + DRM_INFO("Restricting DMA addresses to 44 bits.\n"); +- return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); ++ return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); + } +- return 0; ++ ++ return ret; + } + #else + static int vmw_dma_masks(struct vmw_private *dev_priv) diff --git a/queue-4.9/drm-vmwgfx-return-error-code-from-vmw_execbuf_copy_fence_user.patch b/queue-4.9/drm-vmwgfx-return-error-code-from-vmw_execbuf_copy_fence_user.patch new file mode 100644 index 00000000000..913ec88d96d --- /dev/null +++ b/queue-4.9/drm-vmwgfx-return-error-code-from-vmw_execbuf_copy_fence_user.patch @@ -0,0 +1,38 @@ +From 728354c005c36eaf44b6e5552372b67e60d17f56 Mon Sep 17 00:00:00 2001 +From: Thomas Hellstrom +Date: Thu, 31 Jan 2019 10:55:37 +0100 +Subject: drm/vmwgfx: Return error code from vmw_execbuf_copy_fence_user + +From: Thomas Hellstrom + +commit 728354c005c36eaf44b6e5552372b67e60d17f56 upstream. + +The function was unconditionally returning 0, and a caller would have to +rely on the returned fence pointer being NULL to detect errors. However, +the function vmw_execbuf_copy_fence_user() would expect a non-zero error +code in that case and would BUG otherwise. + +So make sure we return a proper non-zero error code if the fence pointer +returned is NULL. + +Cc: +Fixes: ae2a104058e2: ("vmwgfx: Implement fence objects") +Signed-off-by: Thomas Hellstrom +Reviewed-by: Deepak Rawat +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +@@ -3769,7 +3769,7 @@ int vmw_execbuf_fence_commands(struct dr + *p_fence = NULL; + } + +- return 0; ++ return ret; + } + + /** diff --git a/queue-4.9/mac80211-ensure-that-mgmt-tx-skbs-have-tailroom-for-encryption.patch b/queue-4.9/mac80211-ensure-that-mgmt-tx-skbs-have-tailroom-for-encryption.patch new file mode 100644 index 00000000000..9c4da4cc970 --- /dev/null +++ b/queue-4.9/mac80211-ensure-that-mgmt-tx-skbs-have-tailroom-for-encryption.patch @@ -0,0 +1,57 @@ +From 9d0f50b80222dc273e67e4e14410fcfa4130a90c Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Tue, 29 Jan 2019 11:10:57 +0100 +Subject: mac80211: ensure that mgmt tx skbs have tailroom for encryption + +From: Felix Fietkau + +commit 9d0f50b80222dc273e67e4e14410fcfa4130a90c upstream. + +Some drivers use IEEE80211_KEY_FLAG_SW_MGMT_TX to indicate that management +frames need to be software encrypted. Since normal data packets are still +encrypted by the hardware, crypto_tx_tailroom_needed_cnt gets decremented +after key upload to hw. This can lead to passing skbs to ccmp_encrypt_skb, +which don't have the necessary tailroom for software encryption. + +Change the code to add tailroom for encrypted management packets, even if +crypto_tx_tailroom_needed_cnt is 0. + +Cc: stable@vger.kernel.org +Signed-off-by: Felix Fietkau +Signed-off-by: Johannes Berg +Signed-off-by: Greg Kroah-Hartman + +--- + net/mac80211/tx.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -1852,9 +1852,16 @@ static int ieee80211_skb_resize(struct i + int head_need, bool may_encrypt) + { + struct ieee80211_local *local = sdata->local; ++ struct ieee80211_hdr *hdr; ++ bool enc_tailroom; + int tail_need = 0; + +- if (may_encrypt && sdata->crypto_tx_tailroom_needed_cnt) { ++ hdr = (struct ieee80211_hdr *) skb->data; ++ enc_tailroom = may_encrypt && ++ (sdata->crypto_tx_tailroom_needed_cnt || ++ ieee80211_is_mgmt(hdr->frame_control)); ++ ++ if (enc_tailroom) { + tail_need = IEEE80211_ENCRYPT_TAILROOM; + tail_need -= skb_tailroom(skb); + tail_need = max_t(int, tail_need, 0); +@@ -1862,8 +1869,7 @@ static int ieee80211_skb_resize(struct i + + if (skb_cloned(skb) && + (!ieee80211_hw_check(&local->hw, SUPPORTS_CLONED_SKBS) || +- !skb_clone_writable(skb, ETH_HLEN) || +- (may_encrypt && sdata->crypto_tx_tailroom_needed_cnt))) ++ !skb_clone_writable(skb, ETH_HLEN) || enc_tailroom)) + I802_DEBUG_INC(local->tx_expand_skb_head_cloned); + else if (head_need || tail_need) + I802_DEBUG_INC(local->tx_expand_skb_head); diff --git a/queue-4.9/mips-cm-reprime-error-cause.patch b/queue-4.9/mips-cm-reprime-error-cause.patch new file mode 100644 index 00000000000..4e981f97f7e --- /dev/null +++ b/queue-4.9/mips-cm-reprime-error-cause.patch @@ -0,0 +1,42 @@ +From 05dc6001af0630e200ad5ea08707187fe5537e6d Mon Sep 17 00:00:00 2001 +From: Vladimir Kondratiev +Date: Wed, 6 Feb 2019 13:46:17 +0200 +Subject: mips: cm: reprime error cause + +From: Vladimir Kondratiev + +commit 05dc6001af0630e200ad5ea08707187fe5537e6d upstream. + +Accordingly to the documentation +---cut--- +The GCR_ERROR_CAUSE.ERR_TYPE field and the GCR_ERROR_MULT.ERR_TYPE +fields can be cleared by either a reset or by writing the current +value of GCR_ERROR_CAUSE.ERR_TYPE to the +GCR_ERROR_CAUSE.ERR_TYPE register. +---cut--- +Do exactly this. Original value of cm_error may be safely written back; +it clears error cause and keeps other bits untouched. + +Fixes: 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache errors") +Signed-off-by: Vladimir Kondratiev +Signed-off-by: Paul Burton +Cc: Ralf Baechle +Cc: James Hogan +Cc: linux-mips@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Cc: stable@vger.kernel.org # v4.3+ +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/kernel/mips-cm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/kernel/mips-cm.c ++++ b/arch/mips/kernel/mips-cm.c +@@ -424,5 +424,5 @@ void mips_cm_error_report(void) + } + + /* reprime cause register */ +- write_gcr_error_cause(0); ++ write_gcr_error_cause(cm_error); + } diff --git a/queue-4.9/mips-octeon-don-t-set-octeon_dma_bar_type-if-pci-is-disabled.patch b/queue-4.9/mips-octeon-don-t-set-octeon_dma_bar_type-if-pci-is-disabled.patch new file mode 100644 index 00000000000..0c8566267ac --- /dev/null +++ b/queue-4.9/mips-octeon-don-t-set-octeon_dma_bar_type-if-pci-is-disabled.patch @@ -0,0 +1,49 @@ +From dcf300a69ac307053dfb35c2e33972e754a98bce Mon Sep 17 00:00:00 2001 +From: Aaro Koskinen +Date: Sun, 27 Jan 2019 23:28:33 +0200 +Subject: MIPS: OCTEON: don't set octeon_dma_bar_type if PCI is disabled + +From: Aaro Koskinen + +commit dcf300a69ac307053dfb35c2e33972e754a98bce upstream. + +Don't set octeon_dma_bar_type if PCI is disabled. This avoids creation +of the MSI irqchip later on, and saves a bit of memory. + +Signed-off-by: Aaro Koskinen +Signed-off-by: Paul Burton +Fixes: a214720cbf50 ("Disable MSI also when pcie-octeon.pcie_disable on") +Cc: stable@vger.kernel.org # v3.3+ +Cc: linux-mips@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/pci/pci-octeon.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/mips/pci/pci-octeon.c ++++ b/arch/mips/pci/pci-octeon.c +@@ -573,6 +573,11 @@ static int __init octeon_pci_setup(void) + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) + return 0; + ++ if (!octeon_is_pci_host()) { ++ pr_notice("Not in host mode, PCI Controller not initialized\n"); ++ return 0; ++ } ++ + /* Point pcibios_map_irq() to the PCI version of it */ + octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; + +@@ -584,11 +589,6 @@ static int __init octeon_pci_setup(void) + else + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; + +- if (!octeon_is_pci_host()) { +- pr_notice("Not in host mode, PCI Controller not initialized\n"); +- return 0; +- } +- + /* PCI I/O and PCI MEM values */ + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); + ioport_resource.start = 0; diff --git a/queue-4.9/mips-vdso-include-ccflags-vdso-in-o32-n32-.lds-builds.patch b/queue-4.9/mips-vdso-include-ccflags-vdso-in-o32-n32-.lds-builds.patch new file mode 100644 index 00000000000..c57edbb7c6d --- /dev/null +++ b/queue-4.9/mips-vdso-include-ccflags-vdso-in-o32-n32-.lds-builds.patch @@ -0,0 +1,62 @@ +From 67fc5dc8a541e8f458d7f08bf88ff55933bf9f9d Mon Sep 17 00:00:00 2001 +From: Paul Burton +Date: Mon, 28 Jan 2019 23:16:22 +0000 +Subject: MIPS: VDSO: Include $(ccflags-vdso) in o32,n32 .lds builds + +From: Paul Burton + +commit 67fc5dc8a541e8f458d7f08bf88ff55933bf9f9d upstream. + +When generating vdso-o32.lds & vdso-n32.lds for use with programs +running as compat ABIs under 64b kernels, we previously haven't included +the compiler flags that are supposedly common to all ABIs - ie. those in +the ccflags-vdso variable. + +This is problematic in cases where we need to provide the -m%-float flag +in order to ensure that we don't attempt to use a floating point ABI +that's incompatible with the target CPU & ABI. For example a toolchain +using current gcc trunk configured --with-fp-32=xx fails to build a +64r6el_defconfig kernel with the following error: + + cc1: error: '-march=mips1' requires '-mfp32' + make[2]: *** [arch/mips/vdso/Makefile:135: arch/mips/vdso/vdso-o32.lds] Error 1 + +Include $(ccflags-vdso) for the compat VDSO .lds builds, just as it is +included for the native VDSO .lds & when compiling objects for the +compat VDSOs. This ensures we consistently provide the -msoft-float flag +amongst others, avoiding the problem by ensuring we're agnostic to the +toolchain defaults. + +Signed-off-by: Paul Burton +Fixes: ebb5e78cc634 ("MIPS: Initial implementation of a VDSO") +Cc: linux-mips@vger.kernel.org +Cc: Kevin Hilman +Cc: Guenter Roeck +Cc: Maciej W . Rozycki +Cc: stable@vger.kernel.org # v4.4+ +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/vdso/Makefile | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/mips/vdso/Makefile ++++ b/arch/mips/vdso/Makefile +@@ -116,7 +116,7 @@ $(obj)/%-o32.o: $(src)/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + +-$(obj)/vdso-o32.lds: KBUILD_CPPFLAGS := -mabi=32 ++$(obj)/vdso-o32.lds: KBUILD_CPPFLAGS := $(ccflags-vdso) -mabi=32 + $(obj)/vdso-o32.lds: $(src)/vdso.lds.S FORCE + $(call if_changed_dep,cpp_lds_S) + +@@ -156,7 +156,7 @@ $(obj)/%-n32.o: $(src)/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + +-$(obj)/vdso-n32.lds: KBUILD_CPPFLAGS := -mabi=n32 ++$(obj)/vdso-n32.lds: KBUILD_CPPFLAGS := $(ccflags-vdso) -mabi=n32 + $(obj)/vdso-n32.lds: $(src)/vdso.lds.S FORCE + $(call if_changed_dep,cpp_lds_S) + diff --git a/queue-4.9/series b/queue-4.9/series index 9eb4e59a70b..2d617c3d2e1 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -5,3 +5,12 @@ signal-better-detection-of-synchronous-signals.patch misc-vexpress-off-by-one-in-vexpress_syscfg_exec.patch samples-mei-use-dev-mei0-instead-of-dev-mei.patch debugfs-fix-debugfs_rename-parameter-checking.patch +mips-cm-reprime-error-cause.patch +mips-octeon-don-t-set-octeon_dma_bar_type-if-pci-is-disabled.patch +mips-vdso-include-ccflags-vdso-in-o32-n32-.lds-builds.patch +arm-iop32x-n2100-fix-pci-irq-mapping.patch +arm-tango-improve-arch_multiplatform-compatibility.patch +mac80211-ensure-that-mgmt-tx-skbs-have-tailroom-for-encryption.patch +drm-modes-prevent-division-by-zero-htotal.patch +drm-vmwgfx-fix-setting-of-dma-masks.patch +drm-vmwgfx-return-error-code-from-vmw_execbuf_copy_fence_user.patch