From: Michal Simek Date: Wed, 10 Apr 2019 12:30:50 +0000 (+0200) Subject: arm64: zynqmp: Add x-prc-01/02/03/04 revA support from SC X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=81c679c7530b7b6c5236ad66d4cd5cfe0d93b48c;p=thirdparty%2Fu-boot.git arm64: zynqmp: Add x-prc-01/02/03/04 revA support from SC Add i2c accessible devices with description. There is versal specific eeprom and i2c-gpio controller. SE3 has also clock chip present. Also remove x-prc description from SC dts. Signed-off-by: Michal Simek --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b6268eedced..ea12d88b6ad 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-a2197-g-revA.dtb \ zynqmp-a2197-m-revA.dtb \ zynqmp-a2197-p-revA.dtb \ + zynqmp-a2197-p-revA-x-prc-01-revA.dtbo \ + zynqmp-a2197-p-revA-x-prc-02-revA.dtbo \ + zynqmp-a2197-p-revA-x-prc-03-revA.dtbo \ + zynqmp-a2197-p-revA-x-prc-04-revA.dtbo \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ diff --git a/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-01-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-01-revA.dts new file mode 100644 index 00000000000..c82f7e24225 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-01-revA.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1) + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J242 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u116 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-02-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-02-revA.dts new file mode 100644 index 00000000000..f797fbc15d7 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-02-revA.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u17 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J242 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-03-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-03-revA.dts new file mode 100644 index 00000000000..9ed5b43538c --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-03-revA.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u1 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u3 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + x_prc_si5338: clock-generator@70 { /* U9 */ + compatible = "silabs,si5338"; + reg = <0x70>; /* FIXME */ + }; + }; + }; + + fragment@1 { + target = <&i2c1>; /* Must be enabled via J90/J91 */ + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u2 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-04-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-04-revA.dts new file mode 100644 index 00000000000..47b218dcab4 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-04-revA.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + + si570_gem_tsu: clock-generator@5d { /* u164 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; /* FIXME */ + clock-frequency = <300000000>; + clock-output-names = "si570_gem_tsu_clk"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u153 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA.dts index 1e50075a3dc..986148e5a5c 100644 --- a/arch/arm/dts/zynqmp-a2197-p-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-p-revA.dts @@ -401,46 +401,6 @@ clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; - /* Connection via Samtec J212D */ - /* Use for storing information about X-PRC card */ - x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ - compatible = "atmel,24c02"; - reg = <0x52>; - }; - - /* Use for setting up certain features on X-PRC card */ - x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ - compatible = "nxp,pca9534"; - reg = <0x22>; - gpio-controller; /* IRQ not connected */ - #gpio-cells = <2>; - gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", - "", "", "", ""; - gtr_sel0 { - gpio-hog; - gpios = <0 0>; - input; /* FIXME add meaning */ - line-name = "sw4_1"; - }; - gtr_sel1 { - gpio-hog; - gpios = <1 0>; - input; /* FIXME add meaning */ - line-name = "sw4_2"; - }; - gtr_sel2 { - gpio-hog; - gpios = <2 0>; - input; /* FIXME add meaning */ - line-name = "sw4_3"; - }; - gtr_sel3 { - gpio-hog; - gpios = <3 0>; - input; /* FIXME add meaning */ - line-name = "sw4_4"; - }; - }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>;