From: Lijo Lazar Date: Fri, 10 Jan 2025 07:28:49 +0000 (+0530) Subject: drm/amdgpu: Add VCN v4.0.3 RRMT register offset X-Git-Tag: v6.15-rc1~120^2~17^2~211 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=822b13d19fac05b8299f9e3636dbcce246867d2f;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: Add VCN v4.0.3 RRMT register offset Add RRMT control register offset for VCN v4.0.3 Signed-off-by: Lijo Lazar Reviewed-by: Sathishkumar S Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h index e9742d10de1c6..a0e27aefb56d8 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h @@ -779,7 +779,8 @@ #define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 #define regVCN_RAS_CNTL 0x02df #define regVCN_RAS_CNTL_BASE_IDX 1 - +#define regVCN_RRMT_CNTL 0x0940 +#define regVCN_RRMT_CNTL_BASE_IDX 1 // addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec // base address: 0x20f00