From: Dmitry Osipenko Date: Sat, 24 Nov 2018 21:13:46 +0000 (+0300) Subject: ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+ X-Git-Tag: v5.1-rc1~158^2~3^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=82cdfc382b940b441e93188507c5ae68f9582e3d;p=thirdparty%2Fkernel%2Flinux.git ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+ The memory interface configuration and re-calibration interval are left unassigned on resume from LP1 because these registers are shadowed and require latching after being adjusted. Signed-off-by: Dmitry Osipenko Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Thierry Reding --- diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index dd4a67dabd916..efc6493b61f3a 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -521,6 +521,8 @@ zcal_done: ldr r1, [r5, #0x0] @ restore EMC_CFG str r1, [r0, #EMC_CFG] + emc_timing_update r1, r0 + /* Tegra114 had dual EMC channel, now config the other one */ cmp r10, #TEGRA114 bne __no_dual_emc_chanl