From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Mon, 29 Nov 2021 17:34:44 +0000 (+0100)
Subject: 5.10-stable patches
X-Git-Tag: v5.15.6~12
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8304b863660a51e0f07be3c374291ae5b3d7b895;p=thirdparty%2Fkernel%2Fstable-queue.git

5.10-stable patches

added patches:
	drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch
---

diff --git a/queue-5.10/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch b/queue-5.10/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch
new file mode 100644
index 00000000000..74191e659b6
--- /dev/null
+++ b/queue-5.10/drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch
@@ -0,0 +1,85 @@
+From 53af98c091bc42fd9ec64cfabc40da4e5f3aae93 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Nov 2021 14:50:37 -0500
+Subject: drm/amdgpu/gfx9: switch to golden tsc registers for renoir+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 53af98c091bc42fd9ec64cfabc40da4e5f3aae93 upstream.
+
+Renoir and newer gfx9 APUs have new TSC register that is
+not part of the gfxoff tile, so it can be read without
+needing to disable gfx off.
+
+Acked-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |   46 +++++++++++++++++++++++++---------
+ 1 file changed, 35 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -137,6 +137,11 @@ MODULE_FIRMWARE("amdgpu/green_sardine_rl
+ #define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
+ 
++#define mmGOLDEN_TSC_COUNT_UPPER_Renoir                0x0025
++#define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX       1
++#define mmGOLDEN_TSC_COUNT_LOWER_Renoir                0x0026
++#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX       1
++
+ enum ta_ras_gfx_subblock {
+ 	/*CPC*/
+ 	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+@@ -4147,19 +4152,38 @@ failed_kiq_read:
+ 
+ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
+ {
+-	uint64_t clock;
++	uint64_t clock, clock_lo, clock_hi, hi_check;
+ 
+-	amdgpu_gfx_off_ctrl(adev, false);
+-	mutex_lock(&adev->gfx.gpu_clock_mutex);
+-	if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
+-		clock = gfx_v9_0_kiq_read_clock(adev);
+-	} else {
+-		WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
+-		clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
+-			((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++	switch (adev->asic_type) {
++	case CHIP_RENOIR:
++		preempt_disable();
++		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
++		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
++		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
++		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
++		 * roughly every 42 seconds.
++		 */
++		if (hi_check != clock_hi) {
++			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
++			clock_hi = hi_check;
++		}
++		preempt_enable();
++		clock = clock_lo | (clock_hi << 32ULL);
++		break;
++	default:
++		amdgpu_gfx_off_ctrl(adev, false);
++		mutex_lock(&adev->gfx.gpu_clock_mutex);
++		if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
++			clock = gfx_v9_0_kiq_read_clock(adev);
++		} else {
++			WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
++			clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
++				((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++		}
++		mutex_unlock(&adev->gfx.gpu_clock_mutex);
++		amdgpu_gfx_off_ctrl(adev, true);
++		break;
+ 	}
+-	mutex_unlock(&adev->gfx.gpu_clock_mutex);
+-	amdgpu_gfx_off_ctrl(adev, true);
+ 	return clock;
+ }
+ 
diff --git a/queue-5.10/series b/queue-5.10/series
index 68b0f0a40ee..6486ca6e6ce 100644
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -118,3 +118,4 @@ tty-hvc-replace-bug_on-with-negative-return-value.patch
 s390-mm-validate-vma-in-pgste-manipulation-functions.patch
 shm-extend-forced-shm-destroy-to-support-objects-from-several-ipc-nses.patch
 net-stmmac-platform-fix-build-warning-when-with-config_pm_sleep.patch
+drm-amdgpu-gfx9-switch-to-golden-tsc-registers-for-renoir.patch