From: Anton Blanchard Date: Wed, 30 Oct 2024 04:35:38 +0000 (+1100) Subject: target/riscv: Fix vcompress with rvv_ta_all_1s X-Git-Tag: v7.2.15~12 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=844ffb357a24ac2fae74d73d60a23be9d1db9821;p=thirdparty%2Fqemu.git target/riscv: Fix vcompress with rvv_ta_all_1s vcompress packs vl or less fields into vd, so the tail starts after the last packed field. This could be more clearly expressed in the ISA, but for now this thread helps to explain it: https://github.com/riscv/riscv-v-spec/issues/796 Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241030043538.939712-1-antonb@tenstorrent.com> Signed-off-by: Alistair Francis (cherry picked from commit c128d39edeff337220fc536a3e935bcba01ecb49) Signed-off-by: Michael Tokarev --- diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0020b9a95da..a6ac61c7248 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5273,7 +5273,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ } \ env->vstart = 0; \ /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ + vext_set_elems_1s(vd, vta, num * esz, total_elems * esz); \ } /* Compress into vd elements of vs2 where vs1 is enabled */