From: Bryan O'Donoghue Date: Tue, 11 Jan 2022 12:52:05 +0000 (+0100) Subject: media: dt-bindings: media: camss: Fixup vdda regulator descriptions sdm845 X-Git-Tag: v5.18-rc1~153^2~107 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=849139d46d096bc8022a1a38153e740b464fca46;p=thirdparty%2Fkernel%2Flinux.git media: dt-bindings: media: camss: Fixup vdda regulator descriptions sdm845 If we review the schematic for RB3 Thundercomm document Turbox-845 we see that the CAMSS CSI PHY has the same basic power-rail layout as UFS, PCIe and USB PHYs. We should therefore have two regulator declarations as is the case for UFS, PCIe and USB. Reviewed-by: Robert Foss Signed-off-by: Bryan O'Donoghue Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index 9404d6b9db54c..f9a003882f84f 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -186,9 +186,13 @@ properties: - const: vfe1 - const: vfe_lite - vdda-supply: + vdda-phy-supply: description: - Definition of the regulator used as analog power supply. + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. required: - clock-names @@ -200,7 +204,8 @@ required: - power-domains - reg - reg-names - - vdda-supply + - vdda-phy-supply + - vdda-pll-supply additionalProperties: false @@ -344,7 +349,8 @@ examples: "vfe1", "vfe_lite"; - vdda-supply = <®_2v8>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; ports { #address-cells = <1>;