From: Nicholas Piggin Date: Thu, 5 Sep 2024 22:13:51 +0000 (+1000) Subject: target/ppc: Big-core scratch register fix X-Git-Tag: v9.2.4~50 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=849a6aea3364375da58f5a369a00c1db1ec1b12c;p=thirdparty%2Fqemu.git target/ppc: Big-core scratch register fix The per-core SCRATCH0-7 registers are shared between big cores, which was missed in the big-core implementation. It is difficult to model well with the big-core == 2xPnvCore scheme we moved to, this fix uses the even PnvCore to store the scrach data. Also remove a stray log message that came in with the same patch that introduced patch. Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regular cores") Cc: qemu-stable@nongnu.org Signed-off-by: Nicholas Piggin (cherry picked from commit 9808ce6d5cb75a4f9db76a3d9b508560efdf5ac2) Signed-off-by: Michael Tokarev --- diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index f0ca80153b..af20c39a7a 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -321,6 +321,10 @@ target_ulong helper_load_sprd(CPUPPCState *env) PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; target_ulong sprc = env->spr[SPR_POWER_SPRC]; + if (pc->big_core) { + pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); + } + switch (sprc & 0x3e0) { case 0: /* SCRATCH0-3 */ case 1: /* SCRATCH4-7 */ @@ -357,6 +361,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val) PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; int nr; + if (pc->big_core) { + pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); + } + switch (sprc & 0x3e0) { case 0: /* SCRATCH0-3 */ case 1: /* SCRATCH4-7 */ @@ -367,7 +375,6 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val) * information. Could also dump these upon checkstop. */ nr = (sprc >> 3) & 0x7; - qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr); pc->scratch[nr] = val; break; default: