From: Greg Kroah-Hartman Date: Wed, 9 Oct 2019 09:50:32 +0000 (+0200) Subject: 4.9-stable patches X-Git-Tag: v4.14.149~14 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=84feb66c49bf481aa0376149adf103831acfb0a9;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: coresight-etm4x-use-explicit-barriers-on-enable-disable.patch crypto-caam-fix-concurrency-issue-in-givencrypt-descriptor.patch --- diff --git a/queue-4.9/coresight-etm4x-use-explicit-barriers-on-enable-disable.patch b/queue-4.9/coresight-etm4x-use-explicit-barriers-on-enable-disable.patch new file mode 100644 index 00000000000..bc3bf82bf41 --- /dev/null +++ b/queue-4.9/coresight-etm4x-use-explicit-barriers-on-enable-disable.patch @@ -0,0 +1,72 @@ +From 1004ce4c255fc3eb3ad9145ddd53547d1b7ce327 Mon Sep 17 00:00:00 2001 +From: Andrew Murray +Date: Thu, 29 Aug 2019 14:28:35 -0600 +Subject: coresight: etm4x: Use explicit barriers on enable/disable + +From: Andrew Murray + +commit 1004ce4c255fc3eb3ad9145ddd53547d1b7ce327 upstream. + +Synchronization is recommended before disabling the trace registers +to prevent any start or stop points being speculative at the point +of disabling the unit (section 7.3.77 of ARM IHI 0064D). + +Synchronization is also recommended after programming the trace +registers to ensure all updates are committed prior to normal code +resuming (section 4.3.7 of ARM IHI 0064D). + +Let's ensure these syncronization points are present in the code +and clearly commented. + +Note that we could rely on the barriers in CS_LOCK and +coresight_disclaim_device_unlocked or the context switch to user +space - however coresight may be of use in the kernel. + +On armv8 the mb macro is defined as dsb(sy) - Given that the etm4x is +only used on armv8 let's directly use dsb(sy) instead of mb(). This +removes some ambiguity and makes it easier to correlate the code with +the TRM. + +Signed-off-by: Andrew Murray +Reviewed-by: Suzuki K Poulose +[Fixed capital letter for "use" in title] +Signed-off-by: Mathieu Poirier +Link: https://lore.kernel.org/r/20190829202842.580-11-mathieu.poirier@linaro.org +Cc: stable@vger.kernel.org # 4.9+ +Signed-off-by: Mathieu Poirier +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/hwtracing/coresight/coresight-etm4x.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/hwtracing/coresight/coresight-etm4x.c ++++ b/drivers/hwtracing/coresight/coresight-etm4x.c +@@ -181,6 +181,12 @@ static void etm4_enable_hw(void *info) + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) + dev_err(drvdata->dev, + "timeout while waiting for Idle Trace Status\n"); ++ /* ++ * As recommended by section 4.3.7 ("Synchronization when using the ++ * memory-mapped interface") of ARM IHI 0064D ++ */ ++ dsb(sy); ++ isb(); + + CS_LOCK(drvdata->base); + +@@ -323,8 +329,12 @@ static void etm4_disable_hw(void *info) + /* EN, bit[0] Trace unit enable bit */ + control &= ~0x1; + +- /* make sure everything completes before disabling */ +- mb(); ++ /* ++ * Make sure everything completes before disabling, as recommended ++ * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, ++ * SSTATUS") of ARM IHI 0064D ++ */ ++ dsb(sy); + isb(); + writel_relaxed(control, drvdata->base + TRCPRGCTLR); + diff --git a/queue-4.9/crypto-caam-fix-concurrency-issue-in-givencrypt-descriptor.patch b/queue-4.9/crypto-caam-fix-concurrency-issue-in-givencrypt-descriptor.patch new file mode 100644 index 00000000000..34999dd347d --- /dev/null +++ b/queue-4.9/crypto-caam-fix-concurrency-issue-in-givencrypt-descriptor.patch @@ -0,0 +1,93 @@ +From 48f89d2a2920166c35b1c0b69917dbb0390ebec7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Horia=20Geant=C4=83?= +Date: Tue, 30 Jul 2019 08:48:33 +0300 +Subject: crypto: caam - fix concurrency issue in givencrypt descriptor +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Horia Geantă + +commit 48f89d2a2920166c35b1c0b69917dbb0390ebec7 upstream. + +IV transfer from ofifo to class2 (set up at [29][30]) is not guaranteed +to be scheduled before the data transfer from ofifo to external memory +(set up at [38]: + +[29] 10FA0004 ld: ind-nfifo (len=4) imm +[30] 81F00010 class2 type=msg len=16> +[31] 14820004 ld: ccb2-datasz len=4 offs=0 imm +[32] 00000010 data:0x00000010 +[33] 8210010D operation: cls1-op aes cbc init-final enc +[34] A8080B04 math: (seqin + math0)->vseqout len=4 +[35] 28000010 seqfifold: skip len=16 +[36] A8080A04 math: (seqin + math0)->vseqin len=4 +[37] 2F1E0000 seqfifold: both msg1->2-last2-last1 len=vseqinsz +[38] 69300000 seqfifostr: msg len=vseqoutsz +[39] 5C20000C seqstr: ccb2 ctx len=12 offs=0 + +If ofifo -> external memory transfer happens first, DECO will hang +(issuing a Watchdog Timeout error, if WDOG is enabled) waiting for +data availability in ofifo for the ofifo -> c2 ififo transfer. + +Make sure IV transfer happens first by waiting for all CAAM internal +transfers to end before starting payload transfer. + +New descriptor with jump command inserted at [37]: + +[..] +[36] A8080A04 math: (seqin + math0)->vseqin len=4 +[37] A1000401 jump: jsl1 all-match[!nfifopend] offset=[01] local->[38] +[38] 2F1E0000 seqfifold: both msg1->2-last2-last1 len=vseqinsz +[39] 69300000 seqfifostr: msg len=vseqoutsz +[40] 5C20000C seqstr: ccb2 ctx len=12 offs=0 + +[Note: the issue is present in the descriptor from the very beginning +(cf. Fixes tag). However I've marked it v4.19+ since it's the oldest +maintained kernel that the patch applies clean against.] + +Cc: # v4.19+ +Fixes: 1acebad3d8db8 ("crypto: caam - faster aead implementation") +Signed-off-by: Herbert Xu +[Horia: backport to v4.4, v4.9] +Signed-off-by: Horia Geantă +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/crypto/caam/caamalg.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/drivers/crypto/caam/caamalg.c ++++ b/drivers/crypto/caam/caamalg.c +@@ -75,7 +75,7 @@ + #define DESC_AEAD_BASE (4 * CAAM_CMD_SZ) + #define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 11 * CAAM_CMD_SZ) + #define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 15 * CAAM_CMD_SZ) +-#define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 9 * CAAM_CMD_SZ) ++#define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 10 * CAAM_CMD_SZ) + + /* Note: Nonce is counted in enckeylen */ + #define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ) +@@ -474,6 +474,7 @@ static int aead_set_sh_desc(struct crypt + u32 geniv, moveiv; + u32 ctx1_iv_off = 0; + u32 *desc; ++ u32 *wait_cmd; + const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == + OP_ALG_AAI_CTR_MOD128); + const bool is_rfc3686 = alg->caam.rfc3686; +@@ -736,6 +737,14 @@ copy_iv: + + /* Will read cryptlen */ + append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); ++ ++ /* ++ * Wait for IV transfer (ofifo -> class2) to finish before starting ++ * ciphertext transfer (ofifo -> external memory). ++ */ ++ wait_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | JUMP_COND_NIFP); ++ set_jump_tgt_here(desc, wait_cmd); ++ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | KEY_VLF | + FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LASTBOTH); + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF); diff --git a/queue-4.9/series b/queue-4.9/series index cfb3f29d272..9ddfc8f136f 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -29,3 +29,5 @@ perf-tools-fix-segfault-in-cpu_cache_level__read.patch perf-stat-fix-a-segmentation-fault-when-using-repeat.patch perf-stat-reset-previous-counts-on-repeat-with-inter.patch drm-i915-userptr-acquire-the-page-lock-around-set_pa.patch +crypto-caam-fix-concurrency-issue-in-givencrypt-descriptor.patch +coresight-etm4x-use-explicit-barriers-on-enable-disable.patch