From: Frank Chang <frank.chang@sifive.com>
Date: Tue, 18 Jan 2022 01:45:17 +0000 (+0800)
Subject: target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
X-Git-Tag: v7.0.0-rc0~78^2~29
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8527b5db728b572c288fdcadb126d369040731be;p=thirdparty%2Fqemu.git

target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fe4ad5d008b..b02bb555a6c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2976,6 +2976,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }