From: Greg Kroah-Hartman Date: Sun, 19 Oct 2025 12:09:26 +0000 (+0200) Subject: drop some perf patches from 5.15 that did not build X-Git-Tag: v5.15.195~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8542c7ab7ad3a13849dfe86b1d94f62f1ba7c61b;p=thirdparty%2Fkernel%2Fstable-queue.git drop some perf patches from 5.15 that did not build --- diff --git a/queue-5.15/perf-arm-spe-augment-the-data-source-type-with-neove.patch b/queue-5.15/perf-arm-spe-augment-the-data-source-type-with-neove.patch deleted file mode 100644 index bb5455e4ce..0000000000 --- a/queue-5.15/perf-arm-spe-augment-the-data-source-type-with-neove.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 653349d60f4c061dcccbc356f7c33d79f9efd095 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 26 Sep 2022 21:03:16 +0800 -Subject: perf arm-spe: augment the data source type with neoverse_spe list - -From: Jing Zhang - -[ Upstream commit 74a61d53a6d1ca1172d85964d15c83c2cc3670b3 ] - -When synthesizing event with SPE data source, commit 4e6430cbb1a9("perf -arm-spe: Use SPE data source for neoverse cores") augment the type with -source information by MIDR. However, is_midr_in_range only compares the -first entry in neoverse_spe. - -Change is_midr_in_range to is_midr_in_range_list to traverse the -neoverse_spe array so that all neoverse cores synthesize event with data -source packet. - -Fixes: 4e6430cbb1a9f1dc ("perf arm-spe: Use SPE data source for neoverse cores") -Reviewed-by: Ali Saidi -Reviewed-by: Leo Yan -Signed-off-by: Jing Zhang -Cc: Alexander Shishkin -Cc: Ali Saidi -Cc: German Gomez -Cc: Ingo Molnar -Cc: James Clark -Cc: Jiri Olsa -Cc: John Garry -Cc: linux-arm-kernel@lists.infradead.org -Cc: Mark Rutland -Cc: Mike Leach -Cc: Namhyung Kim -Cc: Peter Zijlstra -Cc: Shuai Xue -Cc: Timothy Hayes -Cc: Will Deacon -Cc: Zhuo Song -Link: https://lore.kernel.org/r/1664197396-42672-1-git-send-email-renyu.zj@linux.alibaba.com -Signed-off-by: Arnaldo Carvalho de Melo -Stable-dep-of: cb300e351505 ("perf arm_spe: Correct memory level for remote access") -Signed-off-by: Sasha Levin ---- - tools/perf/util/arm-spe.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c -index 9e7e56596c60e..2d7fc2b01f36b 100644 ---- a/tools/perf/util/arm-spe.c -+++ b/tools/perf/util/arm-spe.c -@@ -423,7 +423,7 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) - { - union perf_mem_data_src data_src = { 0 }; -- bool is_neoverse = is_midr_in_range(midr, neoverse_spe); -+ bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe); - - if (record->op == ARM_SPE_LD) - data_src.mem_op = PERF_MEM_OP_LOAD; --- -2.51.0 - diff --git a/queue-5.15/perf-arm-spe-refactor-arm-spe-to-support-operation-p.patch b/queue-5.15/perf-arm-spe-refactor-arm-spe-to-support-operation-p.patch deleted file mode 100644 index 336bf78b34..0000000000 --- a/queue-5.15/perf-arm-spe-refactor-arm-spe-to-support-operation-p.patch +++ /dev/null @@ -1,183 +0,0 @@ -From 4ec36ddd5da5384e5bf6e39fcd97518c65ab172b Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 20 Mar 2023 15:15:06 +0000 -Subject: perf arm-spe: Refactor arm-spe to support operation packet type - -From: German Gomez - -[ Upstream commit 0066015a3d8f9c01a17eb04579edba7dac9510af ] - -Extend the decoder of Arm SPE records to support more fields from the -operation packet type. - -Not all fields are being decoded by this commit. Only those needed to -support the use-case SVE load/store/other operations. - -Suggested-by: Leo Yan -Signed-off-by: German Gomez -Acked-by: Ian Rogers -Cc: Adrian Hunter -Cc: Alexander Shishkin -Cc: Anshuman.Khandual@arm.com -Cc: Ingo Molnar -Cc: Jiri Olsa -Cc: John Garry -Cc: Mark Rutland -Cc: Mike Leach -Cc: Namhyung Kim -Cc: Peter Zijlstra -Cc: Will Deacon -Cc: linux-arm-kernel@lists.infradead.org -Link: https://lore.kernel.org/r/20230320151509.1137462-2-james.clark@arm.com -Signed-off-by: James Clark -Signed-off-by: Arnaldo Carvalho de Melo -Stable-dep-of: cb300e351505 ("perf arm_spe: Correct memory level for remote access") -Signed-off-by: Sasha Levin ---- - .../util/arm-spe-decoder/arm-spe-decoder.c | 30 ++++++++++-- - .../util/arm-spe-decoder/arm-spe-decoder.h | 47 +++++++++++++++---- - tools/perf/util/arm-spe.c | 8 ++-- - 3 files changed, 67 insertions(+), 18 deletions(-) - -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -index 3e36934477154..3b937e89654f4 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -@@ -184,11 +184,27 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) - decoder->record.context_id = payload; - break; - case ARM_SPE_OP_TYPE: -- if (idx == SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC) { -- if (payload & 0x1) -- decoder->record.op = ARM_SPE_ST; -+ switch (idx) { -+ case SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC: -+ decoder->record.op |= ARM_SPE_OP_LDST; -+ if (payload & SPE_OP_PKT_ST) -+ decoder->record.op |= ARM_SPE_OP_ST; - else -- decoder->record.op = ARM_SPE_LD; -+ decoder->record.op |= ARM_SPE_OP_LD; -+ if (SPE_OP_PKT_IS_LDST_SVE(payload)) -+ decoder->record.op |= ARM_SPE_OP_SVE_LDST; -+ break; -+ case SPE_OP_PKT_HDR_CLASS_OTHER: -+ decoder->record.op |= ARM_SPE_OP_OTHER; -+ if (SPE_OP_PKT_IS_OTHER_SVE_OP(payload)) -+ decoder->record.op |= ARM_SPE_OP_SVE_OTHER; -+ break; -+ case SPE_OP_PKT_HDR_CLASS_BR_ERET: -+ decoder->record.op |= ARM_SPE_OP_BRANCH_ERET; -+ break; -+ default: -+ pr_err("Get packet error!\n"); -+ return -1; - } - break; - case ARM_SPE_EVENTS: -@@ -216,6 +232,12 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) - if (payload & BIT(EV_MISPRED)) - decoder->record.type |= ARM_SPE_BRANCH_MISS; - -+ if (payload & BIT(EV_PARTIAL_PREDICATE)) -+ decoder->record.type |= ARM_SPE_SVE_PARTIAL_PRED; -+ -+ if (payload & BIT(EV_EMPTY_PREDICATE)) -+ decoder->record.type |= ARM_SPE_SVE_EMPTY_PRED; -+ - break; - case ARM_SPE_DATA_SOURCE: - decoder->record.source = payload; -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -index c3943eb95e305..fa269c9c53b33 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -@@ -14,19 +14,46 @@ - #include "arm-spe-pkt-decoder.h" - - enum arm_spe_sample_type { -- ARM_SPE_L1D_ACCESS = 1 << 0, -- ARM_SPE_L1D_MISS = 1 << 1, -- ARM_SPE_LLC_ACCESS = 1 << 2, -- ARM_SPE_LLC_MISS = 1 << 3, -- ARM_SPE_TLB_ACCESS = 1 << 4, -- ARM_SPE_TLB_MISS = 1 << 5, -- ARM_SPE_BRANCH_MISS = 1 << 6, -- ARM_SPE_REMOTE_ACCESS = 1 << 7, -+ ARM_SPE_L1D_ACCESS = 1 << 0, -+ ARM_SPE_L1D_MISS = 1 << 1, -+ ARM_SPE_LLC_ACCESS = 1 << 2, -+ ARM_SPE_LLC_MISS = 1 << 3, -+ ARM_SPE_TLB_ACCESS = 1 << 4, -+ ARM_SPE_TLB_MISS = 1 << 5, -+ ARM_SPE_BRANCH_MISS = 1 << 6, -+ ARM_SPE_REMOTE_ACCESS = 1 << 7, -+ ARM_SPE_SVE_PARTIAL_PRED = 1 << 8, -+ ARM_SPE_SVE_EMPTY_PRED = 1 << 9, - }; - - enum arm_spe_op_type { -- ARM_SPE_LD = 1 << 0, -- ARM_SPE_ST = 1 << 1, -+ /* First level operation type */ -+ ARM_SPE_OP_OTHER = 1 << 0, -+ ARM_SPE_OP_LDST = 1 << 1, -+ ARM_SPE_OP_BRANCH_ERET = 1 << 2, -+ -+ /* Second level operation type for OTHER */ -+ ARM_SPE_OP_SVE_OTHER = 1 << 16, -+ ARM_SPE_OP_SVE_FP = 1 << 17, -+ ARM_SPE_OP_SVE_PRED_OTHER = 1 << 18, -+ -+ /* Second level operation type for LDST */ -+ ARM_SPE_OP_LD = 1 << 16, -+ ARM_SPE_OP_ST = 1 << 17, -+ ARM_SPE_OP_ATOMIC = 1 << 18, -+ ARM_SPE_OP_EXCL = 1 << 19, -+ ARM_SPE_OP_AR = 1 << 20, -+ ARM_SPE_OP_SIMD_FP = 1 << 21, -+ ARM_SPE_OP_GP_REG = 1 << 22, -+ ARM_SPE_OP_UNSPEC_REG = 1 << 23, -+ ARM_SPE_OP_NV_SYSREG = 1 << 24, -+ ARM_SPE_OP_SVE_LDST = 1 << 25, -+ ARM_SPE_OP_SVE_PRED_LDST = 1 << 26, -+ ARM_SPE_OP_SVE_SG = 1 << 27, -+ -+ /* Second level operation type for BRANCH_ERET */ -+ ARM_SPE_OP_BR_COND = 1 << 16, -+ ARM_SPE_OP_BR_INDIRECT = 1 << 17, - }; - - enum arm_spe_neoverse_data_source { -diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c -index 2d7fc2b01f36b..c86e60b5954c5 100644 ---- a/tools/perf/util/arm-spe.c -+++ b/tools/perf/util/arm-spe.c -@@ -336,7 +336,7 @@ static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *rec - * We have no data on the hit level or data source for stores in the - * Neoverse SPE records. - */ -- if (record->op & ARM_SPE_ST) { -+ if (record->op & ARM_SPE_OP_ST) { - data_src->mem_lvl = PERF_MEM_LVL_NA; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA; - data_src->mem_snoop = PERF_MEM_SNOOP_NA; -@@ -422,12 +422,12 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco - - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) - { -- union perf_mem_data_src data_src = { 0 }; -+ union perf_mem_data_src data_src = { .mem_op = PERF_MEM_OP_NA }; - bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe); - -- if (record->op == ARM_SPE_LD) -+ if (record->op & ARM_SPE_OP_LD) - data_src.mem_op = PERF_MEM_OP_LOAD; -- else if (record->op == ARM_SPE_ST) -+ else if (record->op & ARM_SPE_OP_ST) - data_src.mem_op = PERF_MEM_OP_STORE; - else - return 0; --- -2.51.0 - diff --git a/queue-5.15/perf-arm-spe-rename-the-common-data-source-encoding.patch b/queue-5.15/perf-arm-spe-rename-the-common-data-source-encoding.patch deleted file mode 100644 index e4d36f6f11..0000000000 --- a/queue-5.15/perf-arm-spe-rename-the-common-data-source-encoding.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 2682f978eb47e3f63dc0745dbbb1a849e1b07584 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Thu, 3 Oct 2024 19:53:17 +0100 -Subject: perf arm-spe: Rename the common data source encoding - -From: Leo Yan - -[ Upstream commit 50b8f1d5bf4ad7f09ef8012ccf5f94f741df827b ] - -The Neoverse CPUs follow the common data source encoding, and other -CPU variants can share the same format. - -Rename the CPU list and data source definitions as common data source -names. This change prepares for appending more CPU variants. - -Signed-off-by: Leo Yan -Reviewed-by: James Clark -Link: https://lore.kernel.org/r/20241003185322.192357-3-leo.yan@arm.com -Signed-off-by: Namhyung Kim -Stable-dep-of: cb300e351505 ("perf arm_spe: Correct memory level for remote access") -Signed-off-by: Sasha Levin ---- - .../util/arm-spe-decoder/arm-spe-decoder.h | 18 ++++++------ - tools/perf/util/arm-spe.c | 28 +++++++++---------- - 2 files changed, 23 insertions(+), 23 deletions(-) - -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -index fa269c9c53b33..d9166794e527f 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -@@ -56,15 +56,15 @@ enum arm_spe_op_type { - ARM_SPE_OP_BR_INDIRECT = 1 << 17, - }; - --enum arm_spe_neoverse_data_source { -- ARM_SPE_NV_L1D = 0x0, -- ARM_SPE_NV_L2 = 0x8, -- ARM_SPE_NV_PEER_CORE = 0x9, -- ARM_SPE_NV_LOCAL_CLUSTER = 0xa, -- ARM_SPE_NV_SYS_CACHE = 0xb, -- ARM_SPE_NV_PEER_CLUSTER = 0xc, -- ARM_SPE_NV_REMOTE = 0xd, -- ARM_SPE_NV_DRAM = 0xe, -+enum arm_spe_common_data_source { -+ ARM_SPE_COMMON_DS_L1D = 0x0, -+ ARM_SPE_COMMON_DS_L2 = 0x8, -+ ARM_SPE_COMMON_DS_PEER_CORE = 0x9, -+ ARM_SPE_COMMON_DS_LOCAL_CLUSTER = 0xa, -+ ARM_SPE_COMMON_DS_SYS_CACHE = 0xb, -+ ARM_SPE_COMMON_DS_PEER_CLUSTER = 0xc, -+ ARM_SPE_COMMON_DS_REMOTE = 0xd, -+ ARM_SPE_COMMON_DS_DRAM = 0xe, - }; - - struct arm_spe_record { -diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c -index c86e60b5954c5..68445c1e1db3b 100644 ---- a/tools/perf/util/arm-spe.c -+++ b/tools/perf/util/arm-spe.c -@@ -314,15 +314,15 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq, - return arm_spe_deliver_synth_event(spe, speq, event, &sample); - } - --static const struct midr_range neoverse_spe[] = { -+static const struct midr_range common_ds_encoding_cpus[] = { - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), - {}, - }; - --static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record, -- union perf_mem_data_src *data_src) -+static void arm_spe__synth_data_source_common(const struct arm_spe_record *record, -+ union perf_mem_data_src *data_src) - { - /* - * Even though four levels of cache hierarchy are possible, no known -@@ -344,17 +344,17 @@ static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *rec - } - - switch (record->source) { -- case ARM_SPE_NV_L1D: -+ case ARM_SPE_COMMON_DS_L1D: - data_src->mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1; - data_src->mem_snoop = PERF_MEM_SNOOP_NONE; - break; -- case ARM_SPE_NV_L2: -+ case ARM_SPE_COMMON_DS_L2: - data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2; - data_src->mem_snoop = PERF_MEM_SNOOP_NONE; - break; -- case ARM_SPE_NV_PEER_CORE: -+ case ARM_SPE_COMMON_DS_PEER_CORE: - data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2; - data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; -@@ -363,8 +363,8 @@ static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *rec - * We don't know if this is L1, L2 but we do know it was a cache-2-cache - * transfer, so set SNOOPX_PEER - */ -- case ARM_SPE_NV_LOCAL_CLUSTER: -- case ARM_SPE_NV_PEER_CLUSTER: -+ case ARM_SPE_COMMON_DS_LOCAL_CLUSTER: -+ case ARM_SPE_COMMON_DS_PEER_CLUSTER: - data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3; - data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; -@@ -372,7 +372,7 @@ static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *rec - /* - * System cache is assumed to be L3 - */ -- case ARM_SPE_NV_SYS_CACHE: -+ case ARM_SPE_COMMON_DS_SYS_CACHE: - data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3; - data_src->mem_snoop = PERF_MEM_SNOOP_HIT; -@@ -381,13 +381,13 @@ static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *rec - * We don't know what level it hit in, except it came from the other - * socket - */ -- case ARM_SPE_NV_REMOTE: -+ case ARM_SPE_COMMON_DS_REMOTE: - data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE; - data_src->mem_remote = PERF_MEM_REMOTE_REMOTE; - data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; - break; -- case ARM_SPE_NV_DRAM: -+ case ARM_SPE_COMMON_DS_DRAM: - data_src->mem_lvl = PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT; - data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM; - data_src->mem_snoop = PERF_MEM_SNOOP_NONE; -@@ -423,7 +423,7 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) - { - union perf_mem_data_src data_src = { .mem_op = PERF_MEM_OP_NA }; -- bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe); -+ bool is_common = is_midr_in_range_list(midr, common_ds_encoding_cpus); - - if (record->op & ARM_SPE_OP_LD) - data_src.mem_op = PERF_MEM_OP_LOAD; -@@ -432,8 +432,8 @@ static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 m - else - return 0; - -- if (is_neoverse) -- arm_spe__synth_data_source_neoverse(record, &data_src); -+ if (is_common) -+ arm_spe__synth_data_source_common(record, &data_src); - else - arm_spe__synth_data_source_generic(record, &data_src); - --- -2.51.0 - diff --git a/queue-5.15/perf-arm-spe-save-context-id-in-record.patch b/queue-5.15/perf-arm-spe-save-context-id-in-record.patch deleted file mode 100644 index 890cc1dd84..0000000000 --- a/queue-5.15/perf-arm-spe-save-context-id-in-record.patch +++ /dev/null @@ -1,66 +0,0 @@ -From ad7020e05e83a6049b828ad6de58864d864d02c9 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Thu, 11 Nov 2021 13:36:24 +0000 -Subject: perf arm-spe: Save context ID in record - -From: German Gomez - -[ Upstream commit 169de64f5dc22d9984d45c1f119fb644fa16d64a ] - -This patch is to save context ID in record, this will be used to set TID -for samples. - -Reviewed-by: Leo Yan -Signed-off-by: German Gomez -Acked-by: Namhyung Kim -Cc: Alexander Shishkin -Cc: Jiri Olsa -Cc: John Garry -Cc: Mark Rutland -Cc: Mathieu Poirier -Cc: Will Deacon -Cc: linux-arm-kernel@lists.infradead.org -Link: https://lore.kernel.org/r/20211111133625.193568-4-german.gomez@arm.com -Signed-off-by: Arnaldo Carvalho de Melo -Stable-dep-of: 039fd0634a06 ("perf arm_spe: Correct setting remote access") -Signed-off-by: Sasha Levin ---- - tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 2 ++ - tools/perf/util/arm-spe-decoder/arm-spe-decoder.h | 1 + - 2 files changed, 3 insertions(+) - -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -index 32fe41835fa68..3fc528c9270c2 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -@@ -151,6 +151,7 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) - u64 payload, ip; - - memset(&decoder->record, 0x0, sizeof(decoder->record)); -+ decoder->record.context_id = (u64)-1; - - while (1) { - err = arm_spe_get_next_packet(decoder); -@@ -180,6 +181,7 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) - case ARM_SPE_COUNTER: - break; - case ARM_SPE_CONTEXT: -+ decoder->record.context_id = payload; - break; - case ARM_SPE_OP_TYPE: - if (idx == SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC) { -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -index 59bdb73096741..46a8556a9e956 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -@@ -38,6 +38,7 @@ struct arm_spe_record { - u64 timestamp; - u64 virt_addr; - u64 phys_addr; -+ u64 context_id; - }; - - struct arm_spe_insn; --- -2.51.0 - diff --git a/queue-5.15/perf-arm-spe-use-spe-data-source-for-neoverse-cores.patch b/queue-5.15/perf-arm-spe-use-spe-data-source-for-neoverse-cores.patch deleted file mode 100644 index 0b02040db0..0000000000 --- a/queue-5.15/perf-arm-spe-use-spe-data-source-for-neoverse-cores.patch +++ /dev/null @@ -1,286 +0,0 @@ -From c921941a6d3aafe12beba046b9e0b95909d3dc54 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Thu, 11 Aug 2022 14:24:39 +0800 -Subject: perf arm-spe: Use SPE data source for neoverse cores - -From: Ali Saidi - -[ Upstream commit 4e6430cbb1a9f1dc0a698f93026b6178da437798 ] - -When synthesizing data from SPE, augment the type with source information -for Arm Neoverse cores. The field is IMPLDEF but the Neoverse cores all use -the same encoding. I can't find encoding information for any other SPE -implementations to unify their choices with Arm's thus that is left for -future work. - -This change populates the mem_lvl_num for Neoverse cores as well as the -deprecated mem_lvl namespace. - -Reviewed-by: German Gomez -Reviewed-by: Leo Yan -Signed-off-by: Ali Saidi -Tested-by: Leo Yan -Cc: Adrian Hunter -Cc: Alexander Shishkin -Cc: Anshuman Khandual -Cc: Gustavo A. R. Silva -Cc: Ian Rogers -Cc: Ingo Molnar -Cc: James Clark -Cc: Jiri Olsa -Cc: John Garry -Cc: Kajol Jain -Cc: Like Xu -Cc: Mark Rutland -Cc: Mike Leach -Cc: Namhyung Kim -Cc: Peter Zijlstra -Cc: Timothy Hayes -Cc: Will Deacon -Cc: linux-arm-kernel@lists.infradead.org -Link: https://lore.kernel.org/r/20220811062451.435810-4-leo.yan@linaro.org -Signed-off-by: Leo Yan -Signed-off-by: Arnaldo Carvalho de Melo -Stable-dep-of: 039fd0634a06 ("perf arm_spe: Correct setting remote access") -Signed-off-by: Sasha Levin ---- - .../util/arm-spe-decoder/arm-spe-decoder.c | 1 + - .../util/arm-spe-decoder/arm-spe-decoder.h | 12 ++ - tools/perf/util/arm-spe.c | 130 +++++++++++++++--- - 3 files changed, 127 insertions(+), 16 deletions(-) - -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -index 3fc528c9270c2..3e36934477154 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c -@@ -218,6 +218,7 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) - - break; - case ARM_SPE_DATA_SOURCE: -+ decoder->record.source = payload; - break; - case ARM_SPE_BAD: - break; -diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -index 46a8556a9e956..c3943eb95e305 100644 ---- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h -@@ -29,6 +29,17 @@ enum arm_spe_op_type { - ARM_SPE_ST = 1 << 1, - }; - -+enum arm_spe_neoverse_data_source { -+ ARM_SPE_NV_L1D = 0x0, -+ ARM_SPE_NV_L2 = 0x8, -+ ARM_SPE_NV_PEER_CORE = 0x9, -+ ARM_SPE_NV_LOCAL_CLUSTER = 0xa, -+ ARM_SPE_NV_SYS_CACHE = 0xb, -+ ARM_SPE_NV_PEER_CLUSTER = 0xc, -+ ARM_SPE_NV_REMOTE = 0xd, -+ ARM_SPE_NV_DRAM = 0xe, -+}; -+ - struct arm_spe_record { - enum arm_spe_sample_type type; - int err; -@@ -39,6 +50,7 @@ struct arm_spe_record { - u64 virt_addr; - u64 phys_addr; - u64 context_id; -+ u16 source; - }; - - struct arm_spe_insn; -diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c -index 569e1b8ad0abc..7b16898af4e7f 100644 ---- a/tools/perf/util/arm-spe.c -+++ b/tools/perf/util/arm-spe.c -@@ -34,6 +34,7 @@ - #include "arm-spe-decoder/arm-spe-decoder.h" - #include "arm-spe-decoder/arm-spe-pkt-decoder.h" - -+#include "../../arch/arm64/include/asm/cputype.h" - #define MAX_TIMESTAMP (~0ULL) - - struct arm_spe { -@@ -45,6 +46,7 @@ struct arm_spe { - struct perf_session *session; - struct machine *machine; - u32 pmu_type; -+ u64 midr; - - struct perf_tsc_conversion tc; - -@@ -312,35 +314,128 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq, - return arm_spe_deliver_synth_event(spe, speq, event, &sample); - } - --static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) -+static const struct midr_range neoverse_spe[] = { -+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), -+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), -+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), -+ {}, -+}; -+ -+static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record, -+ union perf_mem_data_src *data_src) - { -- union perf_mem_data_src data_src = { 0 }; -+ /* -+ * Even though four levels of cache hierarchy are possible, no known -+ * production Neoverse systems currently include more than three levels -+ * so for the time being we assume three exist. If a production system -+ * is built with four the this function would have to be changed to -+ * detect the number of levels for reporting. -+ */ - -- if (record->op == ARM_SPE_LD) -- data_src.mem_op = PERF_MEM_OP_LOAD; -- else if (record->op == ARM_SPE_ST) -- data_src.mem_op = PERF_MEM_OP_STORE; -- else -- return 0; -+ /* -+ * We have no data on the hit level or data source for stores in the -+ * Neoverse SPE records. -+ */ -+ if (record->op & ARM_SPE_ST) { -+ data_src->mem_lvl = PERF_MEM_LVL_NA; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA; -+ data_src->mem_snoop = PERF_MEM_SNOOP_NA; -+ return; -+ } -+ -+ switch (record->source) { -+ case ARM_SPE_NV_L1D: -+ data_src->mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1; -+ data_src->mem_snoop = PERF_MEM_SNOOP_NONE; -+ break; -+ case ARM_SPE_NV_L2: -+ data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2; -+ data_src->mem_snoop = PERF_MEM_SNOOP_NONE; -+ break; -+ case ARM_SPE_NV_PEER_CORE: -+ data_src->mem_lvl = PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_L2; -+ data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; -+ break; -+ /* -+ * We don't know if this is L1, L2 but we do know it was a cache-2-cache -+ * transfer, so set SNOOPX_PEER -+ */ -+ case ARM_SPE_NV_LOCAL_CLUSTER: -+ case ARM_SPE_NV_PEER_CLUSTER: -+ data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3; -+ data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; -+ break; -+ /* -+ * System cache is assumed to be L3 -+ */ -+ case ARM_SPE_NV_SYS_CACHE: -+ data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3; -+ data_src->mem_snoop = PERF_MEM_SNOOP_HIT; -+ break; -+ /* -+ * We don't know what level it hit in, except it came from the other -+ * socket -+ */ -+ case ARM_SPE_NV_REMOTE: -+ data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE; -+ data_src->mem_remote = PERF_MEM_REMOTE_REMOTE; -+ data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; -+ break; -+ case ARM_SPE_NV_DRAM: -+ data_src->mem_lvl = PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_RAM; -+ data_src->mem_snoop = PERF_MEM_SNOOP_NONE; -+ break; -+ default: -+ break; -+ } -+} - -+static void arm_spe__synth_data_source_generic(const struct arm_spe_record *record, -+ union perf_mem_data_src *data_src) -+{ - if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { -- data_src.mem_lvl = PERF_MEM_LVL_L3; -+ data_src->mem_lvl = PERF_MEM_LVL_L3; - - if (record->type & ARM_SPE_LLC_MISS) -- data_src.mem_lvl |= PERF_MEM_LVL_MISS; -+ data_src->mem_lvl |= PERF_MEM_LVL_MISS; - else -- data_src.mem_lvl |= PERF_MEM_LVL_HIT; -+ data_src->mem_lvl |= PERF_MEM_LVL_HIT; - } else if (record->type & (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS)) { -- data_src.mem_lvl = PERF_MEM_LVL_L1; -+ data_src->mem_lvl = PERF_MEM_LVL_L1; - - if (record->type & ARM_SPE_L1D_MISS) -- data_src.mem_lvl |= PERF_MEM_LVL_MISS; -+ data_src->mem_lvl |= PERF_MEM_LVL_MISS; - else -- data_src.mem_lvl |= PERF_MEM_LVL_HIT; -+ data_src->mem_lvl |= PERF_MEM_LVL_HIT; - } - - if (record->type & ARM_SPE_REMOTE_ACCESS) -- data_src.mem_lvl |= PERF_MEM_LVL_REM_CCE1; -+ data_src->mem_lvl |= PERF_MEM_LVL_REM_CCE1; -+} -+ -+static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) -+{ -+ union perf_mem_data_src data_src = { 0 }; -+ bool is_neoverse = is_midr_in_range(midr, neoverse_spe); -+ -+ if (record->op == ARM_SPE_LD) -+ data_src.mem_op = PERF_MEM_OP_LOAD; -+ else if (record->op == ARM_SPE_ST) -+ data_src.mem_op = PERF_MEM_OP_STORE; -+ else -+ return 0; -+ -+ if (is_neoverse) -+ arm_spe__synth_data_source_neoverse(record, &data_src); -+ else -+ arm_spe__synth_data_source_generic(record, &data_src); - - if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) { - data_src.mem_dtlb = PERF_MEM_TLB_WK; -@@ -361,7 +456,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) - u64 data_src; - int err; - -- data_src = arm_spe__synth_data_source(record); -+ data_src = arm_spe__synth_data_source(record, spe->midr); - - if (spe->sample_flc) { - if (record->type & ARM_SPE_L1D_MISS) { -@@ -1047,6 +1142,8 @@ int arm_spe_process_auxtrace_info(union perf_event *event, - struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; - size_t min_sz = sizeof(u64) * ARM_SPE_AUXTRACE_PRIV_MAX; - struct perf_record_time_conv *tc = &session->time_conv; -+ const char *cpuid = perf_env__cpuid(session->evlist->env); -+ u64 midr = strtol(cpuid, NULL, 16); - struct arm_spe *spe; - int err; - -@@ -1066,6 +1163,7 @@ int arm_spe_process_auxtrace_info(union perf_event *event, - spe->machine = &session->machines.host; /* No kvm support */ - spe->auxtrace_type = auxtrace_info->type; - spe->pmu_type = auxtrace_info->priv[ARM_SPE_PMU_TYPE]; -+ spe->midr = midr; - - spe->timeless_decoding = arm_spe__is_timeless_decoding(spe); - --- -2.51.0 - diff --git a/queue-5.15/perf-arm_spe-correct-memory-level-for-remote-access.patch b/queue-5.15/perf-arm_spe-correct-memory-level-for-remote-access.patch deleted file mode 100644 index 17d7e9e20f..0000000000 --- a/queue-5.15/perf-arm_spe-correct-memory-level-for-remote-access.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 67f619bb4b76be404b427893d3befb7b3aad0929 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 12 Sep 2025 16:42:09 +0100 -Subject: perf arm_spe: Correct memory level for remote access - -From: Leo Yan - -[ Upstream commit cb300e3515057fb555983ce47e8acc86a5c69c3c ] - -For remote accesses, the data source packet does not contain information -about the memory level. To avoid misinformation, set the memory level to -NA (Not Available). - -Fixes: 4e6430cbb1a9f1dc ("perf arm-spe: Use SPE data source for neoverse cores") -Reviewed-by: James Clark -Signed-off-by: Leo Yan -Cc: Adrian Hunter -Cc: Alexander Shishkin -Cc: Ali Saidi -Cc: German Gomez -Cc: Ian Rogers -Cc: Jiri Olsa -Cc: Mark Rutland -Cc: Namhyung Kim -Cc: Will Deacon -Signed-off-by: Arnaldo Carvalho de Melo -Signed-off-by: Sasha Levin ---- - tools/perf/util/arm-spe.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c -index 68445c1e1db3b..98d6cfadb1130 100644 ---- a/tools/perf/util/arm-spe.c -+++ b/tools/perf/util/arm-spe.c -@@ -382,8 +382,8 @@ static void arm_spe__synth_data_source_common(const struct arm_spe_record *recor - * socket - */ - case ARM_SPE_COMMON_DS_REMOTE: -- data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1; -- data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE; -+ data_src->mem_lvl = PERF_MEM_LVL_NA; -+ data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA; - data_src->mem_remote = PERF_MEM_REMOTE_REMOTE; - data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER; - break; --- -2.51.0 - diff --git a/queue-5.15/perf-arm_spe-correct-setting-remote-access.patch b/queue-5.15/perf-arm_spe-correct-setting-remote-access.patch deleted file mode 100644 index 451d787a3a..0000000000 --- a/queue-5.15/perf-arm_spe-correct-setting-remote-access.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 0c2f44bd920716a99c70d623ef2a7ab46d06dbb2 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 12 Sep 2025 16:42:08 +0100 -Subject: perf arm_spe: Correct setting remote access - -From: Leo Yan - -[ Upstream commit 039fd0634a0629132432632d7ac9a14915406b5c ] - -Set the mem_remote field for a remote access to appropriately represent -the event. - -Fixes: a89dbc9b988f3ba8 ("perf arm-spe: Set sample's data source field") -Reviewed-by: James Clark -Signed-off-by: Leo Yan -Cc: Adrian Hunter -Cc: Alexander Shishkin -Cc: Ali Saidi -Cc: German Gomez -Cc: Ian Rogers -Cc: Jiri Olsa -Cc: Mark Rutland -Cc: Namhyung Kim -Cc: Will Deacon -Signed-off-by: Arnaldo Carvalho de Melo -Signed-off-by: Sasha Levin ---- - tools/perf/util/arm-spe.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c -index 7b16898af4e7f..9e7e56596c60e 100644 ---- a/tools/perf/util/arm-spe.c -+++ b/tools/perf/util/arm-spe.c -@@ -417,7 +417,7 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco - } - - if (record->type & ARM_SPE_REMOTE_ACCESS) -- data_src->mem_lvl |= PERF_MEM_LVL_REM_CCE1; -+ data_src->mem_remote = PERF_MEM_REMOTE_REMOTE; - } - - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) --- -2.51.0 - diff --git a/queue-5.15/series b/queue-5.15/series index 3c28e1ca42..050eedacba 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -125,13 +125,6 @@ libperf-event-ensure-tracing-data-is-multiple-of-8-s.patch clk-at91-peripheral-fix-return-value.patch perf-util-fix-compression-checks-returning-1-as-bool.patch rtc-x1205-fix-xicor-x1205-vendor-prefix.patch -perf-arm-spe-save-context-id-in-record.patch -perf-arm-spe-use-spe-data-source-for-neoverse-cores.patch -perf-arm_spe-correct-setting-remote-access.patch -perf-arm-spe-augment-the-data-source-type-with-neove.patch -perf-arm-spe-refactor-arm-spe-to-support-operation-p.patch -perf-arm-spe-rename-the-common-data-source-encoding.patch -perf-arm_spe-correct-memory-level-for-remote-access.patch perf-session-fix-handling-when-buffer-exceeds-2-gib.patch perf-test-don-t-leak-workload-gopipe-in-perf_record_.patch clk-nxp-lpc18xx-cgu-convert-from-round_rate-to-deter.patch