From: Stanislav Lisovskiy Date: Tue, 14 Jun 2022 12:30:49 +0000 (+0300) Subject: drm/i915/dg2: Bump up CDCLK for DG2 X-Git-Tag: v6.1-rc1~159^2~13^2~80 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=859161b952a453b86362f168fadef72a8ba31a05;p=thirdparty%2Fkernel%2Flinux.git drm/i915/dg2: Bump up CDCLK for DG2 We seem to need this W/A same way as for TGL, in order to fix some of the underruns, which we currently have and those not related to PSR. Signed-off-by: Stanislav Lisovskiy Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20220614123049.16183-2-stanislav.lisovskiy@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 6e80162632ddf..86a22c3766e52 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2300,7 +2300,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); /* - * HACK. Currently for TGL platforms we calculate + * HACK. Currently for TGL/DG2 platforms we calculate * min_cdclk initially based on pixel_rate divided * by 2, accounting for also plane requirements, * however in some cases the lowest possible CDCLK @@ -2308,7 +2308,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * Explicitly stating here that this seems to be currently * rather a Hack, than final solution. */ - if (IS_TIGERLAKE(dev_priv)) { + if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { /* * Clamp to max_cdclk_freq in case pixel rate is higher, * in order not to break an 8K, but still leave W/A at place.