From: Greg Kroah-Hartman Date: Thu, 16 Aug 2012 23:27:26 +0000 (-0700) Subject: 3.0-stable patches X-Git-Tag: v3.5.3~26 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=86069feae679ce00238913ebc68a23fef99c96c8;p=thirdparty%2Fkernel%2Fstable-queue.git 3.0-stable patches added patches: drm-i915-correctly-order-the-ring-init-sequence.patch --- diff --git a/queue-3.0/drm-i915-correctly-order-the-ring-init-sequence.patch b/queue-3.0/drm-i915-correctly-order-the-ring-init-sequence.patch new file mode 100644 index 00000000000..719d4818aa7 --- /dev/null +++ b/queue-3.0/drm-i915-correctly-order-the-ring-init-sequence.patch @@ -0,0 +1,47 @@ +From 0d8957c8a90bbb5d34fab9a304459448a5131e06 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Tue, 7 Aug 2012 09:54:14 +0200 +Subject: drm/i915: correctly order the ring init sequence + +From: Daniel Vetter + +commit 0d8957c8a90bbb5d34fab9a304459448a5131e06 upstream. + +We may only start to set up the new register values after having +confirmed that the ring is truely off. Otherwise the hw might lose the +newly written register values. This is caught later on in the init +sequence, when we check whether the register writes have stuck. + +Reviewed-by: Jani Nikula +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 +Tested-by: Yang Guang +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -150,8 +150,6 @@ static int init_ring_common(struct intel + I915_WRITE_HEAD(ring, 0); + ring->write_tail(ring, 0); + +- /* Initialize the ring. */ +- I915_WRITE_START(ring, obj->gtt_offset); + head = I915_READ_HEAD(ring) & HEAD_ADDR; + + /* G45 ring initialization fails to reset head to zero */ +@@ -177,6 +175,11 @@ static int init_ring_common(struct intel + } + } + ++ /* Initialize the ring. This must happen _after_ we've cleared the ring ++ * registers with the above sequence (the readback of the HEAD registers ++ * also enforces ordering), otherwise the hw might lose the new ring ++ * register values. */ ++ I915_WRITE_START(ring, obj->gtt_offset); + I915_WRITE_CTL(ring, + ((ring->size - PAGE_SIZE) & RING_NR_PAGES) + | RING_REPORT_64K | RING_VALID); diff --git a/queue-3.0/series b/queue-3.0/series index 8afbfd47318..ab2540284bd 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -2,3 +2,4 @@ s390-compat-fix-mmap-compat-system-calls.patch fuse-verify-all-ioctl-retry-iov-elements.patch xen-p2m-reserve-8mb-of-_brk-space-for-p2m-leafs-when-populating-back.patch xen-mark-local-pages-as-foreign-in-the-m2p_override.patch +drm-i915-correctly-order-the-ring-init-sequence.patch