From: Alistair Francis <alistair.francis@wdc.com>
Date: Fri, 27 Mar 2020 19:54:45 +0000 (-0700)
Subject: target/riscv: Report errors validating 2nd-stage PTEs
X-Git-Tag: v5.1.0-rc0~58^2~24
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=88914473e748db20d8e18b9735f647a683319fa6;p=thirdparty%2Fqemu.git

target/riscv: Report errors validating 2nd-stage PTEs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index eda7057663e..75d2ae34349 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,8 +435,13 @@ restart:
             hwaddr vbase;
 
             /* Do the second stage translation on the base PTE address. */
-            get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
-                                 mmu_idx, false, true);
+            int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
+                                                 base, MMU_DATA_LOAD,
+                                                 mmu_idx, false, true);
+
+            if (vbase_ret != TRANSLATE_SUCCESS) {
+                return vbase_ret;
+            }
 
             pte_addr = vbase + idx * ptesize;
         } else {