From: Sasha Levin Date: Wed, 21 Jun 2023 16:39:45 +0000 (-0400) Subject: Fixes for 4.19 X-Git-Tag: v4.14.320~79 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8926be703d7992d458416bc5652a6e707913d01a;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 4.19 Signed-off-by: Sasha Levin --- diff --git a/queue-4.19/serial-lantiq-add-missing-interrupt-ack.patch b/queue-4.19/serial-lantiq-add-missing-interrupt-ack.patch new file mode 100644 index 00000000000..8aea426f4d6 --- /dev/null +++ b/queue-4.19/serial-lantiq-add-missing-interrupt-ack.patch @@ -0,0 +1,42 @@ +From 7c5eb06490ffe0339ea2af5e9ab09fbb5e4417e6 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Jun 2023 15:30:29 +0200 +Subject: serial: lantiq: add missing interrupt ack +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Bernhard Seibold + +[ Upstream commit 306320034e8fbe7ee1cc4f5269c55658b4612048 ] + +Currently, the error interrupt is never acknowledged, so once active it +will stay active indefinitely, causing the handler to be called in an +infinite loop. + +Fixes: 2f0fc4159a6a ("SERIAL: Lantiq: Add driver for MIPS Lantiq SOCs.") +Cc: +Signed-off-by: Bernhard Seibold +Reviewed-by: Ilpo Järvinen +Message-ID: <20230602133029.546-1-mail@bernhard-seibold.de> +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/lantiq.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c +index de2d051cd7664..6cd168cb673fd 100644 +--- a/drivers/tty/serial/lantiq.c ++++ b/drivers/tty/serial/lantiq.c +@@ -259,6 +259,7 @@ lqasc_err_int(int irq, void *_port) + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); ++ __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR); + /* clear any pending interrupts */ + asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); +-- +2.39.2 + diff --git a/queue-4.19/serial-lantiq-change-ltq_w32_mask-to-asc_update_bits.patch b/queue-4.19/serial-lantiq-change-ltq_w32_mask-to-asc_update_bits.patch new file mode 100644 index 00000000000..db8111009be --- /dev/null +++ b/queue-4.19/serial-lantiq-change-ltq_w32_mask-to-asc_update_bits.patch @@ -0,0 +1,133 @@ +From c77c61dfc29fc14920d6b3fc365f5254d43b418e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Oct 2018 17:19:05 +0800 +Subject: serial: lantiq: Change ltq_w32_mask to asc_update_bits + +From: Songjun Wu + +[ Upstream commit fccf231ae907dc9eb45eb8a9adb961195066b2c6 ] + +ltq prefix is platform specific function, asc prefix +is more generic. + +Signed-off-by: Songjun Wu +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: 306320034e8f ("serial: lantiq: add missing interrupt ack") +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/lantiq.c | 33 ++++++++++++++++++++------------- + 1 file changed, 20 insertions(+), 13 deletions(-) + +diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c +index 044128277248b..848286a12c20b 100644 +--- a/drivers/tty/serial/lantiq.c ++++ b/drivers/tty/serial/lantiq.c +@@ -113,6 +113,13 @@ struct ltq_uart_port { + unsigned int err_irq; + }; + ++static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) ++{ ++ u32 tmp = readl(reg); ++ ++ writel((tmp & ~clear) | set, reg); ++} ++ + static inline struct + ltq_uart_port *to_ltq_uart_port(struct uart_port *port) + { +@@ -163,16 +170,16 @@ lqasc_rx_chars(struct uart_port *port) + if (rsr & ASCSTATE_ANY) { + if (rsr & ASCSTATE_PE) { + port->icount.parity++; +- ltq_w32_mask(0, ASCWHBSTATE_CLRPE, ++ asc_update_bits(0, ASCWHBSTATE_CLRPE, + port->membase + LTQ_ASC_WHBSTATE); + } else if (rsr & ASCSTATE_FE) { + port->icount.frame++; +- ltq_w32_mask(0, ASCWHBSTATE_CLRFE, ++ asc_update_bits(0, ASCWHBSTATE_CLRFE, + port->membase + LTQ_ASC_WHBSTATE); + } + if (rsr & ASCSTATE_ROE) { + port->icount.overrun++; +- ltq_w32_mask(0, ASCWHBSTATE_CLRROE, ++ asc_update_bits(0, ASCWHBSTATE_CLRROE, + port->membase + LTQ_ASC_WHBSTATE); + } + +@@ -252,7 +259,7 @@ lqasc_err_int(int irq, void *_port) + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); + /* clear any pending interrupts */ +- ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ++ asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); + spin_unlock_irqrestore(<q_asc_lock, flags); + return IRQ_HANDLED; +@@ -304,7 +311,7 @@ lqasc_startup(struct uart_port *port) + clk_enable(ltq_port->clk); + port->uartclk = clk_get_rate(ltq_port->fpiclk); + +- ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), ++ asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); + + ltq_w32(0, port->membase + LTQ_ASC_PISEL); +@@ -320,7 +327,7 @@ lqasc_startup(struct uart_port *port) + * setting enable bits + */ + wmb(); +- ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ++ asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | + ASCCON_ROEN, port->membase + LTQ_ASC_CON); + + retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, +@@ -364,9 +371,9 @@ lqasc_shutdown(struct uart_port *port) + free_irq(ltq_port->err_irq, port); + + ltq_w32(0, port->membase + LTQ_ASC_CON); +- ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, ++ asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); +- ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, ++ asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); + if (!IS_ERR(ltq_port->clk)) + clk_disable(ltq_port->clk); +@@ -438,7 +445,7 @@ lqasc_set_termios(struct uart_port *port, + spin_lock_irqsave(<q_asc_lock, flags); + + /* set up CON */ +- ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); ++ asc_update_bits(0, con, port->membase + LTQ_ASC_CON); + + /* Set baud rate - take a divider of 2 into account */ + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); +@@ -446,19 +453,19 @@ lqasc_set_termios(struct uart_port *port, + divisor = divisor / 2 - 1; + + /* disable the baudrate generator */ +- ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); ++ asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); + + /* make sure the fractional divider is off */ +- ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); ++ asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); + + /* set up to use divisor of 2 */ +- ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); ++ asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + + /* now we can write the new baudrate into the register */ + ltq_w32(divisor, port->membase + LTQ_ASC_BG); + + /* turn the baudrate generator back on */ +- ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); ++ asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); + + /* enable rx */ + ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); +-- +2.39.2 + diff --git a/queue-4.19/serial-lantiq-do-not-swap-register-read-writes.patch b/queue-4.19/serial-lantiq-do-not-swap-register-read-writes.patch new file mode 100644 index 00000000000..4123cd5a6e5 --- /dev/null +++ b/queue-4.19/serial-lantiq-do-not-swap-register-read-writes.patch @@ -0,0 +1,172 @@ +From 33d6d376408186037a6107347f00b0c012ca13b4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 6 Jan 2019 19:50:37 +0100 +Subject: serial: lantiq: Do not swap register read/writes + +From: Hauke Mehrtens + +[ Upstream commit d3a28a53630e1ca10f59562ef560e3f70785cb09 ] + +The ltq_r32() and ltq_w32() macros use the __raw_readl() and +__raw_writel() functions which do not swap the value to little endian. +On the big endian vrx200 SoC the UART is operated in big endian IO mode, +the readl() and write() functions convert the value to little endian +first and then the driver does not work any more on this SoC. +Currently the vrx200 SoC selects the CONFIG_SWAP_IO_SPACE option, +without this option the serial driver would work, but PCI devices do not +work any more. + +This patch makes the driver use the __raw_readl() and __raw_writel() +functions which do not swap the endianness. On big endian system it is +assumed that the device should be access in big endian IO mode and on a +little endian system it would be access in little endian mode. + +Fixes: 89b8bd2082bb ("serial: lantiq: Use readl/writel instead of ltq_r32/ltq_w32") +Signed-off-by: Hauke Mehrtens +Acked-by: John Crispin +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: 306320034e8f ("serial: lantiq: add missing interrupt ack") +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/lantiq.c | 36 +++++++++++++++++++----------------- + 1 file changed, 19 insertions(+), 17 deletions(-) + +diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c +index c8dce404ed0c2..de2d051cd7664 100644 +--- a/drivers/tty/serial/lantiq.c ++++ b/drivers/tty/serial/lantiq.c +@@ -115,9 +115,9 @@ struct ltq_uart_port { + + static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) + { +- u32 tmp = readl(reg); ++ u32 tmp = __raw_readl(reg); + +- writel((tmp & ~clear) | set, reg); ++ __raw_writel((tmp & ~clear) | set, reg); + } + + static inline struct +@@ -145,7 +145,7 @@ lqasc_start_tx(struct uart_port *port) + static void + lqasc_stop_rx(struct uart_port *port) + { +- writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); ++ __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); + } + + static int +@@ -154,11 +154,12 @@ lqasc_rx_chars(struct uart_port *port) + struct tty_port *tport = &port->state->port; + unsigned int ch = 0, rsr = 0, fifocnt; + +- fifocnt = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; ++ fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & ++ ASCFSTAT_RXFFLMASK; + while (fifocnt--) { + u8 flag = TTY_NORMAL; + ch = readb(port->membase + LTQ_ASC_RBUF); +- rsr = (readl(port->membase + LTQ_ASC_STATE) ++ rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) + & ASCSTATE_ANY) | UART_DUMMY_UER_RX; + tty_flip_buffer_push(tport); + port->icount.rx++; +@@ -218,7 +219,7 @@ lqasc_tx_chars(struct uart_port *port) + return; + } + +- while (((readl(port->membase + LTQ_ASC_FSTAT) & ++ while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { + if (port->x_char) { + writeb(port->x_char, port->membase + LTQ_ASC_TBUF); +@@ -246,7 +247,7 @@ lqasc_tx_int(int irq, void *_port) + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); +- writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); ++ __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + spin_unlock_irqrestore(<q_asc_lock, flags); + lqasc_start_tx(port); + return IRQ_HANDLED; +@@ -271,7 +272,7 @@ lqasc_rx_int(int irq, void *_port) + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); +- writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); ++ __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + lqasc_rx_chars(port); + spin_unlock_irqrestore(<q_asc_lock, flags); + return IRQ_HANDLED; +@@ -281,7 +282,8 @@ static unsigned int + lqasc_tx_empty(struct uart_port *port) + { + int status; +- status = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; ++ status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & ++ ASCFSTAT_TXFFLMASK; + return status ? 0 : TIOCSER_TEMT; + } + +@@ -314,12 +316,12 @@ lqasc_startup(struct uart_port *port) + asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); + +- writel(0, port->membase + LTQ_ASC_PISEL); +- writel( ++ __raw_writel(0, port->membase + LTQ_ASC_PISEL); ++ __raw_writel( + ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | + ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); +- writel( ++ __raw_writel( + ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) + | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); +@@ -351,7 +353,7 @@ lqasc_startup(struct uart_port *port) + goto err2; + } + +- writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, ++ __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + port->membase + LTQ_ASC_IRNREN); + return 0; + +@@ -370,7 +372,7 @@ lqasc_shutdown(struct uart_port *port) + free_irq(ltq_port->rx_irq, port); + free_irq(ltq_port->err_irq, port); + +- writel(0, port->membase + LTQ_ASC_CON); ++ __raw_writel(0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, +@@ -462,13 +464,13 @@ lqasc_set_termios(struct uart_port *port, + asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + + /* now we can write the new baudrate into the register */ +- writel(divisor, port->membase + LTQ_ASC_BG); ++ __raw_writel(divisor, port->membase + LTQ_ASC_BG); + + /* turn the baudrate generator back on */ + asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); + + /* enable rx */ +- writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); ++ __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + + spin_unlock_irqrestore(<q_asc_lock, flags); + +@@ -579,7 +581,7 @@ lqasc_console_putchar(struct uart_port *port, int ch) + return; + + do { +- fifofree = (readl(port->membase + LTQ_ASC_FSTAT) ++ fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT) + & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; + } while (fifofree == 0); + writeb(ch, port->membase + LTQ_ASC_TBUF); +-- +2.39.2 + diff --git a/queue-4.19/serial-lantiq-use-readl-writel-instead-of-ltq_r32-lt.patch b/queue-4.19/serial-lantiq-use-readl-writel-instead-of-ltq_r32-lt.patch new file mode 100644 index 00000000000..9db3d834852 --- /dev/null +++ b/queue-4.19/serial-lantiq-use-readl-writel-instead-of-ltq_r32-lt.patch @@ -0,0 +1,166 @@ +From 0f04ace1695dba10bfcc25f05a40ec0a076e202e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 16 Oct 2018 17:19:07 +0800 +Subject: serial: lantiq: Use readl/writel instead of ltq_r32/ltq_w32 + +From: Songjun Wu + +[ Upstream commit 89b8bd2082bbbccbd95b849b34ff8b6ab3056bf7 ] + +Previous implementation uses platform-dependent functions +ltq_w32()/ltq_r32() to access registers. Those functions are not +available for other SoC which uses the same IP. +Change to OS provided readl()/writel() and readb()/writeb(), so +that different SoCs can use the same driver. + +Signed-off-by: Songjun Wu +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: 306320034e8f ("serial: lantiq: add missing interrupt ack") +Signed-off-by: Sasha Levin +--- + drivers/tty/serial/lantiq.c | 38 ++++++++++++++++++------------------- + 1 file changed, 19 insertions(+), 19 deletions(-) + +diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c +index 848286a12c20b..c8dce404ed0c2 100644 +--- a/drivers/tty/serial/lantiq.c ++++ b/drivers/tty/serial/lantiq.c +@@ -145,7 +145,7 @@ lqasc_start_tx(struct uart_port *port) + static void + lqasc_stop_rx(struct uart_port *port) + { +- ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); ++ writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); + } + + static int +@@ -154,11 +154,11 @@ lqasc_rx_chars(struct uart_port *port) + struct tty_port *tport = &port->state->port; + unsigned int ch = 0, rsr = 0, fifocnt; + +- fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; ++ fifocnt = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + while (fifocnt--) { + u8 flag = TTY_NORMAL; +- ch = ltq_r8(port->membase + LTQ_ASC_RBUF); +- rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) ++ ch = readb(port->membase + LTQ_ASC_RBUF); ++ rsr = (readl(port->membase + LTQ_ASC_STATE) + & ASCSTATE_ANY) | UART_DUMMY_UER_RX; + tty_flip_buffer_push(tport); + port->icount.rx++; +@@ -218,10 +218,10 @@ lqasc_tx_chars(struct uart_port *port) + return; + } + +- while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & ++ while (((readl(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { + if (port->x_char) { +- ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); ++ writeb(port->x_char, port->membase + LTQ_ASC_TBUF); + port->icount.tx++; + port->x_char = 0; + continue; +@@ -230,7 +230,7 @@ lqasc_tx_chars(struct uart_port *port) + if (uart_circ_empty(xmit)) + break; + +- ltq_w8(port->state->xmit.buf[port->state->xmit.tail], ++ writeb(port->state->xmit.buf[port->state->xmit.tail], + port->membase + LTQ_ASC_TBUF); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; +@@ -246,7 +246,7 @@ lqasc_tx_int(int irq, void *_port) + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); +- ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); ++ writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + spin_unlock_irqrestore(<q_asc_lock, flags); + lqasc_start_tx(port); + return IRQ_HANDLED; +@@ -271,7 +271,7 @@ lqasc_rx_int(int irq, void *_port) + unsigned long flags; + struct uart_port *port = (struct uart_port *)_port; + spin_lock_irqsave(<q_asc_lock, flags); +- ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); ++ writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + lqasc_rx_chars(port); + spin_unlock_irqrestore(<q_asc_lock, flags); + return IRQ_HANDLED; +@@ -281,7 +281,7 @@ static unsigned int + lqasc_tx_empty(struct uart_port *port) + { + int status; +- status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; ++ status = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + return status ? 0 : TIOCSER_TEMT; + } + +@@ -314,12 +314,12 @@ lqasc_startup(struct uart_port *port) + asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); + +- ltq_w32(0, port->membase + LTQ_ASC_PISEL); +- ltq_w32( ++ writel(0, port->membase + LTQ_ASC_PISEL); ++ writel( + ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | + ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, + port->membase + LTQ_ASC_TXFCON); +- ltq_w32( ++ writel( + ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) + | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); +@@ -351,7 +351,7 @@ lqasc_startup(struct uart_port *port) + goto err2; + } + +- ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, ++ writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + port->membase + LTQ_ASC_IRNREN); + return 0; + +@@ -370,7 +370,7 @@ lqasc_shutdown(struct uart_port *port) + free_irq(ltq_port->rx_irq, port); + free_irq(ltq_port->err_irq, port); + +- ltq_w32(0, port->membase + LTQ_ASC_CON); ++ writel(0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + port->membase + LTQ_ASC_RXFCON); + asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, +@@ -462,13 +462,13 @@ lqasc_set_termios(struct uart_port *port, + asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + + /* now we can write the new baudrate into the register */ +- ltq_w32(divisor, port->membase + LTQ_ASC_BG); ++ writel(divisor, port->membase + LTQ_ASC_BG); + + /* turn the baudrate generator back on */ + asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); + + /* enable rx */ +- ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); ++ writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + + spin_unlock_irqrestore(<q_asc_lock, flags); + +@@ -579,10 +579,10 @@ lqasc_console_putchar(struct uart_port *port, int ch) + return; + + do { +- fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) ++ fifofree = (readl(port->membase + LTQ_ASC_FSTAT) + & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; + } while (fifofree == 0); +- ltq_w8(ch, port->membase + LTQ_ASC_TBUF); ++ writeb(ch, port->membase + LTQ_ASC_TBUF); + } + + static void lqasc_serial_port_write(struct uart_port *port, const char *s, +-- +2.39.2 + diff --git a/queue-4.19/series b/queue-4.19/series new file mode 100644 index 00000000000..a9b4edb0529 --- /dev/null +++ b/queue-4.19/series @@ -0,0 +1,4 @@ +serial-lantiq-change-ltq_w32_mask-to-asc_update_bits.patch +serial-lantiq-use-readl-writel-instead-of-ltq_r32-lt.patch +serial-lantiq-do-not-swap-register-read-writes.patch +serial-lantiq-add-missing-interrupt-ack.patch