From: Rebecca Cran Date: Tue, 16 Feb 2021 22:45:42 +0000 (-0700) Subject: target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU X-Git-Tag: v6.0.0-rc0~60^2~45 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=89455d1ba6ed190e840cb732e63958755ea42a07;p=thirdparty%2Fqemu.git target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson Message-id: 20210216224543.16142-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c255f1bcc39..f0a9e968c9c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* * Begin with full support for MTE. This will be downgraded to MTE=0 * during realize if the board provides no tag memory, much like @@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_PFR0, DIT, 1); cpu->isar.id_pfr0 = u; + u = cpu->isar.id_pfr2; + u = FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 = u; + u = cpu->isar.id_mmfr3; u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 = u;