From: Oscar A Perez Date: Wed, 1 May 2019 13:26:43 +0000 (+0000) Subject: ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit X-Git-Tag: v5.4-rc1~184^2~3^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=89b97c429e2e77d695b5133572ca12ec256a4ea4;p=thirdparty%2Fkernel%2Flinux.git ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently setting the upper limit to 220 which isn't allowing access to all their GPIOs. The correct upper limit value is 232 (actual number is 228 plus a 4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work correctly on a AST2500 BMC running Linux Kernel v4.19 Fixes: 2039f90d136c ("ARM: dts: aspeed-g5: Add gpio controller to devicetree") Signed-off-by: Oscar A Perez Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f360b6c565a5c..e8feb8b66a2f7 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -301,7 +301,7 @@ compatible = "aspeed,ast2500-gpio"; reg = <0x1e780000 0x1000>; interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; + gpio-ranges = <&pinctrl 0 0 232>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; #interrupt-cells = <2>;