From: Sasha Levin Date: Thu, 6 Apr 2023 11:22:46 +0000 (-0400) Subject: Fixes for 5.4 X-Git-Tag: v5.15.107~60 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8ad8429ec978d824ab4af5501af368e2d73b6bf8;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.4 Signed-off-by: Sasha Levin --- diff --git a/queue-5.4/pinctrl-amd-disable-and-mask-interrupts-on-probe.patch b/queue-5.4/pinctrl-amd-disable-and-mask-interrupts-on-probe.patch new file mode 100644 index 00000000000..fe73fe15323 --- /dev/null +++ b/queue-5.4/pinctrl-amd-disable-and-mask-interrupts-on-probe.patch @@ -0,0 +1,79 @@ +From d4a834938e4ab6eaeb895727568c2185526bc2cc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 9 Oct 2021 14:32:40 +1100 +Subject: pinctrl: amd: disable and mask interrupts on probe + +From: Sachi King + +[ Upstream commit 4e5a04be88fe335ad5331f4f8c17f4ebd357e065 ] + +Some systems such as the Microsoft Surface Laptop 4 leave interrupts +enabled and configured for use in sleep states on boot, which cause +unexpected behaviour such as spurious wakes and failed resumes in +s2idle states. + +As interrupts should not be enabled until they are claimed and +explicitly enabled, disabling any interrupts mistakenly left enabled by +firmware should be safe. + +Signed-off-by: Sachi King +Link: https://lore.kernel.org/r/20211009033240.21543-1-nakato@nakato.io +Signed-off-by: Linus Walleij +Stable-dep-of: b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-amd.c | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c +index c4e1ebd6e4ea1..887dc57704402 100644 +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -770,6 +770,34 @@ static const struct pinconf_ops amd_pinconf_ops = { + .pin_config_group_set = amd_pinconf_group_set, + }; + ++static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) ++{ ++ struct pinctrl_desc *desc = gpio_dev->pctrl->desc; ++ unsigned long flags; ++ u32 pin_reg, mask; ++ int i; ++ ++ mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | ++ BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | ++ BIT(WAKE_CNTRL_OFF_S4); ++ ++ for (i = 0; i < desc->npins; i++) { ++ int pin = desc->pins[i].number; ++ const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); ++ ++ if (!pd) ++ continue; ++ ++ raw_spin_lock_irqsave(&gpio_dev->lock, flags); ++ ++ pin_reg = readl(gpio_dev->base + i * 4); ++ pin_reg &= ~mask; ++ writel(pin_reg, gpio_dev->base + i * 4); ++ ++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); ++ } ++} ++ + #ifdef CONFIG_PM_SLEEP + static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) + { +@@ -914,6 +942,9 @@ static int amd_gpio_probe(struct platform_device *pdev) + return PTR_ERR(gpio_dev->pctrl); + } + ++ /* Disable and mask interrupts */ ++ amd_gpio_irq_init(gpio_dev); ++ + girq = &gpio_dev->gc.irq; + girq->chip = &amd_gpio_irqchip; + /* This will let us handle the parent IRQ in the driver */ +-- +2.39.2 + diff --git a/queue-5.4/pinctrl-amd-disable-and-mask-interrupts-on-resume.patch b/queue-5.4/pinctrl-amd-disable-and-mask-interrupts-on-resume.patch new file mode 100644 index 00000000000..73a56cff90b --- /dev/null +++ b/queue-5.4/pinctrl-amd-disable-and-mask-interrupts-on-resume.patch @@ -0,0 +1,102 @@ +From 814ef70cd66c9d8c4f1697ca35c8b59316f5f740 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Mar 2023 09:32:59 +0000 +Subject: pinctrl: amd: Disable and mask interrupts on resume +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Kornel Dulęba + +[ Upstream commit b26cd9325be4c1fcd331b77f10acb627c560d4d7 ] + +This fixes a similar problem to the one observed in: +commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe"). + +On some systems, during suspend/resume cycle firmware leaves +an interrupt enabled on a pin that is not used by the kernel. +This confuses the AMD pinctrl driver and causes spurious interrupts. + +The driver already has logic to detect if a pin is used by the kernel. +Leverage it to re-initialize interrupt fields of a pin only if it's not +used by us. + +Cc: stable@vger.kernel.org +Fixes: dbad75dd1f25 ("pinctrl: add AMD GPIO driver support.") +Signed-off-by: Kornel Dulęba +Link: https://lore.kernel.org/r/20230320093259.845178-1-korneld@chromium.org +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-amd.c | 36 +++++++++++++++++++---------------- + 1 file changed, 20 insertions(+), 16 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c +index 887dc57704402..347ec9adbdc29 100644 +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -770,32 +770,34 @@ static const struct pinconf_ops amd_pinconf_ops = { + .pin_config_group_set = amd_pinconf_group_set, + }; + +-static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) ++static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin) + { +- struct pinctrl_desc *desc = gpio_dev->pctrl->desc; ++ const struct pin_desc *pd; + unsigned long flags; + u32 pin_reg, mask; +- int i; + + mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | + BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | + BIT(WAKE_CNTRL_OFF_S4); + +- for (i = 0; i < desc->npins; i++) { +- int pin = desc->pins[i].number; +- const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); +- +- if (!pd) +- continue; ++ pd = pin_desc_get(gpio_dev->pctrl, pin); ++ if (!pd) ++ return; + +- raw_spin_lock_irqsave(&gpio_dev->lock, flags); ++ raw_spin_lock_irqsave(&gpio_dev->lock, flags); ++ pin_reg = readl(gpio_dev->base + pin * 4); ++ pin_reg &= ~mask; ++ writel(pin_reg, gpio_dev->base + pin * 4); ++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); ++} + +- pin_reg = readl(gpio_dev->base + i * 4); +- pin_reg &= ~mask; +- writel(pin_reg, gpio_dev->base + i * 4); ++static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) ++{ ++ struct pinctrl_desc *desc = gpio_dev->pctrl->desc; ++ int i; + +- raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); +- } ++ for (i = 0; i < desc->npins; i++) ++ amd_gpio_irq_init_pin(gpio_dev, i); + } + + #ifdef CONFIG_PM_SLEEP +@@ -848,8 +850,10 @@ static int amd_gpio_resume(struct device *dev) + for (i = 0; i < desc->npins; i++) { + int pin = desc->pins[i].number; + +- if (!amd_gpio_should_save(gpio_dev, pin)) ++ if (!amd_gpio_should_save(gpio_dev, pin)) { ++ amd_gpio_irq_init_pin(gpio_dev, pin); + continue; ++ } + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; +-- +2.39.2 + diff --git a/queue-5.4/pinctrl-amd-use-irqchip-template.patch b/queue-5.4/pinctrl-amd-use-irqchip-template.patch new file mode 100644 index 00000000000..d2f3c330576 --- /dev/null +++ b/queue-5.4/pinctrl-amd-use-irqchip-template.patch @@ -0,0 +1,74 @@ +From 453faf44f0ac32c853bd67534c4242ca99772e26 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jul 2020 12:15:45 +0200 +Subject: pinctrl: amd: Use irqchip template + +From: Linus Walleij + +[ Upstream commit e81376ebbafc679a5cea65f25f5ab242172f52df ] + +This makes the driver use the irqchip template to assign +properties to the gpio_irq_chip instead of using the +explicit call to gpiochip_irqchip_add(). + +The irqchip is instead added while adding the gpiochip. + +Signed-off-by: Linus Walleij +Cc: Shyam Sundar S K +Cc: Sandeep Singh +Link: https://lore.kernel.org/r/20200722101545.144373-1-linus.walleij@linaro.org +Stable-dep-of: b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-amd.c | 21 ++++++++++----------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c +index ca3f18aa16acb..c4e1ebd6e4ea1 100644 +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -852,6 +852,7 @@ static int amd_gpio_probe(struct platform_device *pdev) + int irq_base; + struct resource *res; + struct amd_gpio *gpio_dev; ++ struct gpio_irq_chip *girq; + + gpio_dev = devm_kzalloc(&pdev->dev, + sizeof(struct amd_gpio), GFP_KERNEL); +@@ -913,6 +914,15 @@ static int amd_gpio_probe(struct platform_device *pdev) + return PTR_ERR(gpio_dev->pctrl); + } + ++ girq = &gpio_dev->gc.irq; ++ girq->chip = &amd_gpio_irqchip; ++ /* This will let us handle the parent IRQ in the driver */ ++ girq->parent_handler = NULL; ++ girq->num_parents = 0; ++ girq->parents = NULL; ++ girq->default_type = IRQ_TYPE_NONE; ++ girq->handler = handle_simple_irq; ++ + ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); + if (ret) + return ret; +@@ -924,17 +934,6 @@ static int amd_gpio_probe(struct platform_device *pdev) + goto out2; + } + +- ret = gpiochip_irqchip_add(&gpio_dev->gc, +- &amd_gpio_irqchip, +- 0, +- handle_simple_irq, +- IRQ_TYPE_NONE); +- if (ret) { +- dev_err(&pdev->dev, "could not add irqchip\n"); +- ret = -ENODEV; +- goto out2; +- } +- + ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, + IRQF_SHARED, KBUILD_MODNAME, gpio_dev); + if (ret) +-- +2.39.2 + diff --git a/queue-5.4/series b/queue-5.4/series index a983765e916..20ee4c534f9 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -1,3 +1,6 @@ revert-treewide-replace-declare_tasklet-with-declare_tasklet_old.patch treewide-replace-declare_tasklet-with-declare_tasklet_old.patch smb3-fix-problem-with-null-cifs-super-block-with-previous-patch.patch +pinctrl-amd-use-irqchip-template.patch +pinctrl-amd-disable-and-mask-interrupts-on-probe.patch +pinctrl-amd-disable-and-mask-interrupts-on-resume.patch