From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Wed, 28 Jul 2021 15:34:03 +0000 (+0100)
Subject: aarch64: Add smov alternative to sign_extend pattern
X-Git-Tag: basepoints/gcc-13~5741
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8b06ccb20eaf2e7cb85e9dca23f1599ee37d17a7;p=thirdparty%2Fgcc.git

aarch64: Add smov alternative to sign_extend pattern

In the testcase here we were generating a umov + sxth to move
a half-word value from SIMD to GP regs with sign-extension.
We can use a single smov instruction for it instead but the
sign-extend pattern was missing the right alternative.
The *zero_extend<SHORT:mode><GPI:mode>2_aarch64 pattern for
zero-extension already has the right alternative for
the analogous umov instruction, so this mirrors that pattern.

Bootstrapped and tested on aarch64-none-linux-gnu.

The test gcc.target/aarch64/sve/clastb_4.c is adjusted to scan for
the clastb  h0, p0, h0, z0.h form
instead of
the clastb  w0, p0, w0, z0.h form.

This is an improvement as the W forms of the clast instructions are more expensive.

gcc/ChangeLog:

	* config/aarch64/aarch64.md (*extend<SHORT:mode><GPI:mode>2_aarch64):
	Add "r,w" alternative.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/smov_1.c: New test.
	* gcc.target/aarch64/sve/clastb_4.c: Adjust clast scan-assembler.
---

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 8cd259fca9cd..eb8ccd4b97bb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1874,13 +1874,15 @@
 )
 
 (define_insn "*extend<SHORT:mode><GPI:mode>2_aarch64"
-  [(set (match_operand:GPI 0 "register_operand" "=r,r")
-        (sign_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
+  [(set (match_operand:GPI 0 "register_operand" "=r,r,r")
+        (sign_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,w")))]
   ""
   "@
    sxt<SHORT:size>\t%<GPI:w>0, %w1
-   ldrs<SHORT:size>\t%<GPI:w>0, %1"
-  [(set_attr "type" "extend,load_4")]
+   ldrs<SHORT:size>\t%<GPI:w>0, %1
+   smov\t%w0, %1.<SHORT:size>[0]"
+  [(set_attr "type" "extend,load_4,neon_to_gp")
+   (set_attr "arch" "*,*,fp")]
 )
 
 (define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64"
diff --git a/gcc/testsuite/gcc.target/aarch64/smov_1.c b/gcc/testsuite/gcc.target/aarch64/smov_1.c
new file mode 100644
index 000000000000..53280ea77eef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/smov_1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.2-a+sve" } */
+
+/* Check that we avoid an explicit sxth in favour of smov.  */
+
+#include <arm_sve.h>
+
+int foo(svint16_t a) {
+  return svminv_s16(svptrue_b16(), a);
+}
+
+/* { dg-final { scan-assembler-not "sxth" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/clastb_4.c b/gcc/testsuite/gcc.target/aarch64/sve/clastb_4.c
index 788e29fe982f..7603d475a818 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/clastb_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/clastb_4.c
@@ -6,4 +6,4 @@
 #include "clastb_2.c"
 
 /* { dg-final { scan-tree-dump "operating on partial vectors." "vect" } } */
-/* { dg-final { scan-assembler {\tclastb\tw[0-9]+, p[0-7], w[0-9]+, z[0-9]+\.h} } } */
+/* { dg-final { scan-assembler {\tclastb\th[0-9]+, p[0-7], h[0-9]+, z[0-9]+\.h} } } */