From: Alistair Francis <Alistair.Francis@wdc.com>
Date: Sat, 16 Mar 2019 01:21:29 +0000 (+0000)
Subject: riscv: sifive_u: Allow up to 4 CPUs to be created
X-Git-Tag: v4.0.0-rc0~3^2~3
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8b1d0714bfdd1ac2704519200120e326cba31066;p=thirdparty%2Fqemu.git

riscv: sifive_u: Allow up to 4 CPUs to be created

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820fea..3199238ba01 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Board compatible with SiFive U SDK";
     mc->init = riscv_sifive_u_init;
-    mc->max_cpus = 1;
+    /* The real hardware has 5 CPUs, but one of them is a small embedded power
+     * management CPU.
+     */
+    mc->max_cpus = 4;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)