From: Josua Mayer Date: Fri, 1 Nov 2024 11:42:25 +0000 (+0100) Subject: mmc: sdhci-esdhc-imx: Implement emmc hardware reset X-Git-Tag: v6.13-rc1~153^2~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8ba9d45a33c849c50053ba7b6ef4706bbb3ff709;p=thirdparty%2Fkernel%2Flinux.git mmc: sdhci-esdhc-imx: Implement emmc hardware reset NXP ESDHC supports control of native emmc reset signal when pinmux is set accordingly, using uSDHCx_SYS_CTRL register IPP_RST_N bit. Documentation is available in NXP i.MX6Q Reference Manual. Implement the hw_reset function in sdhci_ops asserting reset for at least 1us and waiting at least 200us after deassertion. Lower bounds are based on: JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159. Upper bounds are chosen allowing flexibility to the scheduler. Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is still accessible after boot: - eMMC extcsd has RST_N_FUNCTION=0x01 - sdhc node has cap-mmc-hw-reset - pinmux set for EMMC0_RESET_B - Linux v5.15 Signed-off-by: Josua Mayer Reviewed-by: Haibo Chen Acked-by: Adrian Hunter Message-ID: <20241101-imx-emmc-reset-v3-1-184965eed476@solid-run.com> Signed-off-by: Ulf Hansson --- diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index c7582ad451236..8f0a3d933ea98 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -31,6 +31,7 @@ #include "cqhci.h" #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f +#define ESDHC_SYS_CTRL_IPP_RST_N BIT(23) #define ESDHC_CTRL_D3CD 0x08 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) /* VENDOR SPEC register */ @@ -1407,6 +1408,17 @@ static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) return 0; } +static void esdhc_hw_reset(struct sdhci_host *host) +{ + esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYSTEM_CONTROL); + /* eMMC spec requires minimum 1us, here delay between 1-10us */ + usleep_range(1, 10); + esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, + ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYSTEM_CONTROL); + /* eMMC spec requires minimum 200us, here delay between 200-300us */ + usleep_range(200, 300); +} + static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, @@ -1425,6 +1437,7 @@ static struct sdhci_ops sdhci_esdhc_ops = { .reset = esdhc_reset, .irq = esdhc_cqhci_irq, .dump_vendor_regs = esdhc_dump_debug_regs, + .hw_reset = esdhc_hw_reset, }; static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {