From: Greg Kroah-Hartman Date: Thu, 17 Sep 2020 15:18:43 +0000 (+0200) Subject: 5.8-stable patches X-Git-Tag: v4.4.237~50 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8c64c4757e539c9056ebbde8b55d984196a30a28;p=thirdparty%2Fkernel%2Fstable-queue.git 5.8-stable patches added patches: dt-bindings-spi-fix-spi-bcm-qspi-compatible-ordering.patch rdma-bnxt_re-restrict-the-max_gids-to-256.patch --- diff --git a/queue-5.8/dt-bindings-spi-fix-spi-bcm-qspi-compatible-ordering.patch b/queue-5.8/dt-bindings-spi-fix-spi-bcm-qspi-compatible-ordering.patch new file mode 100644 index 00000000000..0a5bac784cb --- /dev/null +++ b/queue-5.8/dt-bindings-spi-fix-spi-bcm-qspi-compatible-ordering.patch @@ -0,0 +1,83 @@ +From fcd2e4b9ca20faf6de959f67df5b454a5b055c56 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Wed, 26 Aug 2020 16:40:13 -0700 +Subject: dt-bindings: spi: Fix spi-bcm-qspi compatible ordering + +From: Florian Fainelli + +commit fcd2e4b9ca20faf6de959f67df5b454a5b055c56 upstream. + +The binding is currently incorrectly defining the compatible strings +from least specifice to most specific instead of the converse. Re-order +them from most specific (left) to least specific (right) and fix the +examples as well. + +Fixes: 5fc78f4c842a ("spi: Broadcom BRCMSTB, NSP, NS2 SoC bindings") +Reviewed-by: Rob Herring +Signed-off-by: Florian Fainelli +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 16 ++++++------ + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt ++++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +@@ -23,8 +23,8 @@ Required properties: + + - compatible: + Must be one of : +- "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs +- "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI ++ "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs ++ "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs +@@ -36,8 +36,8 @@ Required properties: + BRCMSTB SoCs + "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs +- "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP +- "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs ++ "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP ++ "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs + + - reg: + Define the bases and ranges of the associated I/O address spaces. +@@ -86,7 +86,7 @@ BRCMSTB SoC Example: + spi@f03e3400 { + #address-cells = <0x1>; + #size-cells = <0x0>; +- compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi"; ++ compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; + reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; + reg-names = "cs_reg", "mspi", "bspi"; + interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; +@@ -149,7 +149,7 @@ BRCMSTB SoC Example: + #address-cells = <1>; + #size-cells = <0>; + clocks = <&upg_fixed>; +- compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi"; ++ compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; +@@ -160,7 +160,7 @@ BRCMSTB SoC Example: + iProc SoC Example: + + qspi: spi@18027200 { +- compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; ++ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, +@@ -191,7 +191,7 @@ iProc SoC Example: + NS2 SoC Example: + + qspi: spi@66470200 { +- compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; ++ compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, diff --git a/queue-5.8/rdma-bnxt_re-restrict-the-max_gids-to-256.patch b/queue-5.8/rdma-bnxt_re-restrict-the-max_gids-to-256.patch new file mode 100644 index 00000000000..7a6f8399e2d --- /dev/null +++ b/queue-5.8/rdma-bnxt_re-restrict-the-max_gids-to-256.patch @@ -0,0 +1,45 @@ +From 847b97887ed4569968d5b9a740f2334abca9f99a Mon Sep 17 00:00:00 2001 +From: Naresh Kumar PBS +Date: Mon, 24 Aug 2020 11:14:35 -0700 +Subject: RDMA/bnxt_re: Restrict the max_gids to 256 + +From: Naresh Kumar PBS + +commit 847b97887ed4569968d5b9a740f2334abca9f99a upstream. + +Some adapters report more than 256 gid entries. Restrict it to 256 for +now. + +Fixes: 1ac5a4047975("RDMA/bnxt_re: Add bnxt_re RoCE driver") +Link: https://lore.kernel.org/r/1598292876-26529-6-git-send-email-selvin.xavier@broadcom.com +Signed-off-by: Naresh Kumar PBS +Signed-off-by: Selvin Xavier +Signed-off-by: Jason Gunthorpe +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/infiniband/hw/bnxt_re/qplib_sp.c | 2 +- + drivers/infiniband/hw/bnxt_re/qplib_sp.h | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c ++++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c +@@ -149,7 +149,7 @@ int bnxt_qplib_get_dev_attr(struct bnxt_ + attr->max_inline_data = le32_to_cpu(sb->max_inline_data); + attr->l2_db_size = (sb->l2_db_space_size + 1) * + (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); +- attr->max_sgid = le32_to_cpu(sb->max_gid); ++ attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; + + bnxt_qplib_query_version(rcfw, attr->fw_ver); + +--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.h ++++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.h +@@ -47,6 +47,7 @@ + struct bnxt_qplib_dev_attr { + #define FW_VER_ARR_LEN 4 + u8 fw_ver[FW_VER_ARR_LEN]; ++#define BNXT_QPLIB_NUM_GIDS_SUPPORTED 256 + u16 max_sgid; + u16 max_mrw; + u32 max_qp; diff --git a/queue-5.8/series b/queue-5.8/series new file mode 100644 index 00000000000..70ffaf8d73a --- /dev/null +++ b/queue-5.8/series @@ -0,0 +1,2 @@ +rdma-bnxt_re-restrict-the-max_gids-to-256.patch +dt-bindings-spi-fix-spi-bcm-qspi-compatible-ordering.patch