From: Jin Ma <jinma@linux.alibaba.com>
Date: Fri, 17 Nov 2023 06:20:53 +0000 (+0800)
Subject: RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
X-Git-Tag: binutils-2_42~603
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8cb16b68584e14aade8de166c75e1d85e38507bd;p=thirdparty%2Fbinutils-gdb.git

RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.

The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
XTheadFmv extension in T-Head specific is incorrect, and it also has
some impact on the implementation of the binutils, so this patch
corrects this.

For details see:
https://github.com/T-head-Semi/thead-extension-spec/pull/34

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-fmv.d: Correct test.
	* testsuite/gas/riscv/x-thead-fmv.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
	(MASK_TH_FMV_HW_X): Likewise.
	(MATCH_TH_FMV_X_HW): Likewise.
	(MASK_TH_FMV_X_HW): Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Correct operands.
---

diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
index af8ce0c8ee0..50ccc62413f 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.d
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
@@ -7,5 +7,5 @@
 Disassembly of section .text:
 
 0+000 <target>:
-[ 	]+[0-9a-f]+:[ 	]+5005950b[ 	]+th.fmv.hw.x[ 	]+a0,fa1
-[ 	]+[0-9a-f]+:[ 	]+6005158b[ 	]+th.fmv.x.hw[ 	]+a1,fa0
+[ 	]+[0-9a-f]+:[ 	]+a005158b[ 	]+th.fmv.hw.x[ 	]+fa1,a0
+[ 	]+[0-9a-f]+:[ 	]+c005158b[ 	]+th.fmv.x.hw[ 	]+a1,fa0
diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s
index 250ba8358ae..8ca2ec2f093 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.s
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.s
@@ -1,3 +1,3 @@
 target:
-	th.fmv.hw.x	a0, fa1
+	th.fmv.hw.x	fa1, a0
 	th.fmv.x.hw	a1, fa0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9b6dc603d50..25b7a96dab4 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2515,10 +2515,10 @@
 #define MATCH_TH_FSURW 0x5000700b
 #define MASK_TH_FSURW 0xf800707f
 /* Vendor-specific (T-Head) XTheadFmv instructions. */
-#define MATCH_TH_FMV_HW_X 0x5000100b
-#define MASK_TH_FMV_HW_X 0xfff0707f
-#define MATCH_TH_FMV_X_HW 0x6000100b
-#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_X_HW 0xc000100b
+#define MASK_TH_FMV_X_HW  0xfff0707f
+#define MATCH_TH_FMV_HW_X 0xa000100b
+#define MASK_TH_FMV_HW_X  0xfff0707f
 /* Vendor-specific (T-Head) XTheadInt instructions. */
 #define MATCH_TH_IPOP 0x0050000b
 #define MASK_TH_IPOP 0xffffffff
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 24afb360e03..bf388cdaa2f 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.fsurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
 
 /* Vendor-specific (T-Head) XTheadFmv instructions.  */
-{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X,  MASK_TH_FMV_HW_X,  match_opcode, 0},
+{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X,  MASK_TH_FMV_HW_X,  match_opcode, 0},
 {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW,  MASK_TH_FMV_X_HW,  match_opcode, 0},
 
 /* Vendor-specific (T-Head) XTheadInt instructions.  */