From: Simon Horman Date: Wed, 25 Jun 2025 12:52:10 +0000 (+0100) Subject: tg3: spelling corrections X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8efa26fcbf8a7f783fd1ce7dd2a409e9b7758df0;p=thirdparty%2Fkernel%2Flinux.git tg3: spelling corrections Correct spelling as flagged by codespell. Signed-off-by: Simon Horman Reviewed-by: Michael Chan Signed-off-by: David S. Miller --- diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 91104cc2c2385..c00b05b2e945d 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -6686,7 +6686,7 @@ static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) * We only need to fill in the address because the other members * of the RX descriptor are invariant, see tg3_init_rings. * - * Note the purposeful assymetry of cpu vs. chip accesses. For + * Note the purposeful asymmetry of cpu vs. chip accesses. For * posting buffers we only dirty the first cache line of the RX * descriptor (containing the address). Whereas for the RX status * buffers the cpu only reads the last cacheline of the RX descriptor @@ -10145,7 +10145,7 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) tp->grc_mode |= GRC_MODE_HOST_SENDBDS; /* Pseudo-header checksum is done by hardware logic and not - * the offload processers, so make the chip do the pseudo- + * the offload processors, so make the chip do the pseudo- * header checksums on receive. For transmit it is more * convenient to do the pseudo-header checksum in software * as Linux does that on transmit for us in all cases. diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index b473f8014d9c0..a9e7f88fa26dc 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -2390,7 +2390,7 @@ #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 -/* Fast Ethernet Tranceiver definitions */ +/* Fast Ethernet Transceiver definitions */ #define MII_TG3_FET_PTEST 0x17 #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 #define MII_TG3_FET_PTEST_TRIM_2 0x0002