From: MayShao-oc <MayShao-oc@zhaoxin.com>
Date: Thu, 17 Oct 2024 01:33:17 +0000 (+0800)
Subject: x86: Support x86 ZHAOXIN GMI instructions
X-Git-Tag: gdb-16-branchpoint~641
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=8f0d880434b84b222f87c4ee8f9d6d31d330668d;p=thirdparty%2Fbinutils-gdb.git

x86: Support x86 ZHAOXIN GMI instructions

gas/ChangeLog:

	* NEWS: Support ZHAOXIN GMI instructions.
	* config/tc-i386.c: Add gmi.
	* doc/c-i386.texi: Document gmi.
	* testsuite/gas/i386/i386.exp: Add gmi test.
	* testsuite/gas/i386/gmi.d: Ditto.
	* testsuite/gas/i386/gmi.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c: New comment.
	* i386-gen.c: Add gmi.
	* i386-opc.h (CpuGMI): New.
	* i386-opc.tbl: Add Zhaoxin GMI instructions.
	* i386-tbl.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-init.h: Ditto.
---

diff --git a/gas/NEWS b/gas/NEWS
index d64330143b0..d4c571f3474 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the x86 Zhaoxin GMI instructions.
+
 * On x86 emulation support (for secondary targets) was dropped.
 
 * Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi and CORE-V
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index cfab10d68b8..a695a1599a2 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1219,6 +1219,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (user_msr, USER_MSR, USER_MSR, false),
   SUBARCH (apx_f, APX_F, APX_F, false),
   VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
+  SUBARCH (gmi, GMI, GMI, false),
 };
 
 #undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9667061752d..952ddbc7377 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -274,7 +274,8 @@ accept various extension mnemonics.  For example,
 @code{snp},
 @code{invlpgb},
 @code{tlbsync},
-@code{svme} and
+@code{svme},
+@code{gmi} and
 @code{padlock}.
 Note that these extension mnemonics can be prefixed with @code{no} to revoke
 the respective (and any dependent) functionality.  Note further that the
@@ -1705,7 +1706,8 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
-@item @samp{.tlbsync} @tab @samp{.apx_f}
+@item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi}
+
 @end multitable
 
 Apart from the warning, there are only two other effects on
diff --git a/gas/testsuite/gas/i386/gmi.d b/gas/testsuite/gas/i386/gmi.d
new file mode 100644
index 00000000000..063da8e120a
--- /dev/null
+++ b/gas/testsuite/gas/i386/gmi.d
@@ -0,0 +1,12 @@
+#objdump: -dw
+#name: zhaoxin gmi
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:[	 ]*f2 0f a6 c0 [	 ]*sm2
+   4:[	 ]*f3 0f a6 e8 [	 ]*sm3
+   8:[	 ]*f3 0f a7 f0 [	 ]*sm4
+#pass
diff --git a/gas/testsuite/gas/i386/gmi.s b/gas/testsuite/gas/i386/gmi.s
new file mode 100644
index 00000000000..c412de55d31
--- /dev/null
+++ b/gas/testsuite/gas/i386/gmi.s
@@ -0,0 +1,8 @@
+# ZHAOXIN GMI instructions
+
+	.text
+foo:
+	sm2
+	sm3
+	sm4
+	.p2align 4,0
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 0a979ccf16a..b21474046a1 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -114,6 +114,7 @@ if [gas_32_check] then {
     run_dump_test "quoted2"
     run_dump_test "unary"
     run_dump_test "padlock"
+    run_dump_test "gmi"
     run_dump_test "crx"
     run_list_test "cr-err" ""
     run_dump_test "cdr"
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 9cf7edbbc0e..ca7d30f131e 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -90,6 +90,7 @@ static bool PCLMUL_Fixup (instr_info *, int, int);
 static bool VPCMP_Fixup (instr_info *, int, int);
 static bool VPCOM_Fixup (instr_info *, int, int);
 static bool NOP_Fixup (instr_info *, int, int);
+static bool MONTMUL_Fixup (instr_info *, int, int);
 static bool OP_3DNowSuffix (instr_info *, int, int);
 static bool CMP_Fixup (instr_info *, int, int);
 static bool REP_Fixup (instr_info *, int, int);
@@ -1050,6 +1051,9 @@ enum
   PREFIX_0F7D,
   PREFIX_0F7E,
   PREFIX_0F7F,
+  PREFIX_0FA6_REG_0,
+  PREFIX_0FA6_REG_5,
+  PREFIX_0FA7_REG_6,
   PREFIX_0FAE_REG_0_MOD_3,
   PREFIX_0FAE_REG_1_MOD_3,
   PREFIX_0FAE_REG_2_MOD_3,
@@ -2855,9 +2859,12 @@ static const struct dis386 reg_table[][8] = {
   },
   /* REG_0FA6 */
   {
-    { "montmul",	{ { OP_0f07, 0 } }, 0 },
+    { PREFIX_TABLE (PREFIX_0FA6_REG_0) },
     { "xsha1",		{ { OP_0f07, 0 } }, 0 },
     { "xsha256",	{ { OP_0f07, 0 } }, 0 },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0FA6_REG_5) },
   },
   /* REG_0FA7 */
   {
@@ -2867,6 +2874,7 @@ static const struct dis386 reg_table[][8] = {
     { "xcrypt-ctr",	{ { OP_0f07, 0 } }, 0 },
     { "xcrypt-cfb",	{ { OP_0f07, 0 } }, 0 },
     { "xcrypt-ofb",	{ { OP_0f07, 0 } }, 0 },
+    { PREFIX_TABLE (PREFIX_0FA7_REG_6) },
   },
   /* REG_0FAE */
   {
@@ -3443,6 +3451,26 @@ static const struct dis386 prefix_table[][4] = {
     { "movdqa",	{ EXxS, XM }, PREFIX_OPCODE },
   },
 
+  /* PREFIX_0FA6_REG_0 */
+  {
+    { Bad_Opcode },
+    { "montmul",	{ { MONTMUL_Fixup, 0 } }, 0},
+    { Bad_Opcode },
+    { "sm2",	{ Skip_MODRM }, 0 },
+  },
+
+  /* PREFIX_0FA6_REG_5 */
+  {
+    { Bad_Opcode },
+    { "sm3",	{ Skip_MODRM }, 0 },
+  },
+
+  /* PREFIX_0FA7_REG_6 */
+  {
+    { Bad_Opcode },
+    { "sm4",	{ Skip_MODRM }, 0 },
+  },
+
   /* PREFIX_0FAE_REG_0_MOD_3 */
   {
     { Bad_Opcode },
@@ -13091,6 +13119,24 @@ OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
   return OP_E (ins, bytemode, sizeflag);
 }
 
+/* montmul instruction need display repz and skip modrm */
+
+static bool
+MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+  if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
+    return BadOp (ins);
+
+  /* The 0xf3 prefix should be displayed as "repz" for montmul. */
+  if (ins->prefixes & PREFIX_REPZ)
+    ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
+
+  /* Skip mod/rm byte.  */
+  MODRM_CHECK;
+  ins->codep++;
+  return true;
+}
+
 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
 
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 2b9f4fceadd..053b66675c5 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -334,6 +334,7 @@ static bitfield cpu_flags[] =
   BITFIELD (3dnow),
   BITFIELD (3dnowA),
   BITFIELD (PadLock),
+  BITFIELD (GMI),
   BITFIELD (SVME),
   BITFIELD (VMX),
   BITFIELD (SMX),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c0d5e44d461..d404fbc6b05 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -66,6 +66,8 @@ enum i386_cpu
   CpuSSE3,
   /* VIA PadLock required */
   CpuPadLock,
+  /* ZHAOXIN GMI required */
+  CpuGMI,
   /* AMD Secure Virtual Machine Ext-s required */
   CpuSVME,
   /* VMX Instructions required */
@@ -400,6 +402,7 @@ typedef union i386_cpu_flags
       unsigned int cpusse2:1;
       unsigned int cpusse3:1;
       unsigned int cpupadlock:1;
+      unsigned int cpugmi:1;
       unsigned int cpusvme:1;
       unsigned int cpuvmx:1;
       unsigned int cpusmx:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 96719f9ba57..271704937de 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2131,6 +2131,11 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {}
 // Alias for xstore-rng.
 xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}
 
+// ZHAOXIN GMI instructions
+sm2, 0xf20fa6c0, GMI, NoSuf, {}
+sm3, 0xf30fa6e8, GMI, NoSuf, {}
+sm4, 0xf30fa7f0, GMI, NoSuf, {}
+
 // Multy-precision Add Carry, rdseed instructions.
 <adx:pfx, c:66, o:f3>
 ad<adx>x, 0x<adx:pfx>66, ADX&APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }