From: Greg Kroah-Hartman Date: Wed, 17 Nov 2021 17:59:11 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v5.14.20~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=908ad472fa178dc03a5eb50dfdb06cbe652b4fdc;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch scsi-ufs-fix-interrupt-error-message-for-shared-interrupts.patch --- diff --git a/queue-5.4/mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch b/queue-5.4/mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch new file mode 100644 index 00000000000..f3e79d5bf3d --- /dev/null +++ b/queue-5.4/mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch @@ -0,0 +1,74 @@ +From a923a2676e60683aee46aa4b93c30aff240ac20d Mon Sep 17 00:00:00 2001 +From: "Maciej W. Rozycki" +Date: Fri, 22 Oct 2021 00:58:23 +0200 +Subject: MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL + +From: Maciej W. Rozycki + +commit a923a2676e60683aee46aa4b93c30aff240ac20d upstream. + +Fix assembly errors like: + +{standard input}: Assembler messages: +{standard input}:287: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32' +{standard input}:680: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32' +{standard input}:1274: Error: opcode not supported on this processor: mips3 (mips3) `dins $12,$9,32,32' +{standard input}:2175: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32' +make[1]: *** [scripts/Makefile.build:277: mm/highmem.o] Error 1 + +with code produced from `__cmpxchg64' for MIPS64r2 CPU configurations +using CONFIG_32BIT and CONFIG_PHYS_ADDR_T_64BIT. + +This is due to MIPS_ISA_ARCH_LEVEL downgrading the assembly architecture +to `r4000' i.e. MIPS III for MIPS64r2 configurations, while there is a +block of code containing a DINS MIPS64r2 instruction conditionalized on +MIPS_ISA_REV >= 2 within the scope of the downgrade. + +The assembly architecture override code pattern has been put there for +LL/SC instructions, so that code compiles for configurations that select +a processor to build for that does not support these instructions while +still providing run-time support for processors that do, dynamically +switched by non-constant `cpu_has_llsc'. It went in with linux-mips.org +commit aac8aa7717a2 ("Enable a suitable ISA for the assembler around +ll/sc so that code builds even for processors that don't support the +instructions. Plus minor formatting fixes.") back in 2005. + +Fix the problem by wrapping these instructions along with the adjacent +SYNC instructions only, following the practice established with commit +cfd54de3b0e4 ("MIPS: Avoid move psuedo-instruction whilst using +MIPS_ISA_LEVEL") and commit 378ed6f0e3c5 ("MIPS: Avoid using .set mips0 +to restore ISA"). Strictly speaking the SYNC instructions do not have +to be wrapped as they are only used as a Loongson3 erratum workaround, +so they will be enabled in the assembler by default, but do this so as +to keep code consistent with other places. + +Reported-by: kernel test robot +Signed-off-by: Maciej W. Rozycki +Fixes: c7e2d71dda7a ("MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()") +Cc: stable@vger.kernel.org # v5.1+ +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/include/asm/cmpxchg.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/mips/include/asm/cmpxchg.h ++++ b/arch/mips/include/asm/cmpxchg.h +@@ -239,6 +239,7 @@ static inline unsigned long __cmpxchg64( + " .set " MIPS_ISA_ARCH_LEVEL " \n" + /* Load 64 bits from ptr */ + "1: lld %L0, %3 # __cmpxchg64 \n" ++ " .set pop \n" + /* + * Split the 64 bit value we loaded into the 2 registers that hold the + * ret variable. +@@ -266,6 +267,8 @@ static inline unsigned long __cmpxchg64( + " or %L1, %L1, $at \n" + " .set at \n" + # endif ++ " .set push \n" ++ " .set " MIPS_ISA_ARCH_LEVEL " \n" + /* Attempt to store new at ptr */ + " scd %L1, %2 \n" + /* If we failed, loop! */ diff --git a/queue-5.4/scsi-ufs-fix-interrupt-error-message-for-shared-interrupts.patch b/queue-5.4/scsi-ufs-fix-interrupt-error-message-for-shared-interrupts.patch new file mode 100644 index 00000000000..216092dbf53 --- /dev/null +++ b/queue-5.4/scsi-ufs-fix-interrupt-error-message-for-shared-interrupts.patch @@ -0,0 +1,35 @@ +From 6337f58cec030b34ced435b3d9d7d29d63c96e36 Mon Sep 17 00:00:00 2001 +From: Adrian Hunter +Date: Tue, 11 Aug 2020 16:39:35 +0300 +Subject: scsi: ufs: Fix interrupt error message for shared interrupts + +From: Adrian Hunter + +commit 6337f58cec030b34ced435b3d9d7d29d63c96e36 upstream. + +The interrupt might be shared, in which case it is not an error for the +interrupt handler to be called when the interrupt status is zero, so don't +print the message unless there was enabled interrupt status. + +Link: https://lore.kernel.org/r/20200811133936.19171-1-adrian.hunter@intel.com +Fixes: 9333d7757348 ("scsi: ufs: Fix irq return code") +Reviewed-by: Avri Altman +Signed-off-by: Adrian Hunter +Signed-off-by: Martin K. Petersen +Signed-off-by: Orson Zhai +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/ufs/ufshcd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/scsi/ufs/ufshcd.c ++++ b/drivers/scsi/ufs/ufshcd.c +@@ -5661,7 +5661,7 @@ static irqreturn_t ufshcd_intr(int irq, + intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); + } + +- if (retval == IRQ_NONE) { ++ if (enabled_intr_status && retval == IRQ_NONE) { + dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n", + __func__, intr_status); + ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); diff --git a/queue-5.4/series b/queue-5.4/series index a7518365afe..327a5f5f421 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -1 +1,3 @@ soc-tegra-pmc-fix-imbalanced-clock-disabling-in-error-code-path.patch +scsi-ufs-fix-interrupt-error-message-for-shared-interrupts.patch +mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch