From: Aurelien Jarno <aurelien@aurel32.net>
Date: Tue, 23 Feb 2010 17:31:00 +0000 (+0100)
Subject: target-mips: fix ROTR and DROTR by zero
X-Git-Tag: v0.12.3~20
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=915080e6b136f518793dba4232cbf3ed31a907a8;p=thirdparty%2Fqemu.git

target-mips: fix ROTR and DROTR by zero

Backported from HEAD (cc3f20fee2c9bea3793bf873c531ae6baf68df3a)

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---

diff --git a/target-mips/translate.c b/target-mips/translate.c
index bf983821ac1..f811f50c7ff 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1451,6 +1451,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
                     tcg_gen_rotri_i32(t1, t1, uimm);
                     tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
                     tcg_temp_free_i32(t1);
+                } else {
+                    tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
                 }
                 opn = "rotr";
             } else {
@@ -1489,6 +1491,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
             if (env->insn_flags & ISA_MIPS32R2) {
                 if (uimm != 0) {
                     tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
+                } else {
+                    tcg_gen_mov_tl(cpu_gpr[rt], t0);
                 }
                 opn = "drotr";
             } else {