From: Greg Kroah-Hartman Date: Mon, 6 Jan 2014 17:43:20 +0000 (-0800) Subject: 3.12-stable patches X-Git-Tag: v3.4.76~45 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=91ae9566408064e1ad09e1e840db3974f6e85197;p=thirdparty%2Fkernel%2Fstable-queue.git 3.12-stable patches added patches: drm-radeon-fix-render-backend-setup-for-si-and-cik.patch drm-radeon-fix-uvd-256mb-check.patch --- diff --git a/queue-3.12/drm-radeon-fix-render-backend-setup-for-si-and-cik.patch b/queue-3.12/drm-radeon-fix-render-backend-setup-for-si-and-cik.patch new file mode 100644 index 00000000000..fe194bc041a --- /dev/null +++ b/queue-3.12/drm-radeon-fix-render-backend-setup-for-si-and-cik.patch @@ -0,0 +1,121 @@ +From 9fadb352ed73edd7801a280b552d33a6040c8721 Mon Sep 17 00:00:00 2001 +From: Marek Olšák +Date: Sun, 22 Dec 2013 02:18:00 +0100 +Subject: drm/radeon: fix render backend setup for SI and CIK + +From: Marek Olšák + +commit 9fadb352ed73edd7801a280b552d33a6040c8721 upstream. + +Only the render backends of the first shader engine were enabled. The others +were erroneously disabled. Enabling the other render backends improves +performance a lot. + +Unigine Sanctuary on Bonaire: + Before: 15 fps + After: 90 fps + +Judging from the fan noise, the GPU was also underclocked when the other +render backends were disabled, resulting in horrible performance. The fan is +a lot noisy under load now. + +Signed-off-by: Marek Olšák +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/cik.c | 10 +++++----- + drivers/gpu/drm/radeon/si.c | 10 +++++----- + 2 files changed, 10 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -2608,7 +2608,7 @@ static u32 cik_create_bitmask(u32 bit_wi + * Returns the disabled RB bitmask. + */ + static u32 cik_get_rb_disabled(struct radeon_device *rdev, +- u32 max_rb_num, u32 se_num, ++ u32 max_rb_num_per_se, + u32 sh_per_se) + { + u32 data, mask; +@@ -2622,7 +2622,7 @@ static u32 cik_get_rb_disabled(struct ra + + data >>= BACKEND_DISABLE_SHIFT; + +- mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se); ++ mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se); + + return data & mask; + } +@@ -2639,7 +2639,7 @@ static u32 cik_get_rb_disabled(struct ra + */ + static void cik_setup_rb(struct radeon_device *rdev, + u32 se_num, u32 sh_per_se, +- u32 max_rb_num) ++ u32 max_rb_num_per_se) + { + int i, j; + u32 data, mask; +@@ -2649,14 +2649,14 @@ static void cik_setup_rb(struct radeon_d + for (i = 0; i < se_num; i++) { + for (j = 0; j < sh_per_se; j++) { + cik_select_se_sh(rdev, i, j); +- data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); ++ data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se); + disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH); + } + } + cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); + + mask = 1; +- for (i = 0; i < max_rb_num; i++) { ++ for (i = 0; i < max_rb_num_per_se * se_num; i++) { + if (!(disabled_rbs & mask)) + enabled_rbs |= mask; + mask <<= 1; +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -2816,7 +2816,7 @@ static void si_setup_spi(struct radeon_d + } + + static u32 si_get_rb_disabled(struct radeon_device *rdev, +- u32 max_rb_num, u32 se_num, ++ u32 max_rb_num_per_se, + u32 sh_per_se) + { + u32 data, mask; +@@ -2830,14 +2830,14 @@ static u32 si_get_rb_disabled(struct rad + + data >>= BACKEND_DISABLE_SHIFT; + +- mask = si_create_bitmask(max_rb_num / se_num / sh_per_se); ++ mask = si_create_bitmask(max_rb_num_per_se / sh_per_se); + + return data & mask; + } + + static void si_setup_rb(struct radeon_device *rdev, + u32 se_num, u32 sh_per_se, +- u32 max_rb_num) ++ u32 max_rb_num_per_se) + { + int i, j; + u32 data, mask; +@@ -2847,14 +2847,14 @@ static void si_setup_rb(struct radeon_de + for (i = 0; i < se_num; i++) { + for (j = 0; j < sh_per_se; j++) { + si_select_se_sh(rdev, i, j); +- data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); ++ data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se); + disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); + } + } + si_select_se_sh(rdev, 0xffffffff, 0xffffffff); + + mask = 1; +- for (i = 0; i < max_rb_num; i++) { ++ for (i = 0; i < max_rb_num_per_se * se_num; i++) { + if (!(disabled_rbs & mask)) + enabled_rbs |= mask; + mask <<= 1; diff --git a/queue-3.12/drm-radeon-fix-uvd-256mb-check.patch b/queue-3.12/drm-radeon-fix-uvd-256mb-check.patch new file mode 100644 index 00000000000..a077574eb02 --- /dev/null +++ b/queue-3.12/drm-radeon-fix-uvd-256mb-check.patch @@ -0,0 +1,30 @@ +From bae651dbd7ade3c5d6518f89599ae680a2fe2b85 Mon Sep 17 00:00:00 2001 +From: Christian König +Date: Fri, 20 Dec 2013 17:48:54 +0100 +Subject: drm/radeon: fix UVD 256MB check + +From: Christian König + +commit bae651dbd7ade3c5d6518f89599ae680a2fe2b85 upstream. + +Otherwise the kernel might reject our decoding requests. + +Signed-off-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_uvd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/radeon/radeon_uvd.c ++++ b/drivers/gpu/drm/radeon/radeon_uvd.c +@@ -472,7 +472,7 @@ static int radeon_uvd_cs_reloc(struct ra + return -EINVAL; + } + +- if ((start >> 28) != (end >> 28)) { ++ if ((start >> 28) != ((end - 1) >> 28)) { + DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", + start, end); + return -EINVAL; diff --git a/queue-3.12/series b/queue-3.12/series index 4b245d47d14..6b2405796ec 100644 --- a/queue-3.12/series +++ b/queue-3.12/series @@ -74,3 +74,5 @@ drm-radeon-fix-asic-gfx-values-for-scrapper-asics.patch drm-i915-fix-erroneous-dereference-of-batch_obj-inside-reset_status.patch drm-i915-change-crtc-assertion-on-lcpll-disable.patch drm-i915-use-the-correct-gmch_ctrl-register-for-sandybridge.patch +drm-radeon-fix-uvd-256mb-check.patch +drm-radeon-fix-render-backend-setup-for-si-and-cik.patch