From: Greg Kroah-Hartman Date: Mon, 27 May 2024 18:18:41 +0000 (+0200) Subject: 5.15-stable patches X-Git-Tag: v6.9.3~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=92365aaa4e80016ecaa45d72d159fd0355a5b3b4;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: x86-tsc-trust-initial-offset-in-architectural-tsc-adjust-msrs.patch --- diff --git a/queue-5.15/series b/queue-5.15/series index c8b251dfebe..a3c6414aecc 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -1,3 +1,4 @@ +x86-tsc-trust-initial-offset-in-architectural-tsc-adjust-msrs.patch tty-n_gsm-fix-possible-out-of-bounds-in-gsm0_receive.patch tty-n_gsm-fix-missing-receive-state-reset-after-mode-switch.patch speakup-fix-sizeof-vs-array_size-bug.patch diff --git a/queue-5.15/x86-tsc-trust-initial-offset-in-architectural-tsc-adjust-msrs.patch b/queue-5.15/x86-tsc-trust-initial-offset-in-architectural-tsc-adjust-msrs.patch new file mode 100644 index 00000000000..928977314eb --- /dev/null +++ b/queue-5.15/x86-tsc-trust-initial-offset-in-architectural-tsc-adjust-msrs.patch @@ -0,0 +1,46 @@ +From 455f9075f14484f358b3c1d6845b4a438de198a7 Mon Sep 17 00:00:00 2001 +From: Daniel J Blueman +Date: Fri, 19 Apr 2024 16:51:46 +0800 +Subject: x86/tsc: Trust initial offset in architectural TSC-adjust MSRs + +From: Daniel J Blueman + +commit 455f9075f14484f358b3c1d6845b4a438de198a7 upstream. + +When the BIOS configures the architectural TSC-adjust MSRs on secondary +sockets to correct a constant inter-chassis offset, after Linux brings the +cores online, the TSC sync check later resets the core-local MSR to 0, +triggering HPET fallback and leading to performance loss. + +Fix this by unconditionally using the initial adjust values read from the +MSRs. Trusting the initial offsets in this architectural mechanism is a +better approach than special-casing workarounds for specific platforms. + +Signed-off-by: Daniel J Blueman +Signed-off-by: Thomas Gleixner +Reviewed-by: Steffen Persvold +Reviewed-by: James Cleverdon +Reviewed-by: Dimitri Sivanich +Reviewed-by: Prarit Bhargava +Link: https://lore.kernel.org/r/20240419085146.175665-1-daniel@quora.org +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/tsc_sync.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/arch/x86/kernel/tsc_sync.c ++++ b/arch/x86/kernel/tsc_sync.c +@@ -192,11 +192,9 @@ bool tsc_store_and_check_tsc_adjust(bool + cur->warned = false; + + /* +- * If a non-zero TSC value for socket 0 may be valid then the default +- * adjusted value cannot assumed to be zero either. ++ * The default adjust value cannot be assumed to be zero on any socket. + */ +- if (tsc_async_resets) +- cur->adjusted = bootval; ++ cur->adjusted = bootval; + + /* + * Check whether this CPU is the first in a package to come up. In