From: Naresh Kumar Ravulapalli Date: Thu, 11 Sep 2025 05:21:11 +0000 (-0700) Subject: drivers: clk: agilex: Fix EMAC clock source selection X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=924a9fc4021cf4899c6b1e26d28336f412aa296f;p=thirdparty%2Fu-boot.git drivers: clk: agilex: Fix EMAC clock source selection Fix the incorrect bit masking and bit shift used to compute EMAC control which in turn is used to select EMAC clock from EMAC source A or B. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 46b04895cc5..19c4e8220db 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -546,14 +546,14 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) /* Get EMAC clock source */ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); if (emac_id == AGILEX_EMAC0_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; else if (emac_id == AGILEX_EMAC1_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; else if (emac_id == AGILEX_EMAC2_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; else return 0;