From: Peter Maydell Date: Tue, 19 Nov 2019 13:32:07 +0000 (+0000) Subject: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191119' into... X-Git-Tag: v4.2.0-rc2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9263dec8ef9a5723d87724c5d1de86a2d5f8ba29;p=thirdparty%2Fqemu.git Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191119' into staging target-arm queue: * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY * Relax r13 restriction for ldrex/strex for v8.0 * Do not reject rt == rt2 for strexd * net/cadence_gem: Set PHY autonegotiation restart status * ssi: xilinx_spips: Skip spi bus update for a few register writes * pl031: Expose RTCICR as proper WC register # gpg: Signature made Tue 19 Nov 2019 13:30:35 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell " [ultimate] # gpg: aka "Peter Maydell " [ultimate] # gpg: aka "Peter Maydell " [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20191119: target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY target/arm: Relax r13 restriction for ldrex/strex for v8.0 target/arm: Do not reject rt == rt2 for strexd net/cadence_gem: Set PHY autonegotiation restart status ssi: xilinx_spips: Skip spi bus update for a few register writes target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller pl031: Expose RTCICR as proper WC register Signed-off-by: Peter Maydell --- 9263dec8ef9a5723d87724c5d1de86a2d5f8ba29