From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Date: Thu, 19 Sep 2024 05:50:43 +0000 (+0800)
Subject: target/riscv: Correct SXL return value for RV32 in RV64 QEMU
X-Git-Tag: v9.2.0-rc0~28^2~46
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=929e4277c128772bad41cc795995f754cb9991af;p=thirdparty%2Fqemu.git

target/riscv: Correct SXL return value for RV32 in RV64 QEMU

Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240919055048.562-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1619c3acb66..a63a29744c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -709,8 +709,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 #ifdef CONFIG_USER_ONLY
     return env->misa_mxl;
 #else
-    return get_field(env->mstatus, MSTATUS64_SXL);
+    if (env->misa_mxl != MXL_RV32) {
+        return get_field(env->mstatus, MSTATUS64_SXL);
+    }
 #endif
+    return MXL_RV32;
 }
 #endif