From: Lad Prabhakar Date: Tue, 14 Oct 2025 10:53:48 +0000 (+0100) Subject: clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP X-Git-Tag: v6.19-rc1~58^2~1^2~1^2~9 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=934dcccf3ffc7568fdeb363842bb9fc36e1be608;p=thirdparty%2Flinux.git clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP On the RZ/T2H SoC, a specific sequence is required when releasing a module from the module stop state (i.e. when clearing the corresponding bit in the MSTPCRm register to '0'). After writing to the MSTPCRm register, a read-back of the same register must be performed, followed by at least seven dummy reads of any register within the IP block that is being released. To avoid mapping device registers for this purpose, a short delay is introduced after the read-back to ensure proper hardware stabilization before the module becomes accessible. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251014105348.93705-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 0ffe6ee8f165c..66c20698927c3 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -308,10 +308,21 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); - if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A || - priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) + if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) return 0; + if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { + /* + * For the RZ/T2H case, it is necessary to perform a read-back after + * accessing the MSTPCRm register and to dummy-read any register of + * the IP at least seven times. Instead of memory-mapping the IP + * register, we simply add a delay after the read operation. + */ + cpg_rzt2h_mstp_read(hw, priv->control_regs[reg]); + udelay(10); + return 0; + } + error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], value, !(value & bitmask), 0, 10); if (error)