From: Richard Henderson Date: Mon, 8 Oct 2018 13:55:02 +0000 (+0100) Subject: target/arm: Define ID_AA64ZFR0_EL1 X-Git-Tag: v3.1.0-rc0~61^2~28 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9516d7725ec1deaa6ef5ccc5a26d005650d6c524;p=thirdparty%2Fqemu.git target/arm: Define ID_AA64ZFR0_EL1 Given that the only field defined for this new register may only be 0, we don't actually need to change anything except the name. Reviewed-by: Peter Maydell Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson Message-id: 20181005175350.30752-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e721a65272..050f3d444c6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5018,9 +5018,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, + /* At present, only SVEver == 0 is defined anyway. */ .resetvalue = 0 }, { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,