From: Sasha Levin Date: Sat, 17 Nov 2018 15:18:03 +0000 (-0500) Subject: commits for 4.14 X-Git-Tag: v4.19.3~32 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=956cc20c2baa7b4a63b61fb74b85bec40096d9eb;p=thirdparty%2Fkernel%2Fstable-queue.git commits for 4.14 Signed-off-by: Sasha Levin --- diff --git a/queue-4.14/mips-loongson-3-fix-bridge-irq-delivery-problem.patch b/queue-4.14/mips-loongson-3-fix-bridge-irq-delivery-problem.patch new file mode 100644 index 00000000000..2655a838ef5 --- /dev/null +++ b/queue-4.14/mips-loongson-3-fix-bridge-irq-delivery-problem.patch @@ -0,0 +1,82 @@ +From d1582fc01087d304e19530869fea23059fa94041 Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Wed, 5 Sep 2018 17:33:09 +0800 +Subject: MIPS: Loongson-3: Fix BRIDGE irq delivery problem + +[ Upstream commit 360fe725f8849aaddc53475fef5d4a0c439b05ae ] + +After commit e509bd7da149dc349160 ("genirq: Allow migration of chained +interrupts by installing default action") Loongson-3 fails at here: + +setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); + +This is because both chained_action and cascade_irqaction don't have +IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET +timer interrupt can't be delivered during S3. So we set the irqchip of +the chained irq to loongson_irq_chip which doesn't disable the chained +irq in CP0.Status. + +Cc: stable@vger.kernel.org +Signed-off-by: Huacai Chen +Signed-off-by: Paul Burton +Patchwork: https://patchwork.linux-mips.org/patch/20434/ +Cc: Ralf Baechle +Cc: James Hogan +Cc: linux-mips@linux-mips.org +Cc: Fuxin Zhang +Cc: Zhangjin Wu +Cc: Huacai Chen +Signed-off-by: Sasha Levin +--- + arch/mips/include/asm/mach-loongson64/irq.h | 2 +- + arch/mips/loongson64/loongson-3/irq.c | 13 +++---------- + 2 files changed, 4 insertions(+), 11 deletions(-) + +diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h +index 3644b68c0ccc..be9f727a9328 100644 +--- a/arch/mips/include/asm/mach-loongson64/irq.h ++++ b/arch/mips/include/asm/mach-loongson64/irq.h +@@ -10,7 +10,7 @@ + #define MIPS_CPU_IRQ_BASE 56 + + #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */ +-#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */ ++#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */ + #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */ + + #define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base +diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c +index 2e115ab66a00..5605061f5f98 100644 +--- a/arch/mips/loongson64/loongson-3/irq.c ++++ b/arch/mips/loongson64/loongson-3/irq.c +@@ -96,12 +96,6 @@ void mach_irq_dispatch(unsigned int pending) + } + } + +-static struct irqaction cascade_irqaction = { +- .handler = no_action, +- .flags = IRQF_NO_SUSPEND, +- .name = "cascade", +-}; +- + static inline void mask_loongson_irq(struct irq_data *d) { } + static inline void unmask_loongson_irq(struct irq_data *d) { } + +@@ -147,11 +141,10 @@ void __init mach_init_irq(void) + + irq_set_chip_and_handler(LOONGSON_UART_IRQ, + &loongson_irq_chip, handle_percpu_irq); ++ irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ, ++ &loongson_irq_chip, handle_percpu_irq); + +- /* setup HT1 irq */ +- setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); +- +- set_c0_status(STATUSF_IP2 | STATUSF_IP6); ++ set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6); + } + + #ifdef CONFIG_HOTPLUG_CPU +-- +2.17.1 + diff --git a/queue-4.14/mips-loongson-3-fix-cpu-uart-irq-delivery-problem.patch b/queue-4.14/mips-loongson-3-fix-cpu-uart-irq-delivery-problem.patch new file mode 100644 index 00000000000..b1e562a3583 --- /dev/null +++ b/queue-4.14/mips-loongson-3-fix-cpu-uart-irq-delivery-problem.patch @@ -0,0 +1,94 @@ +From b634f3ad81a17a1d4ba8b7ffbb4a7ef19bff3670 Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Wed, 5 Sep 2018 17:33:08 +0800 +Subject: MIPS: Loongson-3: Fix CPU UART irq delivery problem + +[ Upstream commit d06f8a2f1befb5a3d0aa660ab1c05e9b744456ea ] + +Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to +other CPUs) may cause interrupts be lost, especially in multi-package +machines (Package-0's UART irq cannot be delivered to others). So make +mask_loongson_irq() and unmask_loongson_irq() be no-ops. + +The original problem (UART IRQ may deliver to any core) is also because +of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to +remove all of the stuff. + +Signed-off-by: Huacai Chen +Signed-off-by: Paul Burton +Patchwork: https://patchwork.linux-mips.org/patch/20433/ +Cc: Ralf Baechle +Cc: James Hogan +Cc: linux-mips@linux-mips.org +Cc: Fuxin Zhang +Cc: Zhangjin Wu +Cc: Huacai Chen +Signed-off-by: Sasha Levin +--- + arch/mips/loongson64/loongson-3/irq.c | 43 ++------------------------- + 1 file changed, 3 insertions(+), 40 deletions(-) + +diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c +index cbeb20f9fc95..2e115ab66a00 100644 +--- a/arch/mips/loongson64/loongson-3/irq.c ++++ b/arch/mips/loongson64/loongson-3/irq.c +@@ -102,45 +102,8 @@ static struct irqaction cascade_irqaction = { + .name = "cascade", + }; + +-static inline void mask_loongson_irq(struct irq_data *d) +-{ +- clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); +- irq_disable_hazard(); +- +- /* Workaround: UART IRQ may deliver to any core */ +- if (d->irq == LOONGSON_UART_IRQ) { +- int cpu = smp_processor_id(); +- int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node; +- int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node; +- u64 intenclr_addr = smp_group[node_id] | +- (u64)(&LOONGSON_INT_ROUTER_INTENCLR); +- u64 introuter_lpc_addr = smp_group[node_id] | +- (u64)(&LOONGSON_INT_ROUTER_LPC); +- +- *(volatile u32 *)intenclr_addr = 1 << 10; +- *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<irq == LOONGSON_UART_IRQ) { +- int cpu = smp_processor_id(); +- int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node; +- int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node; +- u64 intenset_addr = smp_group[node_id] | +- (u64)(&LOONGSON_INT_ROUTER_INTENSET); +- u64 introuter_lpc_addr = smp_group[node_id] | +- (u64)(&LOONGSON_INT_ROUTER_LPC); +- +- *(volatile u32 *)intenset_addr = 1 << 10; +- *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<irq - MIPS_CPU_IRQ_BASE)); +- irq_enable_hazard(); +-} ++static inline void mask_loongson_irq(struct irq_data *d) { } ++static inline void unmask_loongson_irq(struct irq_data *d) { } + + /* For MIPS IRQs which shared by all cores */ + static struct irq_chip loongson_irq_chip = { +@@ -183,7 +146,7 @@ void __init mach_init_irq(void) + chip->irq_set_affinity = plat_set_irq_affinity; + + irq_set_chip_and_handler(LOONGSON_UART_IRQ, +- &loongson_irq_chip, handle_level_irq); ++ &loongson_irq_chip, handle_percpu_irq); + + /* setup HT1 irq */ + setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); +-- +2.17.1 + diff --git a/queue-4.14/series b/queue-4.14/series index a44140f542a..994a25efdf4 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -32,3 +32,5 @@ fuse-fix-use-after-free-in-fuse_dev_do_write.patch fuse-fix-blocked_waitq-wakeup.patch fuse-set-fr_sent-while-locked.patch ovl-fix-recursive-oi-lock-in-ovl_link.patch +mips-loongson-3-fix-cpu-uart-irq-delivery-problem.patch +mips-loongson-3-fix-bridge-irq-delivery-problem.patch