From: Greg Kroah-Hartman Date: Sat, 13 Sep 2025 14:26:07 +0000 (+0200) Subject: 6.6-stable patches X-Git-Tag: v6.1.153~61 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=95a39136356d21a8bdd312b84622f4d159f5ba5c;p=thirdparty%2Fkernel%2Fstable-queue.git 6.6-stable patches added patches: mtd-nand-raw-atmel-fix-comment-in-timings-preparation.patch mtd-nand-raw-atmel-respect-tar-tclr-in-read-setup-timing.patch --- diff --git a/queue-6.6/mtd-nand-raw-atmel-fix-comment-in-timings-preparation.patch b/queue-6.6/mtd-nand-raw-atmel-fix-comment-in-timings-preparation.patch new file mode 100644 index 0000000000..d26cfd5c1c --- /dev/null +++ b/queue-6.6/mtd-nand-raw-atmel-fix-comment-in-timings-preparation.patch @@ -0,0 +1,39 @@ +From stable+bounces-179484-greg=kroah.com@vger.kernel.org Sat Sep 13 16:10:24 2025 +From: Sasha Levin +Date: Sat, 13 Sep 2025 10:10:16 -0400 +Subject: mtd: nand: raw: atmel: Fix comment in timings preparation +To: stable@vger.kernel.org +Cc: Alexander Dahl , Nicolas Ferre , Miquel Raynal , Sasha Levin +Message-ID: <20250913141017.1361840-1-sashal@kernel.org> + +From: Alexander Dahl + +[ Upstream commit 1c60e027ffdebd36f4da766d9c9abbd1ea4dd8f9 ] + +Looks like a copy'n'paste mistake introduced when initially adding the +dynamic timings feature with commit f9ce2eddf176 ("mtd: nand: atmel: Add +->setup_data_interface() hooks"). The context around this and +especially the code itself suggests 'read' is meant instead of write. + +Signed-off-by: Alexander Dahl +Reviewed-by: Nicolas Ferre +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20240226122537.75097-1-ada@thorsis.com +Stable-dep-of: fd779eac2d65 ("mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/nand/raw/atmel/nand-controller.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/nand/raw/atmel/nand-controller.c ++++ b/drivers/mtd/nand/raw/atmel/nand-controller.c +@@ -1378,7 +1378,7 @@ static int atmel_smc_nand_prepare_smccon + return ret; + + /* +- * The write cycle timing is directly matching tWC, but is also ++ * The read cycle timing is directly matching tRC, but is also + * dependent on the setup and hold timings we calculated earlier, + * which gives: + * diff --git a/queue-6.6/mtd-nand-raw-atmel-respect-tar-tclr-in-read-setup-timing.patch b/queue-6.6/mtd-nand-raw-atmel-respect-tar-tclr-in-read-setup-timing.patch new file mode 100644 index 0000000000..be6b827342 --- /dev/null +++ b/queue-6.6/mtd-nand-raw-atmel-respect-tar-tclr-in-read-setup-timing.patch @@ -0,0 +1,62 @@ +From stable+bounces-179485-greg=kroah.com@vger.kernel.org Sat Sep 13 16:10:26 2025 +From: Sasha Levin +Date: Sat, 13 Sep 2025 10:10:17 -0400 +Subject: mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing +To: stable@vger.kernel.org +Cc: Alexander Sverdlin , Alexander Dahl , Miquel Raynal , Sasha Levin +Message-ID: <20250913141017.1361840-2-sashal@kernel.org> + +From: Alexander Sverdlin + +[ Upstream commit fd779eac2d659668be4d3dbdac0710afd5d6db12 ] + +Having setup time 0 violates tAR, tCLR of some chips, for instance +TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte +being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of +98 dc 90 15 76 ...). + +Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation +[1], but it looks more appropriate to just calculate setup time properly. + +[1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ApplicationNotes/ApplicationNotes/doc6255.pdf + +Cc: stable@vger.kernel.org +Fixes: f9ce2eddf176 ("mtd: nand: atmel: Add ->setup_data_interface() hooks") +Signed-off-by: Alexander Sverdlin +Tested-by: Alexander Dahl +Signed-off-by: Miquel Raynal +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/nand/raw/atmel/nand-controller.c | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/nand/raw/atmel/nand-controller.c ++++ b/drivers/mtd/nand/raw/atmel/nand-controller.c +@@ -1378,13 +1378,23 @@ static int atmel_smc_nand_prepare_smccon + return ret; + + /* ++ * Read setup timing depends on the operation done on the NAND: ++ * ++ * NRD_SETUP = max(tAR, tCLR) ++ */ ++ timeps = max(conf->timings.sdr.tAR_min, conf->timings.sdr.tCLR_min); ++ ncycles = DIV_ROUND_UP(timeps, mckperiodps); ++ totalcycles += ncycles; ++ ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles); ++ if (ret) ++ return ret; ++ ++ /* + * The read cycle timing is directly matching tRC, but is also + * dependent on the setup and hold timings we calculated earlier, + * which gives: + * +- * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD) +- * +- * NRD_SETUP is always 0. ++ * NRD_CYCLE = max(tRC, NRD_SETUP + NRD_PULSE + NRD_HOLD) + */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); + ncycles = max(totalcycles, ncycles); diff --git a/queue-6.6/series b/queue-6.6/series index 361363b931..16662b0cba 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -44,3 +44,5 @@ mm-damon-core-set-quota-charged_from-to-jiffies-at-first-charge-window.patch drm-mediatek-fix-potential-of-node-use-after-free.patch drm-amdgpu-vcn-allow-limiting-ctx-to-instance-0-for-av1-at-any-time.patch drm-amdgpu-vcn4-fix-ib-parsing-with-multiple-engine-info-packages.patch +mtd-nand-raw-atmel-fix-comment-in-timings-preparation.patch +mtd-nand-raw-atmel-respect-tar-tclr-in-read-setup-timing.patch