From: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Thu, 31 Mar 2016 15:23:29 +0000 (+0000)
Subject: re PR target/70453 (gcc generates invalid instruction vextractu64x4 (should be: vextr... 
X-Git-Tag: basepoints/gcc-7~203
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=95d34b9618011fea39c48544cc8937577720dcc1;p=thirdparty%2Fgcc.git

re PR target/70453 (gcc generates invalid instruction vextractu64x4 (should be: vextracti64x4))

Fix PR target/70453.

gcc/
	* config/i386/sse.md (define_mode_attr shuffletype): Fix typo.

gcc/testsuite/
	* gcc.target/i386/pr70453.c: New test.

From-SVN: r234634
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 64c8fcd5ca51..5a9b32158223 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-31  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/70453
+	* config/i386/sse.md (define_mode_attr shuffletype): Fix typo.
+
 2016-03-31  Jakub Jelinek  <jakub@redhat.com>
 
 	PR rtl-optimization/70460
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 44141ea5d97f..5fd650fde4ac 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -493,7 +493,7 @@
   [(V16SF "f") (V16SI "i") (V8DF "f") (V8DI "i")
   (V8SF "f") (V8SI "i") (V4DF "f") (V4DI "i")
   (V4SF "f") (V4SI "i") (V2DF "f") (V2DI "i")
-  (V32QI "i") (V16HI "u") (V16QI "i") (V8HI "i")
+  (V32QI "i") (V16HI "i") (V16QI "i") (V8HI "i")
   (V64QI "i") (V1TI "i") (V2TI "i")])
 
 (define_mode_attr ssequartermode
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 49c25095da71..4cab39478b7a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-31  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+	PR target/70453
+	* gcc.target/i386/pr70453.c: New test.
+
 2016-03-31  Andrey Belevantsev  <abel@ispras.ru>
 
 	PR target/70292
diff --git a/gcc/testsuite/gcc.target/i386/pr70453.c b/gcc/testsuite/gcc.target/i386/pr70453.c
new file mode 100644
index 000000000000..2ff1fbb804db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70453.c
@@ -0,0 +1,18 @@
+/* PR target/70453 */
+/* { dg-do assemble { target { lp64 } } } */
+/* { dg-require-effective-target avx512vbmi } */
+/* { dg-options "-Og -fschedule-insns -mavx512vbmi" } */
+
+
+typedef char v64u8 __attribute__ ((vector_size (64)));
+typedef short v64u16 __attribute__ ((vector_size (64)));
+typedef __int128 v64u128 __attribute__ ((vector_size (64)));
+
+int
+foo(v64u8 v64u8_0, v64u16 v64u16_0, v64u128 v64u128_0)
+{
+  v64u128_0 /= (v64u128){ v64u8_0[28] }  | 0x1424171b0c;
+  v64u8_0 %= (v64u8){ v64u16_0[25], v64u128_0[1]}  ;
+  v64u128_0 %= (v64u128){ v64u16_0[8] };
+  return v64u8_0[0] + v64u8_0[1] + v64u16_0[0] + v64u128_0[0];
+}