From: Paul Cassidy Date: Fri, 28 Feb 2025 00:09:01 +0000 (+0000) Subject: Flit Mode and Device 3 Capability X-Git-Tag: v3.14.0~9 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=9611db3e0a0f81566f81619d0a525cbd20aae856;p=thirdparty%2Fpciutils.git Flit Mode and Device 3 Capability --- diff --git a/lib/header.h b/lib/header.h index 90da646..9cef020 100644 --- a/lib/header.h +++ b/lib/header.h @@ -259,6 +259,7 @@ #define PCI_EXT_CAP_ID_ALT_PROT 0x2b /* Alternate Protocol */ #define PCI_EXT_CAP_ID_SFI 0x2c /* System Firmware Intermediary */ #define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ +#define PCI_EXT_CAP_ID_DEV3 0x2f /* Device 3 */ #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ #define PCI_EXT_CAP_ID_64GT 0x31 /* Physical Layer 64.0 GT/s */ #define PCI_EXT_CAP_ID_FLIT_LOG 0x32 /* Flit Logging */ @@ -777,6 +778,7 @@ #define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */ #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ +#define PCI_EXP_FLAGS_FLIT_MODE 0x8000 /* FLIT mode supported */ #define PCI_EXP_DEVCAP 0x4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ @@ -835,6 +837,7 @@ #define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */ #define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */ #define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */ +#define PCI_EXP_LNKCTL_FLIT_MODE_DIS 0x2000 /* FLIT mode disable */ #define PCI_EXP_LNKSTA 0x12 /* Link Status */ #define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */ #define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */ @@ -953,6 +956,7 @@ #define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */ #define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */ #define PCI_EXP_LINKSTA2_DRS_RCVD 0x8000 /* DRS Msg Received */ +#define PCI_EXP_LINKSTA2_FLIT_MODE 0x0400 /* FLIT mode active */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ @@ -1502,6 +1506,31 @@ #define PCI_LMR_PORT_STS_READY 0x1 /* Margining Ready */ #define PCI_LMR_PORT_STS_SOFT_READY 0x2 /* Margining Software Ready */ +/* Device 3 Extended Capability */ +#define PCI_DEV3_DEVCAP3 0x04 /* Device Capabilities 3 */ +#define PCI_DEV3_DEVCAP3_DMWR_REQ 0x0001 /* DMWr Request Routing Supported */ +#define PCI_DEV3_DEVCAP3_14BIT_TAG_COMP 0x0002 /* 14-Bit Tag Completer Supported */ +#define PCI_DEV3_DEVCAP3_14BIT_TAG_REQ 0x0004 /* 14-Bit Tag Requester Supported */ +#define PCI_DEV3_DEVCAP3_L0P_SUPP 0x0008 /* L0p Supported */ +#define PCI_DEV3_DEVCAP3_PORT_L0P_EXIT(x) (((x) >> 4) & 0x7) /* Port L0p Exit Latency */ +#define PCI_DEV3_DEVCAP3_RETIMER_L0P_EXIT(x) (((x) >> 7) & 0x7) /* Retimer L0p Exit Latency */ +#define PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_COMP 0x0400 /* UIO Mem RdWr Completer Supported */ +#define PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_REQ 0x0800 /* UIO Mem RdWr Requester Supported */ + +#define PCI_DEV3_DEVCTL3 0x08 /* Device Control 3 */ +#define PCI_DEV3_DEVCTL3_DMWR_REQ_EN 0x0001 /* DMWr Requester Enable */ +#define PCI_DEV3_DEVCTL3_DMWR_EGRESS_BLK 0x0002 /* DMWr Egress Blocking */ +#define PCI_DEV3_DEVCTL3_14BIT_TAG_REQ_EN 0x0004 /* 14-Bit Tag Requester Enable */ +#define PCI_DEV3_DEVCTL3_L0P_EN 0x0008 /* L0p Enable */ +#define PCI_DEV3_DEVCTL3_TARGET_LINK_WIDTH(x) (((x) >> 4) & 0x7) /* Target Link Width */ +#define PCI_DEV3_DEVCTL3_UIO_MEM_RDWR_REQ_EN 0x0080 /* UIO Mem RdWr Requester Enable */ +#define PCI_DEV3_DEVCTL3_UIO_REQ_256B_DIS 0x0100 /* UIO Request 256B Boundary Disable */ + +#define PCI_DEV3_DEVSTA3 0x0C /* Device Status 3 */ +#define PCI_DEV3_DEVSTA3_INIT_LINK_WIDTH(x) ((x) & 0x7) /* Initial Link Width */ +#define PCI_DEV3_DEVSTA3_SEGMENT_CAPTURED 0x0008 /* Segment Captured */ +#define PCI_DEV3_DEVSTA3_REMOTE_L0P_SUPP 0x0010 /* Remote L0p Supported */ + /* Integrity and Data Encryption Extended Capability */ #define PCI_IDE_CAP 0x4 #define PCI_IDE_CAP_LINK_IDE_SUPP 0x1 /* Link IDE Stream Supported */ diff --git a/ls-caps.c b/ls-caps.c index c2aaea5..b4e626c 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -843,14 +843,15 @@ static void cap_express_link(struct device *d, int where, int type) if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); - printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", + printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c FltModeDis%c\n", FLAG(w, PCI_EXP_LNKCTL_DISABLE), FLAG(w, PCI_EXP_LNKCTL_CLOCK), FLAG(w, PCI_EXP_LNKCTL_XSYNCH), FLAG(w, PCI_EXP_LNKCTL_CLOCKPM), FLAG(w, PCI_EXP_LNKCTL_HWAUTWD), FLAG(w, PCI_EXP_LNKCTL_BWMIE), - FLAG(w, PCI_EXP_LNKCTL_AUTBWIE)); + FLAG(w, PCI_EXP_LNKCTL_AUTBWIE), + FLAG(w, PCI_EXP_LNKCTL_FLIT_MODE_DIS)); w = get_conf_word(d, where + PCI_EXP_LNKSTA); sta_speed = w & PCI_EXP_LNKSTA_SPEED; @@ -1366,7 +1367,7 @@ static void cap_express_link2(struct device *d, int where, int type) w = get_conf_word(d, where + PCI_EXP_LNKSTA2); printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n" "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n" - "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s", + "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s, FltMode%c", cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)), FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1), @@ -1375,7 +1376,8 @@ static void cap_express_link2(struct device *d, int where, int type) FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ), FLAG(w, PCI_EXP_LINKSTA2_RETIMER), FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS), - cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w))); + cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)), + FLAG(w, PCI_EXP_LINKSTA2_FLIT_MODE)); if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) { printf(", DRS%c\n" @@ -1502,7 +1504,12 @@ cap_express(struct device *d, int where, int cap) default: printf("Unknown type %d", type); } - printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); + printf(", IntMsgNum %d", (cap & PCI_EXP_FLAGS_IRQ) >> 9); + if (cap & PCI_EXP_FLAGS_FLIT_MODE) + printf(", FLIT Mode Supported\n"); + else + printf("\n"); + if (verbose < 2) return type; diff --git a/ls-ecaps.c b/ls-ecaps.c index 6d652bc..508b607 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -1813,6 +1813,103 @@ cap_ide(struct device *d, int where) } } +static const char *l0p_exit_latency(int value) +{ + static const char *latencies[] = { + "Less than 1us", + "1us to less than 2us", + "2us to less than 4us", + "4us to less than 8us", + "8us to less than 16us", + "16us to less than 32us", + "32us-64us", + "More than 64us" + }; + + if (value >= 0 && value <= 7) + return latencies[value]; + return "Unknown"; +} + +static const char *link_width_str(char *buf, size_t buflen, int width) +{ + switch (width) + { + case 0: + return "x1"; + case 1: + return "x2"; + case 2: + return "x4"; + case 3: + return "x8"; + case 4: + return "x16"; + case 7: + return "Dynamic"; + default: + snprintf(buf, buflen, "Unknown (%d)", width); + return buf; + } +} + +static void +cap_dev3(struct device *d, int where) +{ + u32 devcap3; + u16 devctl3, devsta3; + char buf[16]; + + printf("Device 3\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_DEV3_DEVCAP3, 4)) + return; + devcap3 = get_conf_long(d, where + PCI_DEV3_DEVCAP3); + + printf("\t\tDevCap3: DMWr Request Routing%c, 14-Bit Tag Completer%c, 14-Bit Tag Requester%c\n" + "\t\t\t L0p%c", + FLAG(devcap3, PCI_DEV3_DEVCAP3_DMWR_REQ), + FLAG(devcap3, PCI_DEV3_DEVCAP3_14BIT_TAG_COMP), + FLAG(devcap3, PCI_DEV3_DEVCAP3_14BIT_TAG_REQ), + FLAG(devcap3, PCI_DEV3_DEVCAP3_L0P_SUPP)); + + if (devcap3 & PCI_DEV3_DEVCAP3_L0P_SUPP) + printf(", Port L0p Exit Latency: %s, Retimer L0p Exit Latency: %s", + l0p_exit_latency(PCI_DEV3_DEVCAP3_PORT_L0P_EXIT(devcap3)), + l0p_exit_latency(PCI_DEV3_DEVCAP3_RETIMER_L0P_EXIT(devcap3))); + + printf("\n\t\t\t UIO Mem RdWr Completer%c, UIO Mem RdWr Requester%c\n", + FLAG(devcap3, PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_COMP), + FLAG(devcap3, PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_REQ)); + + if (!config_fetch(d, where + PCI_DEV3_DEVCTL3, 2)) + return; + devctl3 = get_conf_word(d, where + PCI_DEV3_DEVCTL3); + + printf("\t\tDevCtl3: DMWr Requester%c, DMWr Egress Blocking%c, 14-Bit Tag Requester%c\n" + "\t\t\t L0p%c, Target Link Width: %s\n" + "\t\t\t UIO Mem RdWr Requester%c, UIO Request 256B Boundary%c\n", + FLAG(devctl3, PCI_DEV3_DEVCTL3_DMWR_REQ_EN), + FLAG(devctl3, PCI_DEV3_DEVCTL3_DMWR_EGRESS_BLK), + FLAG(devctl3, PCI_DEV3_DEVCTL3_14BIT_TAG_REQ_EN), + FLAG(devctl3, PCI_DEV3_DEVCTL3_L0P_EN), + link_width_str(buf, sizeof(buf), PCI_DEV3_DEVCTL3_TARGET_LINK_WIDTH(devctl3)), + FLAG(devctl3, PCI_DEV3_DEVCTL3_UIO_MEM_RDWR_REQ_EN), + FLAG(~devctl3, PCI_DEV3_DEVCTL3_UIO_REQ_256B_DIS)); + + if (!config_fetch(d, where + PCI_DEV3_DEVSTA3, 2)) + return; + devsta3 = get_conf_word(d, where + PCI_DEV3_DEVSTA3); + + printf("\t\tDevSta3: Initial Link Width: %s, Segment Captured%c, Remote L0p%c\n", + link_width_str(buf, sizeof(buf), PCI_DEV3_DEVSTA3_INIT_LINK_WIDTH(devsta3)), + FLAG(devsta3, PCI_DEV3_DEVSTA3_SEGMENT_CAPTURED), + FLAG(devsta3, PCI_DEV3_DEVSTA3_REMOTE_L0P_SUPP)); +} + void show_ext_caps(struct device *d, int type) { @@ -1972,6 +2069,9 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_64GT: cap_phy_64gt(d, where); break; + case PCI_EXT_CAP_ID_DEV3: + cap_dev3(d, where); + break; default: printf("Extended Capability ID %#02x\n", id); break; diff --git a/tests/cap-dev3 b/tests/cap-dev3 new file mode 100644 index 0000000..c9bc830 --- /dev/null +++ b/tests/cap-dev3 @@ -0,0 +1,324 @@ +01:00.0 Non-Volatile memory controller: Synopsys EPMockUp (rev 03) (prog-if 02 [NVM Express]) + Subsystem: Synopsys EPMockUp + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR-