From: Lad Prabhakar Date: Tue, 26 Jul 2022 17:53:15 +0000 (+0100) Subject: dt-bindings: pinctrl: renesas: Document RZ/Five SoC X-Git-Tag: v6.1-rc1~53^2~91^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=96355be8f0a2a7a91aae2e66c0795a13444db5ba;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: pinctrl: renesas: Document RZ/Five SoC RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch updates the comment to include RZ/Five SoC so that we make it clear "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five SoC. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 997b746391120..f081acb7ba049 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -23,7 +23,7 @@ properties: oneOf: - items: - enum: - - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - items: