From: Jinjie Ruan <ruanjinjie@huawei.com>
Date: Fri, 19 Apr 2024 13:32:58 +0000 (+0100)
Subject: target/arm: Add support for NMI in arm_phys_excp_target_el()
X-Git-Tag: v9.1.0-rc0~136^2~30
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=963e4e3648e0601a8f0b288edaf524b3c98fffbd;p=thirdparty%2Fqemu.git

target/arm: Add support for NMI in arm_phys_excp_target_el()

According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target/arm/helper.c b/target/arm/helper.c
index f61a65d8114..4ee59b37059 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10763,6 +10763,7 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
     hcr_el2 = arm_hcr_el2_eff(env);
     switch (excp_idx) {
     case EXCP_IRQ:
+    case EXCP_NMI:
         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
         hcr = hcr_el2 & HCR_IMO;
         break;